JP2010181998A - Data processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data processor, wherein a time to be spent on the restoration of a normal mode from a power saving mode is shortened by allowing a program to operate on a DRAM even in a power saving mode. <P>SOLUTION: The data processor includes a plurality of a DRAM (1)9 and a DRAM (2)10, and not a program but only data are developed in the DRAM (1)9. Then, both the program information and the data are developed in the DRAM (2)10. The program of the DRAM (2)10 is accessed by using high order bits [15:8] of a DRAM data bus [15:0]21. Even when the DRAM (1)9 is set to a power saving mode, the program information can be accessed, and a time to be spent on the restoration of a normal mode from the power saving mode can be shortened. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a data processing apparatus such as a printer or a copying machine using a DRAM (dynamic random access memory), and more particularly to a data processing apparatus having a power saving mode.

  In recent electronic devices such as printers and copiers, there is a demand for both high-speed data processing and low power consumption. Conventionally, in order to perform high-speed data processing, a program in a low-speed ROM is generally copied to a high-speed DRAM and the program is operated on the DRAM. However, DRAM has a problem of high power consumption, and this must be solved.

  For example, in Patent Document 1 (Japanese Patent Laid-Open No. 7-129287), there is a request to temporarily turn off the power of the ROM after copying the ROM data to the DRAM, and to temporarily stop the power after copying the ROM data to the DRAM. If there is, the subsequent ROM data access is made to the ROM and the DRAM power is turned off. It is disclosed that refresh to the DRAM is resumed at the time of resume and ROM data is copied to the DRAM (see paragraphs 21 to 31).

  Further, in Patent Document 2 (Japanese Patent Laid-Open No. 2007-38580), before shifting to the power saving mode, device setting information or the like is saved in a writable non-volatile memory on the DRAM, and the DRAM is set in the power saving mode. An invention for operating a program is disclosed.

JP-A-7-129287 JP 2007-38580 A

  However, in the above Patent Documents 1 and 2, when restoring from the power saving mode to the normal mode, the program and the saved data must be expanded again in the DRAM. In particular, in the above-mentioned Patent Document 2, it is determined whether or not the restoration is necessary by subdividing the contents of the memory, and only necessary and sufficient information is restored. The reason for operating the program on the ROM in the power saving mode is that, in a data processing device as shown in FIG. 15 in which one DRAM constitutes a part of the bits of the data bus, the program is expanded to all DRAMs. This is because the DRAM cannot be put into the power saving mode while the program is operating. FIG. 15 is a block diagram showing an example of the data processing apparatus. In FIG. 15, 51 is a CPU, 52 is a data bus, and 53a to 53d are DRAMs.

  The present invention has been made in view of the above problems, and provides a data processing device that shortens the time required for recovery from the power saving mode to the normal mode by operating the program on the DRAM even in the power saving mode. For the purpose.

  In order to solve the above-described problems, the present invention provides a data processing apparatus that executes program information stored in a non-volatile memory by developing the program information in a volatile memory. The volatile memory includes a plurality of the volatile memories. A first volatile memory in which only the data is expanded without expanding the program information stored in the nonvolatile memory; and a second volatile memory in which the program information is expanded and the data is expanded A control unit is provided that accesses the program information of the second volatile memory with a small data bus width and accesses the data with a large data width. To do.

  According to the present invention configured as described above, since the program information in the second volatile memory is accessed with a small data bus width, the program is operated even when the first volatile memory is in the power saving mode. This makes it possible to reduce the time required to recover from the power saving mode to the normal mode.

1 is a block diagram illustrating a printing system including a printer device as a data processing device of Embodiment 1. FIG. FIG. 3 is a block diagram illustrating a configuration of a data processing unit according to the first embodiment. It is explanatory drawing which shows the data stored in ROM. It is explanatory drawing which shows the mapping on the space address of CPU. It is explanatory drawing which shows the mapping to the DRAM area | region comprised by DRAM (1) and DRAM (2). 3 is a flowchart showing the operation of the first embodiment. 3 is a flowchart showing the operation of the first embodiment. It is a block diagram which shows the structure of a DRAM controller. 6 is a time chart showing a write access operation to a program area. 6 is a time chart showing a read access operation to a program area. It is a time chart which shows the write access operation | movement to a data area. It is a time chart which shows the read access operation | movement to a data area. It is explanatory drawing which shows the mapping on the address space of CPU in Example 2. FIG. It is explanatory drawing which shows the mapping to the DRAM area | region comprised by DRAM (1) 9 and DRAM (2) 10 in Example 2. FIG. It is a block diagram which shows an example of a data processor.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. In addition, the same code | symbol is attached | subjected to the element common to each drawing. FIG. 1 is a block diagram showing a data processing apparatus according to the first embodiment of the present invention.

  In the data processing apparatus according to the first embodiment, an M × N-bit data bus is configured by using M DRAMs having N-bit data signals, and a program is stored on the DRAM. The memory space is divided into a program area and a data area. The program area maps addresses so that only part of the data bus is used, and the data area maps addresses so that the entire data bus is used. In the power saving mode, the DRAM in which no program is stored is set in the self-refresh mode, so that the program is operated on the DRAM and the power consumption is reduced.

  FIG. 1 is a block diagram illustrating a printing system including a printer apparatus as a data processing apparatus according to the first embodiment. In FIG. 1, a printer apparatus 1 according to the first embodiment includes a data processing unit 2, a mechanical control unit 3, and a mechanical unit 4, and is connected to a personal computer 5. The personal computer 5 is connected with a standard interface such as a LAN or USB.

  The data processing unit 2 communicates with the personal computer 5, receives a print command, generates image data, and transmits it to the mechanical control unit 3. The mechanical control unit 3 controls the mechanical unit 4 to print data received from the data processing unit 2 on a sheet. The mechanical unit 4 constitutes a mechanical unit that prints image data on paper.

  FIG. 2 is a block diagram illustrating the configuration of the data processing unit according to the first embodiment. 2, the data processing unit 2 includes a CPU 6, a DRAM controller 7, a DRAM (1) (volatile memory) 9, a DRAM (2) (volatile memory) 10, a host interface control unit 11, and a mechanical control interface unit 12. A ROM controller 13, a ROM (nonvolatile memory) 14, and an arbiter 22. The CPU 6, DRAM controller 7, ROM controller 13, host interface control unit 11, mechanical control interface unit 13, and arbiter 22 are connected by a system bus 15.

  The system bus 15 includes a bus request signal S_REQ, a bus grant signal S_GNT, an address signal S_A, a 16-bit data signal S_D [15: 0], an address valid signal S_ASTB, a data ready signal S_DRDY, a data ack signal S_DACK, and a write signal S_WR. Composed.

  The DRAM (1) 9 and the DRAM (2) 10 are standard DDR (dynamic device reconfiguration) SDRAM having an 8-bit data signal. A DRAM address bus 17 and a DRAM control signal 18 are connected between the DRAM controller 7 and the DRAM (1) 9 and DRAM (2) 10. The DRAM controller 7 and the DRAM (1) 9 are connected by the chip selection signal (1) 19 and the lower 8 bits of the DRAM data bus [15: 0] 21, and the DRAM controller 7 and the DRAM (2) 10 are The chip selection signal (2) 20 is connected to the upper 8 bits of the DRAM data bus [15: 0] 21. The DRAM control signal 18 is a standard DDR SDRAM control signal excluding the chip selection signal. The ROM controller 13 is connected to the ROM 14.

  The first embodiment having the above configuration has two characteristics. One is that the chip selection signal (1) 19 and the chip selection signal (2) 20 are individually connected to the DRAM (1) 9 and the DRAM (2) 10, respectively. ) 10 can be individually set to the self-refresh mode. In the other, DRAM (1) 9 constitutes the lower 8 bits of the DRAM data bus [15: 0] 21 and DRAM (2) 10 constitutes the upper 8 bits of the DRAM data bus [15: 0] 21. Therefore, for accessing large-capacity data such as image data, both DRAM (1) 9 and DRAM (2) 10 are used for 16-bit high-speed access, and small data such as programs are accessed. Is that 8-bit access using only DRAM (1) 9 becomes possible.

  FIG. 3 is an explanatory diagram showing data stored in the ROM 14. In FIG. 3, the ROM 14 stores a boot program 31 and a compressed system program 32.

  FIG. 4 is an explanatory diagram showing the mapping of the CPU 6 onto the space address. In FIG. 4, the address space of the CPU 6 is divided and mapped into a DRAM area 33, a ROM area 34, and an IO area 35. The DRAM area 33 is further divided into a program area 33a and a data area 33b. The program area 33a includes a work area for temporarily storing program variables, device setting information, and the like. The program area 33a maps address 0x0 to address 0x2 ^ m-1 (0x2 to the power of (m-1)), and the data area 33b maps address 0x2 ^ m * 2 or more. Further, the area from the address 0x2 ^ m to the address 0x2 ^ m * 2-1 is an unusable area 33c.

  FIG. 5 is an explanatory diagram showing mapping to a DRAM area composed of DRAM (1) 9 and DRAM (2) 10. In FIG. 5, addresses 0x0 to 0x2 ^ m * 2-1 are mapped to the program area 36a, and the data area 36b is mapped to 0x2 ^ m * 2 or more. An odd address in the area from address 0x0 to address 0x2 ^ m * 2-1 is an unusable area 36c.

  Next, the operation of the first embodiment will be described. 6 and 7 are flowcharts showing the operation of the first embodiment. FIG. 6 shows the operation until the printer apparatus 1 enters the standby state, and FIG. 7 shows the operation after the standby state. First, when the printer apparatus 1 is powered on (step 1), the CPU 6 reads the boot program 31 from the ROM 14 and starts the operation according to the boot program 31. The CPU 6 issues a command to initialize the DRAM (1) 9 and the DRAM (2) 10. The DRAM controller 7 controls the DRAM address bus 17 and the DRAM control signal 18 to initialize the DRAM (1) 9 and the DRAM (2) 10 (step 2).

  When the initial setting is completed, the DRAM (1) 9 and the DRAM (2) 10 can be read / written. The CPU 6 copies the system program 32 from the ROM 14 to the program area of the DRAM (2) 10 (step 3). Thereafter, the CPU 6 operates the printer apparatus 1 by the system program 32 copied to the DRAM (2) 10 (step 4). As a result, the printer apparatus 1 is in a standby state until a print request is issued from the personal computer 5 (step 5).

  The subsequent steps will be described with reference to the flowchart of FIG. When the CPU 6 counts the time during the standby state and the specified time elapses (step 12), the CPU 6 issues a command to the DRAM controller 7 to set the DRAM (1) 9 to the self-refresh mode in order to shift to the power saving mode. The DRAM controller 7 controls the states of the DRAM control signal 18 and the chip selection signal (1) 19 to set the DRAM (1) 9 to the self-refresh mode, and sets the data processing unit 2 to the power saving mode (step 13).

  When the data processing unit 2 receives a print request from the personal computer 5 to the host interface unit 11 during the power saving mode, the host interface unit 11 generates an interrupt and notifies the CPU 6 of the print request (step 14). Receiving this, the CPU 6 issues a command to the DRAM controller 7 in order to shift the DRAM (1) 9 from the self-refresh mode to the idle state. The DRAM controller 7 controls the states of the DRAM control signal 18 and the chip selection signal (1) 19 to set the DRAM (1) 9 to the idle state (step 15).

  When the DRAM (1) 9 becomes accessible, the host interface unit 11 receives the image data and transmits the received image data to the DRAM controller 7. The DRAM controller 7 writes the image data in the respective data areas 36b of the DRAM (1) 9 and the DRAM (2) 10 (step 16). The CPU 6 performs image processing on the received data to generate raster data in the respective data areas 36b of the DRAM (1) 9 and DRAM (2) 10, and the mechanical control interface unit 12 converts the generated raster data into the mechanical unit 4. (Step 17).

  When a print request is generated from the personal computer 5 while the data processing unit 2 is in a standby state (step 11), the image data received via the host interface unit 11 is transmitted to the DRAM controller 7, and the DRAM controller 7 receives the DRAM (1). 9. Image data is written in each data area 36b of the DRAM (2) 10 (step 16). The CPU 6 performs image processing on the received data to generate raster data in the respective data areas 36b of the DRAM (1) 9 and DRAM (2) 10, and the mechanical control interface unit 12 converts the generated raster data into the mechanical unit 4. (Step 17).

  The DRAM controller 7 determines whether access to the DRAM (1) 9 and DRAM (2) 10 generated on the system bus 14 is access to the program area or data area. In the case of write access to the program area, 16-bit write data on the system bus 15 is converted into two 8-bit data and output to the upper 8 bits of the DRAM data bus [15: 0] 21 to the DRAM (2) 10 Write. At this time, write access also occurs in the DRAM (1) 9, but it is invalid data.

  In the case of read access to the program area, the DRAM controller 7 reads only the 8-bit data output from the DRAM (2) 10, converts the two read 8-bit data into 16-bit data, and sends it to the system bus 15. Output. At this time, data is also output from the DRAM (1) 9, but is discarded because it is invalid data.

  In the case of a write access to the data area, the DRAM controller 7 outputs the 16-bit write data of the system bus 15 to the DRAM data bus [15: 0] 21 as it is, and the DRAM (1) 9 and the DRAM (2) 10 Write to. In the case of read access to the data area, the DRAM controller 7 latches the data output from the DRAM (1) 9 and DRAM (2) 10 into the DRAM data bus [15: 0] 21 and transfers it to the system bus 15. Output.

  FIG. 8 is a block diagram showing the configuration of the DRAM controller. In FIG. 8, the DRAM controller 7 includes a data bus width determination unit 7a, an address command control unit 7b, and a data bus buffer 7c. The data bus width determination unit 7 a outputs the transmitted data to the upper bits of the DRAM data bus 21 or outputs all the bits of the DRAM data bus 21 according to a signal sent from the CPU 6 via the system bus 15. Determine whether. The address command control unit 7b outputs a DRAM address bus 17, a DRAM control signal 18, a chip selection signal (1) 19, and a chip selection signal (2) 20 in accordance with commands from the CPU 6.

Next, the operation when the CPU 6 performs write access to the program areas of the DRAM (1) 9 and the DRAM (2) 10 will be described in detail. FIG. 9 is a time chart showing a write access operation to the program area of the DRAM.
First, at clock 0 (clk0), the CPU 6 turns on the bus request signal S_REQ in order to acquire the right to use the system bus 15. The arbiter 22 turns on the bus grant signal S_GNT to grant the usage right to the CPU 6.

In the clock 1 (clk1), when the bus grant signal S_GNT is turned on, the CPU 6 outputs the address A0 to the address signal S_A, and turns on the address valid signal S_ASTB and the write signal S_WR for one cycle.
At clock 2 (clk2), the DRAM controller 7 latches and decodes the address signal S_A and the write signal S_WR, and recognizes that it is a write access to the program area. The CPU 6 outputs data D [15: 0] to the data signal S_D [15: 0] and turns on the data ready signal S_DRDY. The DRAM controller 7 turns on the data ACK signal S_DACK in order to receive data. The DRAM controller 7 turns on the chip selection signal (2) 20, outputs an activate command to the DRAM control signal 18, and outputs Row adr to the DRAM address bus 17.

In clock 3 (clk3), the CPU 6 turns off the data ready signal S_DRDY when the output of all data is completed. The DRAM controller 7 detects that the data ready signal S_DRDY is turned off, turns off the data ack signal S_DACK, and turns off the chip selection signal (2) 20. DRAM (2) 10 is in a ROW active state, and DRAM (1) 9 remains in an idle state.
In clock 4 (clk4), the DRAM controller 7 turns on the chip selection signal (2) 20, outputs a write command to the DRAM control signal 18, outputs colum adr0 to the DRAM address bus 17, and outputs the DRAM data bus [15 : The data D [15: 8] latched at 8] is output.

At clock 5 (clk5), data D [15: 8] is written into DRAM (2) 10. The DRAM controller 7 turns on the chip selection signal (2) 20, outputs a write command to the DRAM control signal 18, outputs colum adr1 to the DRAM address bus 17, and latches the data latched on the DRAM data bus [15: 8]. D [7: 0] is output.
At clock 6 (clk6), data D [7: 0] is written to DRAM (2) 10. The DRAM controller 7 turns off the chip selection signal (2) 20 and ends the access.

Next, the operation when the CPU 6 performs read access to the program areas of the DRAM (1) 9 and the DRAM (2) 10 will be described in detail with reference to FIG. FIG. 10 is a time chart showing the read access operation to the program area of the DRAM.
First, at clock 0 (clk0), the CPU 6 turns on the bus request signal S_REQ in order to acquire the right to use the system bus 15. The arbiter 22 turns on the bus grant signal S_GNT to grant the usage right to the CPU 6.
In the clock 1 (clk1), when the bus grant signal S_GNT is turned on, the CPU 6 outputs the address A0 to the address signal S_A, and turns on the address valid signal S_ASTB and the write signal S_WR for one cycle.

At clock 2 (clk2), the DRAM controller 7 latches and decodes the address signal S_A and the write signal S_WR, and recognizes that it is a read access to the program area. The CPU 6 turns on the data ready signal S_DRDY to receive data. The DRAM controller 7 turns on the chip selection signal (2) 20, outputs an activate command to the DRAM control signal 18, and outputs Row adr to the DRAM address bus 17.
In clock 3 (clk3), the DRAM controller 7 turns off the chip selection signal (2) 20. DRAM (2) 10 is in a ROW active state, and DRAM (1) 9 remains in an idle state.

At clock 4 (clk4), the DRAM controller 7 turns on the chip selection signal (2) 20, outputs a read command to the DRAM control signal 18, and outputs colum adr0 to the DRAM address bus 17.
At clock 5 (clk5), the DRAM controller 7 turns on the chip selection signal (2) 20, outputs a read command to the DRAM control signal 18, and outputs colum adr1 to the DRAM address bus 17.

At clock 6 (clk6), the DRAM (2) 10 outputs the data D [15: 8] stored in the Row adr and colum adr0 to the DRAM data bus [15: 8] 21. The DRAM controller 7 turns off the chip selection signal (2) 20.
At clock 7 (clk7), the DRAM controller 7 latches data D [15: 8]. The DRAM (2) 10 outputs the data D [7: 0] stored in the Row adr and colum adr1 to the DRAM data bus [15: 8] 21.
At clock 8 (clk8), the DRAM controller 7 latches data D [7: 0].

At clock 9 (clk9), the DRAM controller 7 outputs the latched data D [15: 0] to the data signal S_D [15: 0] of the system bus 15, and the data signal S_D [15: 0] is valid. In order to show that there is a data ACK signal S_DACK is turned on.
At the clock 10 (clk10), the CPU 6 detects that the data ACK signal S_DACK is turned on, latches the data D [15: 0] output to the data signal S_D [15: 0] of the system bus 15, and The ready signal S_DRDY is turned off. The DRAM controller 7 turns off the data ACK signal S_DACK and ends the access.

  In the case of write access and read access to the program area, the DRAM controller 7 doubles the address latched from the system bus 15 and outputs it to the DRAM (2) 10. Row adr, colum adr0, and colum adr1 output by the above clocks 2, 4, 5 (clk2, clk4, clk5) are addresses obtained by doubling address A0, and colum adr1 is colum adr0 + 1.

Next, the operation when the CPU 6 performs write access to the data areas of the DRAM (1) 9 and the DRAM (2) 10 will be described in detail with reference to FIG. FIG. 11 is a time chart showing a write access operation to the data area of the DRAM.
First, at clock 0 (clk0), the CPU 6 turns on the bus request signal S_REQ in order to acquire the right to use the system bus 15. The arbiter 22 turns on the bus grant signal S_GNT to grant the usage right to the CPU 6.
In the clock 1 (clk1), when the bus grant signal S_GNT is turned on, the CPU 6 outputs the address A0 to the address signal S_A, and turns on the address valid signal S_ASTB and the write signal S_WR for one cycle.

  At clock 2 (clk2), the DRAM controller 7 latches and decodes the address signal S_A and the write signal S_WR, and recognizes that it is a write access to the data area. The CPU 6 outputs data D [15: 0] to the data signal S_D [15: 0] and turns on the data ready signal S_DRDY. The DRAM controller 7 turns on the data ACK signal S_DACK in order to receive data. The DRAM controller 7 turns on the chip selection signal (1) 19 and the chip selection signal (2) 20, outputs an activate command to the DRAM control signal 18, and outputs Row adr to the DRAM address bus 17.

  In clock 3 (clk3), the CPU 6 turns off the data ready signal S_DRDY when the output of all data is completed. The DRAM controller 7 detects that the data ready signal S_DRDY is turned off, turns off the data ACK signal S_DACK, and turns off the chip selection signal (1) 19 and the chip selection signal (2) 20. Both the DRAM (1) 9 and the DRAM (2) 10 are in a ROW (low) active state.

At clock 4 (clk4), the DRAM controller 7 turns on the chip selection signal (1) 19 and the chip selection signal (2) 20, outputs a write command to the DRAM control signal 18, and sets a colum adr to the DRAM address bus 17. The data D [15: 0] latched on the DRAM data bus [15: 0] is output.
At clock 5 (clk5), data D [7: 0] is written to DRAM (1) 9, and data D [15: 8] is written to DRAM (2) 10. The DRAM controller 7 turns off the chip selection signal (1) 19 and the chip selection signal (2) 20 and ends the access.

  The difference between the write access to the program area and the write access to the data area is that the row adr and the colum adr are the same as the address signal S_A of the system bus 15 and the DRAM ( 1) 9 and DRAM (2) 10 are simultaneously accessed to perform 16-bit data access.

Next, the operation when the CPU 6 performs read access to the data areas of the DRAM (1) 9 and the DRAM (2) 10 will be described in detail with reference to FIG. FIG. 12 is a time chart showing a read access operation to the data area of the DRAM.
First, at clock 0 (clk0), the CPU 6 turns on the bus request signal S_REQ in order to acquire the right to use the system bus 15. The arbiter 22 turns on the bus grant signal S_GNT to grant the usage right to the CPU 6.
In the clock 1 (clk1), when the bus grant signal S_GNT is turned on, the CPU 6 outputs the address A0 to the address signal S_A, and turns on the address valid signal S_ASTB and the write signal S_WR for one cycle.

  At clock 2 (clk2), the DRAM controller 7 latches and decodes the address signal S_A and the write signal S_WR, and recognizes that it is a read access to the data area. The CPU 6 turns on the data ready signal S_DRDY to receive data. The DRAM controller 7 turns on the chip selection signal (1) 19 and the chip selection signal (2) 20, outputs an activate command to the DRAM control signal 18, and outputs Row adr to the DRAM address bus 17.

In clock 3 (clk3), the DRAM controller 7 turns off the chip selection signal (1) 19 and the chip selection signal (2) 20. Both the DRAM (1) 9 and the DRAM (2) 10 are in a ROW (low) active state.
In the clock 4 (clk4), the DRAM controller 7 turns on the chip selection signal (1) 19 and the chip selection signal (2) 20, outputs a read command to the DRAM control signal 18, and outputs a colum adr to the DRAM address bus 17. Output.
In clock 5 (clk5), the DRAM controller 7 turns off the chip selection signal (1) 19 and the chip selection signal (2) 20.

At clock 6 (clk6), DRAM (1) 9 and DRAM (2) 10 output data D [15: 8] stored in Row adr and colum adr to DRAM data bus [15: 8]. The DRAM (1) 9 outputs the data D [7: 0] stored in the Row adr and colum adr to the DRAM data bus [7: 0].
At clock 7 (clk7), the DRAM controller 7 latches data D [15: 0].

At clock 8 (clk8), the DRAM controller 7 outputs the latched data D [15: 0] to the data signal S_D [15: 0] of the system bus 15, and the data signal S_D [15: 0] is valid. In order to show that there is a data ACK signal S_DACK is turned on.
At the clock 9 (clk9), the CPU 6 detects that the data ACK signal S_DACK is turned on, latches the data D [15: 0] output to the data signal S_D [15: 0] of the system bus 15, and The ready signal S_DRDY is turned off. The DRAM controller 7 turns off the data ACK signal S_DACK and ends the access.

  The difference between the read access to the program area and the read access to the data area is that the row adr and the colum adr are the same as the address signal S_A of the system bus 15 and the DRAM ( 1) 9 and DRAM (2) 10 are simultaneously accessed to perform 16-bit data access.

  As described above, according to the first embodiment, the address area on the DRAM is mapped separately into the program area and the data area, and the DRAM storing the program area uses only a part of the DRAM constituting the data bus and is small. By accessing with the data bus width, the program can be operated on the DRAM even in the power saving mode, and the time required to recover from the power saving mode to the normal mode can be greatly shortened. In addition, a non-volatile memory for saving programs is not necessary, and cost reduction can be realized.

  Next, Example 2 will be described. In the second embodiment, the program area is divided into a program area for interrupt processing and a program area other than for interrupt processing, and only the program area for interrupt processing is stored in only some DRAMs as in the first embodiment. As in the data area, the program area uses all DRAMs to improve the data processing speed.

  The configuration of the second embodiment differs from the configuration of the first embodiment in CPU address mapping and program configuration. FIG. 13 is an explanatory diagram illustrating mapping of the CPU onto the address space in the second embodiment. In FIG. 13, the address space of the CPU 6 is divided and mapped into a DRAM area 43, a ROM area 44, and an IO area 45. The DRAM area 43 is further divided into an interrupt processing area 43a, a program area 43b, and a data area 43c. The interrupt processing area 43a is a program area for performing interrupt processing and a work area necessary for interrupt processing. The program area 43b includes a program area excluding the interrupt processing program and a work area necessary for the processing.

  The interrupt processing area 43a maps from address 0x0 to address 0x2 ^ m, the program area 43b maps from address 0x2 ^ m * 2 to address 0x2 ^ p-1, and the data area 43c maps to address 0x2 ^ p or higher. . Further, the address 0x2 ^ m to the address 0x2 ^ m * 2-1 is an unusable area 43d.

  A program necessary for normal data processing is stored in the program area 43b. Generally, the program capacity is large, and a large amount of access occurs during data processing. Generally, the program in the interrupt processing area 43a is small and the access frequency is low.

  FIG. 14 is an explanatory diagram showing mapping to the DRAM area constituted by the DRAM (1) 9 and the DRAM (2) 10 in the second embodiment. In FIG. 14, addresses 0x0 to 0x2 ^ m * 2-1 are mapped to the interrupt processing area 46a, addresses 0x2 ^ m * 2 to address 0x2 ^ p-1 are mapped to the program area 46b, and address 0x2 ^ The data area 46c is mapped to p or more. The odd address in the area from address 0x0 to address 0x2 ^ m * 2-1 is the unusable area 46d.

  The operation of the second embodiment configured as described above is different from the operation of the first embodiment in the following points. That is, in the first embodiment, when accessing the program area, the DRAM controller 7 accesses using only the [15: 8] bits of the DRAM data bus 21, but in the second embodiment, only in the interrupt processing area. Access is made using only the [15: 8] bits of the DRAM data bus 21, and access to the program area and data area uses all the bit signals [15: 0] bits of the DRAM data bus 21. Therefore, high speed access is possible.

  As described above, according to the second embodiment, the interrupt processing program and the data processing program are divided to map addresses, and the data processing program is accessed at high speed using the entire data bus width. Since access is performed using a part of the data width, it is possible to achieve both high-speed data processing and a power saving mode.

  As described above, in each of the above embodiments, the DDR SDRAM is used as the DRAM. However, the present invention is not limited to this, and a DDR2 SDRAM may be used. Although the DRAM data bus 17 has been described as having 16 bits, the program area is operated on one DRAM using 64 bits and 8 bits of data signals of 8 bits or 4 16 bits of DRAM. You may do it.

  In the above-described embodiments, the printer apparatus is described as an example of the data processing apparatus. However, the present invention can be applied to other electronic devices that operate by storing a program on a DRAM. In particular, it is suitable for electronic devices that require constant energization, such as facsimile machines and multi-function printers.

DESCRIPTION OF SYMBOLS 1 Printer apparatus 2 Data processing part 6 CPU
7 DRAM controller 9 DRAM (1)
10 DRAM (2)
14 ROM
19, 20 Chip selection signal 22 DRAM data bus

Claims (5)

In a data processing apparatus that develops and executes program information stored in a nonvolatile memory in a volatile memory,
A plurality of the volatile memories;
The plurality of volatile memories include a first volatile memory in which only the data is expanded without expanding the program information stored in the nonvolatile memory, and the program information is expanded and the data is expanded. A second volatile memory
A data processing apparatus comprising a control unit that accesses the program information of the second volatile memory with a small data bus width and accesses the data with a large data width. . The data processing apparatus according to claim 1, wherein the control unit sets the first volatile memory to a power saving mode. The first volatile memory and the second volatile memory constitute at least one data bus, and a part of the data bus is used when accessing the program information of the second volatile memory. 3. The data processing apparatus according to claim 1, wherein when the data is accessed, the data is accessed using the entire data bus. 4. The data processing apparatus according to claim 1, wherein the program information developed in the second volatile memory is program information for interrupt processing. The data processing apparatus according to claim 1, wherein the volatile memory is configured by a DRAM.

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