JP4633078B2 - Color image processing apparatus and image memory access control method - Google Patents

Description

  The present invention relates to a color image processing apparatus used for a digital color copying machine, a printer, and the like, and more particularly to an access control method for an image memory for storing color image data.

  A conventional image memory access method will be described by taking a tandem printer engine used in a digital color copier or a color printer as an example.

  FIG. 1 is a schematic block diagram showing the configuration of a general color copying machine using a tandem color laser printer engine. Here, four colors C (cyan), M (magenta), Y (yellow), and K (black) are used as color data.

  Image formation comprising an image writing unit 111 (C to K), a transfer drum 121 (C to K), an image developing unit 131 (C to K), and a primary transfer unit 141 (C to K) for each color of CMYK The devices are arranged at regular intervals. The image writing unit 111 (C to K) writes a corresponding color image electrostatic latent image on the transfer drum 121 (C to K), and the image developing unit 131 (C to K) outputs the electrostatic latent image to the toner. By developing, a colored toner image is formed on the transfer drum 121 (C to K). The colored toner images are transferred to the intermediate transfer belt 151 in sequence by the primary transfer unit 141 (C to K), and one color (CMYK) image is synthesized.

  The recording paper is supplied to the position of the secondary transfer unit 153 through the paper feed path 152, and between the intermediate transfer belt 151 and the secondary transfer unit 153 in synchronization with the color toner image synthesized on the intermediate transfer belt 151. By passing, the color toner image is transferred again to the recording paper by the secondary transfer unit 153. The transferred color toner image is fixed on the recording paper by melting the toner by heat in the fixing unit 154, and the recording paper on which the color image is recorded is discharged to the paper discharge unit 155.

  The image on the original is read by a reading unit 156 which is a so-called color scanner, and the read image signal 157 is subjected to image processing by the controller 158 to generate image writing signals 202 to 205 corresponding to each of CMYK. Supplied to writing units 111 (C to K). At this time, in the system in which toner development is performed for each color, the positions of the transfer drums 121 (C to K) corresponding to the four colors must be shifted, and therefore the image writing unit 111 (C to K). The image writing signals 202 to 205 supplied to () must also be output with a time shift with respect to one image.

  FIG. 2 is a time chart schematically showing a temporal shift of the image writing signals 202 to 205 corresponding to the colors of CMYK. Here, the image write signals 202 to 205 for the respective colors are sequentially output with a time shift with the write start signal 201 as a reference.

  In this case, at the time corresponding to point A 210 in FIG. 2, the image writing signal 202 corresponding to cyan (C) is near the rear end of the image, and the image writing signal 203 corresponding to magenta (M) is the image. The image writing signal 204 corresponding to yellow (Y) is slightly closer to the rear end than the center, and the image writing signal 205 corresponding to black (K) is from the leading end of the image. Need to be output. In order to output at such different timings, it is necessary to once write CMYK images in the image memory and read them with a necessary time difference. That is, it is necessary to read out the CMYK density values corresponding to four locations from one page image.

  As a method of efficiently realizing such access to the image memory, (1) a method of preparing separate image memories corresponding to each of CMYK and realizing simultaneous access, and (2) a read image signal of CMYK. Can be stored in a FIFO memory or the like and then output sequentially. Of these methods, the method (1) of preparing separate image memories allows easy simultaneous access. However, the physical increase of the number of memory chips, the number of LSI terminals related to the memory interface, etc. There is also a problem that general restrictions become stronger and lead to cost increase.

  On the other hand, in the method (2) of temporarily storing in the FIFO memory or the like, physical restrictions are eased, but it is necessary to devise an access method. In particular, when a synchronous DRAM (Dynamic Random Access Memory) is used for the image memory, there are some problems to be solved in terms of operation speed. Hereinafter, a DDR-SDRAM (Double Data Rate-Synchronous DRAM) will be described as an example.

  FIG. 3 is a time chart showing the read operation of the DDR-SDRAM. As shown in FIG. 3, a series of read operations called “activation-read-precharge” is performed for one color, but the time 301 required for this operation is not short. For this reason, it is necessary to take measures to increase the speed of the output image signal. In general, a method of reducing the rate of activation / precharge time by burst access as described below (see, for example, Patent Documents 1 and 2).

  FIG. 4 is a time chart showing a batch read operation by a burst read command of the DDR-SDRAM. As shown in FIG. 4, batch reading is performed by a burst read command, and the amount of data to be read or written at a time is increased, thereby reducing the ratio of the activation / precharge time as a whole and increasing the speed.

JP 2002-117397 A JP 2002-29105 A Japanese Patent Laid-Open No. 10-294856

  However, since the burst access method performs burst access for each color, the color can be read at high speed. However, since the access time for the other three colors also performs the burst operation, eventually one color is obtained. When attention is paid, the maximum value of the data read time interval becomes large. In burst access, since it is necessary to pack a large amount of data in the FIFO memory, the size of the FIFO memory increases, resulting in an increase in LSI cost.

  Furthermore, as in Patent Literature 3, when memory mapping of the image memory is performed in a special format for editing such as rotation processing of image data, and sequential access of the image in a direction different from the scanning line direction is necessary, Most accesses do not have the same column address. That is, random access with a small amount of data is required. When performing such image editing, it is not possible to increase the efficiency in burst access.

  An object of the present invention is to provide a color image processing apparatus and an image memory access control method capable of improving the reading efficiency of color data without increasing the device amount.

  According to the present invention, when color image data is stored in the synchronous DRAM, each color is assigned to each bank of the synchronous DRAM, and one color = 1 bank. By concealing the activation / precharge time when accessing the image data of each color simultaneously, the access efficiency to the image memory can be improved.

A color image processing apparatus according to the present invention includes a synchronous DRAM (Dynamic Random Access Memory) having a plurality of banks therein and having a predetermined memory access unit, and one color image in each bank of the synchronous DRAM. Assign the color components, it has a, and a control unit for reading / writing control of the image data of each color component for said synchronous DRAM, wherein, with respect to the specified address for said synchronous DRAM, the plurality of banks The activation command is issued while sequentially shifting each bank in units of one clock, and subsequently, the read / write command is issued while sequentially shifting the plurality of banks in units of one clock for each bank . Furthermore, random access to unrelated areas of a plurality of banks is also possible .

According to one embodiment of the present invention, cyan (C) and magenta of the printer engine for each bank of a synchronous DRAM (including SDRAM, DDR-SDRAM, DDR2-SDRAM, etc.) having four banks therein. Image memories corresponding to four colors (M), yellow (Y), and black (K) are allocated , and the plurality of banks are sequentially shifted by one clock unit for each bank with respect to a designated address for the synchronous DRAM. Issuing an activation command, and then issuing a read / write command while sequentially shifting the plurality of banks for each bank in units of one clock unit, so that different image parts of CMYK can be obtained using one synchronous DRAM interface. Corresponding image memory access can be performed efficiently.

  According to the present invention, when color image data is stored in a synchronous DRAM, each color is assigned to each bank of the synchronous DRAM, so that one color = 1 bank, thereby simultaneously accessing the image data of each color. The activation / precharge time can be concealed, and the access efficiency to the image memory can be improved.

  In particular, in order to take advantage of the feature that each bank of the SDRAM including four banks can operate independently, when storing CMYK image data in the SDRAM, each color of CMYK is assigned to each bank of the SDRAM. = 1 bank. The access efficiency to the image memory is improved by concealing the activation / precharge time when simultaneously accessing image data for four colors of CMYK.

  Further, when the memory mapping of the synchronous DRAM is performed in a special format in order to perform image rotation processing or the like, it is possible to suppress a decrease in the bus usage rate even for random access with a small amount of data.

  First, a color copying machine to which the color image processing apparatus according to the present invention can be applied will be briefly described, and an embodiment of the present invention will be described in detail using the color copying machine as an example.

  FIG. 5 is a block diagram showing a schematic configuration of an image processing system of a typical digital color copying machine. A reading unit 501 mounted on a digital color copying machine reads a document to be copied by a sensor array including a photoelectric conversion device such as a CCD, and outputs analog signals corresponding to the three primary colors of RGB using an A / D converter or the like. The signal is converted into a signal (for example, 8 bits) and output to the read image processing unit 502 as an RGB image signal. The read image processing unit 502 performs correction processing (for example, density adjustment and image enlargement / reduction) on the RGB image signal. The corrected RGB image signal is compressed by JPEG or the like as necessary by the image management unit 503 and temporarily stored in the image storage unit 504. The image storage unit 504 is a writable / readable recording medium such as a hard disk or a semiconductor memory.

  When the read image is printed, the image management unit 503 reads the RGB image signal accumulated in the image storage unit 504 (or restores the original format if compression has been performed), and performs recorded image processing. Output to the unit 505. The recorded image processing unit 505 converts the RGB image signal into cyan, magenta, yellow, and black (CMYK) signals corresponding to the recording characteristics of the printer, and adjusts the image characteristics according to structural constraints. Editing such as output timing adjustment (see FIG. 2) is performed, and the CMYK image signal thus obtained is output to the printer unit 506.

  As described with reference to FIG. 1, the printer unit 506 includes CMYK color image forming units, and prints color toner images on the intermediate transfer belt 151 based on the CMYK image signals 202 to 205 input from the recording image processing unit 505. After being formed and re-transferred to the recording paper by the secondary transfer unit 153, the recording paper on which the image is thermally fixed is discharged to the paper discharge unit 155.

1. Embodiment FIG. 6 is a block diagram showing a schematic configuration of a recording image processing unit of the color copying machine shown in FIG. 5 to which an embodiment of a color image processing apparatus according to the present invention is applied. The recorded image processing unit 505 converts the RGB image signal into an image signal in the color space CMYK used in the printer by the color space conversion unit 601. The CMYK image signal is output to the image editing control unit 603 after the image processing unit 602 performs correction of the γ characteristic in accordance with the characteristics of the printer engine, conversion processing to a screen pattern, and the like.

  The image editing control unit 603 writes the input CMYK image signal to the image memory 604 while holding the image image, and conforms to the structural constraints as described with reference to FIG. 2 according to the request from the printer unit 506. The image output timing is adjusted and a plurality of images are combined, and the result is output to the printer unit 506.

  The image memory 604 used in the present embodiment is a synchronous DRAM having four banks 0-3 inside. The term “synchronous DRAM” here is a concept including SDRAM, DDR-SDRAM, DDR2-SDRAM and the like. As is well known, the synchronous RAM has a plurality of banks including an address decoder, a memory cell array, and a sense amplifier, and each bank can be controlled independently. In the present embodiment, image memories corresponding to four colors of cyan (C), magenta (M), yellow (Y), and black (K) of the printer engine are allocated to four banks in the synchronous DRAM. . In other words, one color is assigned to one bank. Since each bank can be controlled independently, it is possible to flexibly access different image portions of the image data of each color, and activation / precharge is performed when simultaneously accessing the image data for four colors of CMYK. Since time can be concealed, efficient access is possible.

  The image editing control unit 603 can also be realized by software by executing an image editing control program having a function as described in detail below on the program control processor.

  Next, a more detailed configuration and operation of the image editing control unit 603 using DDR-SDRAM as the image memory 604 will be described with reference to FIGS. 7 to 18 and FIGS. 19 to 20.

2. First Embodiment FIG. 7 is a more detailed block diagram of an image editing control unit using a color image processing apparatus according to a first embodiment of the present invention. The image editing control unit 603 includes CMYK image write control units 701 to 704 that generate a write request to the image memory 604 that is a DDR-SDRAM, and CMYK image read control that generates a read request from the image memory 604. Parts 705 to 708. The data writing control unit 709 performs data writing control to the image memory 604 based on each CMYK writing request. The data read control unit 711 performs data read control from the image memory 604 based on a read request from each CMYK. A refresh control unit 714 refreshes the image memory 604. The operations of the data write control unit 709, the data read control unit 711, and the refresh control unit 714 are arbitrated by the arbitration circuit 710. The selector 712 selects the SDRAM control from the data write control unit 709, the data read control unit 711, and the refresh control unit 714 according to the selection signal from the arbitration circuit 710, and outputs it to the SDRAM interface 713.

  Next, in order to explain the operation of this embodiment, the structure of image data in the image memory 604 will be described first.

2.1) Image Data in Image Memory 604 FIG. 8 is a diagram schematically showing image data stored in the image memory 604, and FIG. 9 is a diagram schematically showing an address configuration of the image memory.

  As shown in FIG. 8, the X-axis increasing direction of the image image is the main scanning direction, the Y-axis increasing direction is the sub-scanning direction, and the image data of one pixel per CMYK color is expressed by a 4-bit density value. To do. Further, the density value of the x-th pixel in the main scanning direction in the y-th line in the sub-scanning direction of the image is expressed in the form of “color (x, y)”. For example, the density value of the upper left corner image of the cyan (C) image plane is “C (0, 0)”, and the density value of the first image in the main scanning direction from the upper left corner of the magenta (M) image plane is “ The density value of the image at the left corner of the first line in the sub-scanning direction of the image plane of M (1, 0) ”and yellow (Y) is expressed as“ Y (0, 1) ”. In the image writing / reading control to be described later, the same control is performed for CMYK four colors, and therefore cyan (C) will be described as a representative example.

  Further, it is assumed that the input image is sequentially input from the top pixel in units of one line. That is, taking cyan as an example, C (0,0), C (1,0), C (2,0), C (3,0) ... C (Xm-1,0); C (0, 1), C (1,1), C (2,1), C (3,1) ... C (Xm-1,1); C (0,2), C (1,2) ...; ..., C (0, Ym-1), C (1, Ym-1)... C (Xm-1, Ym-1), are input for each line. The same applies to other colors. Here, Xm and Ym are the number of pixels in the main scanning direction and the sub-scanning direction of the image, and Xm is a multiple of 16 to simplify the description.

  Also, as shown in FIG. 9, the image memory 604 has a word length of 32 bits, and the images in the image memory 604 are stored in the order of input images in order of 32 bits starting from the youngest address in the designated area of the memory. The address notation is in units of 8 bits, that is, in bytes. Therefore, the address in word length units is 4 skips.

2.2) Image Write Control Unit FIG. 10A is a schematic block diagram for explaining the operation of the image write control unit in FIG. 7, and FIG. 10B is a format diagram of a series of write commands. It is. Hereinafter, the cyan image writing control unit 701 will be described as an example, but the same applies to other colors.

  The 4-bit image data input to the image writing control unit 701 is temporarily stored in an input buffer 1001 configured with a FIFO memory, and time adjustment with the command generation unit 1004 at the next stage is performed. When receiving the RDY signal indicating that the command generation unit 1004 at the next stage is ready, the input buffer 1001 outputs image data for one pixel to the command generation unit 1004.

The coordinate management unit 1002 manages the next image writing coordinates and transmits the writing coordinates to the address conversion unit 1003. The address conversion unit 1003 calculates the next image writing address on the image memory 604 from the next image writing coordinates. Here, from the relationship between the image write address and the coordinates defined in FIGS. 8 and 9, the next image write address is calculated by the following equation:
Image writing address Address = TOP + Y × (Xm / 16) × 2 + X / 2.

  Here, TOP is the start address of the image memory area to be written (that is, the address at which C (0,0) is written), X and Y are the positions of the next image writing coordinates in the main scanning direction and sub-scanning direction, respectively, Xm Is the number of pixels in the main scanning direction of the image to be written. Actually, instead of managing the coordinates, as described in Patent Document 3, by specifying the address and the increment of the address, the coordinate management unit 1002 and the address conversion unit 1003 are integrated to manage the address. It can also be implemented as a part.

  The command generation unit 1004 takes the image data for 16 pixels from the input buffer 1001 and combines it with the next image write address from the address conversion unit 1003 to write to a series of image memories 604 as shown in FIG. A command is generated and output to the command FIFO unit 1005. The operation so far is performed for each color of CMYK.

2.3) Data Write Control Unit FIG. 11 is a schematic block diagram for explaining the operation of the data write control unit in FIG. When a data presence / absence signal is input from the command FIFO unit 1005 (reference numbers 1201 to 1204 in FIG. 11) of the CMYK image write control units 701 to 704, the sequencer 1207 outputs a request signal REQ to the arbitration circuit 710. . When the access right to the SDRAM 604 is acquired from the arbitration circuit 710, the response signal ACK becomes valid, and a write sequence to the SDRAM 604 is generated using the head data of the command FIFO units 1201-1120.

  The arbitration circuit 710 holds that the current SDRAM access right is in the data write control unit 709, and outputs an address / control signal from the data write control unit 709 to the DDR-SDRAM interface unit 713 to the selector 712. To do.

  FIG. 12 is a timing chart showing the data write operation of this embodiment. Here, it is assumed that there is valid data at the head of all the CMYK command FIFO units 1201 to 1204, and the case of continuous writing will be described.

  First, symbols in the timing chart of FIG. 12 will be described. The numerical values of clocks 1 to 20 in the upper part of FIG. 12 are clock numbers given to the SDRAM 604. “Target color” indicates to which color of CMYK the command issued to the SDRAM 604 corresponds. “Bank address” indicates a bank address when an Activate command is issued to the SDRAM 604. “RA” is a RowAddress given to the SDRAM 604, and the address corresponding to which color of CMYK is described in parentheses. “CA” is a ColumnAddress given to the SDRAM 604, and the address corresponding to which color of CMYK is described in parentheses. “ACT” indicates an Activate command given to the SDRAM 604. “WRA” indicates a write command with auto precharge given to the SDRAM 604. For each command, refer to specifications and explanations of general SDRAM and DDR-SDRAM.

  In FIG. 12, at clock 1, the address selector 1205 first selects and outputs the bank address 00 and RowAddress corresponding to cyan C from the command FIFO 1201 as addresses to the SDRAM 604, and simultaneously outputs the ACT command. The output bank address, RowAddress, and ACT command are output to the DDR-SDRAM as the image memory 604 through the selector 712 and the DDR-SDRAM interface 713 shown in FIG.

  Similarly, in clocks 2, 3, and 4, the address selector 1205 displays the bank addresses 01, 10, and 11 corresponding to M (magenta), Y (yellow), and K (black) and RowAddress corresponding to M, Y, and K. Are selected from the color command FIFOs 1202 to 1204 and output as addresses to the SDRAM 604, and at the same time, an ACT command is output.

At the time of clock 5, since a period corresponding to t _RCD has elapsed since the ACT command for bank address 00 output at clock 1, a new command for bank 00 can be issued. Therefore, the address selector 1205 selects and outputs the ColumnAddress corresponding to cyan C from the cyan command FIFO unit 1201 at the time of clock 5, and simultaneously outputs the WRA command. Data is selected and output from the C (cyan) command FIFO unit 1201 at the timing corresponding to the WRA command. Similarly, the ColumnAddress and the WRA command corresponding to M, Y, and K are output at the timing of the clocks 6 to 8, and the data is selected and output from the command FIFO units 1202 to 1204 at the timing corresponding to each WRA command. .

Since t _WR and t _RP for the WRA command at clock 5 have passed at the timing of clock 12, data writing corresponding to the next command FIFO portion of each CMYK is started. The sequence is the same as that of clock 1.

2.4) Image Reading Control Unit FIG. 13 is a schematic block diagram for explaining the operation of the image reading control unit in FIG. Hereinafter, the cyan image reading control unit 705 will be described as an example, but the same applies to other colors.

The coordinate management unit 1402 manages the next image readout coordinate and transmits the readout coordinate to the address conversion unit 1403. The address conversion unit 1403 calculates an image read address on the next image memory from the next image read coordinate. Here, from the relationship between the image readout address and the coordinates defined in FIGS. 8 and 9, the next image readout address is calculated by the following equation:
Image readout address Address = TOP + Y × (Xm / 16) × 2 + X / 2
Where TOP is the start address of the image memory area to be read (that is, the address to read C (0,0)), and X and Y are the positions of the next image readout coordinates in the main scanning direction and sub-scanning direction, respectively. , Xm is the number of pixels in the main scanning direction of the image to be read.

  The command generation unit 1404 receives the FIFO empty status (indicating whether sufficient data can be received) of the output buffer 1401 composed of FIFO, and if there is sufficient free space in the output buffer 1401, the next command from the address conversion unit 1403 Using the image read address, a read command from the image memory 604 is generated and transmitted to the command FIFO unit 1405.

2.5) Data Read Control Unit FIG. 14 is a schematic block diagram for explaining the operation of the data read control unit in FIG. When data presence / absence signals are input from command FIFO units 1405 (reference numbers 1501 to 1504 in FIG. 14) of the CMYK image read control units 705 to 708, the sequencer 1506 outputs a request signal REQ to the arbitration circuit 710. . When the access right to the SDRAM 604 is acquired from the arbitration circuit 710, the response signal ACK becomes valid, and a read sequence from the SDRAM 604 is generated using the top data of the command FIFO units 1501-1504.

  FIG. 15 is a timing chart showing the data read operation of this embodiment. Here, it is assumed that there is valid data at the head of all the CMYK command FIFO units 1501 to 1504, and the case of continuous writing will be described.

  First, symbols in FIG. 15 will be described. “Target color” indicates to which color of CMYK the command issued to the SDRAM 604 corresponds. “Bank address” indicates a bank address when an Activate command is issued to the SDRAM 604. “RA” is a RowAddress given to the SDRAM 604, and the address corresponding to which color of CMYK is described in parentheses. “CA” is a ColumnAddress given to the SDRAM 604, and the address corresponding to which color of CMYK is described in parentheses. “ACT” indicates an Activate command given to the SDRAM 604. “RDA” indicates a read command with auto precharge given to the SDRAM 604.

  In clock 1, the address selector 1505 first selects and outputs the bank address 00 and RowAddress corresponding to C (cyan) from the command FIFO unit 1501 as addresses to the SDRAM 604, and simultaneously outputs the ACT command. The output bank address, RowAddress, and ACT command are output to the DDR-SDRAM as the image memory 604 through the selector 712 and the DDR-SDRAM interface 713 shown in FIG.

  Subsequently, the address selector 1505 applies the bank addresses 01, 10, 11 and M, Y, K corresponding to M (magenta), Y (yellow), and K (black), respectively, with clocks 2, 3, and 4. The corresponding RowAddress is selected from the command FIFO unit for each color and output as an address to the SDRAM 604, and at the same time, the ACT command is output.

Since a period corresponding to t _RCD has elapsed since the ACT command for the bank address 00 output at the clock 1 at the time of the clock 5, a new command for the bank 00 can be issued. At the time of clock 5, the address selector 1505 selects and outputs ColumnAddress corresponding to cyan C from the command FIFO unit 1501, and simultaneously outputs the RDA command. Data read from the SDRAM 604 is output to the cyan output buffer 1401 at a timing corresponding to the RDA command.

  Similarly, ColumnAddress and RDA commands corresponding to M, Y, and K are output at timings of clocks 6 to 8, and data read from SDRAM 604 is output to output buffers 1401 for each color at timings corresponding to RDA commands. .

Since t _RP for the RDA command in clock 5 elapses at the timing of clock 12, reading of data corresponding to the next command FIFO section of each CMYK is started. The sequence is the same as that of clock 1.

  Note that valid data is not always included at the beginning of all CMYK command FIFOs. As shown in FIGS. 16 and 17, if there is a command FIFO without valid data, the command is not issued corresponding to that color.

  FIG. 16 is a timing chart showing a data read operation when there is valid data only in the CMK command FIFO, and FIG. 17 is a timing chart showing a data write operation when there is valid data only in the CMK command FIFO. . Thus, when only CMK command FIFO has valid data, the command corresponding to Y is not issued.

  FIG. 18 is a timing chart showing another example of the data read / write operation in this embodiment. In this example, a read operation corresponding to each of CMYK by clocks 1 to 11, a write operation corresponding to each of CMYK by clocks 12 to 22, a read operation corresponding to each of CMYK by clocks 23 to 33, a clock of 34 to The write operation corresponding to each of the second CMYK is performed. The same applies hereinafter.

2.6) Effects As described above, according to the first embodiment of the present invention, image data can be input or output simultaneously to each of the four banks with respect to the SDRAM 604 in one chip, and the same amount. When the data is input / output, the cycle can be shortened. Therefore, the image input / output speed can be improved, and therefore the size of the image input / output buffer can be reduced. This is because by assigning one color to each of the four banks of the SDRAM, it is possible to schedule image writing / data writing control and image reading / data reading control so as to access the four banks in parallel. .

  For example, when only reading an image, if this method is not used, the access described with reference to FIG. 3 is required, and 10 clocks are required for each color, and CMYK four-color simultaneous access occurs. The cycle of reading the (cyan) image from the image memory is 40 clocks.

  On the other hand, when the access method according to the present embodiment is adopted, as shown in FIG. 15, the cycle of reading the C (cyan) image from the image memory is 12 clocks. Therefore, the average data reading speed when memory access is 32 bits per word and 2-burst access is 64 bits / 40 clocks = 1.6 bits / clock when the access method according to this embodiment is not used. In the case of using the method, 64 bits / 12 clocks = about 5.3 bits / clock, and the average speed can be improved three times or more.

  If the conventional burst access is used to improve the speed without adopting this method, for example, when one access is expanded to 8 words as shown in FIG. 4, simultaneous access of CMYK four colors occurs. Then, the read cycle of the C (cyan) image from the image memory is 13 × 4 colors = 52 clocks per color. Therefore, the average data reading speed is 256 bits / 52 clocks = about 4.9 bits / clock, and the same speed can be obtained, but the size of the image input / output buffer that can send and receive 256 bits of data at a time. Is required. In the case of the access method according to the present embodiment, the average data reading speed of about the same level can be obtained with 64 bits of data exchange once.

  In particular, in the present invention, since data access is performed in small units, it is particularly effective when random access is performed instead of continuous address access to each of the four areas.

3. Second Embodiment Next, as a second embodiment of the present invention, an example in which the present invention is applied to the image rotation processing described in Patent Document 3 will be described.

  The image data rotation processing apparatus described in Patent Document 3 uses an image memory capable of storing n × n pixel data, and divides the image in the image memory into units of k pixels × k lines and accesses the memory access After assigning to the unit, the image of k pixels × k lines in the image memory is read out, and the area of k pixels × 1 line or 1 pixel × k lines is replaced and written back to the image memory. The image rotation processing is realized with this. In Patent Document 3, a monochrome image rotation process is targeted, but this can be applied to a color image rotation process composed of CMYK.

3.1) Image Rotation Processing Unit FIG. 19 is a detailed block diagram of an image rotation processing apparatus using a color image processing apparatus according to the second embodiment of the present invention. In this embodiment, as in the first embodiment, when storing CMYK image data in the SDRAM image memory 604, each color of CMYK is assigned to each bank of the SDRAM, and access control is performed with 1 color = 1 bank. . Further, blocks having the same basic functions as those of the first embodiment shown in FIG. 7 are denoted by the same reference numerals, and detailed description thereof is omitted.

  Note that the image rotation processing units 1601 to 1604 that perform image rotation processing on CMYK image data have the same block configuration, and thus the configuration and operation of the cyan (C) image rotation processing unit 1601 are used as representative examples. explain.

  In FIG. 19, an image rotation processing unit 1601 has an input unit 1701, an area selection control unit 1702, and an output unit 1703. When input image data is input every k pixels through the input unit 1701, the area selection control unit 1702 Each pixel data of the input image data is stored in the area of the selected image memory 604. Also, the rotated image data is read from the area of the image memory 604 selected by the area selection control unit 1702 and output for every k pixels through the output unit 1703.

  The operation control unit 1705 supplies rotation mode data, which is information on the size of the original image data and the angle to be rotated, to the area selection control unit 1702 and the address control unit 1707, and line information serving as a count-up start command to the line counter 1706. Supply. Based on the line information from the operation control unit 1705, the line counter 1706 designates the pixel of the k-th line designated in the image data of the page to be rotated and counts the pixels. The value is output to the area selection control unit 1702 and the address control unit 1707.

  The address control unit 1707 is based on various information such as rotation mode data input from the operation control unit 1705, the page counter 1704, and the line counter 1706, and is set in advance according to the size and rotation angle of the original image data. Is selected, and the address data of the image memory 604 to read / write the pixel is updated in accordance with the selected control procedure, and supplied to the data write control unit 709 or the data read control unit 711.

  The area selection control unit 1702 is read from the area of the image memory 604 designated by the address data based on various information such as rotation mode data input from the operation control unit 1705, the page counter 1704, and the line counter 1706. Among the k pixels, k pixels that should constitute the output image data are extracted from the selected k areas, and the k pixels are output as output image data to the output unit 1703 and input from the input unit 1701. The input image data of k pixels is written in the same area at the same selected address.

  As described above, the image rotation processing units 1601 to 1604 read the image of k pixels × k lines in the image memory 604 and replace the area of k pixels × 1 line or 1 pixel × k lines of the image memory 604. By performing the process of writing back to, a rotation process is executed for each of the CMYK images.

  Further, the image memory access from the address control unit 1707 and the area selection control unit 1702 of each CMYK is individually arranged for the CMYK by the data read control unit 711 and the data write control unit 709 once organized. Such access can be realized without preparing an image memory.

  FIG. 20 is a timing chart showing the operation of the second embodiment of the present invention. First, symbols in FIG. 20 will be described. “Target color” indicates to which color of CMYK the command issued to the SDRAM corresponds. “Bank address” indicates a bank address when an Activate command is issued to the SDRAM. “RA” is a RowAddress given to the SDRAM and indicates which color of CMYK corresponds to the address in parentheses. “CA” is a ColumnAddress given to the SDRAM, and indicates the color corresponding to CMYK in parentheses. “ACT” represents an Activate command given to the SDRAM, and “RD” represents a Read command given to the SDRAM. “WRA” indicates a write command with auto precharge given to the SDRAM. In FIG. 20, the image rotation processing for each of CMYK is described as being operated, but may be operating separately, or some of them may not be operating. When some of them are not operating, the operation of some commands is suppressed as shown in FIGS.

  In FIG. 19, the data read control unit 711 and the data write control unit 709 execute the control described in the first embodiment with respect to the access request address output from each of the CMYK address control units 1707. However, since reading and writing are executed at the same address, each of CMYK reads data in parallel with clocks 1 to 11 as shown in FIG. 20, and the data read with clocks 1, 5, and 8 is converted to C ( Cyan) area selection controller 1702 reads data read with clocks 2, 6, and 9 into M (magenta) area selection controller 1702 and reads data read with clocks 3, 7, and 10 to Y ( The data read by the clocks 4, 8, and 11 are transferred to the K (black) area selection control unit 1702, respectively. After the necessary bits are rewritten by the area selection control unit 1702, writing back to the same address is performed with the clocks 12-16. Since it is a write-back to the same address, the read command issued at clocks 5-8 can be a read command without precharge, and the WRA command at clocks 12-15 can be issued without issuing the next ACT command. it can.

3.2) Effect According to the second embodiment of the present invention, the image in the image memory is divided into units of k pixels × k lines and assigned to the unit of one access of the memory, An image rotation process is realized by reading an image of k pixels × k lines, replacing the area of k pixels × 1 line, or 1 pixel × k lines, and writing it back to the image memory. With the access method according to the present invention, random access to the image memory can be efficiently performed in smaller units. For example, on the premise of a binary image, comparing the case of random access in units of 64 bits as in the access method of the present embodiment and the case of random access in units of 256 bits shown in FIG. In the case of random access, since 64 = 8 × 8, it is possible to handle 8 pixels in 12 clocks, that is, about 0.66 pixels / 1 clock, whereas in the past, since 256 = 16 × 16, 52 The clock can only handle 16 pixels, ie about 0.31 pixels / clock. Therefore, it can be seen that the access method according to the embodiment can be efficiently accessed in a small unit and is preferable.

  Although not mentioned in the embodiment, when the same block configuration as that of the second embodiment shown in FIG. 19 is used and an image is stored in the image memory as shown in FIGS. 8 and 9, the sub-scanning direction (Y Direction) (for example, in the order of C (0,0), C (0,1), C (0,2), C (0,3), ...) In contrast to the conventional access method described with reference to FIG. 4, only one pixel image can be read out in 52 clocks, whereas in the access method according to this embodiment, one pixel can be read out in 12 clocks. The image data can be read out at a speed of.

  The present invention can be applied to a color image processing apparatus or a color printer engine using a synchronous DRAM, and can be used particularly for a digital color copying machine or a printer using a CMYK tandem printer engine.

1 is a schematic block diagram showing a configuration of a general color copying machine using a tandem color laser printer engine. 4 is a time chart schematically showing temporal shifts of image writing signals 202 to 205 corresponding to CMYK colors, respectively. It is a time chart which shows the read-out operation | movement of DDR-SDRAM. It is a time chart which shows the batch read operation by the burst read command of DDR-SDRAM. 1 is a block diagram showing a schematic configuration of an image processing system of a typical digital color copying machine. FIG. 6 is a block diagram showing a schematic configuration of a recording image processing unit of the color copying machine shown in FIG. 5 to which an embodiment of a color image processing apparatus according to the present invention is applied. FIG. 3 is a more detailed block diagram of an image editing control unit using the color image processing apparatus according to the first embodiment of the present invention. 3 is a diagram schematically showing image data stored in an image memory 604. FIG. It is a figure which shows typically the address structure of an image memory. (A) is a schematic block diagram for explaining the operation of the image writing control unit in FIG. 7, and (B) is a format diagram of a series of writing commands. It is a schematic block diagram for demonstrating operation | movement of the data writing control part in FIG. It is a timing chart which shows the data write-in operation | movement of a present Example. It is a schematic block diagram for demonstrating operation | movement of the image reading control part in FIG. It is a schematic block diagram for demonstrating operation | movement of the data read-out control part in FIG. It is a timing chart which shows the data read-out operation | movement of a present Example. 10 is a timing chart showing a data read operation when there is valid data only in a command FIFO of CMK. 6 is a timing chart showing a data write operation when only CMK command FIFO has valid data. It is a timing chart which shows the other example of the data reading / writing operation | movement in a present Example. It is a detailed block diagram of the image rotation processing apparatus using the color image processing apparatus by 2nd Example of this invention. It is a timing chart which shows operation | movement of 2nd Example of this invention.

Explanation of symbols

501 Reading unit 502 Reading image processing unit 503 Image management unit 504 Image storage unit 505 Recording image processing unit 506 Printer unit 601 Color space conversion unit 602 Image processing unit 603 Image editing control unit 604 Image memory (synchronous DRAM)

Claims (8)

In a color image processing apparatus for processing a color image composed of a plurality of color components,
A synchronous DRAM (Dynamic Random Access Memory) having a plurality of banks inside and having a predetermined memory access unit ;
Control means for assigning one color component of the color image to each bank of the synchronous DRAM and performing read / write control of image data of each color component to the synchronous DRAM;
I have a,
The control means issues an activation command to the designated address for the synchronous DRAM while sequentially shifting the plurality of banks by one clock unit for each bank, and subsequently, the plurality of banks is set to one for each bank. A color image processing apparatus which issues a read / write command while sequentially shifting in units of clocks .   The color image processing apparatus according to claim 1, wherein the control unit randomly accesses unrelated areas of the plurality of banks. The synchronous DRAM includes four banks therein, and four color components of C (cyan), M (magenta), Y (yellow), and K (black) are assigned to each bank. The color image processing apparatus according to 1 or 2 . In a method for controlling access to a synchronous DRAM (Dynamic Random Access Memory) in a predetermined memory access unit having a plurality of banks inside and storing a color image composed of a plurality of color components,
Assigning one color component of the color image to each bank of the synchronous DRAM ;
An activation command is issued while sequentially shifting the plurality of banks in units of one clock for each bank with respect to the designated address for the synchronous DRAM, and then sequentially shifting the plurality of banks in units of one clock for each bank. An access control method characterized by issuing a read / write command . 5. The access control method according to claim 4 , wherein random access is made to unrelated areas of the plurality of banks. In a program for causing a computer to execute access control to a synchronous DRAM (Dynamic Random Access Memory) having a plurality of banks therein and storing a color image composed of a plurality of color components,
A function of assigning one color component of the color image to each bank of the synchronous DRAM;
An activation command is issued while sequentially shifting the plurality of banks in units of one clock for each bank with respect to the designated address for the synchronous DRAM, and then sequentially shifting the plurality of banks in units of one clock for each bank. While issuing a read / write command ,
A program characterized by realizing .   A color copying machine comprising the color image processing apparatus according to claim 1.   A color printer comprising the color image processing apparatus according to claim 1.

Images