JP5530823B2 - Memory check method and image processing apparatus - Google Patents

Description

  The present invention relates to a memory check method and an image processing apparatus.

  An image processing apparatus that is provided in a multi-function multifunction peripheral and performs various image processing on image data includes a processor that performs processing based on program data and data transfer, and a system memory that can read and write data by the processor ( Main memory or main storage device), and non-volatile memory such as HDD (hard disk drive) and flash memory.

  In the nonvolatile memory, a system program that controls the entire operation of the image processing apparatus is stored as system program data. The system program data stored in the non-volatile memory is transferred to and stored in the system memory, and the system program is started when the processor performs a predetermined process based on the stored system program data. When the start processing of the system program is completed, the image processing apparatus can perform image processing on the image data.

  The system memory stores not only system program data but also various data such as application program data and image data. In the case of a multifunction multifunction peripheral, the system memory stores, for example, input image data input from the image input device, output image data output to the image output device, and the like. If a failure occurs in any one of the memory cells in the system memory, data such as system program data cannot be stored normally, and the image processing apparatus cannot operate normally. For this reason, it is required to check whether or not a failure has occurred in the memory cell of the system memory and to prevent the occurrence of problems in actual operation.

  In general, the system memory may fail due to external factors such as the environment even if there is no failure at the time of manufacture or shipment of the image processing apparatus. Therefore, in order for the image processing apparatus to operate stably, it is necessary to perform a memory check of the system memory every time the image processing apparatus is activated. However, recent image processing apparatuses have a high resolution of the image to be processed, and the capacity of the system memory to be mounted is increased in proportion to this, so that the time required for the memory check is also increased. Conventionally, the system program data transfer process and the system program start process are performed after the memory check is completed. Therefore, if the time required for the memory check increases, the system program start process is completed and the image processing apparatus can be used. There is a problem that it takes a lot of time to become.

  Patent Document 1 discloses a device for performing a memory check of a system memory by a multiprocessor system as a device for solving this problem.

JP 2009-169897 A

  The device described in Patent Document 1 causes a plurality of sub processors to perform a memory check of a memory check target area that is an area other than an area in which predetermined program data is stored in a system memory. Therefore, according to the apparatus described in Patent Document 1, the memory check in the memory check target area can be completed earlier than before.

  However, in the apparatus described in Patent Document 1, there is a problem that the system program activation process cannot be performed unless the check by all the sub processors is completed, that is, unless the memory check of the entire memory check target area is completed. is there. In the apparatus described in Patent Document 1, since a memory check is performed only for a memory cell in a memory check target area, a failure cannot be found in a memory cell in an area other than the memory check target area.

  An object of the present invention is to solve the above-described problems, and to provide a memory check method and an image processing apparatus capable of performing a memory check of a system memory and a startup process of a system program in parallel. .

The present invention includes a processor;
System memory consisting of storage area, work area and image area;
Non-volatile memory;
A memory check circuit including a direct memory access controller, wherein predetermined data is written to a memory cell of the system memory via the direct memory access controller, and then the memory of the system memory is transmitted via the direct memory access controller. The data is read from the memory cell in which the predetermined data is written, the predetermined data written is compared with the read data, and when the data does not match as a result of the comparison, there is a failure in the memory cell. A memory check circuit that performs a memory check, and a memory check method for the system memory in a startup process of an image processing apparatus comprising:
A first step in which the memory check circuit performs a memory check on memory cells in the storage area;
When not all memory cells in the storage area have failed in the memory check in the first step,
The memory check circuit performs a memory check on the memory cells in the work area;
The processor starts transferring the system program data stored in advance in the nonvolatile memory to the storage area, and until the memory check for the memory cells in the work area is completed, the system program data A second step of completing the transfer to the storage area or the memory check for the memory cells in the work area and the transfer of the system program data to the storage area at the same time ;
When all the memory cells in the work area have not failed in the memory check in the second step,
The memory check circuit performs a memory check on the memory cells in the image area;
A memory check including: a third step of performing at least a system program start process among the start processes of the image processing apparatus based on the system program data transferred to the storage area; Is the method.

  According to the present invention, the startup processing of the image processing apparatus performed in the third step includes at least one of startup processing of an application program and initialization of an external device in addition to the startup processing of the system program. It is characterized by that.

  Further, the present invention is characterized in that when the memory check circuit writes the predetermined data to the system memory via the direct memory access controller, the memory check circuit writes in one or more burst units.

  Further, the present invention is characterized in that when the memory check circuit writes the predetermined data to the system memory via the direct memory access controller, the memory check circuit writes the data in units of 1 byte.

  According to the present invention, the memory check circuit writes pseudo random number pattern data as the predetermined data to the system memory via the direct memory access controller.

  According to the present invention, the memory check circuit writes fixed pattern data as the predetermined data to the system memory via the direct memory access controller.

The present invention is also an image processing apparatus comprising a processor, a system memory, a nonvolatile memory, and a memory check circuit,
The system memory includes a storage area, a work area, and an image area.
The nonvolatile memory stores system program data in advance,
The memory check circuit includes a direct memory access controller, writes predetermined data to a memory cell of the system memory via the direct memory access controller, and then passes the direct memory access controller to the memory of the system memory. The data is read from the memory cell in which the predetermined data is written, the predetermined data written is compared with the read data, and when the data does not match as a result of the comparison, there is a failure in the memory cell. A memory check circuit that performs
The memory check circuit is configured to perform a memory check on memory cells in the storage area;
When not all memory cells in the storage area have failed in the memory check for the memory cells in the storage area,
The memory check circuit performs a memory check on the memory cells in the work area;
The processor starts transferring the system program data to the storage area and completes the transfer of the system program data to the storage area until the memory check for the memory cells in the work area is completed. Or the memory check for the memory cells in the work area and the transfer of the system program data to the storage area are completed simultaneously ,
When all the memory cells in the work area have not failed in the memory check for the memory cells in the work area,
The memory check circuit performs a memory check on the memory cells in the image area;
An image processing apparatus, wherein the processor is configured to perform at least a system program activation process among the activation processes of the image processing apparatus based on system program data transferred to the storage area. is there.

  According to the present invention, in the second step, the startup process of the system program and the memory check of the system memory can be performed in parallel by the processor and the memory check circuit. Thereby, the time required for the memory check of the system memory can be effectively utilized. In the present invention, since the memory check circuit performs a memory check of the system memory via the direct memory access controller, the load on the processor is reduced even when the memory check is performed for all the memory cells of the system memory. be able to.

According to the invention, in the third step, in addition to the system program startup process, at least one of the application program startup process and the external device initialization is performed by the memory check circuit for checking the memory of the system memory. Can be done in parallel. Therefore, the time required for the memory check of the system memory can be utilized more effectively.

  According to the invention, the memory check circuit writes data via the direct memory access controller in units of one or a plurality of bursts. As a result, the time required for the memory check of the system memory can be reduced as compared with the case where data is written in units of 1 byte.

  According to the present invention, the memory check circuit writes data via the direct memory access controller in units of 1 byte. Therefore, since the data mask signal is used at the time of data writing, not only the memory check of the system memory but also a check as to whether or not an abnormality has occurred in the data mask signal can be performed.

  According to the invention, the memory check circuit writes the pseudo random number pattern data in the system memory. As a result, even if the failure mode of the memory cell of the system memory is a failure mode that changes in association with writing to another memory cell, the failure of the memory cell can be detected more easily.

  According to the invention, the memory check circuit writes fixed pattern data in the system memory. As a result, when a failure of the memory cell is discovered, the data that should have been originally written to the failed memory cell can be confirmed without generating the fixed pattern data again.

  In addition, according to the present invention, the startup process of the system program and the memory check of the system memory can be performed in parallel by the processor and the memory check circuit. Thereby, the time required for the memory check of the system memory can be effectively utilized. In the present invention, since the memory check circuit performs memory check of the system memory via the direct memory access controller, the memory check can be performed for all the memory cells of the system memory while reducing the load on the processor. .

1 is a schematic diagram illustrating a configuration of a multifunction machine 1000. FIG. 2 is a conceptual diagram of each area of a system memory 4. FIG. 3 is a block diagram showing a configuration of a memory check circuit 2. FIG. It is a flowchart showing a memory check method. It is a flowchart showing the process by the memory check circuit 2 in 1st step S1.

  Hereinafter, a multifunction peripheral 1000 including the image processing apparatus 100 according to an embodiment of the present invention will be described. FIG. 1 is a schematic diagram showing the configuration of the multifunction machine 1000. The multifunction machine 1000 includes an image processing apparatus 100, an image input apparatus 200, and an image output apparatus 300. The multi-function peripheral 1000 has three types of printing modes: a copier mode (copying mode), a printer mode, and a facsimile mode. In each printing mode, a full-color or monochrome image is formed on a recording medium such as recording paper. To do. The printing mode of the multifunction machine 1000 is set according to a command from a personal computer, a portable terminal device, an information recording medium, etc., an operation input from an operation unit (not shown), and the like.

The image input device 200 is, for example, a CCD (Charge Coupled) arranged in a line.
Device) An image reading apparatus having a scanner unit including an image sensor. The scanner unit reads the reflected light image from the document by moving in a direction (sub-scanning direction) perpendicular to the arrangement direction (main scanning direction) of the CCD image sensor. The reflected light image is color-separated into a red (R) component, a green (G) component, and a blue (B) component, and is read by the scanner unit as an analog signal indicating the reflectance of each component. The image input device 200 creates analog signal image data by collecting the RGB analog signals read for each pixel as one data, and outputs the analog signal image data to the image processing device 100.

  The image processing apparatus 100 stores analog signal image data input from the image input apparatus 200 as input image data. The image processing apparatus 100 performs various image processing on the stored input image data and outputs the processed image as output image data to the image output apparatus 300. Examples of image processing performed by the image processing apparatus 100 on input image data include processing for correcting image data such as image quality adjustment processing, color correction processing, and gradation reproduction processing. In addition, for example, a process for correcting image data based on a user instruction, such as an enlargement process, a reduction process, or a two-color process. A specific configuration of the image processing apparatus 100 will be described later.

  The image output apparatus 300 is an image forming apparatus such as an electrophotographic system or an inkjet system. The image output device 300 forms an image on a recording medium based on the output image data input from the image processing device 100.

  As shown in FIG. 1, the image processing apparatus 100 includes a processor 1, a memory check circuit 2, a cache memory 3, a system memory 4, a first nonvolatile memory 5, a second nonvolatile memory 6, and an interface. The unit 7 and the display unit 8 are included.

  The processor 1 is a control arithmetic device that performs arithmetic processing based on program data, data transfer control processing between different electronic devices, and the like. As the processor 1, a single CPU (Central Processing Unit) may be used, or a plurality of CPUs may be used. However, when a plurality of CPUs are used, it is necessary to synchronize the CPUs.

  The cache memory 3 is a semiconductor memory such as SRAM (Static Random Access Memory). The cache memory 3 is configured such that the processor 1 can directly read and write data.

  The second non-volatile memory 6 is a non-volatile memory such as an HDD or an SD memory card. The second nonvolatile memory 6 stores system program data, secondary downloader program data, and application program data.

  The system program data is data representing a system program that is a program for controlling the entire image processing apparatus 100 and performing predetermined image processing on input image data. The system program data is data indicating the execution procedure of the predetermined process, and the data indicating the setting related to the predetermined process is not included in the system program data.

  The processor 1 starts a predetermined process based on the system program data, so that a system program activation process is started. The system program activation process is a process performed based on the system program data in a period from the start of the system program activation process until the image processing apparatus 100 can perform the image process.

  The application program data is data representing an application program which is a program for starting an external device externally attached to the image processing apparatus 100 or performing processing not included in the system program for input image data. It is. When the processor 1 starts a predetermined process based on the application program data, an application program activation process is started. The application program activation process is a process performed based on the application program data during a period from the start of the application program activation process until the application program becomes available.

  The secondary downloader program data is data representing a program for transferring the system program data from the second nonvolatile memory 6 to the system memory 4 in the startup process of the image processing apparatus 100. Here, the activation process of the image processing apparatus 100 is a process performed by the image processing apparatus 100 during a period from when the image processing apparatus 100 is powered on until the image processing apparatus 100 becomes usable. The embodiment includes the above-described system program start processing and application program start processing, initialization of an external device, etc., and memory check by the memory check circuit 2 described later. The secondary downloader program also includes memory check setting data that is setting data related to the memory check. The memory check setting data is sent to the memory check circuit 2 by the processor 1.

The first nonvolatile memory 5 is, for example, a flash memory, NVRAM (Non Volatile
Random Access Memory) and other non-volatile semiconductor memories. The first nonvolatile memory 5 is configured so that the processor 1 can directly read data. The first non-volatile memory 5 stores primary downloader program data. The primary downloader program data is data representing a program for transferring the secondary downloader program data from the second nonvolatile memory 6 to the cache memory 3 in the startup process of the image processing apparatus 100.

  In the present embodiment, as described above, the primary downloader program data is stored in the first nonvolatile memory 5, and the system program data and the secondary downloader program data are stored in the second nonvolatile memory 6. On the other hand, as another embodiment of the present invention, secondary downloader program data may be stored in the first nonvolatile memory 5 instead of the primary downloader program data.

  The memory check circuit 2 is a digital electronic circuit connected to the processor 1 and the system memory 4 via a data bus and an address bus (not shown). The memory check circuit 2 performs a memory check on the system memory 4 during system program startup processing. In the memory check by the memory check circuit 2, first, pattern data is written in the memory cell of the system memory 4, and then data is read from the memory cell in the system memory 4 in which the pattern data is written. Then, the written data and the read data are compared, and when the data does not match as a result of the comparison, it is determined that the memory cell in the system memory 4 has failed.

The system memory 4 is, for example, a DDR SDRAM (Double Data Rate Synchronous).
Semiconductor memory such as Dynamic Random Access Memory. In the present invention, the system memory 4 is conceptually divided into three areas: a storage area 41, a work area 42, and an image area 43. Each area is a part of the system memory 4 and includes a plurality of memory cells.

  FIG. 2 is a conceptual diagram of each area of the system memory 4. The storage area 41 is an area in which at least system program data is stored (stored). When the storage capacity of the entire system memory 4 is 2 gigabytes, the storage capacity of the storage area 41 is, for example, 128 megabytes.

  The work area 42 is an area necessary for at least a system program activation process based on the system program data stored (stored) in the storage area 41. The work area 42 stores, for example, setting data necessary for starting the system program and the result of arithmetic processing based on the system program data. The work area 42 can store application program data, and the application program is activated based on the application program data. When the storage capacity of the entire system memory 4 is 2 gigabytes, the storage capacity of the work area 42 is, for example, 512 megabytes.

  The image area 43 is an area other than the storage area 41 and the work area 42 in the system memory 4. In the image area 43, input image data is mainly stored. When the storage capacity of the entire system memory 4 is 2 gigabytes, the storage capacity of the image area 43 is 1.4 gigabytes, for example.

  The interface unit 7 is a connection unit for USB (Universal Serial Bus) connection, ETHER network connection, and the like. For example, the image processing apparatus 100 can be connected to a USB memory or the like via the interface unit 7 and can store image data stored in the USB memory as input image data. The display unit 8 is composed of, for example, a touch panel. The display unit 8 displays an image for operating the image processing apparatus 100, a result of a memory check by the memory check circuit 2, and the like.

  According to such an image processing apparatus 100, image processing is performed on input image data stored in the system memory 4 based on system program data stored in the system memory 4, and an image is output as output image data. It is output to the output device 300. Also, according to the image processing apparatus 100, the memory check circuit 2 described in detail below performs a memory check on the system memory 4 in the system program startup process.

FIG. 3 is a block diagram showing a configuration of the memory check circuit 2. The memory check circuit 2 includes a control register unit 21, a memory read DMAC (Direct Memory Access).
Controller) 22, memory write DMAC 23, comparison unit 24, and pattern data generation unit 25.

  The control register unit 21 includes a register that stores memory check setting data sent by the processor 1. The control register unit 21 also has a function of storing the result of the memory check and transmitting it to the processor 1. The memory check setting data includes start address data indicating the start address in the memory check in the system memory 4 and size data indicating the storage capacity of the area where the memory check is performed.

  The memory read DMAC 22 is a DMAC that reads data from the system memory 4 without using the processor 1. The data read by the memory read DMAC 22 is sent to the comparison unit 24. Data reading by the memory read DMAC 22 is performed in units of one or a plurality of bursts. In one burst, for example, 8-byte data is read. Therefore, for example, in 8 bursts, 64 bytes of data are continuously read.

  The memory write DMAC 23 is a DMAC that writes pattern data sent from a pattern data generation unit 25 described later to the system memory 4 without going through the processor 1. The pattern data is written by the memory write DMAC 23 in units of one or a plurality of bursts or one byte.

  When writing pattern data in units of 1 byte, the memory write DMAC 23 sends 8 bytes (one burst) of pattern data including 1 byte of pattern data to be written to the system memory 4, and other than the 1 byte of data. A data mask signal for masking 7-byte pattern data is sent. As a result, 1-byte pattern data is written into the system memory 4. Data indicating whether the pattern data is written by the memory write DMAC 23 in units of bursts or in units of 1 byte is sent from the processor 1 to the control register unit 21 as one of the memory check setting data.

  In the present embodiment, as described above, data reading and data writing are performed by the two DMACs of the memory read DMAC 22 and the memory write DMAC 23. On the other hand, as another embodiment of the present invention, data reading and data writing may be performed by one DMAC.

  The pattern data generation unit 25 generates fixed pattern data, pseudorandom pattern data, and the like, and sends them to the memory write DMAC 23 and the comparison unit 24 as pattern data used for memory check. More specifically, the pattern data generation unit 25 generates pattern data and sends it to the memory write DMAC 23, and then generates again the same pattern data as the pattern data and sends it to the comparison unit 24.

  The fixed pattern data is data that is fixed when the memory check is performed, and has no correlation with the number of times sent to the memory write DMAC 23. The fixed pattern data may be, for example, data in which a value of 0 and a value of 1 are repeated for each bit or data representing an appropriate integer. The pseudo random number pattern data is data that is not fixed when the memory check is performed, and is data that represents a pseudo random number whose value fluctuates each time the data is sent to the memory write DMAC 23. The pattern data generated by the pattern data generation unit 25 may be, in addition to the fixed pattern data and the pseudo random number pattern data, increment pattern data representing an integer whose value increases by 1 each time it is sent to the memory write DMAC 23. Good.

  In the case of a configuration for generating pseudo-random pattern data, the pattern data generation unit 25, for example, a circuit in which four 2-byte linear feedback shift registers (LFSR) are connected in parallel and an 8-byte pseudo-random pattern data. And an acquisition register for holding random number pattern data. The 2-byte LFSR includes a 2-byte seed register, a tap register, and a shift register. Predetermined values are set in the seed register and tap register, and the shift register sends data representing a pseudo random number of 2 bytes to the acquisition register every clock based on the values set in the seed register and tap register. .

  The acquisition register holds each 2-byte data sent from the four LFSRs as 8-byte pseudo random number pattern data, and sends the pseudo random pattern data to the memory write DMAC 23 and the comparison unit 24. The memory write DMAC 23 writes 8-byte pseudorandom pattern data in one clock when writing to the system memory 4 in one burst unit. Further, when writing to the system memory 4 in units of 1 byte, the memory write DMAC 23 writes 8-byte pseudo random pattern data in 8 clocks by shifting the mask position by the data mask signal.

  When the pattern data generation unit 25 includes a tap register and a seed register as described above, a value set in the tap register and the seed register is sent from the processor 1 to the control register unit 21 as one of the memory check setting data. It is done.

  In the case of a configuration for generating fixed pattern data, the pattern data generation unit 25 includes, for example, an acquisition register that holds 8-byte fixed pattern data. In this case, as one of the memory check setting data, 8-byte data is sent from the processor 1 to the control register unit 21 and then sent to the acquisition register. The acquisition register holds the 8-byte data as fixed pattern data, and sends the fixed pattern data to the memory write DMAC 23 and the comparison unit 24.

  The pattern data generation unit 25 may be configured to be able to select whether to generate fixed pattern data or a pseudo random number pattern. In the case of such a selectable configuration, data indicating whether to generate fixed pattern data or a pseudorandom pattern is sent from the processor 1 to the control register unit 21 as one of the memory check setting data.

  The pattern data generation unit 25 generates inverted data that is data obtained by inverting fixed pattern data, pseudo random number pattern data, and the like to be sent to the memory write DMAC 23 and the comparison unit 24. To the DMAC 23 and the comparison unit 24. For example, the pattern data generation unit 25 includes a signal inversion circuit including a plurality of NOT circuits in order to generate inverted data, and the random number pattern data held in the acquisition register is inverted by the signal inversion circuit. The data is sent to the memory write DMAC 23 and the comparison unit 24 as pattern data.

  The comparison unit 24 compares the data sent from the memory read DMAC 22 with the pattern data sent from the pattern data generation unit 25, for example, in units of one burst. If the data does not match as a result of the comparison, the comparison unit 24 sends data indicating that there is a failure to the control register unit 21, assuming that the memory cell read by the memory read DMAC 22 has a failure. . When there is a failure in the memory cell, the control register unit 21 specifies the address of the memory cell based on the start address in the memory check and the number of comparisons by the comparison unit 24 until the failure is found. The address is stored. In addition, the control register unit 21 confirms data (value of 0 or 1) that should have been originally written in the memory cell based on the address of the failed memory cell, and stores the data. . Data indicating that a memory cell has failed, the address of the memory cell, and data that should have been originally written to the memory cell are transmitted from the control register unit 21 to the processor 1.

  When the processor 1 receives data indicating that a memory cell in the system memory 4 has failed, for example, the processor 1 displays on the display unit 8 that the memory cell in the system memory 4 has failed, and replaces the system memory 4. Prompt. Further, the processor 1 may cause the display unit 8 to display the address of the failed memory cell and the data that should have been originally written in the memory cell in order to check the failed system memory 4.

  Note that the failure mode of the memory cell of the system memory 4 that can be found by the memory check circuit 2 is not limited to a failure mode in which at least one of a value of 0 and a value of 1 cannot be written in the memory cell. There are also failure modes in which data changes with writing to other memory cells.

  Next, a memory check method executed by the image processing apparatus 100 will be described. FIG. 4 is a flowchart showing a memory check method. In the memory check method according to the present embodiment, the activation process of the image processing apparatus 100 is started in the 0th step S0. Next, in the first step S1, the memory check circuit 2 performs a memory check on the memory cells in the storage area 41. Next, in the second step S2, the memory check circuit 2 performs a memory check on the memory cells in the work area 42, and the processor 1 transfers the system program data in the second nonvolatile memory 6 to the storage area 41. Start. Finally, in the third step S3, the memory check circuit 2 performs a memory check on the memory cells in the image area 43, and the processor 1 transfers the system program data to the storage area 41 based on the stored system program data. Perform startup processing. Hereinafter, each step of the memory check method will be described in detail.

  In the 0th step S0, first, the image processing apparatus 100 is powered on by a user or by a device other than the image processing apparatus 100. Next, the processor 1 initializes the second non-volatile memory 6 according to the primary downloader program data in the first non-volatile memory 5, and transfers the secondary downloader program from the second non-volatile memory 6 to the cache memory 3. Transfer data.

  Then, the processor 1 performs setting (mode register setting, synchronization setting, etc.) and initialization of the system memory 4 according to the secondary downloader program data transferred and stored in the cache memory 3. At this time, the processor 1 transfers the memory check setting data to the memory check circuit 2 in accordance with the secondary downloader program data stored in the cache memory 3. Finally, the processor 1 causes the memory check circuit 2 to start a memory check of the storage area 41.

  In the first step S1, the memory check circuit 2 starts a memory check of the storage area 41. When the memory check of the storage area 41 is completed, the memory check circuit 2 notifies the processor 1 of the completion of the memory check of the storage area 41.

  The processing in the second step S2 is performed when no failure has occurred in all the memory cells in the storage area 41 in the memory check in the first step S1. In the present invention, as will be described later, even if a failure has occurred in the memory cell in the storage area 41, the process of the second step S2 may be performed. In the second step S2, the memory check circuit 2 starts a memory check of the work area. In parallel with this, the processor 1 starts transferring the system program data from the second nonvolatile memory 6 to the storage area 41. More specifically, the transfer process is a process in which the processor 1 reads the system program data in the second nonvolatile memory 6 and writes the read system program data to the storage area 41.

  In the present embodiment, when the processor 1 is reading the system program data in the second nonvolatile memory 6 as described above, the memory check circuit 2 performs a work via the memory write DMAC 23 for the memory check. The pattern data is written to the area 42 or the data is read from the work area 42 via the memory read DMAC 22. When the processor 1 performs the process of writing the system program data to the storage area 41, the memory check circuit 2 does not write pattern data or read data. That is, in the present embodiment, the processing for writing the system program data to the storage area 41 by the processor 1 is interrupted with respect to the memory check by the memory check circuit 2. In this way, the image processing apparatus 100 performs in parallel the transfer of the system program data by the processor 1 and the memory check by the memory check circuit 2.

  As another embodiment of the present invention, the image processing apparatus 100 may be configured such that the processor 1 and the memory check circuit 2 can simultaneously access the system memory 4. With such a configuration, writing of system program data by the processor 1 and writing of pattern data or reading of data by the memory check circuit 2 can be performed in parallel.

In the present embodiment, as described above, the writing process to the system memory 4 by the processor 1 is performed in preference to the memory check by the memory check circuit 2, so that the system by the processor 1 has a higher priority than the memory check by the memory check circuit 2. Transfer of program data is completed earlier. On the other hand, as a reference mode, the memory check by the memory check circuit 2 is prioritized over the writing process to the system memory 4 by the processor 1, so that the memory check circuit 2 has a higher priority than the system program data transfer by the processor 1. It may be configured so that the memory check according to is completed earlier. As another embodiment of the present invention, a memory check by the memory check circuit 2 and a transfer of system program data by the processor 1 may be completed simultaneously. However, the transfer of the system program data by the processor 1 is completed at the latest before the memory check of the image area 43 in the third step S3 is completed.

  When the memory check of the work area 42 is completed, the memory check circuit 2 notifies the processor 1 of the completion of the memory check of the work area 42.

  The process in the third step S3 is performed when no failure has occurred in all the memory cells in the work area 42 in the memory check in the second step S2. In the present invention, even if a failure has occurred in the memory cell in the work area 42, the process of the third step S3 may be performed. In the third step S3, the memory check circuit 2 starts a memory check of the image area 43. In parallel with this, the processor 1 starts system program startup processing, and further starts application program startup processing and initialization of the external device, the interface unit 7 and the display unit 8. Various processes by the processor 1 are performed by interrupting the memory check of the work area 42 by the memory check circuit 2 as in the second step S2.

  In the present embodiment, since the writing process to the system memory 4 by the processor 1 is performed in preference to the memory check by the memory check circuit 2, the above-described various processes by the processor 1 are performed rather than the memory check by the memory check circuit 2. Is completed early. On the other hand, as another embodiment of the present invention, the memory check by the memory check circuit 2 is prioritized over the write process to the system memory 4 by the processor 1, so that the memory 1 You may comprise so that the memory check by the check circuit 2 may be completed earlier. Further, the memory check by the memory check circuit 2 and the various processes by the processor 1 may be completed at the same time.

  When the memory check of the image area 43 is completed, the memory check circuit 2 notifies the processor 1 of the completion of the memory check of the image area 43. The processor 1 receives the completion of the memory check of the image area 43, and if the various processes are completed, the processor 1 causes the display unit 8 to display that the image processing apparatus 100 is usable.

  In the memory check method according to the present embodiment, if there is a memory cell failure in the first step S1, the second step S2, and the third step S3, the memory check circuit 2 has a memory cell failure. To the processor 1. After informing the processor 1 that the memory cell has failed, the memory check circuit 2 may continue the subsequent memory check as in the case where the memory cell has not failed. For example, when a memory cell in the storage area 41 is defective in the memory check in the first step S1, the memory check circuit 2 continues the memory check for the memory cell at the address after the address of the memory cell, and the system A memory check may be performed for all the memory cells of the memory 4.

  Next, the memory check in the first step S1 will be described in detail. FIG. 5 is a flowchart showing processing by the memory check circuit 2 in the first step S1. In the 0th step S0 before the first step S1, memory check setting data is sent from the processor 1 to the control register unit 21. Based on this memory check setting data, a memory check by the memory check circuit 2 is performed. Is done. Note that the memory check setting data sent to the control register unit 21 need not be sent all at once in the 0th step S0. For example, in the first step S1, the memory check setting data is controlled from the processor 1 at an appropriate time as necessary. May be sent to the register unit 21.

  In the memory check in the first step S1, when an instruction to start the memory check of the storage area 41 is transmitted from the processor 1 to the control register unit 21, the memory check circuit 2 performs steps A0 to A15 described below. Processing is performed.

  In step A0, the control register unit 21 instructs the pattern data generation unit 25 to generate pattern data (fixed pattern data or pseudorandom pattern data) and send the generated pattern data to the memory write DMAC 23. put out.

  In step A1, the pattern data generation unit 25 generates pattern data and sends the generated pattern data to the memory write DMAC 23. Then, the memory write DMAC 23 writes the pattern data in units of one byte or one or a plurality of bursts from the top of the storage area 41.

  In step A2, the control register unit 21 determines whether or not the pattern data has been written to the entire storage area 41 based on the top address data and size data for the storage area 41 and the number of writes by the memory write DMAC 23. To do. If the pattern data is written in all the storage areas 41, the process by the memory check circuit 2 proceeds to step A3. If the pattern data is not written in all the storage areas 41, the process by the memory check circuit 2 proceeds to step A1. Return.

  In step A 3, the control register unit 21 instructs the memory read DMAC 22 to read the memory cell data in the storage area 41 in units of one or more bursts and send the read data to the comparison unit 24. In parallel with this, the control register unit 21 generates the same pattern data as the pattern data written in the storage area 41 in the pattern data generation unit 25, and sends the generated pattern data to the comparison unit 24. Give instructions.

  In step A 4, the memory read DMAC 22 reads data from the head of the storage area 41 in units of one or more bursts, and sends the read data to the comparison unit 24. In parallel with this, the pattern data generation unit 25 generates the same pattern data as the pattern data written in the storage area 41, and sends the generated pattern data to the comparison unit 24.

  In step A5, the comparison unit 24 compares the data sent from the memory read DMAC 22 with the data sent from the pattern data generation unit 25, and determines whether or not the two data match. The data comparison is performed, for example, in units of 1 burst (8 bytes). If the data match, the process by the memory check circuit 2 proceeds to step A6. If the data does not match, the process by the memory check circuit 2 proceeds to step A14.

  In step A6, the control register unit 21 determines whether or not the comparison unit 24 in step A5 has performed comparison for all the storage regions 41 based on the size data for the storage region 41 and the number of comparisons by the comparison unit 24. to decide. If all the storage areas 41 have been compared, the process by the memory check circuit 2 proceeds to step A7. If all the storage areas 41 have not been compared, the process by the memory check circuit 2 returns to step A4.

  In step A7, the control register unit 21 generates inversion data obtained by inverting the pattern data written in the storage area 41 in step A8 to the pattern data generation unit 25, and sends the generated inversion data to the memory write DMAC 23. Give instructions to do so. In parallel with this, the control register unit 21 instructs the memory read DMAC 22 to stop reading data from the storage area 41.

  As in the present embodiment, in the memory check, by using the inverted data as described above, a memory cell failure can be found more reliably. For example, when a memory check is performed using one pattern data, it can be confirmed that a value of 0 can be written in the memory cell. When a memory check is performed using the inverted data of the pattern data, it can be confirmed that a value of 1 can be written in the memory cell. As described above, by performing the memory check using the inverted data, it can be confirmed that both the value of 0 and the value of 1 can be normally written in the memory cell.

  In step A8, the pattern data generation unit 25 generates inverted data and sends it to the memory write DMAC 23. Then, the memory write DMAC 23 writes the pattern data in units of one byte or one or a plurality of bursts from the top of the storage area 41.

  In step A9, the control register unit 21 determines whether or not inverted data has been written in all of the storage areas 41 based on the top address data and size data for the storage areas 41 and the number of writes by the memory write DMAC 23. To do. If the inverted data is written in all the storage areas 41, the process by the memory check circuit 2 proceeds to step A10. If the inverted data is not written in all the storage areas 41, the process by the memory check circuit 2 proceeds to step A8. Return.

  In step A 10, the control register unit 21 instructs the memory read DMAC 22 to read the memory cell data in the storage area 41 in units of one or more bursts and send the read data to the comparison unit 24. In parallel with this, the control register unit 21 generates inversion data identical to the inversion data written in the storage area 41 in the pattern data generation unit 25, and sends the generated inversion data to the comparison unit 24. Give instructions.

  In step A 11, the memory read DMAC 22 reads data from the head of the storage area 41 in units of one or more bursts, and sends the read data to the comparison unit 24. In parallel with this, the pattern data generation unit 25 generates the same inverted data as the inverted data written in the storage area 41, and sends the generated inverted data to the comparison unit 24.

  In step A12, the comparison unit 24 compares the data sent from the memory read DMAC 22 with the data sent from the pattern data generation unit 25, and determines whether or not the two data match. The data comparison is performed, for example, in units of 1 burst (8 bytes). If the data match, the process by the memory check circuit 2 proceeds to step A13. If the data does not match, the process by the memory check circuit 2 proceeds to step A14.

  In step A13, the control register unit 21 determines whether or not the comparison unit 24 in step A12 has performed comparison for all the storage regions 41 based on the size data for the storage region 41 and the number of comparisons by the comparison unit 24. to decide. If all the storage areas 41 have been compared, the process by the memory check circuit 2 proceeds to step A15. If all the storage areas 41 have not been compared, the process by the memory check circuit 2 returns to step A11.

  The process of step A14 is a process performed when data does not match in step A5 or step A12, and is a process after a failure is found in a memory cell. The fact that the data written to the system memory 4 does not match the data read from the system memory 4 means that normal data cannot be written to the system memory 4. That is, a failure has occurred in the memory cell of the system memory 4. Therefore, in step A14, the control register unit 21 stores the address of the memory cell that has failed, and informs the processor 1 that a memory cell in the system memory 4 has failed.

  In the present embodiment, the memory check circuit 2 notifies the processor 1 of the failure of the memory cell, and then performs processing according to the processing of step A1 to step A13 to store the memory area 41 other than the memory cell that has failed. A memory check is performed for all the memory cells, and if a failure occurs in another memory cell, the address of the memory cell is stored in the control register unit 21. When the memory check is completed for all the memory cells in the storage area 41, the memory check circuit 2 advances the process to step A15.

  As described above, in this embodiment, even if some of the memory cells in the storage area 41 have failed, the memory check is performed for all the memory cells in the storage area 41 in step A14. Therefore, more information about the failed system memory 4 can be acquired, and the cause of the failure can be easily identified. As another embodiment of the present invention, the image processing apparatus 100 stops the memory check by the memory check circuit 2 after the memory check circuit 2 notifies the processor 1 of the failure of the memory cell, and issues a user instruction. It may be configured to wait.

  In step A15, the control register unit 21 notifies the processor 1 that the memory check of the storage area 41 has been completed. Thereby, the first step S1 of the memory check method described above is completed. Note that the memory check of the work area 42 in the second step S2 and the memory check of the image area 43 in the third step S3 are also performed in the same manner as the processes in the steps A0 to A15.

  According to the present embodiment as described above, the memory check circuit 2 performs the memory check of the system memory 4 via the memory read DMAC 22 and the memory write DMAC 23, so that the memory check is performed for all the memory cells of the system memory 4. Even at times, the load on the processor 1 can be reduced. In the present embodiment, in the second step S2 described above, the processor 1 and the memory check circuit 2 can perform the system program activation process and the memory check of the system memory 4 in parallel. Therefore, the time required for the memory check of the system memory 4 can be used effectively.

  In the present embodiment, in the above-described second step S2, various processes other than the system program activation process (application program activation process and initialization of the external device, the interface unit 7, and the display unit 8) are also performed. This can be performed in parallel with the memory check of the system memory 4. Therefore, the time required for the memory check of the system memory 4 can be utilized more effectively.

  In the embodiment described above, when the pattern data is written by the memory write DMAC 23 in units of one or a plurality of bursts, the time required for the memory check of the system memory 4 is shortened compared to the case of writing pattern data in units of 1 byte. can do. On the other hand, when pattern data is written by the memory write DMAC 23 in units of 1 byte, a data mask signal is used, so that not only a memory check of the system memory 4 but also an abnormality occurs in the data mask signal. You can also check whether or not In order to shorten the time required for the memory check of the system memory 4, it is preferable to read data by the memory read DMAC 22 in units of one or a plurality of bursts.

  In the above-described embodiment, when using pseudo random number pattern data as pattern data, it is assumed that the failure mode of the memory cell of the system memory 4 is a failure mode that changes accompanying writing to another memory cell. However, the failure of the memory cell can be found more easily. However, when using pseudorandom pattern data, the data that should have been originally written in the memory cell that has failed must be confirmed by generating pseudorandom pattern data again. On the other hand, when the fixed pattern data is used as the pattern data, the data that should have been originally written in the memory cell that has failed can be confirmed without generating the pattern data again.

  In the embodiment described above, the memory check circuit 2 is a dedicated electronic circuit for executing the memory check method according to the present invention. As another embodiment of the present invention, a control arithmetic device and a semiconductor memory can be provided in place of the memory check circuit 2. That is, as another embodiment of the present invention, a semiconductor memory for storing program data for executing the memory check method according to the present invention, and in parallel with a system program startup process by the processor 1 according to the program data The image processing apparatus may include a control arithmetic device that performs a memory check of the system memory 4. With such a configuration, other program data can be stored in the semiconductor memory, so that it is possible to start another program by the control arithmetic device.

  In the above-described embodiment, only one memory check circuit 2 is provided. However, as another embodiment of the present invention, a plurality of memory check circuits 2 may be provided. If a plurality of memory check circuits 2 are provided, the memory check of the system memory 4 can be performed in a distributed manner. For example, in the memory check of the storage area 41, it can be said that the storage area 41 is further subdivided, and the plurality of memory check circuits 2 perform memory checks on the subdivided areas.

DESCRIPTION OF SYMBOLS 1 Processor 2 Memory check circuit 3 Cache memory 4 System memory 5 1st non-volatile memory 6 2nd non-volatile memory 21 Control register part 22 Memory read DMAC
23 DMAC for memory write
24 comparison unit 25 pattern data generation unit 41 storage area 42 work area 43 image area 100 image processing apparatus 200 image input apparatus 300 image output apparatus 1000 MFP

Claims (7)

A processor;
System memory consisting of storage area, work area and image area;
Non-volatile memory;
A memory check circuit including a direct memory access controller, wherein predetermined data is written to a memory cell of the system memory via the direct memory access controller, and then the memory of the system memory is transmitted via the direct memory access controller. The data is read from the memory cell in which the predetermined data is written, the predetermined data written is compared with the read data, and when the data does not match as a result of the comparison, there is a failure in the memory cell. A memory check circuit that performs a memory check, and a memory check method for the system memory in a startup process of an image processing apparatus comprising:
A first step in which the memory check circuit performs a memory check on memory cells in the storage area;
When not all memory cells in the storage area have failed in the memory check in the first step,
The memory check circuit performs a memory check on the memory cells in the work area;
The processor starts transferring the system program data stored in advance in the nonvolatile memory to the storage area, and until the memory check for the memory cells in the work area is completed, the system program data A second step of completing the transfer to the storage area or the memory check for the memory cells in the work area and the transfer of the system program data to the storage area at the same time ;
When all the memory cells in the work area have not failed in the memory check in the second step,
The memory check circuit performs a memory check on the memory cells in the image area;
A memory check including: a third step of performing at least a system program start process among the start processes of the image processing apparatus based on the system program data transferred to the storage area; Method.   The startup processing of the image processing apparatus performed in the third step includes at least one of startup processing of an application program and initialization of an external device in addition to the startup processing of the system program. The memory check method according to claim 1.   The memory check method according to claim 1 or 2, wherein the memory check circuit writes the predetermined data in the system memory via the direct memory access controller in units of one or a plurality of bursts.   The memory check method according to claim 1 or 2, wherein the memory check circuit writes the predetermined data in the system memory via the direct memory access controller in units of 1 byte.   5. The memory check according to claim 1, wherein the memory check circuit writes pseudo random number pattern data as the predetermined data to the system memory via the direct memory access controller. Method.   5. The memory check method according to claim 1, wherein the memory check circuit writes fixed pattern data as the predetermined data into the system memory via the direct memory access controller. . An image processing apparatus comprising a processor, a system memory, a nonvolatile memory, and a memory check circuit,
The system memory includes a storage area, a work area, and an image area.
The nonvolatile memory stores system program data in advance,
The memory check circuit includes a direct memory access controller, writes predetermined data to a memory cell of the system memory via the direct memory access controller, and then passes the direct memory access controller to the memory of the system memory. The data is read from the memory cell in which the predetermined data is written, the predetermined data written is compared with the read data, and when the data does not match as a result of the comparison, there is a failure in the memory cell. A memory check circuit that performs
The memory check circuit is configured to perform a memory check on memory cells in the storage area;
When not all memory cells in the storage area have failed in the memory check for the memory cells in the storage area,
The memory check circuit performs a memory check on the memory cells in the work area;
The processor starts transferring the system program data to the storage area and completes the transfer of the system program data to the storage area until the memory check for the memory cells in the work area is completed. Or the memory check for the memory cells in the work area and the transfer of the system program data to the storage area are completed simultaneously ,
When all the memory cells in the work area have not failed in the memory check for the memory cells in the work area,
The memory check circuit performs a memory check on the memory cells in the image area;
An image processing apparatus, wherein the processor is configured to perform at least a system program activation process among the activation processes of the image processing apparatus based on system program data transferred to the storage area.

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