JP2010181723A - Signal processing integrated circuit and effect imparting device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make parameters of two or more steps different in values from each other according to the operation of an operator. <P>SOLUTION: A first select circuit 21 outputs a select signal according to an effect type EFT selected by the operation of an EF select operator 3 to memories 22-25 and outputs an UPT according to the EFT. A μ program memory 22 outputs a μ code including UPTC from a μ program according to the EFT. An UP counter 29 is reset at every sampling period, and is incremented by one at every step where the UPT and the UPTC match to generate a count value UPC. A conversion table memory 25 switches the conversion table set according to the EFT one by one based on the UPC, and outputs a user parameter controlled to a different value corresponding to the operation value of the operator at every step where the UPT and the UPTC match. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a signal processing integrated circuit that performs signal processing of a predetermined number of steps for each sampling period, and more particularly to a signal processing integrated circuit applied to an effect applying device that applies an effect to an acoustic signal, and the signal processing integrated circuit. The present invention relates to an effect applying device.

  Conventionally, there has been a digital effector that performs an effect (effect imparting) process on an acoustic signal (waveform data) using a digital signal processing integrated circuit (“DSP LSI”, hereinafter simply referred to as “DSP”). This type of digital effector has a CPU that controls the overall operation of the digital effector. Then, the CPU accesses a register in the DSP to a microprogram composed of a predetermined number of steps of microcode, a number of coefficient data corresponding to the total number of steps of the predetermined number of steps of the microprogram, and a delay memory in one sampling period The number of address data corresponding to the number of possible steps is set, and the DSP executes signal processing based on the microprogram, coefficient data, and address data set in the register by the CPU (for example, the following patents) Reference 1).

  A conventional digital effector has a plurality of types of effect types, and there is a model in which a user can select an effect type to be used (type of effector) using an operator. In addition, in the conventional digital effector, there is a model having an operator for manually adjusting the parameter value of the effect processing. In a conventional digital effector having these operation elements, a detection signal corresponding to the operation of the operation element is supplied to the CPU, and the CPU executes a process corresponding to the supplied detection signal. For example, when an operation for switching the effect type is performed, the CPU performs a process of switching the microprogram according to the newly selected effect type and setting the microprogram in the DSP register. Further, when an operation for controlling the parameter of the effect processing is performed, the CPU changes the value of the coefficient data or address data of a specific step set in the DSP register according to the operation value, and Processing to reflect the change in the DSP was performed.

  As described above, in a conventional DSP, various processes (selection of effect type and change of parameters (coefficient data or address data)) according to the operation of the user's operator are generally controlled by the CPU. As a result, the DSP could not operate without a CPU.

  Further, a conventionally known DSP stores a plurality of microprograms in an internal memory of the DSP, and selectively uses one of the plurality of microprograms according to a microprogram switching operation by a user. There was a configuration for performing signal processing. This DSP has a mechanism for switching microprograms inside, and it is relatively easy to improve this configuration to a configuration in which the DSP itself switches microprograms according to the effect type selection operation by the user. (For example, refer to Patent Document 2 below).

JP-A-11-203129 Japanese Patent No. 2765426

  To configure an effector that can operate without a CPU, the internal memory of the integrated circuit constituting the DSP stores a microprogram for each of the plurality of effect types, a coefficient for each of the plurality of effect types, and address data for each of the plurality of effect types. The DSP selects the microprogram, coefficient data, and address data corresponding to the effect type selection operation, and the DSP executes signal processing based on the selected microprogram, coefficient data, and address data. It is possible.

As described above, the switching of the signal processing contents in accordance with the change of the effect type merely replaces the microprogram, the coefficient data, and the address data in the switching range, and thus is described in the prior art document (for example, Patent Document 2). This can be realized relatively easily by improving the technique for controlling the read address of the existing microprogram. However, the change of the coefficient data and the address data according to the operation of the operation element is a change related to a specific step of the microprogram, and the coefficient data and the address data corresponding to the operation data from the operation element must be generated. Therefore, the improvement of the technique shown in the prior art document cannot be realized easily. In particular, it is difficult to control each parameter of a plurality of steps during signal processing based on a microprogram to a different value for each parameter of each step in accordance with the operation of the operation element.
On the other hand, it is also conceivable that the coefficient data and address data generation process according to the operation data from the operation element and the coefficient data and address data change process at a specific step are microprogrammed and executed by the DSP itself. In that case, many steps are consumed in the generation process and the change process, and there is a problem that the number of steps that can be used for signal processing on the input waveform data that should have been the original purpose is greatly reduced.

  The present invention has been made in view of the above points, and does not depend on CPU control and uses a plurality of specific steps corresponding to the currently selected effect type without much use of DSP processing steps. It is an object of the present invention to provide a signal processing integrated circuit in which the parameters (coefficient data or address data) can be controlled to different values according to the operation of the operation element. Moreover, it aims at providing the effect provision apparatus provided with the signal processing integrated circuit.

  The present invention is a signal processing integrated circuit that performs signal processing for a predetermined number of steps on an input acoustic signal every predetermined sampling period, an operation data receiving unit that receives operation data indicating operation of an operator, Stores a microprogram consisting of a multi-step microcode including a replacement code indicating that a parameter is replaced from a preset parameter to a user parameter, and outputs each microcode of the microprogram sequentially for each step. A user parameter count unit that counts the number of times parameter substitution is indicated by a replacement code included in the microcode output from the microcode output unit for each sampling period, and a count of the user parameter count unit Based on the value, A user parameter output unit that outputs a user parameter corresponding to the operation data received by the data reception unit, and a replacement code included in the microcode output from the microcode output unit indicates parameter replacement for each step. A parameter selection unit that selects a user parameter to be output from the user parameter output unit, a microcode output from the microcode output unit, and a parameter selected by the parameter selection unit, And a signal processing unit that performs signal processing on the input acoustic signal and outputs the processed acoustic signal.

  According to this invention, the replacement code included in the microcode is output for each step by the microcode output unit, and the number of times the parameter replacement is indicated by the replacement code by the user parameter count unit for each sampling period. Count. Since the user parameter output unit outputs the user parameter according to the operation data based on the count value corresponding to the number of times the parameter replacement is indicated by the replacement code, each time the parameter replacement is indicated by the replacement code, Different values can be output as user parameters according to the operation data. When the replacement code indicates parameter replacement, the user parameter output from the user parameter output unit is selected by the parameter selection unit and output to the signal processing unit.

  According to an embodiment of the present invention, the signal processing integrated circuit further includes a preset parameter output unit that sequentially outputs each preset parameter of a preset parameter set including preset parameters for a plurality of steps for each step, The parameter selection unit selects the user parameter output from the user parameter output unit when the replacement code included in the microcode output from the microcode output unit indicates parameter replacement for each step. When the replacement code does not indicate parameter replacement, the preset parameter output from the preset parameter output unit is selected.

  According to an embodiment of the present invention, the signal processing integrated circuit further includes an effect type receiving unit that receives type data specifying an effect type, and the microcode output unit stores a plurality of the microprograms. The microcode of the microprogram corresponding to the effect type specified by the type data is sequentially output for each step, and the preset parameter output unit stores a plurality of the preset parameter sets, and the type Each preset parameter of the preset parameter set corresponding to the effect type specified by the data is sequentially output for each step, and the user parameter output unit includes the effect type specified by the type data and the user parameter count unit. Based on the count value. And it outputs the user parameters according to the operation data received by the data receiving unit.

  The signal processing integrated circuit according to another embodiment of the present invention further includes an effect type receiving unit that receives type data specifying an effect type, and the user parameter output unit is received by the operation data receiving unit. A conversion table for converting operation data into user parameters is constituted by a conversion table set having a number corresponding to the number of times the parameter substitution unit counts for each sampling period is indicated, and is designated by the type data Based on the effect type and the count value of the user parameter count unit, the conversion table of the conversion table set is switched one by one, and the user parameter corresponding to the operation data based on the switched conversion table Is output.

  According to the user parameter output unit configured as described above, since the conversion table of the conversion table set is switched one by one based on the effect type specified by the type data and the count value of the user parameter count unit, each time the conversion table is switched. The operation data can be converted into user parameters and output based on conversion tables having different conversion characteristics. Therefore, each time the conversion table is switched, the user parameter for the operation data can be set to a different value.

  Furthermore, in the signal processing integrated circuit according to one embodiment of the present invention, the user parameter output unit stores a plurality of the conversion table sets, and the plurality of conversions according to the effect type specified by the type data. One of the table sets is selected, and the conversion tables of the selected conversion table set are switched one by one based on the count value of the user parameter count unit.

  According to the user parameter output unit configured as described above, a conversion table set corresponding to the effect type designated by the type data can be used among the plurality of conversion table sets.

According to a sixth aspect of the present invention, there is provided the signal processing integrated circuit according to any one of the first to fifth aspects, an input unit that inputs the acoustic signal from the outside and supplies the acoustic signal to the signal processing circuit, An operation unit is provided, operation data corresponding to the operation of the operation unit is generated, a parameter operation unit supplied to the signal processing circuit, and an acoustic signal output from the signal processing integrated circuit are output to the outside An effect imparting device including an output unit.
According to a seventh aspect of the present invention, there is provided the signal processing integrated circuit according to any one of the third or fifth aspect, an input unit that inputs the acoustic signal from the outside and supplies the acoustic signal to the signal processing circuit, A control unit that generates operation data corresponding to the operation of the control unit and supplies the operation data to the signal processing circuit; and a selection control unit. The effect providing apparatus includes a selection operation unit that generates the type data and supplies the type data to the signal processing integrated circuit, and an output unit that outputs an acoustic signal output from the signal processing integrated circuit to the outside.

  According to the present invention, the number of times the parameter replacement is indicated by the replacement code is counted for each sampling period, and the user parameter corresponding to the operation data is output based on the count value. Since each time a replacement is indicated, a different value can be output as a user parameter according to the operation data. Therefore, a simple configuration without a CPU for controlling the signal processing integrated circuit (DSP) is provided. However, the user parameters of a plurality of specific steps corresponding to the currently specified effect type are controlled to different values according to the operation data indicating the operation of the operation element, without using the DSP processing steps too much. There is an excellent effect of being able to. In addition, by using a signal processing integrated circuit (DSP) having a simple configuration that does not have a control CPU, a plurality of effect types can be selected without using many DSP processing steps. There is an excellent effect that it is possible to provide an effect applying device that can control each parameter of a specific plurality of steps to different values depending on the operation of the operator.

The block diagram which shows the structural example of the digital effector to which the signal processing integrated circuit (DSP) concerning this invention is applied. The example of the effect type mounted in the digital effector shown in FIG. 3 is a configuration example of a data set stored in each memory of the DSP of FIG. (A) is a description example of a μ program for EF processing, and (b) is a configuration example of UPT and UPTC. The block diagram explaining the content of the signal processing which DSP of FIG. 1 performs for every sampling period. The figure explaining the various timings of operation | movement of DSP of FIG. (A)-(c) is a block diagram which shows the specific example of the EF process performed in the EF process part of FIG. 5 according to the effect type. The figure explaining the timing of the operation | movement at the time of EF switching. The figure explaining the timing of the operation | movement at the time of effect provision function ON / OFF switching. The block diagram explaining the structural example of the level production | generation process which the level value production | generation part of FIG. 5 performs.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. In the embodiments described below, an example in which the signal processing integrated circuit according to the present invention is applied to an effect applying device (digital effector) that performs an effect applying process on an acoustic signal will be described. In this specification, the digital acoustic signal is also referred to as “waveform data”.

<< Overall structure of effector >>
FIG. 1 is a block diagram for explaining the overall configuration of the digital effector according to the present invention, and shows the internal configuration of the signal processing integrated circuit in detail.
In FIG. 1, the digital effector includes a signal processing integrated circuit (DSP) 1 that performs signal processing on a digital acoustic signal (waveform data), and an analog acoustic signal (from an external source) is output to the DSP 1. An analog waveform) is converted into a digital sound signal (waveform data) and input to the DSP 1, and a digital sound signal (waveform data) output as a processing result of the DSP 1 is converted into an analog sound signal (analog waveform). An output unit for output, a user parameter adjustment operator (UP adjustment operator) 2, an effect type selection operator (EF selection operator) 3, a user parameter function on / off switch (UP on / off SW) 4, , Effect applying function ON / OFF switch (EF ON / OFF SW) 5, each component in the DSP 1 and digital effect A power switch 6 for turning on / off the supply of power to other various parts are connected. As shown in FIG. 1, the digital effector according to the present embodiment has a simple configuration that does not include a CPU for controlling the operation of the DSP 1.

The digital effector has a plurality of types of effect types, and the user can select an effect type (effector type) to be used by using the operator. The DSP 1 executes signal processing of a plurality of predetermined steps (for example, 512 steps) based on a microprogram corresponding to the effect type selected by the user at a predetermined sampling period, and inputs the audio signal to the input audio signal by the user. Gives an effect according to the selected effect type.
As will be described in detail later, the DSP 1 of this embodiment has a simple configuration that does not include a CPU for controlling the operation of the DSP 1, and does not use the processing steps of the DSP 1 so much. It is characterized in that a parameter of a specific step corresponding to the currently selected effect type among the steps can be controlled by a user parameter corresponding to the operation of the UP adjustment operator 2. (2) Another feature is that the user parameters of a specific plurality of steps corresponding to the currently selected effect type can be set to different values for each step. In this specification, “parameter” is a general term for “coefficient data” and “address data” used for signal processing.

<Input section and output section>
The input unit of the digital effector includes an analog / digital conversion unit (ADC) 7 and two analog waveform input channels. Each of the two input channels is provided with level controls 8 and 9 for adjusting the volume level of the input analog waveform. The mixing unit 10 adds up the analog waveforms for each channel whose levels have been adjusted by the level operators 8 and 9, and outputs the combined analog waveform for one channel. The outputs of the level operators 8 and 9 of each input channel are input to the mixing unit 10 and branched to an output unit described later. This is because the output unit mixes the original sound before applying the effect (so-called DRY signal) and the signal after applying the effect (so-called WET signal). Further, a level operator 11 that adjusts the level of the output signal of the mixing unit 10 is provided at the subsequent stage of the mixing unit 10 of the input unit. By adjusting the level of the output signal of the mixing unit 10 by the level operator 11, the level of the signal after applying the effect (so-called WET signal), that is, the ratio of the WET signal in the output signal of the digital effector is adjusted.

  The analog-to-digital converter (ADC) 7 has two input channels, and an analog waveform for one channel output from the mixing unit 10 of the input unit is input to one input channel (for example, R channel), An analog signal (operation value data SD) corresponding to the operation position of the parameter operation operator (UP adjustment operator) 2 is input to the other input channel (for example, L channel). The ADC 7 converts the input analog waveform and the analog signal indicating the operation of the UP adjustment operator 2 into a digital signal having a predetermined sampling frequency. The converted digital signal (2ch serial signal) is output from the ADC 7 every predetermined sampling period and input to the DSP 1.

  The output unit of the digital effector includes a digital-analog converter (DAC) 12 and two output channels. From the DSP 1, an effect-added digital acoustic signal (WET signal) for two channels is output for each sampling period, and is input to the DAC 12. The DAC 12 converts the two-channel digital sound signal (WET signal) input from the DSP 1 into the analog waveform (WET signal) for each sampling period, and outputs the converted analog waveform for each channel to two output channels. Are distributed and output one by one. Each of the two output channels is provided with mixing units 13 and 14. In each mixing unit 13 and 14, an effected analog waveform (WET signal) output from the DAC 12 for each channel and an input unit are provided. The original sound (DRY signal) for each channel supplied from is summed, and the summed analog waveform is output for each channel. The mixing ratio of the DRY signal and the WET signal in each of the mixing units 13 and 14 is adjusted by the level operator 11 provided in the input unit.

<Operators>
The user parameter adjustment operator (UP adjustment operator) 2 is an operator for adjusting the value of the parameter (coefficient data or address data) of the effect applying process executed by the DSP 1 by a user operation. In the present specification, a parameter controlled using the UP adjustment operator 2 is referred to as a “user parameter”, and a function thereof is referred to as a “user parameter function (UP function)”. For user parameters, parameters stored in advance in a ROM, which will be described later, are referred to as “preset parameters”. In this embodiment, the UP adjustment operator 2 is constituted by a rotary switch with a knob, for example, and generates a plurality of bits of operation value data SD (operation data) corresponding to the operation position and outputs it to the DSP 1. When the user operates the UP adjustment operator 2, operation value data SD (analog signal) corresponding to the operation position is output to the ADC 7. That is, the UP adjustment operator 2 and the ADC 7 constitute a parameter operation unit that generates operation data according to the operation of the operator and supplies the operation data to the DSP 1.

  The effect type selection operator (EF selection operator) 3 is an operator for selecting one effect type from among a plurality of predetermined effect types (effector types) by a user operation. The EF selection operator 3 is composed of, for example, a rotary switch with a knob, generates a multi-bit effect type selection code EFT (type data) corresponding to the operation position, and outputs it to the DSP 1. The effect type selection code EFT is a plurality of codes corresponding to each of a plurality of effect types mounted on the digital effector, that is, type data designating an effect type. When the EF selection operator 3 is operated by the user, an effect type selection code EFT corresponding to the operation position is supplied to the first selection circuit 21 in the DSP 1. That is, the EF selection operator 3 constitutes a selection operation unit that generates the type data corresponding to the operation and supplies it to the DSP 1.

  The UP on / off SW 4 is a switch for switching between use / non-use of the parameter adjustment function (user parameter (UP) function) using the UP adjustment operator 2, and the UP on / off SW 4 is in the switch off state. A control signal UPON of “high level (H)” indicating use of the function and a control signal UPON of “low level (L)” indicating non-use of the UP function in the switch ON state are supplied to the first selection circuit 21. Output. Note that the terminal for inputting the control signal UPON from the UP on / off SW 4 is connected to the pull-up resistor 4 a inside the DSP 1, so that if nothing is connected to the terminal, the control signal UPON is always “H”. “(UP use)”, and the UP function can be fixed to “valid”. If the terminal is grounded, the control signal UPON becomes “L” (UP not used), and the UP function can be fixed to “invalid”.

  The EF on / off switch 5 is a switch for switching the effect imparting function of the DSP 1 to “on” or “off” (whether or not the effect imparting is valid), and the effect imparting function is activated according to the off / on state of the switch. A control signal EFON that indicates “on” or “off” with two values of “high level (H”) or “low level (L)” is output. When the EF on / off switch SW5 is in the off state, the control signal EFON is “H” indicating “on” of the DSP1 effect imparting function, and “L” indicating “off” of the DSP1 effect imparting function in the switch on state. " When the effect imparting function of the DSP 1 is turned off by the EF on / off SW5, the output signal of the digital effector is only the original sound (DRY signal). Note that the terminal to which the control signal EFON from the EF on / off switch 5 is input is connected to the pull-up resistor 5a in the DSP 1, so that if nothing is connected to the terminal, the control signal EFON is “H”. It is fixed by (effect imparting function on).

<< Configuration of DSP >>
Next, the detailed configuration inside the DSP 1 shown in FIG. 1 will be described. Each block indicated by reference numerals 21 to 31 in FIG. 1 is a microprogram memory, a data memory, or the like. The CPU performs switching control of a microprogram for signal processing executed by the DSP 1 and parameter control for each step of signal processing. This is a constituent element for performing by the DSP 1 itself, not the control by the control. In addition, each block indicated by reference numerals 40 to 52 in FIG. 1 is a component that constitutes an arithmetic unit that performs signal processing on waveform data. Each block denoted by reference numerals 53 to 55 is a component that generates data for accessing the delay memory. Therefore, each part shown with the code | symbol 40-55 is equivalent to the signal processing part which performs a signal processing to the acoustic signal input into DSP1, and outputs the acoustic signal by which the signal processing was carried out.

  The clock generation circuit 20 generates a clock signal using a crystal resonator. The clock signal generated by the clock generation circuit 20 is an operation clock Φo, a word clock signal (WC signal), a C / E signal, or the like as an operation reference of the DSP 1. The operation clock Φo is a clock signal for each step cycle of signal processing to be described later, and each part of the DSP 1 operates based on the operation clock Φo. The WC signal is a clock signal having a waveform data sampling period, and the DSP 1, ADC 7, and DAC 12 each perform an operation synchronized with the sampling period based on the WC signal. The C / E signal is used to control the timing of switching between effect processing (EF processing) and constant processing (C processing) other than EF processing, among signal processing of a predetermined number of steps executed by the DSP 1 for each sampling period. Signal.

  The first selection circuit 21 receives an effect type selection code EFT corresponding to the operating position of the EF selection operator 3, and in accordance with the input effect type selection code EFT, the μ program selection signal μPsel, user parameter type designation A signal UPT, a coefficient set selection signal Csel, an address data selection signal Asel, a conversion table set selection signal Tsel, and a user parameter range control signal UPR are output. That is, the first selection circuit 21 is an effect type reception unit that receives type data (EFT) that specifies an effect type (effect type). When the user operates the EF selection operator 3 to specify an effect type, the reception unit receives type data (EFT) corresponding to the operation, and an effect type switching process is performed. The effect type is selected. The timing for executing this effect type switching process is controlled by a CHG signal and an ACK signal, as will be described in detail later.

  When the UP function is used (UPON = “H”), the first selection circuit 21 sends a user parameter type designation signal UPT corresponding to the currently selected effect type (EFT) to the second selection circuit 26. Output. The user parameter type designation signal UPT is a signal composed of a code for designating a “type” of a user parameter (coefficient data or address data) according to the currently selected effect type, and a plurality of types of coefficient data are selected. There are signals (codes) to be specified, and there are signals (codes) to specify a plurality of types of address data. When the control signal UPON indicates that UP is not used (UPON = “L”), a second signal indicating “UP not used” is used as the user parameter type designation signal UPT regardless of the currently selected effect type. By outputting to the selection circuit 26, the UP function is invalidated.

  The micro program memory (μ program memory) 22 is a ROM that stores a plurality of micro programs (μ programs) composed of micro codes (μ codes) of a predetermined plurality of steps (for example, 512 steps). In the μ program memory 22, one μ program corresponding to the currently selected effect type (EFT) is selected from a plurality of μ programs based on the μPsel signal supplied from the first selection circuit 21. The μ program memory 22 executes the signal processing step period (the period for executing the μ code) indicated by the operation clock Φo in order to execute a predetermined plurality of steps (for example, 512 steps) μ code in one sampling period. From the address of the μ program memory 22, the μ code of the μ program corresponding to the effect type designated by the EFT is sequentially output step by step. That is, the μ program memory 22 is a microcode output unit.

  The μ code for one step is constituted by a set of control signals for each of a plurality of components of the DSP 1. Each control signal included in the μ code for one step includes blocks (operation units indicated by reference numerals 40 to 52, the operation value register 30 and the RAD register 55), adder 53, Each of the selection circuits 26 is output to a corresponding one. The μ program memory 22 is connected to each of the output destinations of these control signals by control lines. However, for the sake of simplicity of illustration, these control lines are not shown and a plurality of arrows drawn from the μ program memory 22 are used. We expressed the purpose by drawing.

  In FIG. 1, only the control lines for outputting the user parameter type code UPTC from the μ program memory 22 to the second selection circuit 26 among the control lines for outputting the respective control signals from the μ program memory 22 are clearly shown. The code UPTC is a plurality of control signals (codes) for instructing the “type” of the user parameter (coefficient data or address data) according to the currently selected effect type, and the user parameter type designation signal UPT and Similarly, there are a control signal (code) indicating a plurality of types of coefficient data and a control signal (code) indicating a plurality of types of address data. As will be described later, the code UPTC functions as a code for selecting a user parameter in a specific step corresponding to the effect type, that is, a “replacement code” for instructing “parameter replacement” used for signal processing. Note that “parameter replacement” refers to replacing preset parameters with user parameters.

  The coefficient memory 23 is a ROM that stores a plurality of coefficient sets including preset coefficient data PC for a predetermined plurality of steps (for example, 512 steps). In the coefficient memory 23, based on the Csel signal supplied from the first selection circuit 21, one coefficient set corresponding to the currently selected effect type (EFT) is selected from the plurality of coefficient sets, and the signal Preset coefficient data PC of the selected coefficient set is sequentially output step by step from the address of the coefficient memory 23 for each processing step cycle. That is, the coefficient memory 23 is a preset parameter output unit.

  The address memory 24 is a ROM that stores a plurality of address sets including preset address data PA for a plurality of steps. In the address memory 24, an address set corresponding to the currently selected effect type (EFT) is selected from the plurality of address sets based on the Asel signal supplied from the first selection circuit 21, and the delay memory 50 is selected. The preset address data PA of the selected address set is sequentially output step by step from the address of the address memory 24 for each step to be accessed. That is, the address memory 24 is a preset parameter output unit.

  The conversion table memory 25 is a ROM that stores a plurality of conversion table sets. Each of the plurality of conversion table sets includes a plurality of conversion tables, and each conversion table stores operation value data of the UP adjustment operator 2 (operation value data XD supplied from a range control unit 31 described later). It is a data table for converting into a user parameter and outputting. In the conversion table memory 25, a conversion table set corresponding to the currently selected effect type (EFT) is selected from a plurality of conversion table sets based on the Tsel signal supplied from the first selection circuit 21, and One conversion table in the conversion table set is selected based on a count value UPC generated by an UP counter 29 to be described later, and an UP adjustment operator 2 is selected based on the selected conversion table for each step cycle of signal processing. Is converted into user parameters (user coefficient data UC or user address data UA) and output. That is, the conversion table memory 25 constitutes a user parameter output unit that outputs user parameters in accordance with the operation of the operator.

  The second selection circuit 26 receives the user parameter type designation signal UPT output from the first selection circuit 21 and the user parameter type code UPTC output from the μ program memory 22 and receives UPTC for each step cycle of signal processing. A selection signal (first selection signal P / U1 or second selection signal P / U2) based on UPT is output to selectors 27 and 28 in the subsequent stage. The selection signal for the coefficient data selector 27 is “first selection signal P / U1”, and the selection signal for the address data selector 28 is second selection signal P / U2.

  The first selection signal P / U1 and the second selection signal P / U2 are binary signals each taking either a high level or a low level. The second selection circuit 26 outputs the first selection signal P / U1 of “H” level to the coefficient data selector 27 in a step in which UPTC matches with the same type coefficient type code as UPT. Further, the second selection circuit 26 outputs the second selection signal P / U2 of “H” level to the address data selector 28 in the step in which UPTC matches with the same address type code as UPT. In other cases, the first selection signal P / U1 and the second selection signal are each at the “L” level.

  When the first selection signal P / U1 supplied from the second selection circuit 26 is “H” level for each signal processing step cycle, the coefficient data selector 27 matches the coefficient type code of the same type as UPTC (UPTC). When the user coefficient data UC output from the conversion table memory 25 is selected, and the first selection signal P / U1 supplied from the second selection circuit 26 is at the “L” level, the coefficient memory 23 The output preset coefficient data PC is selected. One of the preset coefficient data PC and the user coefficient data UC selected by the coefficient data selector 27 is output to the fourth selector 45 as the coefficient data CD used for the multiplication of the multiplication unit 47. In other words, the second selection circuit 26 and the coefficient data selector 27 perform conversion for each step based on the type data (UPT corresponding to the effect type specified by the EFT) and the UPTC output from the μ program memory 22. A parameter selection unit for selecting a parameter to be output from either the table memory 25 or the coefficient memory 23 is configured.

  When the second selection signal P / U2 supplied from the second selection circuit 26 is at “H” level for each step cycle of signal processing, the address data selector 28 matches (UPTC is the same type of address type code as UPT). When the user address data UA output from the conversion table memory 25 is selected and the second selection signal P / U2 supplied from the second selection circuit 26 is “L” level, the user address data UA is output from the address memory 24. Selected preset address data PA is selected. One of the preset address data PA and the user address data UA selected by the address data selector 28 is output to the adder 53 as address data AD used for generating memory address data MAD for accessing the delay memory 50. The In other words, the second selection circuit 26 and the address data selector 28 perform conversion for each step based on the type data (UPT corresponding to the effect type specified by the EFT) and the UPTC output from the μ program memory 22. A parameter selection unit for selecting a parameter to be output from either the table memory 25 or the address memory 24 is configured.

  The UP counter 29 is connected to the output line of the first selection signal P / U1 and the output line of the second selection signal P / U2 of the second selection circuit 26, and is reset for each sampling period, Each time the first selection signal P / U1 or the second selection signal P / U2 of “H” level is output from the selection circuit 26, a count value UPC that is incremented by one is generated, and the generated count value UPC is generated. Is output to the conversion table memory 25. That is, the UP counter 29 counts the number of steps in which UPT and UPTC match, in other words, the number of times “parameter replacement” is instructed by UPTC.

The operation value register 30 operates the UP adjustment operator 2 supplied via an arithmetic unit (such as TempRAM 43) of the DSP 1 to be described later, based on the μ code output from the μ program memory 22 at each signal processing step period. The value data SD is held, and the operation value data SD is supplied to the range control unit 31. That is, the operation value register 30 corresponds to an operation data receiving unit that receives operation value data SD (operation data) corresponding to the operation position of the UP adjustment operator 2 in the DSP 1.
The operation value register 30 is connected to the output line of the second selection signal P / U2 of the second selection circuit 26, and receives the second selection signal P / U2. This is a configuration for controlling the timing of changing the value of the user address data UA in accordance with the operation of the UP adjustment operator 2 using a CHG signal and an ACK signal, which will be described later.

  The range control unit 31 receives the user parameter range control signal UPR corresponding to the effect type designated by the user and the operation value data SD of the UP adjustment operator 2. Since the variable range (range) of the operation value data SD output from the UP adjustment operator 2 corresponds to the movable range of the UP adjustment operator 2, the range control unit 31 sets the variable range (range) according to the effect type. Convert to the variable range. The range control unit 31 performs range control on the input operation value data SD to a value corresponding to the variable range of the parameter corresponding to the effect type indicated by the UPR, and the range-controlled operation value data XD is sent to the conversion table memory 25. Output. That is, the range control unit 31 constitutes a user parameter output unit that outputs user parameters in accordance with the operation of the operator.

<< Configuration of signal processing unit >>
The configuration of the calculation unit (block indicated by a dotted line) of the DSP 1 is generally the same as that of the conventional one. Each part of the arithmetic unit of the DSP 1 is controlled based on a control signal included in the μ code output from the μ program memory 22 for each step period of signal processing. Hereinafter, the control signal supplied to each part (i) of the DSP 1 is represented as “control signal (i)”. Note that “i” is a symbol assigned to each part.
The first selector 40, in response to the control signal (40), 2ch input data (waveform data and operation value data of the UP adjustment operator 2) input from the ADC 7 via the S / P converter 56, One of the data on the bus 49 is selected, and the selected data is output to the input / output RAM (I / O RAM) 41. In response to the control signal (41), the input / output RAM 41 stores the data from the first selector 40 at the address indicated by the control signal (41), or reads and outputs the data from the address indicated by the control signal (41). To do. The input / output RAM 41 also stores input data for two channels input from the ADC 7 via the S / P converter 56, waveform data to be output to the DCA 12 by converting the P / S converter 57, and the like. In response to the control signal (42), the temporary RAM (TempRAM) 42 stores the output data of the bus 49 and the read data MRD from the delay memory 50 at the address indicated by the control signal (42) or the control signal (42). Data is read from the address indicated by The temporary RAM 42 stores operation value data to be passed to the register 30 in addition to data during signal processing.

  The second selector 43 receives the output of the input / output RAM 41, the temporary RAM 42, and the output of the bus 49, and selects and adds one of these three input data according to the control signal (43). Supply to one input of unit 46. The third selector 44 receives the output of the input / output RAM 41 and the output of the temporary RAM 42, selects either of them according to the control signal (44), and supplies it to one input of the multiplier 47. The fourth selector 45 receives the coefficient data CD output from the coefficient data selector 27 and the output of the bus 49, and selects one of them according to the control signal (45). Supply to the input.

  The adder 46 adds the output of the second selector 43 and the output of the multiplier 47 and outputs the result to the shifter 48. It is also possible to force the output to zero in response to the control signal (46). The multiplier 47 multiplies the output of the third selector 44 and the output of the fourth selector 45 at high speed. The shifter 48 shifts the output of the adder 46 by the number of bits indicated by the control signal (48) and outputs the result to the bus 49.

  The delay memory 50 is a memory used for delaying the digital waveform data, and is constituted by an internal memory provided in the DSP 1. The delay memory 50 is accessed using the memory address data MAD based on the control signal (50), and reads waveform data (memory read data) MRD from the address MAD of the delay memory 50 according to the contents of the control signal, Alternatively, the waveform data (memory write data) MWD is written to the address MAD of the delay memory 50.

  The write data register 51 takes in the waveform data (memory write data) MWD on the bus 49 based on the control signal (51) and outputs the memory write data MWD to the delay memory 50. The read data register 52 stores the waveform data (memory read data) MRD read from the delay memory 50 based on the control signal (52), and outputs the memory read data RD waveform data to the temporary RAM 42. .

《Delay memory address generation》
The adder 53 adds the address data AD output from the address data selector 28, the count value SC output from the sample counter 54, and the register address data RAD output from the RAD register 55 for each step. Then, memory address data MAD used for accessing the delay memory 50 is generated. The memory address MAD is controlled so as to return the address indicated by the memory address MAD to the head address of the delay memory 50 by truncating the upper bit data indicating the predetermined upper address of the delay memory 50. By this upper bit truncation control, the delay memory 50 can be used as a ring memory.

  The sample counter 54 is a counter that counts down one by one for each sampling period and outputs a count value SC. In the adder 53, by adding the count value SC of the sample counter 54 to the address data AD, the memory address data MAD at each step can be shifted by one address every sampling period.

  Based on the control signal (55), the RAD register 55 takes in the data output to the bus 49 in a predetermined step as register address data RAD, and outputs the register address data RAD to the adder 53. The register address data RAD is data for converting the memory address data MAD output from the adder 53 in order to modulate the delay time in a modulation type effect type such as a chorus register address effect or a flanger effect. By adding the register address data RAD to the address data AD in the adder 53, the delay time of the delay sound read out by the memory address data MAD can be periodically modulated according to the register address data RAD.

  A serial / parallel conversion unit (S / P conversion unit) 56 converts a 2-channel serial signal (operation value data SD and waveform data of the UP adjustment operator 2) input from the ADC 7 at each sampling period into a parallel signal. , Output to the first selector 40. The two-channel data output to the first selector 40 is input with the waveform data address input to the input / output RAM 41 based on the control signal (40) and control signal (41) of a predetermined step. Stored in the address for the operation value data. The parallel-serial converter (P / S converter) 57 receives 2-channel waveform data read from an address for waveform data to be output from the input / output RAM 41 based on a control signal 41 in a predetermined step. Entered. The P / S converter 57 converts the input 2-channel waveform data (parallel signal) into a 2-channel serial signal, and outputs it to the DAC 12 for each sampling period.

《Effect types to be listed》
FIG. 2 is a diagram for explaining a plurality of types of effects mounted on the digital effector having the above-described configuration. In FIG. 2, the “TYPE” column shows the type names of a plurality of effect types mounted on the digital effector. Any one of these multiple types of effect types is selected based on the effect type selection code EFT. The right column of “TYPE” is the “PRG.” Column, which indicates the μ program used in the corresponding effect type. The right column of the “PRG.” Column is the “RANGE” column, which indicates the range of parameters controlled by the corresponding effect type (variable range: how many values the parameter can take). Yes. In the drawing, for the sake of convenience, a different alphabet character is shown in the “RANGE” column for each effect type to indicate that the range of parameter values differs for each effect type. Although not shown, the parameter type (coefficient or address) and value (conversion curve) to be controlled by the user parameter are also set for each effect type.

  For example, the type names “Reverb1”, “Reverb2”, and “Reverb3” are different types of reverberation effects, and these effect types use a common reverb μ program “Rev. (Reverb)”. Is shown in the figure. As shown in the “RANGE” column, “Reverb1”, “Reverb2”, and “Reverb3” have different parameter ranges. For example, the type names “Ehco1” and “Ehco2” are different types of echo effects, and the parameter ranges are different as shown in the “RANGE” column. The reverb μ program “Rev.” is also used for these echo effect types.

<Memory configuration>
FIG. 3 is a diagram illustrating the configuration of a plurality of data sets stored in each of the μ program memory 22, the coefficient memory 23, the address memory 24, and the conversion table memory 25 in FIG. The plurality of data sets stored in each of the memories 22 to 25 are roughly classified into a data set for “C processing” and a data set for “EF processing”.
“EF processing” refers to signal processing (effect imparting processing) in which processing content is converted based on an effect type selection code EFT in signal processing of a program executed in one sampling period. The “C processing” is “constant processing” that does not depend on the value of the effect type selection code EFT, such as input / output control of waveform data, input / output filter processing for input / output waveform data, or level control processing. is there. The DSP 1 executes “C processing” for a predetermined Nc step and “EF processing” for a predetermined Nef step in a time division manner for each sampling period. That is, the sum of Nc and Nef is a predetermined plurality of steps (512 steps). Since the processing to be mainly performed by the DSP 1 is “EF processing”, Nc is set to have a smaller number of steps than Nef.

  The μ program memory 22 stores one μ program for C processing and a plurality of μ programs for EF processing. The C processing μ program is composed of Nc steps of microcode (μcode) stored in predetermined Nc addresses. Each EF processing μ program is composed of N codes corresponding to Nef steps stored at predetermined Nef addresses. The EF processing μ program μ code includes a user parameter type code UPTC and an access code for the delay memory 50, but the C processing μ program does not include these codes.

  The μ program for C processing is commonly used for all effect types. As for the EF processing μ program, one EF processing μ corresponding to the currently selected effect type based on the Psel signal supplied from the first selection circuit 21 among the plurality of EF processing μ programs. A program is selected. Since the same EF processing μ program may be shared by a plurality of effect types, the number of EF processing μ programs stored in the μ program memory 22 is based on the total number of effect types installed in the digital effector. There are few.

  The coefficient memory 23 stores one coefficient set for C processing and a plurality of sets of coefficient sets for EF processing corresponding to each of the selectable effect types. The coefficient set for C processing includes preset coefficient data for Nc steps stored at predetermined Nc addresses. Each EF processing coefficient set is composed of preset coefficient data for Nef steps stored at predetermined Nef addresses. The coefficient set for C processing is commonly used for all effect types. As for the EF processing coefficient set, one EF processing coefficient set corresponding to the currently selected effect type is selected from the plurality of EF processing coefficient sets based on the Asel signal supplied from the first selection circuit 21. A coefficient set is selected. One set of EF processing coefficient sets is prepared for each effect type listed in the digital effect.

  The address memory 24 stores only a plurality of EF processing address sets. Basically, one set of EF processing address sets is prepared for each effect type listed in the digital effect. However, an effect type that does not perform delay processing using the delay memory 50 (EF processing). No address set is required for the μ code of the program for use without the access code). One EF processing address set corresponding to the currently selected effect type is selected from the plurality of EF processing address sets based on the Asel signal supplied from the first selection circuit 21. Since access to the delay memory 50 is performed only by EF processing, an address set for C processing is not required.

  Each address set is composed of preset address data corresponding to the number of steps for accessing the delay memory 50 in the effect type EF processing corresponding to the address set. “The number of steps to access the delay memory 50” means “the access code for the delay memory 50” (“data read instruction”) in the μ code for each step of the μ program for EF processing used in the effect type corresponding to the address set. Or “data write command”) (see FIG. 4A described later). Therefore, the number of address data included in the address set is smaller than the number of steps (Nef step) of the EF processing μ program.

  The conversion table memory 25 stores a plurality of sets of conversion table sets for EF processing corresponding to each of a plurality of selectable effect types. One conversion table set is prepared for each effect type listed in the digital effect. One conversion table set corresponding to the currently selected effect type is selected from the plurality of conversion table sets based on the Tsel signal output from the first selection circuit. Note that the user parameter control using the operation value data XD is performed only in the EF process, so that a conversion table set for the C process is unnecessary.

  Each conversion table set includes a plurality of conversion tables corresponding to the number of steps using user parameters (user coefficient data UC or user address data UA) among a plurality of steps (Nef steps) of the EF processing of the effect type. Consists of. The data size of the conversion table in each conversion table set corresponds to the range of the operation value data XD corresponding to the effect type corresponding to the conversion table set. The wider the range of operation value data XD, the larger the size of each conversion table in the conversion table set corresponding to that effect type. The narrower the range of operation value data XD, the more conversion table set corresponding to that effect type. The size of each conversion table becomes smaller. Therefore, the number of conversion tables included in each conversion table set and the data size of the conversion table differ for each effect type.

  Each conversion table converts the operation value data XD of the UP adjustment operator 2 into a user parameter, and uses a user parameter in a plurality of steps of the EF process based on the count value UPC generated by the UP counter 29. One sheet is switched for each step. By using conversion tables having different conversion characteristics for each step using the user parameter, the operation value data XD of the UP adjustment operator 2 can be controlled to a different value for each parameter of the step using the user parameter. Become.

<< Micro program for EF processing >>
FIG. 4A shows a description example of one EF processing μ program among a plurality of EF processing μ programs stored in the μ program memory 22. As shown in FIG. 4A, in one EF processing μ program, one μ code is stored in each of a total of Nef addresses from the 0th address to the Nef address, and stored in one address. The μ code is output at every signal processing step cycle. The μ code of each step includes control for each block (operation unit indicated by reference numerals 40 to 52, a register indicated by reference numeral 31), the second selection circuit 26, and each part of the adder 53, which are drawn by dotted lines in FIG. Although a signal is included, FIG. 4A shows only a part of the signal for convenience of illustration.

  Of the μ code in the EF processing μ program, the control signal “UPTC” is a user parameter type code UPTC output to the second selection circuit 26, and is a 3-bit binary value that can specify eight types. Consists of. A UPTC value is set for each address from the 0th address to the Nef address. For example, in FIG. 4A, the value of “UPTC” of the 0th address is “111”, whereas the value of “UPTC” of the second address is “010”, and for each address, Different parameter types are set.

  The control signal (50) “delay RAM” in the μ code is an access code for the delay memory 50. The access code for the delay memory 50 is constituted by a 2-bit binary value indicating a data read instruction from the delay memory 50, a data write instruction to the delay memory 50, or three instructions indicating no access. Among the Nef steps of the EF processing μ program, a step in which a data read command or a data write command is entered as an access code is a “step for accessing the delay memory 50”. For example, if the value of the control signal “delay RAM” is “01” indicating a read command and “10” indicates a write command, the first address, the third address, etc. in FIG. It is shown in the figure that “the step of accessing the memory 50” and “the step of accessing the delay memory 50” are only a part of the Nef step.

<< UPTC and UPT >>
FIG. 4B is a diagram illustrating a configuration example of the user parameter type code UPTC user parameter type designation signal UPT included in the μ code and the user parameter type designation signal UPT output from the first selection circuit 21. As described above, UPTC and UPT are codes indicating the “type” of a parameter (coefficient data or address data). Numbers “0” to “7” are assigned to the eight types of UPT and UPTC shown in FIG.

  In (b), UPTC “0”, “1”, and “2” are assigned to different coefficient type codes (type 1 coefficient to type 3 coefficient), respectively. Further, UPTC “4”, “5”, and “6” are assigned to different address type codes (type 1 address to type 3 address), respectively. Also, UPTC “7” is assigned a NOP instruction (no type designation process), and UPTC “3” is not used as a code (Don't use).

  Similarly to UPTC, “0”, “1”, and “2” of UPT are assigned to different coefficient type codes (type 1 coefficient to type 3 coefficient), respectively, and user parameter type designation signal UPT. “4”, “5”, and “6” are assigned to different address type codes (type 1 address to type 3 address) as in the case of UPTC. Further, UPT “3” is assigned to UP non-use (UPON = L), and UPT “7” is not used as a code (Don't use).

  In FIG. 4B, UPT and UPTC assigned the same numbers “0” to “7” are codes corresponding to (matching) with each other. When the UP function is used (UPON = H), the UPT corresponding to the effect type currently selected by the EF selection operator 3 is output. Therefore, a plurality of μ programs for EF processing corresponding to the effect type are output. Among the steps, a step in which a UPTC corresponding to (matching) the UPT is set is a step using user parameters among a plurality of steps of the EF processing. That is, which of the plurality of EF processing steps corresponds to the step using the user parameter in the currently selected effect type depends on the value of UPTC set for each step of the EF processing μ program. Identified. In this sense, the UPTC that matches the UPT corresponding to the currently selected effect type functions as a “replacement code” indicating “parameter replacement”.

  On the other hand, when the UP function is not used (UPON = L), “3” is output as the UPT value, but the corresponding UPTC “3” is not used as a code. The UPTC never matches. Therefore, as a result, the preset parameter is always selected by the coefficient data selector 27 and the address data selector 28, and the UP function is not used. In addition, since UPTC “7” is assigned to the NOP instruction, the preset parameter is always selected by the coefficient data selector 27 and the address data selector 28 in any effect type in the step of the μ code where the value is set. Will be.

<< Contents of signal processing executed by DSP1 >>
FIG. 5 is a block diagram illustrating the contents of signal processing executed by the DSP 1 having the above-described configuration for each sampling period. In FIG. 5, the processing of each block surrounded by a dotted line is performed based on the control signal included in the μ code output from the μ program memory 22 for each step period of signal processing. Each section indicated by ˜52) is executed.
In FIG. 5, each hatched block is a block related to EF processing based on the μ program for EF processing in signal processing. The contents of data and signal processing in each block relating to these EF processes differ depending on the effect type currently selected based on the effect type selection code EFT. The other blocks shown in white are blocks related to C processing. The contents of signal processing in each block relating to the C processing are common to all effect types.

  From the ADC 7, a 2-channel digital signal obtained by converting a 2-channel analog signal of the input analog waveform and the operation value data SD of the UP adjustment operator 2 into a digital signal at a predetermined sampling frequency is obtained for each sampling period. Is output to DSP1. Of the two-channel (Lch and Rch) digital signals, waveform data is assigned to Rch, and operation value data SD is assigned to Lch.

<< C processing on input side >>
The Rch input unit 60 inputs the waveform data from the ADC 7 by performing processing for taking the R channel data from the S / P conversion unit 56 into the input / output RAM 41. The HPF processing and level control unit 62 performs high-pass filter processing on the waveform data input by the Rch input unit 60, and further controls the level of the waveform data with a level value generated by a level value generation unit 77 to be described later. Output the processed waveform data. The Din writing unit 63 writes the processed waveform data to the effect data processing unit (EF processing unit) 64 by writing the processed waveform data to the waveform data address to be input to the EF processing of the input / output recording RAM 41. Supply. On the other hand, the Lch input unit 61 inputs the operation value data SD from the ADC 7 by performing processing for taking the L channel data from the S / P conversion unit 56 into the input / output RAM 41. The LPF processing unit 65 performs low-pass filter processing on the operation value data SD input by the Lch input unit 61 and writes the processed operation value data SD to the processed operation value data address in the temporary RAM 42. The SD output unit 66 reads out the written operation value data SD from the temporary RAM 42 and stores the operation value data SD in the operation value register 30 to output the low-pass filtered operation value data SD to the range control unit 67. Do.

<EF treatment>
The EF processing unit 64 performs EF processing on the waveform data (monaural) written to the input / output RAM 41 by the Din writing unit 63 according to the effect type currently selected based on the effect type selection code EFT. An effect imparting process (EF process) based on the μ program is performed, and EF-processed stereo 2 channel (L channel and R channel) waveform data is obtained. A specific example of the EF processing for each effect type will be described later. Parameters used in each step of the EF processing executed by the EF processing unit 64 are controlled by coefficient data CD supplied from the coefficient supply unit 71 for each step and address data AD supplied from the address supply unit 72 for each step. The Then, the 2-channel waveform data subjected to the EF processing is written to the address for waveform data output from the EF processing of the input / output RAM 41. That is, the EF processing unit 64 is selected by the microcode output from the microcode output unit (μ program memory 22) and the parameter selection unit (second selection circuit 26, coefficient data selector 27, and address data selector 28). Based on the parameters, the input acoustic signal is subjected to signal processing, and the signal-processed acoustic signal is output.

<< C processing on output side >>
The Dout reading unit 73 reads the EF-processed two-channel waveform data for each channel from the input / output RAM 41 and outputs it to the level control unit 74. The level control unit 74 controls the level of the waveform data for each channel read by the Dout reading unit 73 based on the level value generated by the level value generation unit 77 described later, and the level-controlled waveform of the two channels. The data is written to the waveform data address to be output to the DAC 12 of the input / output RAM 41. The L channel output unit 75 and the R channel output unit 76 read the level-controlled waveform data of the two channels from the input / output RAM 41 and write them to the P / S conversion unit 57, thereby converting the waveform data of the two channels. Output to the DAC 12.

  Further, the level value generation unit 77 (FIG. 10) included in the C processing block performs level control of the HPF processing and level control unit 62 and the level control unit 74 (refer to FIGS. 8 and 9 for details). However, a level value used for (described later) is generated. The level value generator 77 generates a level value used for level control executed in the next sampling cycle. In other words, the HPF processing and level control unit 62 and the level control unit 74 perform level control using the level value generated by the level value generation unit 77 in the immediately preceding sampling cycle.

<Supplying parameters>
The range control unit 67, the conversion table unit 68, the coefficient setting unit 69, and the address setting unit 70 are blocks that perform processing for outputting parameters used for EF processing. The processing of each block is not controlled by the μ program. In FIG. 5, the purpose of not receiving control by the μ program is expressed by drawing these blocks outside the dotted line.

  The range control unit 67 corresponds to the range control unit 31 of FIG. 1, and the variable range (range) of the operation value data SD output from the SD output unit 66 is a parameter corresponding to the currently selected effect type. The operation value data XD subjected to the range control is output to the conversion table unit 68 under the control of the variable range (range).

<Switching conversion table>
The conversion table unit 68 corresponds to the conversion table memory 25 of FIG. In the conversion table unit 68, one conversion table set is selected from the plurality of conversion table sets according to the currently selected effect type, and one of the conversion table sets is selected based on the count value UPC generated by the UP counter 29. Two conversion tables are selected. As described above, the count value UPC of the UP counter 29 is reset at every sampling period, and at each step where parameter replacement is instructed by UPTC (a step in which UPTC and UPTC match, and a user parameter is used) Therefore, in the conversion table unit 68, the conversion table in the conversion table set corresponding to the currently selected effect type is converted into parameter values by UPTC in order from the beginning of the sampling period. Switching is performed one by one for each step in which replacement is instructed (for each step using the user parameter). Then, at the beginning of the next sampling cycle, the conversion table selected in the conversion table unit 68 returns to the first one, and is switched one by one for each step in which UPT and UPTC match, as in the previous time.

  As the conversion table of the conversion table unit 68 is switched based on the count value UPC of the UP counter 29 as described above, the operation value data XD of the UP adjustment operator 2 differs for each of a plurality of specific steps according to the effect type. Different values are converted by the conversion table of the conversion characteristics.

《Preset parameter output》
The coefficient setting unit 69 corresponds to the coefficient memory 23 of FIG. 1, and outputs preset coefficient data PC from each address of the coefficient set corresponding to the currently selected effect type for each step period of signal processing. To do. The address set unit 70 corresponds to an address data set corresponding to the currently selected effect type in the address memory 24 of FIG. 1, and is preset from each address of the address data set for each step cycle of the number processing. Address data PA is output. Note that the preset address data PA is data necessary only for the step of accessing the delay memory 50, and is therefore not output at every step of the EF processing.

<< Control of user parameters at specific steps >>
The coefficient supply unit 71 and the address supply unit 72 correspond to the operations of the second selection circuit 26, the coefficient data selector 27, and the address data selector 28 in FIG. That is, the coefficient supply unit 71 sets the coefficient type code (FIG. 4B) with the same UPTC output from the μ program memory 22 for each signal processing step cycle and the UPT corresponding to the currently selected effect type. The user coefficient data UC output from the conversion table unit 68 is selected in the step that matches in any one of the 1 coefficient to the type 3 coefficient), and in the other steps, the preset coefficient data PC output from the coefficient setting unit 69 is selected. The selected data is output to the EF processing unit 64 as the coefficient data CD of that step. In addition, the address supply unit 72 uses the same type of address type code (FIG. 4B) as the UPTC output from the μ program memory 22 for each step period of signal processing and the UPT corresponding to the currently selected effect type. The user address data UA output from the conversion table unit 68 is selected at the step that matches with any one of the 1 address to the type 3 address), and the preset address data PA output from the address set unit 70 is selected at the other steps. Then, the selected data is output to the EF processing unit 64 as the address data AD of that step.

  Therefore, when the UP function is used, the EF processing unit 64 uses the parameter of the specific step according to the currently selected effect type (the step in which UPT and UPTC match) as the operation value data of the UP adjustment operator 2. It becomes possible to control by user parameters (user coefficient data UC or user address data UA) according to XD. Since a step in which UPTC and UPTC match, that is, a step using user parameters, is determined by a combination of the UPTC for each step of the μ program for EF processing and the UPT corresponding to the currently selected effect type, a plurality of effect types are determined. Even when the same EF processing μ program is shared, the parameters of a specific step can be used as user parameters for each effect type.

<Operation timing>
The timing at which the DSP 1 executes the signal processing shown in FIG. 5 will be described with reference to the timing diagram of FIG. In FIG. 6, the horizontal axis is time. The operation clock Φo in FIG. 6A indicates the signal processing timing for each step by counting the count values for a plurality of steps (512 steps) of the μ program processing executed by the DSP 1 for each sampling period. (B) is a word clock signal (WC signal), which is a clock signal for each sampling period. (C) is a C / E signal for controlling the switching timing of the C process and the E process in one sampling period, and is a period of Nc steps in the first half of one sampling period (Nc steps from the rising edge of the WC signal). "C" (high level) pulse is generated in the period of minutes, and "E" (low level) in the period of Nc steps thereafter.

  (D) shows the input timing of the 2-channel serial signal serially transmitted from the ADC 7 to the DSP 1 for each sampling period. As shown in (d), the rising edge of the WC signal indicates the beginning of the Lch data, the falling edge indicates the beginning of the Rch data, and within one half cycle of the WC signal, a sample of data for one channel is obtained. The signal is input to the S / P converter 56 of the DSP 1.

  (E) shows the switching timing of the C process and the EF process in the μ program process executed by the DSP 1 for each sampling period. The rising timing of the C / E signal (timing rising to the C side) indicates the start of C processing, and the falling timing indicates the start of EF processing. That is, C processing for Nc steps is executed during the C output period of the C / E signal, and EF processing for Nfe steps is executed during the E output period of the C / E signal.

  (F) shows the output timing of the 2-channel serial signal serially transmitted from the DSP 1 to the DCA 12 for each sampling period. The Lch of the serial signal is assigned to the L channel of the 2-channel waveform data output from the EF processing unit 64 of FIG. 5 via the level control unit 74, and Rch is the R channel of the 2-channel waveform data of stereo. Assigned. As shown in (f), the data for one channel of the stereo signal is output from the P / S converter 57 of the DSP 1 within a half cycle of the WC signal. In the illustrated example, the falling timing of the WC signal indicates the end of the Lch data, and the rising timing indicates the end of the Rch data.

  In the lane indicating the input of the serial signal in (d), the data input in the first sampling cycle shown at the left end in the drawing is indicated by a bold line. In the lane indicating the μ program processing in (e), the C processing and EF processing executed in the second sampling cycle are indicated by bold lines, and a downward arrow is drawn at the head of the sampling cycle. This indicates that in the μ program processing of the second sampling period, signal processing is performed on the data sample input in the immediately preceding first sampling period. In addition, in the lane indicating the input of the serial signal in (f), data output in the third sampling period is indicated by a bold line, and a downward arrow is drawn at the head of the sampling period. This indicates that in the third sampling period, the waveform data subjected to the μ program processing in the immediately preceding second sampling period is output to the DCA 12.

  An example of the procedure of μ program processing executed by the DSP 1 for each sampling period will be described. First, in the C process, the 2-channel waveform data subjected to the EF process in the immediately preceding sampling cycle is read by the Dout reading unit 73, and the level is controlled by the level control unit 74, so that the L channel output unit 75 and the R channel output unit 76 Thus, the level-controlled 2-channel waveform data is output to the P / S converter 57 (DAC 12). After performing this output processing, waveform data to be signaled in the sampling cycle (that is, data serially input from the ADC 7 in the immediately preceding sampling cycle) is taken from the S / P converter 56 by the Rch input unit 60, The HPF processing and level control unit 62 performs high-pass filter processing and level control, the Din writing unit 63 writes to the EF processing unit 64, and further generates a level value to be used in the next sampling cycle. This is performed by level value generation 77. Up to this point, the C processing is performed by executing the μ code of the Nc step of the C processing μ program in the first half of the sampling period corresponding to the Nc step. Subsequently, by executing the Nef step μ code of the EF processing μ program, Nef step signal processing is performed on the data input from the ADC 7 in the immediately preceding sampling period based on the Nef step μ code. .

<< Specific examples of EF treatment >>
FIGS. 7A to 7C are block diagrams showing the contents of EF processing executed by the EF processing unit 64 of FIG. 5 based on the EF processing μ program for each effect type.
FIG. 7A is a block diagram showing the processing contents of the reverb μ program (“Rev.” in FIG. 2) used for the reverb effect, echo effect, and the like. The reverb effect and the echo effect are effects that add reverberation to the input sound and output it. EF processing such as reverb and echo shown in (a) includes a low-pass filter (LPF) 80 in the input stage, an initial reflected sound control unit (“Early Ref.”) 81, a reverberation control unit (“Reverb”) 82, It consists of mixing sections (MIX) 83 and 84 provided corresponding to each of the two output channels, and is designed so that the two types of reverberation of the initial reflection sound and the reverberation sound are controlled separately. The initial reflected sound control unit 81 controls the initial reflected sound using the delay processing using the delay memory 50 for the waveform data subjected to the low pass filter processing by the LPF 80. In addition, the reverberation control unit 82 controls the reverberant sound using a delay process using the delay memory 50 with respect to the output of the initial reflected sound control unit 81. The mixing units 83 and 84 for each of the two output channels mix and output the output of the initial reflected sound control unit 81 and the output of the reverberation control unit 82, respectively.

  The reverb μ program shown in (a) includes a plurality of types of reverb (“Reverb 1” to “Reverb 3” in FIG. 2), a plurality of types of echo (“Echo 1”, “Echo 2” in FIG. 2), etc. Commonly used for multiple effect types. In the signal processing using the reverberation μ program, there are a case where the coefficient data CD is controlled by the operation value data XD of the UP adjustment operator 2 and a case where the address data AD is controlled according to the effect type. That is, depending on the effect type, whether the user coefficient data UC is output from the conversion table unit 68 or the user address data UA is output. In the signal processing using the reverb μ program, the initial reflection is performed using the user parameter (user coefficient data UC or user address data UA) corresponding to the operation value data XD of the UP adjustment operator 2 according to the effect type. There are cases where the sound controller 81 is controlled and where the reverberation controller 82 is controlled. That is, the target controlled by the user parameter differs depending on the effect type.

FIG. 7B is a block diagram showing the processing contents of the modulation μ program (“Mod.” In FIG. 2) used for the modulation effect type for chorus, flanger, and the like. The EF processing shown in (b) is provided corresponding to each of the two output channels, the low-pass filter (LPF) 85 in the input stage, the delay unit (DELAY) 86, the LFO 87 that oscillates a low-frequency signal, and so on. And taps and mixing units (TAP & MIX) 88 and 89. The input waveform data is input to the delay unit 86 through the LPF 85. The delay unit 86 also delays the input waveform data by a predetermined delay time, and delays it with a different delay time from a plurality of (three) taps provided corresponding to each of the two output channels. Output waveform data. The tap and mixing units 88 and 89 respectively extract the waveform data delayed by different delay times output from a plurality of (three) taps of the delay unit 86 and use the low frequency signal generated by the LFO 87. The delay time of the waveform data output from each tap is modulated, and the waveform data having these different delay times are added together and output.
In the signal processing using the μ program for modulation, the coefficient data CD is controlled by the operation value data XD of the UP adjustment operator 2. That is, the conversion table unit 68 outputs user coefficient data UC. Then, the LFO 87 is controlled by the user parameter (user coefficient data UC) corresponding to the operation value data XD of the UP adjustment operator 2.

FIG. 7C is a block diagram showing the processing contents of the EF processing μ program used for distortion-type effect types such as distortion. The EF processing shown in (c) includes an input stage low-pass filter (LPF) 90, a non-linear control unit (Non-Liner) 91, a low-pass filter (LPF) 92 to which the output of the non-linear control unit 91 is input, It consists of mixing units (MIX) 93 and 94 for each of the two outputs. The non-linear control unit 91 distorts the waveform data subjected to the low-pass filter processing by the LPF 90 with the non-linear characteristic, and outputs the waveform data to which the effect is applied to each of the two systems of the mixing units 93 and 94 through the LPF 92. The mixing sections 93 and 94 mix the waveform data (WET signal) output from the LPF 92 and the waveform data (original sound) before being input to the non-linear control section 91 and output them.
In the effect type using the μ program for EF processing, the coefficient data CD is controlled by the operation value data XD of the UP adjustment operator 2. That is, the conversion table unit 68 outputs user coefficient data UC corresponding to the operation value data XD of the UP adjustment operator 2. Then, the nonlinear controller 91 is controlled by the user parameter (user coefficient data UC) corresponding to the operation value data XD of the UP adjustment operator 2.

  Note that the EF processing illustrated in FIGS. 7A to 7C is an example, and the digital effector has EF processing for each effect type in addition to those shown in the drawing. The details of the configuration of the EF processing described with reference to FIGS. 7A to 7C and the parameters to be controlled for each effect type are merely examples, and the present invention is not limited to these.

<Effect type switching>
When the EF selection operator 3 is operated by the user and an effect type switching is instructed, the DSP 1 once mutes the level of the WET signal (the EF-processed waveform) and then performs an effect type switching process. FIG. 8 shows the timing of various operations when the effect type switching process is performed, and the horizontal axis is time. In FIG. 8, the time axis is shown in a reduced scale compared to the timing chart of FIG.

  When an EFT signal corresponding to the operation of the EF selection operator 3 is supplied to the first selection circuit 21, the first selection circuit 21 outputs a CHG signal (see FIG. 1). The CHG signal is a binary signal of high level (H) and low level (L) as shown in FIG. When the effect type indicated by the effect type selection code EFT is changed by the operation of the EF selection operator 3, the CHG signal output from the first selection circuit 21 rises to “H” as shown in FIG. Then, at the rising edge timing of the CHG signal, the level value generation unit 77 sets “−∞ dB” as a new target value of the level value. As a result, the level value output by the level value generator 77 starts to attenuate and gradually changes from 0 dB (maximum value) to -∞ dB (minimum value) over a plurality of sampling periods. As a result, the waveform data (input signal to the EF process) output from the HPF processing and level control unit 62 and the 2-channel waveform data (WET signal) output from the level control unit 74 are faded out.

  In the level value generation process, a one-shot pulse of the ACK signal is generated at a timing when the level value is lowered to −∞ dB, and the generated ACK signal is input to the first selection circuit 21. At the timing of the rising edge of the ACK signal, the CHG signal output from the first selection circuit 21 falls to “L”, and the effect type switching process (EF switching) starts. That is, a process of outputting μPsel, UPT, Csel, Tsel, Asel, and UPR signals from the first selection circuit 21 and reflecting the effect type change according to the operation of the EF selection operator 3 on the DSP 1 or a delay memory Processing to clear 50 is performed. By the EF switching process, the processing content of each block hatched in FIG. 5 is changed.

  This EF switching process takes a predetermined number of sampling periods. A predetermined number of sampling periods from the generation of the ACK signal wait in a state where the level value is −∞ dB to secure a time for executing the EF switching process (see FIG. 8). When the EF switching process ends (after waiting for a predetermined number of sampling cycles), the level value generation unit 77 sets “0 dB” as a new target value of the level value, and the level value generation unit 77 gradually increases the level value. Begin. As a result, the level value returns from −∞ dB to 0 dB over a plurality of sampling periods, and is output from the HPF process and level control unit 62 waveform data (EF process input signal) and the level control unit 74. The two-channel waveform data (WET signal) is faded in. When the effect type selection code EFT changes, the output signal is temporarily muted in this way to change the μ program, coefficient, etc., thereby preventing inconvenience such as generation of undesired noise accompanying switching of EF processing. It is out. If the level value returns to 0 dB, waveform data that has undergone EF processing according to the effect type newly selected this time is output from the DSP 1 thereafter.

<Change of user address data value>
Also, when the value of the user address data UA is changed by the operation of the UP operator 2, the level using the CHG signal and the ACK signal is the same as in the effect type switching process described with reference to FIG. Control is performed. That is, in FIG. 1, the operation value register 30 is connected to the connection line of the second selection signal P / U2, and is configured to receive the H level of the second selection signal P / U2. When the user address data UA is controlled by the operation value data SD of the UP adjustment operator 2 (H level of the second selection signal P / U2 is input, and the value of the user address data UA is changed by the operation of the UP adjustment operator 2) When the change is instructed), the operation value register 30 outputs the operation value data SD corresponding to the operation of the UP adjustment operator 2 in the same manner as the operation described in FIG. Output level. The DSP 1 starts the level value generation process at the timing of the rising edge of the CHG signal, lowers the level value from 0 dB to −∞ dB, and then inputs the ACK signal to the operation value register 30. The operation value register 30 outputs operation value data SD corresponding to the operation of the UP adjustment operator 2 to the range control unit 31 at the input timing of the ACK signal, and lowers the CHG signal to the L level. As a result, the level of the WET signal (the EF-processed waveform) is once muted, and the value change caused by the operation of the UP adjustment operator 2 is reflected in the memory address MAD.

<< UP use / non-use switch >>
Also, when the UP on / off SW 4 is operated, the level control using the CHG signal and the ACK signal is performed as in the effect type switching process described with reference to FIG. When the UP on / off SW 4 is turned off and UP non-use is instructed, the first selection circuit 21 starts the level value generation process by outputting the H level of the CHG signal, and sets the level value to −∞. A value “3” indicating that the UP function is not used as the user parameter type designation signal UPT after the CHG signal is lowered to the L level at the input timing of the ACK signal after being lowered to dB (see FIG. 4B) Is output. Thereafter, the level value generation process returns the level value to 0 dB. When the UP on / off SW 4 is turned on and the use of UP is instructed, the first selection circuit 21 starts the level value generation process by outputting the H level of the CHG signal, and sets the level value to − After being lowered to ∞ dB, the CHG signal is lowered to the L level at the input timing of the ACK signal, and a value corresponding to the currently selected effect type selection code EFT is output as the user parameter type designation signal UPT. Thereafter, the level value generation process returns the level value to 0 dB. As a result, the level of the WET signal (the EF-processed waveform) is once muted, and switching between UP use and non-use is performed.

<Switching effect on / off>
Even when the effect imparting function is switched on / off by the operation of the EF on / off SW5, level control substantially similar to the above is performed. However, in this case, in the level control, the WET signal level is lowered to −∞ dB (minimum value) while the effect applying function is off, and the WET signal level is set to 0 dB (maximum) while the effect applying function is on. Here, the DSP 1 performs level control by level value generation processing according to H and L of the control signal EFON output by the operation of the EF on / off SW5.

  FIG. 9 shows various timings related to level control when the on / off of the effect providing function is switched by the operation of the EF on / off SW5, and the horizontal axis is time. In FIG. 9, the time axis is reduced as compared with the timing chart of FIG. 6, as in FIG. As described above, the control signal EFON indicating “ON” or “OFF” of the effect imparting function indicates “ON” of the effect imparting function at the “H” level, and “OFF” of the effect imparting function at the “L” level. Show. When the effect imparting function is turned off by the operation of the EF on / off SW5, the level value generation process is started at the timing of the edge at which the control signal EFON falls to the L level, and the level value is gradually decreased. To reduce the level value to -∞ dB. While the effect imparting function is “off” (when EFON = L), the level value remains set to −∞ dB. On the other hand, when the effect imparting function is turned on by operating the EF on / off SW5, the level value generation process is started at the timing of the edge when the control signal EFON rises to the H level, and the level value is gradually increased. The level value is returned to 0 dB over a plurality of sampling periods. While the effect imparting function is “ON” (when EFON = H), the level value remains set to 0 dB. In the timing chart of FIG. 9, the level value gradually increases at the edge timing when EFON rises to the H level. However, the level value is delayed later than the edge timing when EFON rises to the H level. The gradual increase may be started.

<Level value generation processing>
FIG. 10 is a block diagram for explaining the contents of the level value generation process executed by the level value generation unit 77 for each sampling period. In FIG. 10, the level value generation processing includes an update control unit 95, a register 96 that holds the current level value, a target value (Target) output from the update control unit 95, and a current level value that the register 96 holds. Are compared with each other, and an update unit 98 that generates a new level value under the control of the update control unit 95. The level value is data in decibels composed of a binary value having a predetermined number of bits (for example, 14 bits).

  The update control unit 95 receives the CHG signal, the control signal EFON, and a reset signal Reset for instructing resetting of the digital effector as trigger signals for starting the level value generation process. The update control unit 95 outputs “−∞ dB” as a target value to the comparison unit 97 when the value of the input CHG signal is “H” or when the input control signal EFON is “L”. When the value of the input CHG signal is “L” or when the input control signal EFON is “L”, “0 dB” is output to the comparison unit 97 as a target value. In addition, the update control unit 95 outputs an ACK signal when the current level value decreases to “−∞ dB”.

  The register 96 outputs the current level value (level value generated in the immediately preceding sampling period) for each sampling period, and takes in a new level value generated in the sampling period from the update unit 98. The comparison unit 97 compares the current level value output from the register 96 with the target value output from the update control unit 95 for each sampling period, and compares the result (whether the target value is greater than the level value). Or smaller) is supplied to the update control unit 95.

  The update control unit 95 outputs a control signal corresponding to the comparison result of the comparison unit 97 to the update unit 98 for each sampling period. The control signal is a command that causes the updating unit 98 to increase the level value by one step when the target value is larger than the level value, and a command that causes the updating unit 98 to decrease the level value by one step when the target value is smaller than the level value. is there. The update unit 98 generates a new level value by increasing or decreasing the current level value output from the register 96 step by step based on the control signal input from the update control unit 95 at each sampling period. To do.

  With the level value generation process configured as described above, the level value can be increased or decreased over a plurality of sampling periods, and the current level value can be matched with the target value (−∞ dB or 0 dB). Therefore, level control as described with reference to FIGS. 8 and 9 can be performed. When a reset signal Reset is input as a trigger signal for starting the level value generation process (when a reset is instructed by the user), the same level control as described in FIG. 8 or FIG. 9 may be performed. That is, when reset is instructed, “−∞ dB” is output as the target value, and the level value is decreased to perform the operation to complete the reset operation, and then “0 dB” is output as the target value. The level value may be returned to the maximum value. Further, since the target value as a comparison reference in the comparison unit 97 is either −∞ dB (minimum value) or 0 dB (maximum value), the operation of the comparison unit 97 is an AND operation or OR of all bits of the current level value. It can be realized only by calculation.

  As described above, according to the embodiment of the present invention, every time a UPTC corresponding to the UPT corresponding to the currently specified effect type is output from the μ program memory 22, that is, the parameter is replaced by the replacement code. Each time the count value UPC is output from the UP counter 29, the user parameter corresponding to the operation value data XD (operation data) of the UP adjustment operator 2 is converted into the conversion table based on the output count value UPC. Since the data is output from the memory 25, the value of the user parameter corresponding to the operation data can be changed every time parameter replacement is indicated by the user parameter replacement code (UPTC). Therefore, even in a simple configuration that does not include a CPU for controlling the DSP 1, a user parameter of a specific plurality of steps corresponding to the currently designated effect type can be obtained without using the processing steps of the DSP 1 much. According to the operation value data XD of the UP adjustment operator 2, there is an excellent effect that the values can be controlled to be different from each other.

In the above-described embodiment, the digital effector to which the acoustic signal processing device according to the present invention is applied stores a plurality of μ programs for EF processing in the μ program memory 22, and an effect is selected from a plurality of effect types. Although an example in which a single-stage effector that uses only one effect type specified by the type selection code EFT has been described, the present invention is not limited to this, and the present invention can be used in parallel with a plurality of effect types as an example system. It may be applied to a so-called “multi-effector” to be used.
In the above-described embodiment, an example in which there are two signal processing parameters, coefficient data and address data, has been described. However, depending on the type of effect type installed in the digital effector to which the acoustic signal processing device is applied, the parameter May be only coefficient data or address data. Even in such a case, the acoustic signal processing apparatus according to the present invention can be applied.

  Further, even when the effect type itself has only one type, the acoustic signal processing device according to the present invention can be applied. In that case, in particular, regarding the parameter of the step to be controlled according to the operation value of the UP adjustment operator 2 in the effect type, the operation value of the UP adjustment operator 2 is converted differently for each parameter of each step. There is an advantageous effect of the present invention in that it is converted into a parameter value by characteristics. When only one effect type is listed, UPTC in the μ program is not a plurality of codes as shown in FIG. 4B, but indicates whether the parameter is replaced with a user parameter for each step. Can consist of bit flags. Further, the user parameter code UPTC is included in the μ code in each step of the μ program for EF processing. However, the code UPTC may be stored separately from the μ code. For example, the code UPTC may be included in the coefficient data of each step of the coefficient set stored in the coefficient memory 23. Alternatively, the present invention can also be applied to a configuration in which the DSP 1 further includes a memory that stores a plurality of code sets each including the code UPTC of each step. Furthermore, the user parameter type code UPTC does not serve as data indicating whether or not to replace each step, and supports one or more of the steps of the μ program that use the user parameter. Step number data may be used. In that case, the step number of the μ program currently being read is compared with one or more codes UPTC, and the user parameter is used instead of the coefficient data in the coefficient memory at the step that matches one of the codes UPTC. You can do it.

  In FIG. 1, the example in which the acoustic signal processing device according to the present invention is applied to a single digital effector is shown. However, the acoustic signal processing device according to the present invention may be a mixer, an electronic musical instrument, or a sound source, for example. It may be a digital effector mounted on other music equipment such as a device.

  In the above embodiment, the UP adjustment operator 2 and the EF selection operator 3 are output data (operation value data SD and effect type selection code EFT) corresponding to the absolute operation position of the operator, respectively. However, the present invention is not limited to this, and output data corresponding to the relative operation position (operation displacement amount) of the operator may be output. In addition, the UP adjustment operator 2 and the EF selection operator 3 are each configured by a rotary variable resistor (rotary SW), but the form of the operator is not limited. , A slide-type switch (level operation element), or a push-button type switch such as a numeric keypad or an increment / decrement switch may be used.

In the configuration of the effector in FIG. 1, the mixing of the WET signal and the DRY signal is performed by an analog circuit outside the DSP 1, but this mixing may be performed by the μ program of the DSP 1. .
In the above-described embodiment, the operation data (operation value data SD) input to the DSP 1 is not directly stored in the operation value register 30 but is stored in the operation value register 30 after being subjected to the low-pass filter processing by the C processing μ program. It is supposed to be. This is because, unlike the parameter generation process of the present invention, this low-pass filter process can be realized with a relatively short μ program, and providing dedicated hardware is structurally inefficient. However, when an analog or digital low-pass filter can be separately prepared outside the DSP 1, the low-pass filter processing is configured to be left to the external low-pass filter, and the DSP 1 receives the operation data (operation value data SD) to be input. It is preferable to directly store the operation value register 30 without performing the μ program processing.

1 DSP, 2 UP adjustment operation, 3 EF selection operation, 4 UP on / off switch, 5 EF on / off switch, 6 Power switch, 7 ADC, 8, 9 level operation, 10 Mixing unit, 11 level operation , 12 DAC, 13, 14 mixing unit, 20 clock generation circuit, 21 first selection circuit, 22 μ program memory (microcode output unit), 23 coefficient memory, 24 address memory, 25 conversion table memory, 26 second selection circuit 27 coefficient data selector, 28 address data selector, 29 UP counter, 30 operation value register, 31 range control unit, 60 Rch input unit, 61 Lch input unit, 62 HPF processing & level control unit, 63 Din writing unit, 64 EF Processing unit, 65 LPF processing unit, 66 SD output unit, 67 Range control 68 conversion table section 69 coefficient setting section 70 address setting section 71 coefficient supplying section 72 address supplying section 73 Dout reading section 74 level control section 75 Rch channel output section 76 Lch channel output section 77 level Value generator

Claims (7)

A signal processing integrated circuit that performs signal processing of a predetermined number of steps on an input acoustic signal for each predetermined sampling period,
An operation data receiving unit that receives operation data indicating an operation of the operator;
Stores a microprogram consisting of a multi-step microcode including a replacement code indicating that a parameter is replaced from a preset parameter to a user parameter, and outputs each microcode of the microprogram sequentially for each step. And
A user parameter count unit that counts the number of times parameter replacement is indicated by a replacement code included in the microcode output from the microcode output unit for each sampling period;
Based on the count value of the user parameter count unit, a user parameter output unit that outputs user parameters according to the operation data received by the operation data reception unit;
For each step, when the replacement code included in the microcode output from the microcode output unit indicates parameter replacement, a parameter selection unit that selects a user parameter output by the user parameter output unit;
Signal processing that performs signal processing on the input acoustic signal based on the microcode output from the microcode output unit and the parameter selected by the parameter selection unit, and outputs the signal processed acoustic signal And a signal processing integrated circuit. A preset parameter output unit that sequentially outputs each preset parameter of a preset parameter set including preset parameters for a plurality of steps for each step,
The parameter selection unit selects a user parameter output from the user parameter output unit when the replacement code included in the microcode output from the microcode output unit indicates parameter replacement at each step. 2. The signal processing integrated circuit according to claim 1, wherein when the replacement code does not indicate parameter replacement, the preset parameter output from the preset parameter output unit is selected. It further includes an effect type reception unit that receives type data for specifying an effect type,
The microcode output unit stores a plurality of the microprograms, and sequentially outputs microcodes of microprograms corresponding to the effect type specified by the type data for each step,
The preset parameter output unit stores a plurality of the preset parameter sets, and sequentially outputs each preset parameter of the preset parameter set corresponding to the effect type designated by the type data for each step,
The user parameter output unit outputs a user parameter corresponding to the operation data received by the operation data receiving unit, based on the effect type specified by the type data and the count value of the user parameter counting unit. The signal processing integrated circuit according to claim 1, wherein the integrated circuit is a signal processing integrated circuit. It further includes an effect type reception unit that receives type data for specifying an effect type,
The user parameter output unit sets the conversion table for converting the operation data received by the operation data receiving unit into user parameters, and the number of times the parameter substitution unit counts for each sampling period is indicated. Consists of conversion table sets having a corresponding number, and switches the conversion table set of the conversion table set one by one based on the effect type specified by the type data and the count value of the user parameter count unit, 2. The signal integrated circuit according to claim 1, wherein a user parameter corresponding to the operation data is output based on the switched conversion table. The user parameter output unit stores a plurality of the conversion table sets,
One of the plurality of conversion table sets is selected according to the effect type specified by the type data, and the conversion table of the selected conversion table set is selected based on the count value of the user parameter count unit. 5. The signal processing integrated circuit according to claim 4, wherein the signal processing integrated circuit switches one by one, converts the operation data into a user parameter corresponding to the effect type based on the switched conversion table, and outputs the user parameter. . A signal processing integrated circuit according to any one of claims 1 to 5;
An input unit that inputs the acoustic signal from the outside and supplies the signal to the signal processing circuit;
A parameter operation section (2, 7) that includes the operation element, generates operation data corresponding to the operation of the operation element, and supplies the operation data to the signal processing circuit;
An effect applying apparatus comprising: an output unit that outputs an acoustic signal output from the signal processing integrated circuit to the outside. A signal processing integrated circuit according to any one of claims 3 and 5,
An input unit that inputs the acoustic signal from the outside and supplies the signal to the signal processing circuit;
A parameter operation unit that includes the operation element, generates operation data corresponding to the operation of the operation element, and supplies the operation data to the signal processing circuit;
A selection operator that includes a selection operator, generates the type data according to the operation of the selection operator, and supplies the type data to the signal processing integrated circuit;
An effect applying apparatus comprising: an output unit that outputs an acoustic signal output from the signal processing integrated circuit to the outside.

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