JP2010178384A - Image signal processing circuit, camera and image signal processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress an error in a clamp level even if a level shift occurs in a signal from a light-shielding pixel without remarkably increasing a circuit scale. <P>SOLUTION: In an image signal processing circuit for applying predetermined processing to an image signal from a solid-state image pickup element including a plurality of effective pixels and a plurality of light-shielding pixels, a median value of signals from the plurality of light-shielding pixels is extracted and outputted and on the basis of the output value, the signals from the light-shielding pixels are adjusted to a predetermined level. Thus, an offset quantity can be properly adjusted on the basis of the signals from the light-shielding pixels in a state where a signal having level shift is removed only by adding a few circuits. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an image signal processing technique for an image signal output from a solid-state image sensor, and more particularly to a control technique for clamp means in image signal processing.

  FIG. 7 is a block diagram showing a circuit configuration of a general image signal processing circuit related to an image signal output from a solid-state imaging device such as a CCD or a CMOS sensor. As shown in FIG. 7, the image signal processing circuit includes a correlated double sampling (CDS) circuit 1, a variable gain amplifier (PGA) 2, an AD converter (ADC) 3, a comparison circuit 4, a clamp level register 5, and a clamp circuit 6. Consists of

  An image signal of a solid-state imaging device (not shown) such as a CCD or CMOS sensor is input to an image signal processing circuit via an input terminal IN. The input image signal is subjected to predetermined processing such as sample hold and amplification by the CDS circuit 1 and the variable gain amplifier 2, and then converted from an analog signal to a digital signal by the AD converter 3, and from the output terminal OUT. Is output.

  In the image signal processing circuit shown in FIG. 7, the clamp circuit 6 uses the signal from the light-shielded pixel (OB) in the solid-state image sensor to add to the input image signal so that the black level becomes a predetermined level. Control the amount. Specifically, the signal from the light-shielded pixel output from the AD converter 3 is first compared with the clamp level held as data in the clamp level register 5 by the comparison circuit 4. The clamp circuit 6 performs control based on the comparison result (difference level) in the comparison circuit 4, and adjusts and supplies the offset level to be added to the CDS circuit 1 as an input unit. Note that the light-shielding pixel (OB) is a pixel in which a photoelectric conversion element such as a photodiode is formed in a solid-state imaging element but incident light from a subject is not incident.

The conventional image signal processing circuit described above has the following problems.
For example, as shown in FIG. 8A, when the light-shielding pixel portions HOB and VOB of the solid-state imaging device have a defect 81 and an abnormal level signal is output as a signal from the light-shielding pixel, the clamp circuit 6 Operates so as to perform the clamping process using the signal of the abnormal level, and an error of the clamping level occurs. That is, the solid-state image sensor is required to be defect-free even in the light-shielded pixels, which causes a decrease in the yield of the solid-state image sensor.

  For example, as shown in FIG. 8B, when a high-luminance subject is photographed, an excessive amount of light is incident on the solid-state imaging device, and light is incident on the light-shielding pixel portions HOB and VOB due to multiple reflections. As a result, even when the signal from the light-shielded pixel fluctuates, the clamp circuit 6 operates so as to perform the clamping process using the signal level, so that an error in the clamp level occurs. As shown in FIG. 8B, the signal level from the light-shielding pixel 83 is increased in the high luminance region 82, and the clamp circuit 6 operates to decrease the signal level. As a result, the level of the row (high luminance region 82) is lowered as a whole, so that the level is lowered like a strip as shown in the figure.

  On the other hand, as a method for avoiding erroneous clamping processing, a first clamping level using a signal from a light-shielded pixel in a solid-state imaging device and a horizontal blanking period in which no signal is read from a photoelectric conversion device (pixel) are used. A second clamp level using a signal level is provided, and when the first clamp level becomes an abnormal level, there is a switch to the second clamp level (see, for example, Patent Document 1).

Japanese Patent Laid-Open No. 9-247552

  Further, in order to solve these problems described above, it is an effective technique to reduce the error of the clamp level by sufficiently reducing the gain value of the clamp circuit 6. However, if the gain of the clamp circuit 6 is set to a small value, the time from when the power is turned on until it reaches a desired level becomes long, and the shading in which the offset amount changes in the vertical direction of the solid-state imaging device is large. However, there is a problem that the correction becomes insufficient. That is, since the gain is actually set in the relationship of these trade-offs, making the gain value of the clamp circuit 6 sufficiently small is not sufficient to solve the above-described problem.

  As a known method for solving these problems, the address of the defective pixel among the light-shielded pixels is stored in a storage means (generally a nonvolatile memory is used), and the clamp level is determined. There is a method of excluding signals from defective light shielding pixels. However, since this method requires a storage means, the circuit scale increases, and it is necessary to test and adjust each solid-state imaging device. Further, an integrated circuit of a special process such as a nonvolatile memory is required. There was a problem that there was.

  As another known method, there is a method in which signals from a plurality of light-shielding pixel portions are averaged, and a clamping process is performed using a signal level obtained as the average. According to this method, it is possible to reduce the influence of the signal level shift due to the defect of the light-shielding pixel and the light incidence to some extent, and to perform the clamping operation under the condition with less random noise. However, when the level deviation of the signal from the light-shielded pixel is large, although the influence can be reduced to some extent by averaging, there is a problem that the error of the clamp level cannot be sufficiently reduced.

  The present invention has been made in view of such a problem, and makes it possible to suppress a clamp level error even if a level shift occurs in a signal from a light-shielded pixel without extremely increasing the circuit scale. For the purpose.

An image signal processing circuit of the present invention is an image signal processing circuit that performs predetermined processing on an image signal from a solid-state imaging device having a plurality of effective pixels and a plurality of light-shielding pixels, and the signals from the plurality of light-shielding pixels. Intermediate value output means for extracting and outputting the median value of the image, and clamping means for adjusting the signal from the light-shielded pixel to a predetermined level based on the output value output from the intermediate value output means. Features.
An image signal processing circuit of the present invention is an image signal processing circuit that performs predetermined processing on an image signal from a solid-state imaging device having a plurality of effective pixels and a plurality of light-shielding pixels, and the signals from the plurality of light-shielding pixels. Calculating means for calculating and outputting an average value of signals excluding the maximum value and the minimum value, and adjusting the signal from the light-shielded pixel to a predetermined level based on the average value calculated by the calculating means And clamping means.
According to another aspect of the present invention, there is provided a camera comprising: the above-described image signal processing circuit; a lens for forming an optical image on a solid-state imaging device; and a diaphragm for changing the amount of light passing through the lens. .
The image signal processing method of the present invention is an image signal processing method for performing predetermined processing on an image signal from a solid-state imaging device having a plurality of effective pixels and a plurality of light-shielding pixels, and the signals from the plurality of light-shielding pixels. An intermediate value output step for extracting and outputting the median value of the image, and a clamping step for adjusting the signal from the light-shielded pixel to a predetermined level based on the output value output in the intermediate value output step. It is characterized by.
The image signal processing method of the present invention is an image signal processing method for performing predetermined processing on an image signal from a solid-state imaging device having a plurality of effective pixels and a plurality of light-shielding pixels, and the signals from the plurality of light-shielding pixels. And calculating an average value of signals excluding the maximum value and minimum value, and adjusting the signal from the light-shielded pixel to a predetermined level based on the average value calculated in the calculation step. And a clamping process.

  According to the present invention, even if a slight circuit is added, even if a level shift occurs in some of the signals from the plurality of light-shielded pixels due to defects or light incidence in the light-shielded pixels of the solid-state imaging device, a level shift occurs. Therefore, the offset amount to be added to the signal from the solid-state imaging device can be appropriately adjusted. Therefore, even if a level shift occurs in the signal from the light-shielded pixel, it is possible to suppress occurrence of a clamp level error without extremely increasing the circuit scale, and to perform good image signal processing. Become. In addition, a certain amount of defects in the light-shielding pixel portion of the solid-state imaging device can be tolerated, the selection criteria can be relaxed, and the yield can be increased.

It is a figure which shows the structural example of the image signal processing circuit by the 1st Embodiment of this invention. It is a figure which shows the structural example of the image signal processing circuit by 2nd Embodiment. It is a figure which shows the structural example of the image signal processing circuit by 3rd Embodiment. It is a figure which shows the structural example of the image signal processing circuit by 4th Embodiment. It is a figure which shows the structural example of the image signal processing circuit by 5th Embodiment. It is a figure which shows the structural example of the camera to which the image signal processing circuit in embodiment of this invention is applied. It is a figure which shows the structure of a general image signal processing circuit. It is a figure for demonstrating the problem in the conventional image signal processing circuit.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
The image signal processing circuits according to the first to fifth embodiments of the present invention to be described below are correlated double sampling (CDS) circuits and variable gain amplifiers (PGA) in FIGS. ) Is not shown, but similarly to the image signal processing circuit shown in FIG. 7, a correlated double sampling (CDS) circuit and a variable gain amplifier (PGA) are provided before the AD converter.

(First embodiment)
FIG. 1 is a block diagram showing a circuit configuration example of an image signal processing circuit according to the first embodiment of the present invention. In FIG. 1, blocks having the same functions as those shown in FIG. 7 are denoted by the same reference numerals.

  In FIG. 1, reference numeral 3 denotes an AD converter that converts an analog signal into a digital signal (digital data). The AD converter 3 receives an image signal from a solid-state imaging device (for example, a CCD or a CMOS sensor) having a plurality of effective pixels and a plurality of light-shielding pixels via a CDS circuit and a variable gain amplifier (not shown). Is converted into a digital signal (digital data) and output.

  Reference numeral 11 denotes a digital filter, which detects and removes a signal whose level is shifted (abnormal level) from the light-shielded pixels output from the AD converter 3. That is, the digital filter 11 removes the signal when the signal level is outside the predetermined range, and passes the signal as it is when it is within the predetermined range.

  Reference numeral 4A denotes a comparison circuit, more specifically a digital subtractor. The comparison circuit 4A receives the signal from the light-shielded pixel filtered by the digital filter 11 and the clamp setting level held in the clamp level register 5, and outputs a signal corresponding to the difference level.

  Reference numeral 6 denotes a clamp circuit, which is controlled based on a signal corresponding to the difference level supplied from the comparison circuit 4A, and is an offset amount (offset level) to be added to an input image signal to be added by an input unit (a CDS circuit not shown). Adjust.

  In the image signal processing circuit according to the first embodiment described above, a signal from the solid-state imaging device is input to the AD converter 3 via a CDS circuit and a variable gain amplifier (not shown), and is converted into a digital signal (digital data) to be imaged. It is output outside the signal processing circuit. The digital signal output from the AD converter 3 is also supplied to the comparison circuit 4 via the digital filter 11, and the signal from the light-shielded pixel and the clamp setting level from the clamp level register 5 are compared with each other in the comparison circuit 4A. And a signal corresponding to the difference level is output. The clamp circuit 6 is controlled by a signal corresponding to the difference level output from the comparison circuit 4A, and the offset amount of the circuit is adjusted.

  Here, of the signals from the light-shielded pixels of the solid-state image sensor, an abnormal level signal whose level is shifted due to a pixel defect or light leakage is output from the AD converter 3 but is not passed through the digital filter 11 ( As a result, the signal is not input to the clamp circuit 6.

  As a result, according to the first embodiment, out of the signals from the light-shielding pixels of the solid-state imaging device, the abnormal level signal whose level is shifted is detected and removed by the digital filter 11, and thus the light shielding except for the abnormal level signal is performed. The offset amount of the circuit can be appropriately adjusted based only on the signal from the pixel. Therefore, since it is only necessary to add the digital filter 11, it is possible to suppress a clamping error caused by a pixel defect or light leakage of the solid-state image sensor without extremely increasing the circuit scale. Good image signal processing can be performed on the signal. In addition, a defect in the light-shielding pixel portion of the solid-state imaging device can be accepted to some extent, and the selection criteria (selection standard) can be relaxed to increase the yield.

(Second Embodiment)
Next, a second embodiment will be described. FIG. 2 is a block diagram showing a circuit configuration example of an image signal processing circuit according to the second embodiment of the present invention. In FIG. 2, blocks having the same functions as those shown in FIG. 1 are denoted by the same reference numerals, and redundant description is omitted.

  In FIG. 2, reference numeral 21 denotes a comparison circuit (digital subtractor), which receives a signal from the light-shielded pixel output from the AD converter 3 and a signal level held in the maximum value register 22. The switch 23 is controlled accordingly. Specifically, the comparison circuit 21 closes the switch 23 when the signal from the light-shielded pixel output from the AD converter 3 is larger than the signal level held in the maximum value register 22, and otherwise The switch 23 is controlled to open. The switch 23 is for selectively supplying a signal from the light-shielded pixel output from the AD converter 3 to the maximum value register 22.

  That is, as a result of the comparison in the comparison circuit 21, when the signal from the light-shielded pixel output from the AD converter 3 is higher than the signal level held in the maximum value register 22, the light-shielded output from the AD converter 3. A signal from the pixel is supplied to the maximum value register 22 as an update value and held. In this way, the circuit including the comparison circuit 21, the maximum value register 22, and the switch 23 detects the maximum value in the signal from the light shielding pixel output from the AD converter 3.

  A comparison circuit 24 receives the signal from the light-shielded pixel output from the AD converter 3 and the signal level held in the minimum value register 25, and compares them. As a result of this comparison, the comparison circuit 24 closes the switch 26 when the signal from the light-shielded pixel output from the AD converter 3 is lower than the signal level held in the minimum value register 25, and otherwise, The switch 26 is controlled to open. The switch 26 is for selectively supplying a signal from the light-shielded pixel output from the AD converter 3 to the minimum value register 25.

  That is, as a result of the comparison in the comparison circuit 24, if the signal from the light-shielded pixel output from the AD converter 3 is lower than the signal level held in the minimum value register 25, the light-shielded output from the AD converter 3 is used. A signal from the pixel is supplied to the minimum value register 25 as an update value and held. In this manner, the circuit including the comparison circuit 24, the minimum value register 25, and the switch 26 detects the minimum value in the signal from the light-shielded pixel output from the AD converter 3.

  A sum (Σ) register 27 receives a signal from the light-shielded pixel output from the AD converter 3 and sequentially adds the input signal from the light-shielded pixel to calculate and hold the sum.

A subtractor 28 is supplied with the register values of the maximum value register 22, the minimum value register 25, and the sum total register 27, and performs predetermined arithmetic processing using them, and outputs an arithmetic result. Specifically, the subtractor 28 calculates and outputs a value of [(total) − (maximum value) − (minimum value)] based on the register value of each register.
A divider 29 divides the output value of the subtractor 28 by (the number of shaded images−2).

  Reference numeral 4B denotes a comparison circuit, which corresponds to the comparison circuit 4A shown in FIG. The comparison circuit 4B receives the output signal from the divider 29 and the clamp setting level held in the clamp level register 5, and outputs a signal corresponding to the difference level.

  In the image signal processing circuit according to the second embodiment described above, a signal from the solid-state imaging device is input to the AD converter 3 via a CDS circuit and a variable gain amplifier (not shown), converted into a digital signal, and external to the image signal processing circuit. Is output. Further, among the digital signals output from the AD converter 3, the signal from the light-shielded pixel is updated by adding to the register value of the sum total register 27 as needed, and at the same time, the register values of the maximum value register 22 and the minimum value register 25 By performing the comparison, the maximum value and the minimum value in the signal from the light-shielded pixel are detected.

  Then, as a result of processing data for a predetermined number of light-shielded pixels, the sum, maximum value, and minimum value are stored in the respective registers 22, 25, 27, and {(sum)-(maximum value)-(minimum). (Value)} / (number of pixels−2) is performed by the subtractor 28 and the divider 29, and the average value of signals excluding the maximum value and the minimum value among the signals from the light-shielded pixels is calculated. The calculation result and the clamp setting level from the clamp level register 5 are compared by the comparison circuit 4B, and a signal corresponding to the difference level is output. The clamp circuit 6 is operated by a signal corresponding to the difference level output from the comparison circuit 4B, and the offset amount of the circuit is adjusted.

  As described above, according to the second embodiment, by removing the signal having the highest signal level and the signal having the lowest signal level from among the signals from the plurality of light-shielding pixels, the maximum value and the minimum value are obtained. The offset amount of the circuit can be appropriately adjusted based on the average value of the signal from the light-shielded pixel excluding the signal, and a clamping operation with a smaller clamping error can be achieved by adding a few circuits. Therefore, it is possible to perform better image signal processing on the signal from the solid-state image sensor, and to ease the selection criteria (selection standard) of the solid-state image sensor and increase the yield.

(Third embodiment)
Next, a third embodiment will be described.
FIG. 3 is a block diagram showing a circuit configuration example of an image signal processing circuit according to the third embodiment of the present invention. In FIG. 3, blocks having the same functions as those shown in FIG. 1 are denoted by the same reference numerals, and redundant description is omitted.

  In FIG. 3, 31 and 33 are registers that hold three input signals (data values). Reference numerals 32 and 34 denote median filters that extract median values (intermediate values) from the three signals (data values) held in the registers 31 and 33, respectively.

  The register 31 and the median filter 32 constitute a first median filter block that extracts the median value from the signals from the three light-shielded pixels output from the AD converter 3. Further, the register 33 and the median filter 34 constitute a second median filter block that extracts the median value in the three median values extracted by the first median filter block.

  In other words, the registers 31 and 33 and the median filters 32 and 34 (first and second median filter blocks) make the median value in the signal from the light-shielded pixels for nine pixels or a median value that is not exactly an intermediate value, but accurate. A corresponding substantially intermediate value is extracted.

  Reference numeral 4C denotes a comparison circuit, which corresponds to the comparison circuit 4A shown in FIG. The comparison circuit 4C receives the output signal from the median filter 34 and the clamp setting level held in the clamp level register 5, and outputs a signal corresponding to the difference level.

  In the image signal processing circuit according to the third embodiment described above, a signal from the solid-state imaging device is input to the AD converter 3 via a CDS circuit and a variable gain amplifier (not shown), converted into a digital signal, and external to the image signal processing circuit. Is output.

  Of the digital signals output from the AD converter 3, the signals from the light-shielded pixels are continuously 3 in the first median filter block including the register 31 and the median filter 32 with respect to the signals for 9 pixels. Intermediate value extraction is performed as needed for a group of signals for pixels, and the extracted three intermediate values are stored in the register 33. Further, in the second median filter block composed of the register 33 and the median filter 34, intermediate value extraction is performed using the three values stored in the register 33, and the extracted intermediate value is input to the comparison circuit 4C. Is output.

  The output value of the median filter 34 (the intermediate value or the substantially intermediate value of the signals from the light-shielding pixels for nine pixels) and the clamp setting level from the clamp level register 5 are compared by the comparison circuit 4C and output as a result. The clamp circuit 6 is operated by a signal corresponding to the signal corresponding to the difference level, and the offset amount of the circuit is adjusted.

  As described above, according to the third embodiment, the signals from the light-shielding pixels for nine pixels are divided into three sets of three pixels, and the median value is extracted by the median filter 32, and further extracted for each set. Using the three median values in total, the median value is extracted by the median filter 34, and a pseudo intermediate value is extracted from the signals from the light-shielded pixels for nine pixels. Then, the offset amount of the circuit is appropriately adjusted based on the pseudo intermediate value.

  Here, the circuit scale of the 9 → 1 median filter that extracts one median value from the nine elements themselves increases. For this reason, in the present embodiment, a 3 → 1 median filter for extracting one median value from three elements is cascaded to form a two-stage configuration, so that a plurality of (9 It is possible to extract a pseudo intermediate value from signals from the light-shielded pixels (for pixels). Since the clamp operation is performed using the extracted pseudo intermediate value, it is possible to suppress the occurrence of a clamp error and to perform a clamp operation with a smaller error, and to perform a good image signal processing on a signal from a solid-state image sensor. Can be applied. In addition, defects in the light-shielding pixel portion of the solid-state imaging device can be more tolerated, and the selection criterion (selection standard) can be remarkably relaxed to increase the yield.

  In the above description, a case where processing is performed using signals from light-shielding pixels for nine pixels is shown as an example, but the present invention is not limited to this, and the number of signals from light-shielding pixels to be used (number of pixels) ) Is optional, and by appropriately changing the registers 31 and 32 and the median filters 32 and 34 in accordance with the number of signals, it is possible to perform processing using signals from arbitrary light-shielded pixels. .

(Fourth embodiment)
Next, a fourth embodiment will be described.
FIG. 4 is a block diagram showing a circuit configuration example of an image signal processing circuit according to the fourth embodiment of the present invention. In FIG. 4, blocks having the same functions as those shown in FIG. 1 are denoted by the same reference numerals, and redundant description is omitted.

  In FIG. 4, reference numeral 41 denotes a switch for selectively supplying the signal from the light-shielded pixel output from the AD converter 3 or the output value from the 1H-previous OB average register 43 to the OB level averaging circuit 42.

  The OB level averaging circuit 42 outputs a signal from the light-shielded pixel output from the AD converter 3 and supplied via the switch 41 (the output value from the 1H-previous register 43 may be included in part or all). Calculate and output the average value. The 1H-previous OB average register 43 is a register that holds the average value calculated by the OB level averaging circuit 42 used in the previous clamping process.

  Reference numeral 44 denotes an adder that adds the average value used in the previous clamping process held in the OB average register 43 before 1H and the scratch threshold held in the scratch threshold register 45. Output the calculation result.

  A comparison circuit 46 receives the signal from the light-shielded pixel output from the AD converter 3 and the output value of the adder 44, and compares them. As a result of this comparison, when the signal from the light-shielded pixel output from the AD converter 3 is equal to or less than the output value of the adder 44 (average value of one frame before + scratch threshold value), the comparison circuit 46 determines that AD The switch 41 is controlled so that the signal from the light-shielded pixel output from the converter 3 is supplied to the OB level averaging circuit 42. On the other hand, when the signal from the light-shielded pixel output from the AD converter 3 is larger than the output value of the adder 44, the output value from the 1H previous OB average register 43 is supplied to the OB level averaging circuit 42. The switch 41 is controlled.

  Reference numeral 4D denotes a comparison circuit, which corresponds to the comparison circuit 4A shown in FIG. The comparison circuit 4D receives the average value output from the OB level averaging circuit 42 and the clamp setting level held in the clamp level register 5, and outputs a signal corresponding to the difference level.

  In the image signal processing circuit according to the fourth embodiment described above, a signal from the solid-state imaging device is input to the AD converter 3 via a CDS circuit and a variable gain amplifier (not shown), converted into a digital signal, and external to the image signal processing circuit. Is output. Of the digital signal output from the AD converter 3, the signal from the light-shielded pixel is averaged by the OB level averaging circuit 42. At this time, the average value used for the previous processing (one frame before) is stored in the OB average register 43 before 1H, and (the previous average value + scratch threshold) and the current AD converter 3 for each pixel. The comparison circuit 46 compares the level of the signal output from the light-shielded pixel with the signal level.

  As a result of the comparison by the comparison circuit 46, when the signal level from the current light-shielded pixel is higher than (previous average value + scratch threshold), in other words, the previous average value and the signal level from the current light-shielded pixel are Is larger than the scratch threshold, it is determined that the signal from the current light-shielded pixel is at an abnormal level due to the influence of defects or light leakage, and is not input to the OB level averaging circuit 42. Instead, the previous average value is input to the OB level averaging circuit 42. The signal from the current light-shielded pixel and the previous average value are also exchanged for each pixel.

  The average value calculated by the OB level averaging circuit 42 is also supplied to the comparison circuit 4D, and the average value and the clamp setting level from the clamp level register 5 are compared by the comparison circuit 4D and output as a result. The clamp circuit 6 is operated by a signal corresponding to the signal corresponding to the difference level to adjust the offset amount of the circuit.

  As described above, according to the fourth embodiment, by averaging the signals from the plurality of light-shielding pixels of the solid-state imaging device and appropriately adjusting the offset amount of the circuit based on the averaged signal level, The occurrence of clamping error can be suppressed, and the influence of random noise can be reduced. If the difference between the previous average value and the signal level from the current light-shielded pixel is larger than the scratch threshold, the signal from the light-shielded pixel is determined to be an abnormal level and the previous average value is used instead. Thus, a signal from a light-shielded pixel determined to be an abnormal level is not used for the clamping operation, and a clamping operation with a smaller error becomes possible, and a good image signal processing can be performed on the signal from the solid-state imaging device. it can. In addition, a defect in the light-shielding pixel portion of the solid-state imaging device can be accepted to some extent, and the selection criteria (selection standard) can be relaxed to increase the yield.

  Note that the image signal processing circuit shown in FIG. 4 is designed to remove defects corresponding to white flaws in the light-shielding pixels of the solid-state imaging device, but to remove defects corresponding to black flaws. In this case, a subtractor may be used instead of the adder 46.

(Fifth embodiment)
Next, a fifth embodiment will be described.
FIG. 5 is a block diagram showing a circuit configuration example of an image signal processing circuit according to the fifth embodiment of the present invention. The image signal processing circuit according to the fifth embodiment described below is obtained by adding a circuit block related to setting of a scratch threshold to the image signal processing circuit according to the fourth embodiment described above. In FIG. 5, blocks having the same functions as those shown in FIGS. 1 and 4 are denoted by the same reference numerals, and redundant description is omitted.

  In FIG. 5, reference numeral 47 denotes a multiplier that quadruples a clamp error (a signal corresponding to a difference level that is an output of the comparison circuit 4D).

  A comparison circuit 48 receives the output signal of the multiplier 47 and the reference level of the scratch threshold value held in the reference level register 49 and compares them. As a result of the comparison, when the output signal of the multiplier 47 is equal to or higher than the reference level, the comparison circuit 48 supplies the output signal of the multiplier 47 to the adder 44A (corresponding to the adder 44 shown in FIG. 4). The switch 50 is controlled. On the other hand, when the output signal of the multiplier 47 is smaller than the reference level, the switch 50 is controlled so that the reference level held in the reference level register 49 is supplied to the adder 44A.

  The image signal processing circuit according to the fifth embodiment described above operates in the same manner as the image signal processing circuit according to the fourth embodiment, and the same effects as those of the fourth embodiment can be obtained. However, in the image signal processing circuit according to the fifth embodiment, the clamp operation reaches the target clamp level by repeating the operation a plurality of times after the power is turned on. The difference from the output signal from the light-shielding pixel is large, and the correction amount per clamping process is large. Therefore, the difference between the average value used in the previous process and the current level always exists as a difference by this correction amount. Therefore, if a value larger than the correction amount is not set as the scratch threshold value, all the current levels are determined as abnormal levels, and the clamping operation cannot be performed normally.

  Therefore, in the example shown in FIG. 5, four times the current clamping error is used as the scratch threshold value in proportion to the current clamping error. In the above-described example, the gain value is set to four times. However, the gain value is not limited to this, and the optimum value varies depending on the system including the characteristics of the solid-state imaging device. The gain value should be set above.

  In the image signal processing circuit shown in FIG. 5, the level of (clamp error) × 4 (gain) is compared with the reference level held in the reference level register 49, and the larger one is the scratch threshold value. Is supplied to the adder 44A. Here, the reference level means a minimum level necessary as a scratch threshold.

  If the level of (clamp error) × 4 is always set as the scratch threshold without performing the comparison process with the reference level, the scratch threshold becomes 0 when the clamp error is reduced to zero. Thus, it is determined that all the current levels are abnormal levels. For this reason, the image signal processing circuit according to the fifth embodiment is provided with the register 49 for holding the reference level, and the level of (clamp error) × 4 is compared with the reference level, so that the scratch threshold is the reference value. It is configured so that the following can be reliably avoided.

(Other embodiments of the present invention)
Next, a case where the image signal processing circuit in each of the above-described embodiments is applied to a camera will be described.
FIG. 6 is a block diagram showing a configuration example when the image signal processing circuit in each embodiment is applied to a “still video camera”.

  In FIG. 6, reference numeral 61 denotes a barrier that serves both as lens protection and a main switch, 62 denotes a lens that forms an optical image of a subject on the solid-state imaging device 64, 63 denotes a diaphragm for changing the amount of light passing through the lens 62, and 64 A solid-state imaging device for capturing an object imaged by the lens 62 as an image signal, 65 is an image signal processing circuit according to any of the above-described embodiments, and 66 is various corrections to the image data output from the image signal processing circuit 65 Is a signal processing unit that performs data compression and compresses data, 67 is a solid-state imaging device 64, an image signal processing circuit 65, a timing generation unit that outputs various timing signals to the signal processing unit 66, and 68 is a variety of arithmetic and still video cameras. An overall control / arithmetic unit 69 for controlling the whole, a memory unit 69 for temporarily storing image data, and 70 for recording or reading on a recording medium. Interface unit for performing out, a semiconductor memory or the like of a removable recording medium for recording or reading of the image data 71, 72 is an interface unit for communicating with an external computer or the like.

Next, the operation of the still video camera at the time of shooting in the above configuration will be described.
When the barrier 61 is opened, the main power supply is turned on, the control system power supply is turned on, and the image pickup system circuit such as the image signal processing circuit 65 is turned on.

Then, in order to control the exposure amount, the overall control / arithmetic unit 68 opens the diaphragm 63, and the signal output from the solid-state imaging device 64 is subjected to predetermined processing by the image signal processing circuit 65 and then subjected to signal processing. Input to the unit 66.
Based on the data, exposure calculation is performed by the overall control / calculation unit 68.
The brightness is determined based on the result of the photometry, and the overall control / calculation unit 68 controls the aperture according to the result.

  Next, based on the signal output from the solid-state imaging device 64, the high-frequency component is extracted and the distance to the subject is calculated by the overall control / calculation unit 68. Thereafter, the lens 62 is driven to determine whether or not it is in focus. When it is determined that the lens is not in focus, the lens 62 is driven again to perform distance measurement.

Then, after the in-focus state is confirmed, the main exposure starts.
When the exposure is completed, the image signal output from the solid-state imaging device 64 is subjected to predetermined processing including A / D conversion and the like in the image signal processing circuit 65, passes through the signal processing unit 66 and is stored in the memory by the overall control / calculation unit 68. Part 69 is written.

Thereafter, the data stored in the memory unit 69 is recorded on a removable recording medium 71 such as a semiconductor memory through the recording medium control I / F unit 70 under the control of the overall control / arithmetic unit 68.
Further, the image may be processed by directly inputting to a computer or the like through the external I / F unit 72.

In the above embodiment, in the process of adjusting the offset amount of the circuit, a signal from the light-shielded pixel of the solid-state imaging device output from the AD converter 3 is used. A signal from the solid-state image sensor may be used. In this case, each circuit may be appropriately configured with an analog circuit.
In addition, each of the above-described embodiments is merely an example of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

3 AD converter 4A to 4D comparison circuit 5 clamp level register 6 clamp circuit 42 OB level averaging circuit 43 OB average register 1H before 44 adder 45 scratch threshold register 46 comparison circuit

Claims (9)

An image signal processing circuit that performs predetermined processing on an image signal from a solid-state imaging device having a plurality of effective pixels and a plurality of light-shielding pixels,
Intermediate value output means for extracting and outputting median values of signals from the plurality of light-shielding pixels;
An image signal processing circuit comprising: clamp means for adjusting a signal from the light-shielded pixel to a predetermined level based on an output value output from the intermediate value output means. The intermediate value output means divides n × m (n and m are arbitrary natural numbers) signals from the light-shielded pixels into n groups, and extracts and outputs the median value in each group. Intermediate value output means,
A second intermediate value output means for extracting and outputting the median value in the output value as a set of m output values output by the first intermediate value output means;
2. The image signal processing circuit according to claim 1, wherein the clamp unit adjusts a signal from the light-shielding pixel to a predetermined level based on an output value output from the second intermediate value output unit. . The first intermediate value output means includes a first storage means for storing n signals from the light-shielded pixels, and a median value of signals from the n light-shielded pixels stored in the first storage means. First intermediate value extracting means for extracting and outputting
The second intermediate value output means includes second storage means for storing m output values of the first intermediate value extraction means, and m output values stored in the second storage means. 3. The image signal processing circuit according to claim 2, further comprising second intermediate value extraction means for extracting and outputting a median value. An image signal processing circuit that performs predetermined processing on an image signal from a solid-state imaging device having a plurality of effective pixels and a plurality of light-shielding pixels,
Intermediate value output means for extracting and outputting a substantially intermediate value in statistics of signals from the plurality of light-shielding pixels;
An image signal processing circuit comprising: clamp means for adjusting a signal from the light-shielded pixel to a predetermined level based on an output value output from the intermediate value output means. An image signal processing circuit that performs predetermined processing on an image signal from a solid-state imaging device having a plurality of effective pixels and a plurality of light-shielding pixels,
An arithmetic means for calculating and outputting an average value of signals excluding the maximum value and the minimum value among the signals from the plurality of light shielding pixels,
An image signal processing circuit comprising: a clamp unit that adjusts a signal from the light-shielded pixel to a predetermined level based on an average value calculated by the arithmetic unit. The calculating means includes a maximum value detecting means for detecting a maximum value in signals from the plurality of light shielding pixels, and
Minimum value detecting means for detecting a minimum value in signals from the plurality of light-shielding pixels;
A sum total calculating means for calculating a sum of signals from the plurality of light shielding pixels;
6. The four arithmetic operation means for calculating the average value based on the detection result by the maximum value detecting means and the minimum value detecting means and the sum calculated by the sum calculating means. Image signal processing circuit. An image signal processing circuit according to any one of claims 1, 4, and 5,
A lens for forming an optical image on a solid-state imaging device;
A camera comprising: an aperture for changing the amount of light passing through the lens. An image signal processing method for performing predetermined processing on an image signal from a solid-state imaging device having a plurality of effective pixels and a plurality of light-shielding pixels,
An intermediate value output step of extracting and outputting median values of signals from the plurality of light-shielding pixels;
And a clamping step of adjusting a signal from the light-shielding pixel to a predetermined level based on the output value output in the intermediate value output step. An image signal processing method for performing predetermined processing on an image signal from a solid-state imaging device having a plurality of effective pixels and a plurality of light-shielding pixels,
An arithmetic step of calculating and outputting an average value of signals excluding the maximum value and the minimum value among the signals from the plurality of light shielding pixels,
And a clamping step of adjusting a signal from the light-shielding pixel to a predetermined level based on the average value calculated in the calculation step.

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