JP2010177594A - Solid-state imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging apparatus capable of electrically controlling light receiving sensitivity of a long wavelength band. <P>SOLUTION: An imaging portion 10A uses one surface of a p-type Si substrate as an imaging surface. Then, the imaging portion 10A has a plurality of pixels 10 each of which contains a first n-type impurity layer formed near the imaging surface of the p-type Si substrate, is generated in the p-type Si substrate by photoelectric conversion, and outputs a pixel signal showing electric charges accumulated in the first n-type impurity layer. In addition, the imaging portion 10A has a second impurity layer at a position deeper from the imaging surface rather than the first n-type impurity layer. A collection range control means 51 of a timing generator 50 controls a collection range of the electric charges generated by the photoelectric conversion in the p-type Si substrate by controlling control voltage Vsb to be provided in the second n-type impurity layer. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device capable of controlling light receiving sensitivity in a long wavelength band.

  In general, a color solid-state imaging device has a configuration in which any one of R, G, and B color filters is provided for each pixel, and light that has passed through the color filter is converted into a pixel signal that is an electrical signal. In order to obtain the required color reproducibility, it is common to use an IR (InfraRed) cut filter in combination with R, G, and B color filters so that the photoelectric conversion element does not receive wavelengths other than RGB. It is. On the other hand, in-vehicle / surveillance cameras need to improve sensitivity at low illuminance in the dark, so it is necessary to receive light in the NIR (Near InfraRed) band. In many cases, imaging is performed by applying light from a subject to a photoelectric conversion element without cutting the light. However, when image capturing is performed without cutting the NIR band in this way, color reproducibility is impaired. Therefore, an imaging apparatus is provided in which an IR cut filter can be mechanically attached and detached to improve the sensitivity of imaging at low illuminance without sacrificing color reproducibility.

JP 2008-91753 A

  By the way, the above-described imaging device in which the IR cut filter is detachable has a complicated mechanical configuration for attaching and detaching the IR cut filter and is expensive, and thus is not adopted for a small and inexpensive camera. . For this reason, an imaging device that can adjust the light receiving sensitivity in the NIR band at low cost without sacrificing color reproducibility is desired as a popular product suitable for in-vehicle use or monitoring.

  The present invention has been made in view of the circumstances described above, and an object thereof is to provide a solid-state imaging device capable of electrically controlling the light receiving sensitivity in the long wavelength band.

  The present invention includes a first conductivity type first impurity layer formed for each pixel in the vicinity of the imaging surface of the semiconductor substrate, wherein one surface of the first conductivity type semiconductor substrate is an imaging surface, An imaging unit that outputs pixel signals each indicating a charge generated in the semiconductor substrate by photoelectric conversion and accumulated in the first impurity layer, at a position deeper from the imaging surface than the first impurity layer By controlling the imaging unit having the second impurity layer of the second conductivity type and the control voltage applied to the second impurity layer, the first impurity layer and the semiconductor substrate are joined. A first depletion layer connected to the second depletion layer formed by the junction of the second impurity layer and the semiconductor substrate, and a connection portion between the first depletion layer and the second depletion layer; Position in the depth direction from the surface of the semiconductor substrate Controlled, to provide a solid-state imaging apparatus characterized by comprising a collecting range controlling means for controlling the acquisition range of charges generated by photoelectric conversion in said semiconductor substrate.

  In such a solid-state imaging device, light having a short wavelength out of light incident on the surface of the semiconductor substrate does not reach the deep part of the substrate, but light having a long wavelength reaches the deep part of the substrate and generates electric charge by photoelectric conversion. Accordingly, the collection range control means controls the control voltage applied to the second impurity layer to control the charge collection range in the semiconductor substrate, so that the component of the band having a long wavelength out of the received light amount represented by the pixel signal can be obtained. The proportion occupied can be controlled.

  Patent Document 1 discloses a technique related to improvement of light reception sensitivity in a long wavelength band in a solid-state imaging device, but a technique for controlling light reception sensitivity in a long wavelength band by electrical control as in the present invention. Is not disclosed.

  By the way, in imaging at low illuminance, the amount of charge generated by photoelectric conversion is extremely small. Therefore, in order to obtain a desired image quality, it is strongly desired to reduce the ratio of leak noise in the pixel signal.

  Therefore, the present invention uses a first conductivity type semiconductor substrate as an imaging surface, and includes a second conductivity type first impurity layer formed in the vicinity of the imaging surface of the semiconductor substrate. In a solid-state imaging device having a plurality of pixels each outputting a pixel signal indicating charges generated in the semiconductor substrate by conversion and accumulated in the first impurity layer, the first impurity layer, the semiconductor substrate, The impurity concentration of the first conductivity type at the boundary surface of the depletion layer generated by the junction between the first impurity layer and the semiconductor substrate in a state where the maximum reverse bias during normal use is applied during The solid-state imaging device is characterized in that it is higher than the impurity concentration of the first conductivity type in the region.

  According to such a solid-state imaging device, since the impurity concentration of the first conductivity type at the boundary surface of the depletion layer is high, the charge density of minority carriers generated by thermal excitation at the boundary surface is reduced, and the first density via the depletion layer is reduced. Leakage current flowing in one impurity layer can be reduced.

  The present invention also includes a first impurity layer of a second conductivity type formed in the vicinity of the imaging surface of the semiconductor substrate, wherein one surface of the first conductivity type semiconductor substrate is an imaging surface, In a solid-state imaging device having an imaging unit having a plurality of pixels each outputting a pixel signal indicating the electric charge generated in the semiconductor substrate by conversion and accumulated in the first impurity layer, the semiconductor substrate includes the A second depletion layer connected to the first depletion layer generated by the junction of the first impurity layer and the semiconductor substrate and having an electric field opposite to the electric field in the first depletion layer is generated. Provided is a solid-state imaging device that is configured.

  In such a solid-state imaging device, a potential barrier that hinders the movement of electric charges that cause leakage to the first impurity layer is generated at the connection between the first depletion layer and the second depletion layer. Therefore, the leakage current flowing through the first impurity layer can be reduced.

It is a block diagram which shows the structure of the CMOS solid-state imaging device which is one Embodiment of this invention. It is a figure which shows the relationship between this pixel 10 and each circuit which performs the drive control while showing one equivalent circuit of the some pixels 10 which comprise 10 A of imaging parts of the CMOS solid-state imaging device. It is a figure which shows the cross-section of the imaging part of a general CMOS solid-state imaging device. It is a figure which shows the impurity concentration, electric field strength, electron potential, and energy band in each position on the virtual axis which passes through the center of PD formation area in the imaging part of a general CMOS solid-state imaging device. It is a figure which illustrates the cross-section of the image pick-up part of the CMOS solid-state image pick-up device which took the countermeasure against leakage. It is a figure which shows the impurity concentration and energy band in each position on the virtual axis which passes the center of PD formation area in the imaging part. It is a figure which shows the cross-section of 10 A of imaging parts of the CMOS solid-state imaging device by one Embodiment of this invention. It is a figure which shows the electric potential of the electron in each position on the virtual axis which passes along the center of the formation area of the transfer transistor 102 in the imaging part 10A. It is a figure which shows the impurity concentration and energy band in each position on the virtual axis | shaft which passes along the center of PD formation area in the imaging part 10A. It is a figure which shows the impurity concentration in each position on the virtual axis which passes the center of PD formation area in the same imaging part 10A, and the potential of an electron. It is a figure which shows the example of the potential curve along the density profile of the pixel in the same embodiment, and the depth direction from the substrate surface. It is a figure which shows the relationship between the wavelength of the light in a semiconductor substrate, and an absorption coefficient. When the depth t from the substrate surface is changed for each light of blue (λ = 460 nm), green (λ = 530 nm), red (λ = 700 nm), and lower limit wavelength (λ = 780 nm) in the near infrared band. calculating the ratio r = I / I ₀ of the reaching light amount I with respect to the amount of incident light I _0, is a diagram showing the relationship between the depth t and the ratio r. 4 is a time chart showing an operation for one frame of the CMOS solid-state imaging device according to the embodiment and a time chart showing an operation in one horizontal scanning period of the one frame. It is a figure which shows the cross-section of the imaging part of the CMOS solid-state imaging device by other Embodiment of this invention. It is a figure which shows the cross-section of the imaging part of the CMOS solid-state imaging device by other Embodiment of this invention. It is a figure which shows the content of the image process in the CMOS solid-state imaging device by other embodiment of this invention.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the embodiment described below, the first conductivity type is p-type and the second conductivity type is n-type. However, in the present invention, the first conductivity type is n-type and the second conductivity type is p-type. It can also be implemented as a mold.

<A: Overall configuration>
FIG. 1 is a block diagram showing a configuration of a CMOS solid-state imaging device according to an embodiment of the present invention. FIG. 2 is a diagram illustrating an equivalent circuit of one of the plurality of pixels 10 constituting the imaging unit 10A in FIG. 1 and a relationship between the pixel 10 and each circuit that performs drive control thereof.

  As shown in FIG. 2, each pixel 10 includes a PD (Photo Diode) 101, a transfer transistor 102, a reset transistor 103, an amplification transistor 104, and a row selection transistor 105, each of which is a MOS transistor, a color, The filter 106 is configured.

  In FIG. 2, a PD 101 is formed by forming a buried layer of low-concentration n-type impurities on a p-type semiconductor substrate. The PD 101 is a photoelectric conversion element that collects charges generated in the semiconductor substrate by photoelectric conversion in a cathode (in this case, an n-type impurity buried layer) and accumulates the signal charges. On the path of incident light with respect to the PD 101, color filters 106 corresponding to any of R, G, and B are provided. Here, the G and B color filters 106 have a transmission characteristic that transmits light in the G or B wavelength band and transmits light in the NIR band or more. The R color filter 106 has a transmission characteristic that transmits light having a wavelength equal to or greater than the R wavelength band including the NIR band.

  The transfer transistor 102 has a source serving as a cathode of the PD 101 and a drain serving as an FD (Floating Diffusion) 102d. The transfer transistor 102 transfers the signal charge accumulated in the PD 101 to the FD 102d when a transfer pulse TXi is applied to the gate. The reset transistor 103 has a source fixed to the power supply voltage VDD and a drain FD102d. The reset transistor 103 resets the FD 102d to the power supply voltage VDD when a reset pulse RTi is given to the gate. The amplification transistor 104 has a drain fixed to the power supply voltage VDD and a gate connected to the FD 102d. The row selection transistor 105 is interposed between the source of the amplification transistor 104 and the column signal line 11, and a row selection pulse SLi is given to the gate. The amplification transistor 104 and the row selection transistor 105 serve as a readout circuit that reads out a voltage corresponding to the electric charge accumulated in the FD 102d to the column signal line 11 when the row selection pulse SLi is applied.

  In the configuration described above, light having a short wavelength out of light transmitted through the color filter 106 and incident on the PD 101 has a large momentum, and therefore reaches only a shallow portion from the surface of the semiconductor substrate. On the other hand, light having a long wavelength has a small momentum and therefore reaches a deep position from the substrate surface. For this reason, when it goes deep from the substrate surface, the charges generated by the light having a short wavelength are reduced, and the charges generated by the light having a long wavelength occupy a large number. Therefore, when charges in the range from the substrate surface to a shallow portion of the charges generated in the semiconductor substrate by photoelectric conversion are collected on the cathode of the PD 101, a lot of charges generated by light having a short wavelength are generated in the cathode of the PD 101. get together. However, in the case where charges in a range sufficiently deep from the substrate surface are collected on the cathode of the PD 101, light having a long wavelength including light in the NIR band as well as the charge generated by light having a short wavelength is generated. A lot of electric charges generated by. The feature of this embodiment is that the charge collection range in the depth direction from the substrate surface is switched by electrical control. The purpose is to obtain the same effect as switching the transmittance of the color filter 106 in the near-infrared band as shown in FIG. The timing generator 50 in FIG. 1 has a function as a collection range control means 51 that generates a control voltage Vsb used for controlling the charge collection range. The imaging unit 10A according to the present embodiment employs a novel configuration that enables electrical control of such a charge collection range. A new configuration of the imaging unit 10A will be described later.

  Similar to a general CMOS solid-state imaging device, in the imaging unit 10A, as shown in FIG. 1, a plurality of pixels 10 are arranged in a matrix. A plurality of pixels 10 forming each column are connected to a column signal line 11 provided for each column. As shown in FIG. 2, each column signal line 11 is connected to a constant current source 11 c serving as a load of the amplification transistor 104 of each pixel 10 connected to the column signal line 11. Each column signal line 11 is connected to a column CDS (Correlated Double Sampling) unit 20 as shown in FIG. The column CDS unit 20 is an aggregate of CDS circuits provided for each column of the pixels 10 in the imaging unit 10A. Each CDS circuit samples a voltage read to each column signal line 11 of the imaging unit 10A at each timing when the sampling pulses φr and φs are supplied from the timing generator 50, detects a difference, and outputs an analog pixel signal, respectively. To do. The column ADC unit 30 is an aggregate of ADCs (Analog to Digital Converters) provided for each column of the pixels 10 in the imaging unit 10A. Each ADC converts an analog pixel signal output from each CDS circuit into a digital pixel signal under the control of the timing generator 50. The horizontal scanning circuit 40 is a shift register having the same number of stages as the number of columns of the imaging unit 10A. Under the control of the timing generator 50, the horizontal scanning circuit 40 repeats the operation of taking one row of digital pixel signals output from the column ADC unit 30 and transferring them serially to the image processing unit 70 for each horizontal scanning period.

  The timing generator 50 is a circuit that generates signals for timing control of each part of the CMOS solid-state imaging device, such as the vertical scanning circuit 60, the column CDS unit 20, the column ADC unit 30, and the horizontal scanning circuit 40. Further, the timing generator 50 has a function as the collection range control means 51 described above. The vertical scanning circuit 60 controls driving of the imaging unit 10A for exposure under the control of the timing generator 50, that is, selects each row of the imaging unit 10A, and selects the row selection pulse SLi, the reset pulse RTi, and the transfer to each selected row. This circuit performs control to generate the pulse TXi.

  In the present embodiment, exposure is performed twice per frame under the control of the timing generator 50. In the first exposure, the charge collection range in the depth direction from the substrate surface is widened over the entire exposure period. In the second exposure, the charge collection range in the depth direction from the substrate surface is narrowed in a part of the exposure period.

  The image processing unit 70 is a device that processes digital pixel signals supplied via the horizontal scanning circuit 40 and synthesizes image data for one screen for each frame. As described above, in the present embodiment, exposure is performed twice within one frame period. The image processing unit 70 uses the digital pixel signal acquired through the horizontal scanning circuit 40 in the first exposure and the digital pixel signal acquired through the horizontal scanning circuit 40 in the second exposure. Synthesize image data. The image data synthesized by the image processing unit 70 is displayed on a monitor (not shown) or recorded on a recording medium such as an HD (hard disk) (not shown). The U / I (user interface) unit 80 includes a display device such as a liquid crystal display panel and various operators such as push buttons. The U / I unit 80 displays various guidance information related to the operation of the CMOS solid-state imaging device, and plays a role of acquiring various information related to imaging conditions and the like from the user via the operation element. The control unit 90 is a device that controls each unit of the CMOS solid-state imaging device in accordance with an instruction from the user acquired via the U / I unit 80.

<B: Configuration of Imaging Unit 10A>
<B-1: Configuration of Imaging Unit in General CMOS Solid-State Imaging Device>
In order to facilitate understanding of the imaging unit 10A in the present embodiment, the configuration of the imaging unit in a general CMOS solid-state imaging device will be described prior to the description of the configuration of the imaging unit 10A. FIG. 3 is a diagram schematically illustrating a cross-sectional structure of one pixel of an imaging unit in a general CMOS solid-state imaging device. In FIG. 3, the same reference numerals as those in FIG. 2 are used for the elements corresponding to the elements shown in FIG. 2 for easy understanding of the correspondence with the elements constituting the pixel. Further, in FIG. 3, in order to prevent the drawing from becoming complicated, illustration of portions corresponding to the amplification transistor 104, the row selection transistor 105, and the color filter 106 in FIG. 2 is omitted.

  In the example shown in FIG. 3, each element constituting the pixel is formed on a p-type Si substrate 200. In the present specification and drawings, for convenience of explanation, each region of the p-type Si substrate 200 doped with a p-type impurity is distinguished from a pk layer (k is different from other regions doped with a p-type impurity). Each region doped with an n-type impurity is denoted as an nk layer (k is an index for distinguishing from other regions doped with an n-type impurity). For a region doped with a high-concentration impurity, for example, an n + layer may be used, and a notation with + added to n indicating the conductivity type may be used.

  In FIG. 3, the p-type Si substrate 200 has a high-concentration p3 layer on the back side, and most of the section from the p3 layer to the substrate surface is a p2 layer having a lower concentration than the p3 layer. . In the region around the pixel, the p3 layer extends from the substrate surface to the substrate back surface. The p3 layer is grounded on the substrate surface side. The PD 101 uses the p2 layer as an anode and the n1 layer embedded near the substrate surface as a cathode. The region of the substrate surface immediately above the n1 layer is a p1 layer having a higher concentration than the p2 layer.

  The transfer transistor 102 uses the n1 layer that is the cathode of the PD 101 as a source and the n + layer that is the FD 102d as a drain. The gate of the transfer transistor 102 to which the transfer pulse TX is applied is opposed to the channel formation region between the n1 layer and the n + layer that is the FD 102d with the insulating film interposed therebetween. The reset transistor 103 uses the n + layer, which is the FD 102d, as a drain and uses another n + layer provided on the substrate surface as a source. Here, the source of the reset transistor 103 is fixed to the power supply voltage VDD. The gate of the reset transistor 103 to which the reset pulse RT is applied is opposed to the channel formation region between the drain and source with the insulating film interposed therebetween.

  FIG. 4A shows the concentration profile of each part along a virtual axis passing through the center of the region where the PD 101 is formed. In this figure, the horizontal axis is the depth t from the substrate surface, the + direction on the vertical axis is the acceptor concentration, and the − direction is the donor concentration. 4 (b) to 4 (d) share the horizontal axis with FIG. 4 (a). FIG. 4B shows the electric field strength at each position along a virtual axis passing through the center of the PD101 formation region. In FIG. 4B, the electric field from the substrate surface to the substrate back surface is a positive electric field, and the electric field from the substrate back surface to the substrate surface is a negative electric field. FIG. 4C shows the relative electron potential of each part virtually along the axis, where the electron potential on the substrate surface is zero. In the present specification and drawings, the “electron potential” is determined so that electrons move from a high potential to a low potential. FIG. 4D shows the energy band at each position along the virtual axis. In FIG. 4D, Ev is the upper limit energy level of the valence band, and Ec is the lower limit energy level of the conduction band. 4 (b) to 4 (d) are illustrated assuming that the n1 layer has a positive potential and a reverse bias is applied between the n1 layer and the surrounding p1 and p2 layers. Yes.

  4A, at the junction between the n1 layer and the p2 layer, electrons that are majority carriers in the n1 layer diffuse into the p2 layer, and holes that are majority carriers in the p2 layer diffuse into the n1 layer. For this reason, the region in the vicinity of the boundary with the p2 layer in the n1 layer is positively charged through the removal of electrons, and the region in the vicinity of the boundary with the n1 layer in the p2 layer is negatively charged through the removal of holes. In the vicinity of the junction, only space charge exists, and a depletion layer (space charge region) in which no carrier exists. The depletion layer in the vicinity of the junction between the n1 layer and the p2 layer includes a positively charged potential of the n1 layer and a negatively charged potential of the p2 layer as shown in FIG. 4B. A positive electric field is generated based on the diffusion voltage, which is the difference between. Here, when a reverse bias is applied between the n1 layer and the p2 layer, the reverse bias widens the diffusion voltage and strengthens the positive electric field based on the diffusion voltage. As shown in FIG. 4B, this positive electric field has a peak at the boundary surface between the n1 layer and the p2 layer, and in each of the n1 layer and the p2 layer, as the distance from the boundary surface between the n1 layer and the p2 layer increases. become weak. In the p2 layer, the electric field becomes 0 at a position away from the interface with the n1 layer. The surface where the electric field becomes zero is the depletion layer boundary surface S.

  In the depletion layer in the vicinity of the junction between the n1 layer and the p2 layer, a drift current (a flow of holes in the direction of the electric field and a flow of electrons in the direction opposite to the electric field) caused by such an electric field, Is balanced, and no current flows when viewed as a whole.

  In general, in a CMOS solid-state imaging device, as shown in the drawing, an acceptor concentration higher than the donor concentration of the n1 layer and a shallow p1 layer are provided as an upper layer of the n1 layer. This is because the depletion layer generated by the junction between the p2 layer and the n1 layer does not reach the surface of the p-type Si substrate 200 having many dangling bonds (interface states), and the potential generated in the n1 layer is reduced. This is because the bottom is not positioned too deeply. The bottom of the latter potential will be described later.

  When the p1 layer is provided as an upper layer of the n1 layer, a depletion layer is also generated near the junction between the n1 layer and the p1 layer. That is, at the junction between the n1 layer and the p1 layer, there is diffusion of electrons from the n1 layer to the p1 layer and diffusion of holes from the p1 layer to the n1 layer, and these diffusions cause a junction between the n1 layer and the p1 layer. A depletion layer is generated in the vicinity, and an electric field in a negative direction from the n1 layer to the p1 layer is generated in the depletion layer as shown in FIG. 4B. As shown in FIG. 4B, the electric field in the negative direction has a peak at the boundary surface between the n1 layer and the p1 layer, and from each of the n1 layer and the p1 layer, the boundary surface between the n1 layer and the p1 layer. It gets weaker as you leave. In the p1 layer, the surface where the electric field is zero away from the boundary surface with the n1 layer becomes the other boundary surface S of the depletion layer. In general, in the CMOS solid-state imaging device, the concentration of the p1 layer is adjusted so that the depletion layer boundary surface S in the p1 layer is generated at a position slightly advanced in the depth direction from the substrate surface.

  When the electric field strength shown in FIG. 4B is integrated along the depth direction of the substrate, a potential curve shown in FIG. 4C is obtained. In a region where a negative electric field from the substrate back side to the substrate surface side is generated near the boundary between the p1 layer and the n1 layer, as shown in FIG. Electron potential decreases. An inflection point b1 of the potential curve occurs at the boundary between the p1 layer and the n1 layer where the negative electric field peaks. On the other hand, in a region where a positive electric field is generated from the substrate surface side to the substrate back surface side in the vicinity of the boundary between the n1 layer and the p2 layer, as shown in FIG. The electron potential decreases as it goes. An inflection point b3 of the potential curve occurs at the boundary between the n1 layer and the p2 layer where the electric field in the positive direction peaks. Inside the n1 layer, there is a point where the electric field becomes 0, and at this point, the potential becomes the minimum value b2. This potential b2 is the bottom of the potential described above. Electrons generated by the photoelectric effect in the substrate gather at the bottom b2 of this potential.

  When few electrons collect at the bottom b2 of the potential, the electrons accumulate at the position of the bottom b2 of the local potential. However, when more electrons gather at the bottom b2 of the potential and the charge density becomes the same as the impurity concentration of the n1 layer, the electron expands the existing region of the potential bottom b2 that has been localized until then, and this flat It accumulates in a region with a bottom b2 of a great potential. As the potential bottom b2 region expands in this way, the depletion layer around the n1 layer is reduced accordingly.

  The electrons accumulated at the bottom b2 of the potential in the n1 layer are transferred to the FD 102d when the transfer transistor 102 in FIG. 3 is turned on. The electrons transferred to the FD 102d are read out as electric signals.

<B-2: Configuration of Pixels in Imaging Unit for Leak Reduction>
If the amount of light incident on the pixel is large when reading a signal from the pixel, the light shot noise is dominant in the noise in the read pixel signal, and the leak noise can be ignored. However, when there is no incident light on the pixel when reading a signal from the pixel, or when the amount of incident light is extremely low even when there is incident light, leak noise occupies a large weight in the noise in the pixel signal. In order to reduce this leakage noise, after the reset operation for applying the power supply voltage VDD to the FD 102d is performed, the transfer transistor 102 is turned on, and the power supply voltage VDD is supplied to the n1 layer of the PD 101. It is necessary to reduce the leakage current when the maximum reverse bias is applied between the p1 layer and the p2 layer.

  Here, in the depletion layer generated by the junction of the n1 layer and the surrounding p2 layer or the p1 layer, there is no excitation of electrons from the valence band to the conduction band due to the photoelectric effect in a state where there is no incident light or a very small amount. Further, inside the depletion layer, the probability of excitation of electrons from the valence band to the conduction band due to heat is low, and the occurrence of leakage due to this thermal excitation can be ignored. A leak that cannot be ignored is a leak that passes through the boundary surface S of the depletion layer.

  In FIG. 4D, when conduction band electrons are generated by thermal excitation near the boundary surface S of the depletion layer in the p1 layer or the p2 layer, the electrons as minority carriers pass through the boundary surface S of the depletion layer. Then, it may occur that the potential moves to the bottom b2 of the potential in the n1 layer (that is, a leak current from the substrate to the n1 layer occurs). The magnitude of the leak current generated in this way is proportional to the minority carrier densities Np1 and Np2 in the vicinity of the boundary surface S of the depletion layer in the p1 layer and in the vicinity of the boundary surface S of the depletion layer in the p2 layer. Here, the minority carrier densities Np1 and Np2 in the vicinity of each boundary surface S are given by the product of the Fermi-Dirac distribution function and the state density function of the conduction band at their respective positions. The higher the temperature, the higher the minority carrier density. At this time, the higher the impurity concentration at each position, the smaller the minority carrier density increases with increasing temperature. Therefore, in order to reduce the leakage current, the position of the boundary surface S of the depletion layer when the maximum reverse bias is applied between the n1 layer, the p1 layer, and the p2 layer at the time of resetting is obtained. It is effective to increase the concentration of the p-type impurity in the vicinity of the boundary surface S.

  FIG. 5 is a cross-sectional view illustrating a configuration example of a pixel of an imaging unit in which leakage countermeasures are taken in accordance with such a concept. FIG. 6 shows a density profile and an energy band along a virtual axis passing through the center of the formation region of the PD 101 in the pixel shown in FIG.

  In the pixel in this example, the boundary surface between the p3 layer and the p2 layer is closer to the n1 layer side than the pixel shown in FIG. 3, and the boundary surface S of the depletion layer generated by the junction between the n1 layer and the p2 layer at the reset is p3. To occur in the layer. The acceptor concentration of the p1 layer and the p3 layer where the depletion layer boundary surface S is generated at the time of reset is sufficiently higher than that of the p2 layer, and the minority carrier density Np1 and Np3 generated at each boundary surface S in each layer is sufficiently high. I try to lower it. Therefore, according to the configuration shown in FIG. 5, the leakage current at the time of reset can be reduced as compared with the configuration shown in FIG.

  In FIG. 6, in order to prevent the illustration from becoming complicated, the impurity concentration distributions of the p1 layer and the p2 layer are drawn in a square shape. However, the impurity concentration at the position of the boundary surface S of the depletion layer at the time of resetting is illustrated. It is preferable that the impurity concentration profile has a maximum value. The p2 layer may be a p-type layer, and its acceptor concentration may be as close to 0 as possible.

<B-3: Configuration of Imaging Unit 10A According to the Present Embodiment>
FIG. 7 is a diagram illustrating a cross-sectional structure of the pixel 10 of the imaging unit 10A according to the present embodiment. As shown in FIG. 7, in the pixel 10 according to the present embodiment, an n2 layer having a higher concentration than the n1 layer is provided as a lower layer of the p3 layer. A control voltage Vsb is applied to the n2 layer from the timing generator 50 shown in FIG. The n2 layer may be formed by doping n-type impurities from the back surface of the p-type Si substrate 200, or may be a buried layer in the p-type Si substrate 200. In the pixel 10 according to the present embodiment, the p2 layer protrudes toward the gate of the transfer transistor 102 in a region immediately below the gate of the transfer transistor 102. A p4 layer having a higher acceptor concentration than the p2 layer is buried in a region slightly below the surface region of the p-type Si substrate 200 immediately below the gate of the transfer transistor 102.

The concentration profile of the p4 layer is determined so as to satisfy the following condition.
a. When the power supply voltage VDD is applied to the gate of the transfer transistor 102 to turn it on, the potential on the current path from the PD 101 to the FD 102d decreases monotonously.
b. The current path from the PD 101 to the FD 102d does not contact the surface of the p-type Si substrate 200 immediately below the gate of the transfer transistor 102.
c. When the transfer transistor 102 is turned off, a sufficient potential barrier is generated between the PD 101 and the FD 102d.

Further, in order to suppress flicker noise of the transfer transistor 102, it is preferable to determine the concentration profile of the p4 layer so as to satisfy the following condition.
d. The potential of electrons at each position along a virtual axis that vertically penetrates the region directly below the gate of the transfer transistor 102 draws a curve as shown in FIG.
That is, the following conditions must be satisfied.
d1. A dip having a potential lower than the interface potential on the surface of the p-type Si substrate 200 is generated at a position away from the substrate surface. A region where this potential dip occurs is a current path from the PD 101 to the FD 102d.
d2. The potential D on the surface of the p-type Si substrate 200 is higher than the interface state on the substrate surface, and there is a potential barrier V in the vicinity of the substrate surface in the interval from the surface to the predetermined distance in the depth direction.

Here, the size of the potential barrier V only needs to satisfy the following equation.
V >> kT / e = 0.0259 (V) (1)
However, in said Formula (1), k is a Boltzmann constant and T is the absolute temperature in the use environment of a CMOS solid-state imaging device. Here, it is necessary to make the width of the potential barrier V in the substrate depth direction narrow so that electrons do not pass through the potential barrier due to the tunnel current. By doing so, it is possible to prevent electrons in the valence band from flowing into the current path from the PD 101 to the FD 102d through the interface state on the substrate surface immediately below the gate of the transfer transistor 102.

When the potential curve as shown in FIG. 8 is determined, the necessary concentration profile can be calculated from the potential φ on the potential curve, for example, by the following equation.
ρ = ε _s ε ₀ Δφ (2)
Here, ρ is a charge density (that is, impurity concentration), ε _s is a relative dielectric constant, ε ₀ is a vacuum dielectric constant, and Δ is a Laplacian operator. That is, a necessary potential curve as shown in FIG. 8 is drawn, and this curve may be differentiated twice by the depth t.

  FIG. 9A shows a concentration profile along a virtual axis that crosses the center of the formation region of the PD 101 in the configuration shown in FIG. 7 from the substrate surface to the substrate back surface. The concentration profile shown in FIG. 9A assumes a case where the impurity concentration of the p3 layer is set to the same concentration as that of the configuration shown in FIG. FIG. 9B is an energy band diagram when the concentration profile shown in FIG. 9A is adopted in the configuration shown in FIG.

  In the example shown in FIG. 9A, in the state where the maximum reverse bias (reverse bias immediately after the reset of the pixel 10) is applied to the junction of the n1 layer and the p2 layer as in the configuration of FIG. 5 described above, n1 and p2 The interface S of the depletion layer generated from the junction of the layers reaches the inside of the high concentration p3 layer. Minority carriers Np3 are generated by thermal excitation at the interface S of the depletion layer. When the p3 layer has a high concentration, the density of this minority carrier Np3 is low, and the current value of the leakage current resulting from this is small. However, as long as there is a minority carrier Np3, a leak current corresponding to the minority carrier Np3 flows. Therefore, in this embodiment, the interface S of the depletion layer where the minority carrier Np3 is generated is eliminated. Details will be described below.

  In the pixel 10 according to the present embodiment, as shown in FIG. 7, there is an n2 layer below the p3 layer, and a depletion layer is generated in the vicinity of the junction between the p3 layer and the n2 layer. Here, when the concentration of the p3 layer is lowered, the interface S of the depletion layer in the p3 layer shown in FIG. 9A moves in a deeper direction (a direction with the substrate back surface). Then, by reducing the concentration of the p3 layer as necessary, a depletion layer extending from the n1 layer side (a depletion layer generated by the junction of the n1 layer and the p2 layer) in the p3 layer is extended from the n2 layer side. Layer (a depletion layer generated by the junction of the p3 layer and the n2 layer).

  FIG. 10A shows the density profile in such a state. FIGS. 10B to 10E show the electron potential of each part when the concentration profile of FIG. 10A is adopted. More specifically, FIGS. 10B and 10C show the potential of each part when the control voltage Vsb is very close to 0 V, and FIG. 10B shows the accumulation of charges in the n1 layer. FIG. 10C shows the potential when electrons are accumulated in the n1 layer up to the vicinity of the saturation state. FIGS. 10D and 10E show the potential of each part when the control voltage Vsb is a predetermined value sufficiently higher than 0 V. FIG. 10D shows the charge in the n1 layer. FIG. 10E shows the potential in the case where electrons are accumulated in the n1 layer up to the vicinity of the saturation state.

  In the example shown in FIG. 10B, in the vicinity of the junction with the n2 layer in the p3 layer, the depletion layer D1 extending from the n1 layer side and the depletion layer D2 extending from the n2 layer side are connected. Since the connection portion between the depletion layer D1 and the depletion layer D2 is also depleted, minority carriers due to thermal excitation are not generated here. In the depletion layer D1, the potential increases from the substrate surface side to the substrate back surface side, and in the depletion layer D2, the potential increases from the substrate back surface side to the substrate surface side. Therefore, at the connection portion of the depletion layers D1 and D2 A potential peak occurs. This potential peak serves as a potential barrier that prevents the movement of charges between the n1 layer and the n2 layer, and is preferably sufficiently high. According to such a configuration, it is possible to prevent leakage from the deep portion of the substrate to the n1 layer in the PD101 formation region.

  In a preferred embodiment, a leak prevention measure based on the same principle is applied to a horizontal leak parallel to the substrate surface. More specifically, a depletion layer extending from the n2 layer side of the PD 101 of one pixel 10 and a depletion layer extending from the n2 layer side of the PD 101 of the other pixel 10 are connected between adjacent pixels 10. Further, in each pixel 10, the depletion layer extending from the n2 layer side of the PD 101 and the depletion layer extending from the FD 102d side are connected. However, it is necessary to adjust the concentration of each part so that the potential barrier generated at the connection part of the two depletion layers is sufficiently high.

In addition to the above, the section from the n2 layer of the PD 101 to the surface of the p-type Si substrate 200 can be considered as a target for taking measures against leakage. In a CMOS solid-state imaging device, when light reception in a short wavelength region may be sacrificed, the following can be adopted as a configuration for eliminating leakage in this section. First, a gate oxide film (SiO ₂ film) is provided on the substrate surface region immediately above the n1 layer, and a gate electrode facing the substrate surface region immediately above the n1 layer is provided thereon. By applying a positive voltage to the gate electrode, a depletion layer extending in the depth direction from the substrate surface side and connected to the depletion layer generated by the junction of the n1 layer and the p1 layer is generated in the p1 layer. This provides a potential barrier that prevents the movement of electrons between the interface state on the substrate surface and the bottom of the potential in the n1 layer.

By taking all the above countermeasures against leakage, it is possible to form the envelope surface of the connection portion of the depletion layer serving as the potential barrier so as to surround the generation position of the bottom of the potential inside the n1 layer from all directions. Therefore, if the p-type Si substrate 200 is a defect-free crystal and there is no excitation of electrons from the valence band to the conduction band, the leakage is free.

  Next, the control function of the electron collection range, which is the greatest feature of the pixel 10 according to the present embodiment, will be described. In FIG. 10B, a positive electric field is generated in the depletion layer D1 extending from the n1 layer side from the substrate back side to the substrate surface side. On the other hand, in the depletion layer D2 extending from the n2 layer side, a negative electric field is generated from the substrate surface side to the substrate back side. Accordingly, among the electrons generated in the p-type Si substrate 200 generated by the photoelectric effect, the electrons in the depletion layer D1 gather at the bottom of the potential in the n1 layer. That is, the range of the depletion layer D1 is a collection range of electrons generated by the photoelectric effect.

  When the control voltage Vsb is close to 0 V and the depletion layer D1 extends from the substrate surface to a deep position as shown in FIG. 10B, electrons having short wavelengths are generated at a shallow position from the substrate surface. In addition, electrons generated by light having a long wavelength deep from the substrate surface also gather at the bottom of the potential in the n1 layer.

  When the control voltage Vsb applied to the n2 layer is switched from a value close to 0V to a predetermined value sufficiently larger than 0V, the potential curve changes from that shown in FIG. 10 (b) to that shown in FIG. 10 (d). To do. As shown in FIG. 10 (d), when the control voltage Vsb is increased, the dimension of the depletion layer D2 in the depth direction is lengthened, and the dimension of the depletion layer D1 is shortened accordingly, and the connection part of the depletion layers D1 and D2 is increased. Moves to the n1 layer side. That is, the collection range of electrons generated by the photoelectric effect is narrower than that shown in FIG. This is because when the control voltage Vsb increases, the diffusion voltage generated at the junction between the n2 layer and the p3 layer increases correspondingly, and the depletion layer D2 increases in thickness.

  When the control voltage Vsb is sufficiently larger than 0V and the depletion layer D1 extends only to a shallow part from the substrate surface as shown in FIG. 10D, light having a short wavelength is shallow at the substrate surface. Only the generated electrons gather at the bottom of the potential in the n1 layer.

  As described above, in the pixel 10 according to this embodiment, the collection range of electrons generated by the photoelectric effect can be changed by changing the control voltage Vsb, and the light receiving sensitivity in the long wavelength band can be controlled.

  The above effects are prominent when the amount of charge accumulated in the n1 layer of the pixel is extremely small, such as when shooting in a dark environment or when shooting an object with low illuminance. When the illuminance of the pixel is increased, a charge accumulation region is formed in the n1 layer, and as shown in FIGS. 10C and 10E, the thickness of the depletion layer D1 generated by the junction of the n1 layer and the p2 layer is reduced. It will not reach the deep part of the board. For this reason, when the control voltage Vsb is close to 0 V, the depletion layer D1 is separated from the depletion layer D2, as shown in FIG. In the state where the control voltage Vsb is sufficiently larger than 0V, the depletion layer D2 itself is sufficiently thick. Therefore, even if the accumulation of charges in the n1 layer increases and the thickness of the depletion layer D1 decreases, the depletion layers D1 and D2 are connected. However, as shown in FIG. 10E, the position of the connection part of the depletion layers D1 and D2 is compared with the case where no charge is accumulated in the n1 layer (see FIG. 10D). Move slightly toward the substrate surface. The amount of movement of the connecting portion depends on the concentration ratio of the p2 layer and the p3 layer, but if the concentration of the p2 layer is sufficiently higher than the concentration of the p3 layer, the amount of movement should be negligible. it can. Therefore, when the control voltage Vsb is sufficiently higher than 0 V, the charge collection range generated by the photoelectric effect can be kept almost constant regardless of the amount of charge accumulated in the n1 layer.

  In summary, the effects of the present embodiment are as follows. That is, according to the present embodiment, by setting the control voltage Vsb to a value close to 0 V, the charge collection range can be extended from the substrate surface to a deep place during a period when the charge accumulation in the n1 layer is small. By setting the voltage Vsb to a value sufficiently higher than 0 V, the charge collection range can be maintained at a certain position near the substrate surface regardless of the amount of charge accumulation in the n1 layer. Therefore, according to the present embodiment, by reducing the control voltage Vsb, the ratio of the signal component corresponding to the component in the long wavelength region included in the pixel signal is increased, and by increasing the control voltage Vsb, It is possible to reduce the ratio of the signal component corresponding to the included component in the long wavelength region.

  Here, a specific example is given and the effect of this embodiment is demonstrated in detail. FIGS. 11A and 11B show examples of density profiles along a virtual axis passing through the center of the PD formation region in the imaging unit 10A shown in FIG. Here, in FIG. 11A, the p-type impurity concentration is shown as a positive concentration, and the n-type impurity concentration is shown as a negative concentration. FIG. 11B ignores the conductivity type of impurities and displays the magnitude of concentration in common logarithm. In FIGS. 11A and 11B, the thicknesses of the p1, n1, p2, and p3 layers in the depth direction from the substrate surface are clarified. In each of these drawings, the concentration of the n2 layer is not shown.

  11 (c) and 11 (d) show the result of the simulation of the potential curve along the virtual axis passing through the center of the PD formation region, assuming the concentration profile shown in FIGS. 11 (a) and 11 (b). FIG. 11C shows a potential curve when the control voltage Vsb is 0V, and FIG. 11D shows a potential curve when the control voltage Vsb is 0.33V. When the control voltage Vsb is 0 V, as shown in FIG. 11C, the potential rises while gradually decreasing the gradient as it goes from the bottom position of the potential in the n1 layer to the deep part of the substrate. However, when the control voltage Vsb is 0.33 V, as shown in FIG. 11D, the peak portion of the potential barrier is generated at a depth of about 6 μm from the substrate surface. When the peak portion of the potential barrier is generated at this position, it is possible to effectively prevent electrons generated by the photoelectric effect of light in the near infrared band from moving to the n1 layer. The reason will be described below.

FIG. 12 shows the relationship between the wavelength of light and the light absorption rate α in a semiconductor substrate (more specifically, a Si single crystal substrate). Here, when light is incident perpendicular to the surface of the semiconductor substrate, the amount of incident light on the substrate surface is I ₀ , and the amount of light reaching the position of the depth t from the surface of the semiconductor substrate is I. the ratio r = I / I ₀ of the reaching light amount I to _0, with absorption rate α shown in FIG. 11 can be calculated according to the following equation.
r = I / I ₀ = e ^−αt (3)
The absorptance α in the above formula (3) depends on the wavelength λ of the incident light. The absorptance α increases as the wavelength λ is shorter, and the absorptance α decreases as the wavelength λ is longer.

FIG. 13 shows the depth t from the substrate surface for each light of blue (λ = 460 nm), green (λ = 530 nm), red (λ = 700 nm), and lower limit wavelength (λ = 780 nm) in the near infrared band. the ratio r = I / I0 of reaching light amount I with respect to the amount of incident light I ₀ when changing are those calculated according to equation (3) shows the relationship between the depth t and the ratio r. In calculating the ratio r according to the equation (3), the absorptance α at each wavelength λ is the one read from FIG. 12, and α = 2 × 10 ⁴ cm ⁻ for blue (λ = 460 nm). ¹ , α = 1 × 10 ⁴ cm ⁻¹ for green (λ = 530 nm), α = 2 × 10 ³ cm ⁻¹ for red (λ = 700 nm), lower limit wavelength of near infrared band (λ = 780 nm) Is set to α = 1 × 10 ³ cm ⁻¹ .

In FIG. 13, paying attention to the position where the depth t from the substrate surface is 6 μm, the ratio r of the reached light quantity I to the incident light quantity I ₀ is about 1/3 for red (λ = 700 nm) and green (λ = 530 nm). ) And blue (λ = 460 nm) are even lower values. Therefore, about 2/3 of the red (λ = 700 nm) light is absorbed by the semiconductor substrate while generating electrons by the photoelectric effect until reaching the position of depth t = 6 μm from the substrate surface, Further, green (λ = 530 nm) and blue (λ = 460 nm) incident light having a ratio higher than that is absorbed by the semiconductor substrate while generating electrons by the photoelectric effect. As shown in FIG. 11D, when the control voltage Vsb is set to 0.33 V, a peak portion of the potential barrier is generated at a position where the depth t = 6 μm from the substrate surface, and the depth t = 6 μm from the substrate surface. This range is the collection range of electrons generated by the photoelectric effect. Therefore, in this case, red (λ = 700 nm), green (λ = 530 nm), and blue (λ = 460 nm) incident light collects electrons generated in the photoelectric effect in the semiconductor substrate at a high ratio in the n1 layer. Will be.

On the other hand, at the lower limit wavelength (λ = 780 nm) in the near-infrared band, the ratio r of the reached light amount I at the position of the depth t = 6 μm with respect to the incident light amount I ₀ is about ½. At a wavelength λ longer than the lower limit wavelength of the near infrared band, the ratio r is even lower. Accordingly, as shown in FIG. 11D, when the peak portion of the potential barrier is generated at a position of depth t = 6 μm from the substrate surface, electrons generated in the semiconductor substrate by light in the near infrared band due to the photoelectric effect. Only less than half of the electrons gather in the n1 layer.

  On the other hand, when the control voltage Vsb is 0 V, the potential barrier as shown in FIG. 10D does not occur near the substrate surface, and the potential is in the n1 layer as shown in FIG. As it goes from the bottom position of the potential to the deep part of the substrate, the gradient gradually increases while decreasing. Accordingly, not only electrons generated by the photoelectric effect of blue, green, and red incident light, but also electrons generated by the photoelectric effect of incident light in the near infrared band are collected in the n1 layer at a high ratio. .

  As described above, according to the present embodiment, the light receiving sensitivity in the near infrared band can be controlled by the control voltage Vsb.

<C: Operation of the present embodiment>
FIG. 14A is a time chart showing the operation of one frame of the CMOS solid-state imaging device according to the present embodiment, and FIG. 14B is a time chart showing the operation in one horizontal scanning period of the one frame. is there.

  In the CMOS solid-state imaging device, horizontal scanning is performed in which each row i of the pixels 10 constituting the imaging unit 10A is sequentially selected and a pixel signal is read from each pixel 10 in the selected row i. When attention is paid to one row i, as shown in FIG. 14A, one frame is composed of a first subframe SF1 and a second subframe SF2, and the last and first subframes SF1 and SF1 are displayed. The last of the two subframes SF2 is a horizontal scanning period R.

  In one horizontal scanning period R, the vertical scanning circuit 60 selects one row i, generates a selection pulse SLi corresponding to the row i, and turns on the row selection transistor 105 of each pixel 10 in the row i. To do. The vertical scanning circuit 60 sequentially generates the reset pulse RTi and the transfer pulse TXi corresponding to the row i within the period in which the row selection pulse SLi corresponding to the row i is generated, and resets each pixel 10 in the row i. The transistor 103 and the transfer transistor 102 are sequentially turned on.

  The column CDS section 20 samples and holds the voltage (reset voltage) read to each column readout line 11 at the timing before the transfer pulse TXi rises after the reset pulse RTi falls (in FIG. 14B). S / H (1)), the voltage read to each column readout line 11 at the timing after the transfer pulse TXi falls is sampled and held (S / H (2) in FIG. 14B), the latter Each voltage obtained by subtracting the former voltage from the above voltage is output as an analog pixel signal in each column. The column ADC unit 30 converts the analog pixel signal of each column into a digital pixel signal, and the horizontal scanning circuit 40 transfers the digital pixel signal of each column to the image processing unit 70. At the end timing of the first subframe SF1 and the end timing of the second subframe SF2, the above horizontal scanning is executed.

  As shown in FIG. 14A, the timing generator 50 according to the present embodiment has the first row i = 1 from the timing when the horizontal scanning period R that is the end of the first subframe SF1 of the last row i = n ends. The control voltage Vsb is set to the power supply voltage VDD during the period until the horizontal scanning period R that is the end of the second subframe SF1 starts, and the control voltage Vsb is set to 0 V during the other periods.

In each pixel 10, the exposure time is the time from the application of the transfer pulse TXi to the application of the next transfer pulse TXi. As shown in FIG. 14A, in this embodiment, the pixel 10 is exposed and the pixel signal is read in both the first subframe SF1 and the second subframe SF2 in one frame. Exposure time in the first sub-frame SF1 is _{t 1.} In the first subfield SF1, from beginning to end control voltage Vsb exposure time _{t 1} is 0V. Exposure time in the second sub-frame SF2, the control voltage Vsb is the time _{t 2} is a predetermined high voltage higher than 0V, the control voltage Vsb is from the time _{t 3} Metropolitan is 0V, the entire exposure time _t 2 + _{t 3} It is. Here, the magnitude of the control voltage Vsb generated within the time t2 is determined so that the peak portion of the potential barrier can be formed in the vicinity of the depth t = 6 μm from the substrate surface. Then, the exposure time _{t 1} at the first subfield SF1 relationship between the exposure time _t 2 + _{t 3} in the second sub-field SF2 _has a _{t 1> t 2 + t 3} .

The image processing unit 70 configures the image data 1 by the digital pixel signal that is the exposure result of the first subfield SF1 obtained from each pixel 10, and the image data by the digital pixel signal that is the exposure result of the second subfield SF2. 2 is configured. Here, the image data 1 is obtained when the control voltage Vsb is 0V. Therefore, the pixel value of each pixel 10 in the image data 1 (the signal value of the above-described digital pixel signal) indicates the amount of received light in both the R, G, and B color bands and the NIR band. On the other hand, the image data 2, which the control voltage Vsb is the control voltage Vsb is exposed in a state that is higher predetermined voltage than 0V (exposure time t ₂₎ was obtained through the exposure in the state of 0V (exposure time t ₃₎ It is. Therefore, the ratio of the R, G, and B components to the NIR band components in each pixel value differs between the image data 1 and the image data 2. The image processing unit 70 according to the present embodiment uses the image data 1 and the image data 2 to obtain image data suitable for the designated application.

  When imaging an object with low illuminance, it is preferable that the received light amount of not only the R, G, and B band components but also the NIR band components is reflected in the pixel value. Therefore, in the imaging of a low-illuminance subject, the image processing unit 70 sets the image data 1 as final image data.

  On the other hand, since color reproducibility is important for viewing applications, the pixel value of each pixel 10 in the image data indicates only the components in each of the R, G, and B bands excluding the NIR band components. Is desired. Therefore, the image processing unit 70 uses the image data 1 and the image data 2 to synthesize image data indicating only the components in the R, G, and B bands excluding the NIR component. This synthesis method may have various modes, but the following can be considered as simple ones.

For example, in the case of the pixel 10 having the B color filter 106, when the received light amount per unit time in the B color band is B and the received light amount per unit time in the NIR band is NIR, the first subfield SF1 The pixel value DP1 that is the exposure result can be expressed as follows, for example.
DP1 = (B + NIR) · k · t ₁ (4)
Here, k is a proportionality constant.

On the other hand, the pixel value DP2, which is the exposure result in the second subfield SF2, can be expressed as follows.
DP2 = (B + NIR) · k · t ₂ + B · k · t ₃ (5)
Solving equation (4) for B + NIR yields:
B + NIR = DP1 / (k · t ₁ ) (6)

By applying this equation (6) to equation (5), the following equation is obtained.
DP2 = DP1 · (t ₂ / t ₁ ) + B · k · t ₃ (7)
Solving the above equation (7) for B yields:
B = {DP2-DP1 · (t ₂ / t ₁ )} / (k · t ₃ ) (8)
Therefore, the image processing unit 70 calculates the received light amount B per unit time in the B color band from the pixel value DP1 of the image data 1 and the pixel value DP2 of the image data 2 according to the above equation (8), and the B color The pixel value indicating only the component is obtained. The same applies to the other colors R and G.

<D: Effect of this embodiment>
As described above, according to the present embodiment, the light receiving sensitivity in the long wave band, specifically, the NIR band can be switched electrically. Therefore, it is possible to obtain image data suitable for a use such as a monitoring use in a vehicle that requires safety and security or a visual use that requires color reproducibility with a simple configuration. In addition, according to the present embodiment, since the leakage of the pixel 10 to the PD 101 can be reduced, the quality of the image particularly in imaging with low illuminance can be improved.

<E: Other embodiments>
Although one embodiment of the present invention has been described above, other embodiments are conceivable for the present invention. For example:

(1) The pixel 10 may be configured as shown in FIGS. 15 (a) and 15 (b). In the pixel shown in FIG. 7 described above, the p3 layer is provided below the bottom surface of the p2 layer in addition to the side of the p2 layer, but in the pixel shown in FIGS. 15A and 15B, the p2 layer is provided. The p3 layer below the bottom of is removed. In the pixels shown in FIGS. 15A and 15B, the p3 layer has a higher impurity concentration than the p2 layer, and has the role of fixing the p2 layer to the ground potential. The pressure of the depletion layer extending from the n2 layer side to the n1 layer side depends on the impurity concentration of the p2 layer. 15 (a) and 15 (b), a broken line H indicates a connection portion between the depletion layer D2 extending from the n2 layer side to the n1 layer side and the depletion layer D1 extending from the n1 layer side to the n2 layer side. FIG. 15A shows the case where 0V is applied as the control voltage Vbs to the n2 layer, and FIG. 15B shows the case where the power supply voltage VDD is applied. Also in this aspect, the depth of the depletion layer D1, which is a collection range of electrons generated by the photoelectric effect, can be controlled by changing the control voltage Vbs as in the above embodiment.

(2) The pixel 10 may be configured as shown in FIGS. In this example, the n2 layer is located at a position away from the back side of the substrate by a predetermined distance, and an area located below the formation area of the pixel 10 is open. The p2 layer which is the background of the PD 101, the transistors 102, 103, etc. is connected to the p2 layer on the back surface of the substrate through this opening. The n2 layer extends to the substrate surface through the side of the pixel 10 formation region. The control voltage Vbs is applied to the n2 layer exposed from the substrate surface. The p3 layer is buried from the substrate surface to a predetermined depth along the n2 layer on the side of the pixel 10 formation region. Similar to the embodiments shown in FIGS. 15A and 15B, this p3 layer also plays a role of fixing the p2 layer to the ground potential.

  In FIGS. 16A and 16B, a broken line H indicates a connection portion between the depletion layer D2 extending from the n2 layer side to the n1 layer side and the depletion layer D1 extending from the n1 layer side to the n2 layer side. 16 (a) shows a case where 0V is applied as the control voltage Vbs to the n2 layer, and FIG. 16 (b) shows a predetermined voltage higher than 0V (a voltage capable of forming a peak portion of the potential barrier in the vicinity of a depth of 6 μm). Each case is shown.

  In this aspect as well, the collection range of electrons generated by the photoelectric effect can be controlled by changing the control voltage Vbs as in the above embodiment. Further, in this aspect, since the control voltage Vbs is applied to the n2 layer exposed from the substrate surface, each transistor constituting a circuit for generating the control voltage Vbs can be formed simultaneously with the transistor 102 and the like.

(3) When imaging a subject with extremely low illuminance, if only the R, G, and B band components of incident light from the subject are converted into pixel signals, the S / N ratio of the pixel signals is poor, and The gradation disappears and the temporal change (noise) of the pixel signal becomes very large, resulting in an image that is difficult to see. Therefore, when an extremely low illuminance subject is imaged in the above embodiment, the image processing unit 70 may execute the following image processing.

  First, RGB image data not including an NIR component and near-infrared intensity data VIR indicating the NIR component are generated for each frame by the method described in the above embodiment. Next, the RGB image data is multiplied by a predetermined conversion matrix, and converted into lightness data VAY, saturation data VAS, and hue data VAH respectively indicating the lightness, saturation, and hue of the color of the pixel as shown in FIG. Note that the RGB data conversion destination data may not be VAY, VAS, and VAH data, but may be data of YUV, YCbCr, YIQ, Lab, XYZ, or the like.

  Then, the brightness data VAY of each pixel is compared with the threshold value VAYth, and when the brightness data VAY of a certain pixel becomes lower than the threshold value VAYth, the brightness data VAY is replaced with the near-infrared intensity data VIR of that pixel. Each of the saturation data VAS and the hue data VAH is averaged spatially and temporally. For example, at a certain time T, for a pixel having the plane coordinates x and y, for example, the x coordinate is from x−Δx to x + Δy, and the y coordinate is from time T−ΔT to time T in the range from y−Δy to y + Δy. The average value of each of the saturation data VAS and the hue data VAH in the interval up to the above may be used as the saturation data VAS and the hue data VAH of the pixel after averaging. The averaged saturation data VAS is amplified. At this time, the saturation data VAS is amplified in accordance with an amplification characteristic (input / output transmission characteristic) for drawing an S curve so that the saturation is not overemphasized and saturated. By causing the image processing unit 70 to perform the above image processing, an image that is easy to see for viewing can be obtained even in an extremely low illuminance environment.

(4) In the above embodiment, the present invention is applied to a solid-state imaging device that performs color imaging. However, the present invention may be applied to a solid-state imaging device that performs monochrome imaging.

(5) In the above embodiment, a CMOS solid-state imaging device is shown as an example of the solid-state imaging device according to the present invention. However, the present invention can also be applied to other solid-state imaging devices such as a CCD solid-state imaging device.

DESCRIPTION OF SYMBOLS 10 ... Pixel, 10A ... Imaging unit, 20 ... Column CDS unit, 30 ... Column ADC unit, 40 ... Horizontal scanning circuit, 50 ... Timing generator, 60 ... Vertical scanning circuit, 70 ... Image processing Part, 80... U / I part, 90... Control part, 11... Column signal line, 101... PD, 102. Selection transistor, 102d ... FD, 51 ... collection range control means, 200 ... p-type Si substrate.

Claims (6)

One surface of the semiconductor substrate of the first conductivity type is an imaging surface, and each includes a first impurity layer of a second conductivity type formed for each pixel in the vicinity of the imaging surface of the semiconductor substrate. An image pickup unit that outputs pixel signals generated in the semiconductor substrate and indicating charges accumulated in the first impurity layer, each of which is a second deeper position from the image pickup surface than the first impurity layer. An imaging unit having a second impurity layer of conductivity type;
By controlling a control voltage applied to the second impurity layer, the second impurity layer and the semiconductor substrate with respect to the first depletion layer generated by the junction between the first impurity layer and the semiconductor substrate. And connecting a second depletion layer generated by the junction with the semiconductor substrate, controlling a position in a depth direction from a surface of the semiconductor substrate of a connection portion of the first depletion layer and the second depletion layer, and controlling the semiconductor A solid-state imaging device comprising: a collection range control means for controlling a collection range of charges generated by photoelectric conversion in the substrate.   While performing the collection range control unit to switch the collection range, the pixel signal is output to the imaging unit and the exposure control for emptying the accumulated charge in the first impurity layer of each pixel of the imaging unit is performed a plurality of times. The solid-state imaging device according to claim 1, wherein a plurality of types of image data having different wavelength characteristics are generated.   The collection range control means includes a first range that includes a deep portion of the semiconductor substrate, and includes a large amount of charges that are generated by photoelectric conversion of light in the near-infrared band among incident light on the surface of the semiconductor substrate; The collection range is not included in the deep part of the semiconductor substrate, and the collection range is set to a second range in which light having a wavelength shorter than the near-infrared band among incident light on the surface of the semiconductor substrate is present in a large amount due to photoelectric conversion. 3. The solid-state imaging device according to claim 2, wherein the first image data including a large amount of near-infrared band components and the second image data including a small number of near-infrared band components are generated.   Lightness, saturation, and hue components are extracted from the second image data, near-infrared band components are extracted from the first image data and the second image data, and the second image data 4. The solid-state imaging device according to claim 3, wherein color image data with high brightness and good color reproducibility is synthesized by replacing the brightness component in the image with a component in the near infrared band. One surface of the first conductivity type semiconductor substrate is used as an imaging surface, and each of the first conductivity type first impurity layers formed in the vicinity of the imaging surface of the semiconductor substrate is included. In a solid-state imaging device having a plurality of pixels that each output a pixel signal indicating a charge generated in the first impurity layer and accumulated in the first impurity layer,
At the boundary surface of the depletion layer generated by the junction between the first impurity layer and the semiconductor substrate in a state where the maximum reverse bias is applied between the first impurity layer and the semiconductor substrate during normal use. A solid-state imaging device, wherein the impurity concentration of the first conductivity type is higher than the impurity concentration of the first conductivity type in another region. One surface of the first conductivity type semiconductor substrate is used as an imaging surface, and each of the first conductivity type first impurity layers formed in the vicinity of the imaging surface of the semiconductor substrate is included. In a solid-state imaging device having an imaging unit having a plurality of pixels each outputting a pixel signal indicating a charge accumulated in the first impurity layer,
A second depletion layer connected to the first depletion layer formed by joining the first impurity layer and the semiconductor substrate and having an electric field opposite to the electric field in the first depletion layer in the semiconductor substrate; A solid-state imaging device configured to generate a depletion layer.

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