JP6578834B2 - Imaging device and imaging apparatus - Google Patents

Description

  The present invention relates to an image sensor, and more particularly to an image sensor using a chalcopyrite compound semiconductor photoelectric conversion film.

  Conventionally, an image sensor using a chalcopyrite compound semiconductor (hereinafter referred to as a CIGS compound semiconductor) as a photoelectric conversion film is known (see Patent Document 1). A CIGS compound semiconductor has a high light absorption coefficient, and performs photoelectric conversion with high energy conversion efficiency. High sensitivity by impact ionization (avalanche multiplication) is realized by sandwiching a CIGS compound semiconductor photoelectric conversion film (hereinafter referred to as a CIGS photoelectric conversion film) between electrodes.

  On the other hand, an imaging device having a complete charge transfer type CIGS photoelectric conversion film adopts a configuration in which a CIGS photoelectric conversion film is directly laminated on a silicon substrate, and the conduction band between the CIGS compound semiconductor and the silicon semiconductor is adopted. Avalanche multiplication is caused by the difference in electron affinity (see Patent Document 2).

JP 2009-259872 A Japanese Patent Laying-Open No. 2011-199057 (see paragraphs [0301] to [0320], FIGS. 31 and 32)

  In Patent Document 1, it is possible to realize avalanche multiplication relatively easily. However, since complete charge transfer cannot be performed, reset noise removal by correlated double sampling (CDS) cannot be performed, and the SN ratio decreases. End up. On the other hand, Patent Document 2 says that avalanche multiplication can be realized in the complete charge transfer type, but it is difficult to actually generate avalanche multiplication.

  Accordingly, it is required to effectively realize avalanche multiplication even in a complete charge transfer type imaging device having a structure in which a chalcopyrite compound semiconductor is stacked on a semiconductor substrate as a photoelectric conversion film.

  The image pickup device of the present invention is a multilayer image pickup device applicable to an image pickup apparatus or the like, and includes a second conductivity type of a first type semiconductor formed in a first conductivity type semiconductor substrate of a first type semiconductor. A first semiconductor region; a second semiconductor region made of a first conductivity type of a first type semiconductor formed on a surface portion of the semiconductor substrate so as to be joined to the first semiconductor region; and a second semiconductor region; And a photoelectric conversion film using a second type semiconductor formed so as to be bonded.

  For example, the first type semiconductor can be configured as a silicon semiconductor, and the second type semiconductor can be configured as a chalcopyrite compound semiconductor, and the first conductivity type can be p-type and the second conductivity type can be n-type. If the first conductivity type is a p-type semiconductor, it becomes an n-type first semiconductor region and a p-type second semiconductor region. When the conductivity type is reversed, the semiconductor region also has the opposite conductivity type.

  In the present invention, the energy band of the photoelectric conversion film is inclined so that photogenerated photocharges move from the photoelectric conversion film to the semiconductor substrate. For example, in the case of a p-type semiconductor substrate, n-type, i-type, and p-type conductive regions may be sequentially formed from the semiconductor substrate toward the surface of the photoelectric conversion film. In the case of an n-type semiconductor substrate, p-type, i-type, and n-type may be used.

Furthermore, according to the present invention, an impurity concentration profile of the semiconductor substrate is formed such that when photocharge is injected into the junction between the first semiconductor region and the second semiconductor region, charge multiplication occurs at the junction. ing. For example, the first semiconductor region has an impurity concentration of about 10 ¹⁷ / cm ³ and a thickness of about 500 nm, and the second semiconductor region has an impurity concentration of about 10 ¹⁸ / cm ³ and a thickness of 30 to 50 nm. What is necessary is just to set the voltage which resets a semiconductor region to at least 5V or more.

  A CIGS compound semiconductor is formed between the photoelectric conversion film and the first semiconductor region by providing, on the substrate surface side, a second semiconductor region in which a junction portion forms a charge multiplication region by a pn junction. The avalanche multiplication can be realized in the image pickup device to be stacked as.

  In order to suppress generation of dark current at the junction between the photoelectric conversion film and the second semiconductor region, a first conductivity type conductive region formed so as to cover the photoelectric conversion film may be further formed.

  In order to maintain the strength of the electric field of the first semiconductor region during the charge accumulation period, the image sensor driving unit provided in the imaging device converts the charge accumulated in the first semiconductor region during the photoelectric conversion period into the first semiconductor. What is necessary is just to intermittently transfer to the third semiconductor region of the second conductivity type formed adjacent to the region.

  ADVANTAGE OF THE INVENTION According to this invention, an image pick-up element provided with high sensitivity performance is implement | achieved, and it can equip with an imaging device etc.

It is a block diagram of the digital camera which is 1st Embodiment. It is a schematic block diagram of the image pick-up element used for the image sensor and photometry sensor of this embodiment. It is a schematic block diagram of the image pick-up element used for the distance measuring sensor of this embodiment. It is a schematic sectional drawing of the arbitrary pixel parts in the image sensor of this embodiment. FIG. 5 is an equivalent circuit diagram of the pixel shown in FIG. 4. It is the figure which showed roughly the energy band in the steady state along the X1-X2 direction of FIG. It is the figure which showed roughly the energy band and internal electric field along the X1-X2 direction in the process in which the photoelectric charge produced | generated when light entered was accumulate | stored. It is the figure which showed roughly the energy band in the heterojunction which laminated | stacked the CIGS photoelectric converting film directly on the silicon substrate. It is the figure which showed the drive timing chart with respect to the image pick-up element of this embodiment. It is the figure which showed the drive timing chart different from FIG. It is a schematic sectional drawing of the image sensor in 2nd Embodiment. It is a schematic sectional drawing of the image sensor in 3rd Embodiment. It is a schematic sectional drawing of the image sensor in 4th Embodiment. It is a schematic sectional drawing of the image sensor in 5th Embodiment. It is a schematic sectional drawing of the image sensor in 6th Embodiment.

  Below, the digital camera which is this embodiment is demonstrated with reference to drawings. FIG. 1 is a block diagram of a digital camera according to the first embodiment.

  Here, the digital camera 10 is configured as a single-lens reflex digital camera, and includes a camera body 30 and an interchangeable lens 20 that is detachably attached to the camera body 30. The system control circuit 40 including the camera CPU outputs a control signal to the lens control circuit 56, the image processing circuit 34, etc. in accordance with an input operation to a release button, a mode selection dial (not shown), etc., and controls exposure and recording. Performs overall camera operation control, such as operations and playback display operations. A camera operation control program is stored in a recording medium such as the ROM 55.

  In the photographing mode, the light passing through the photographing optical system 22 is guided to a finder (not shown) by the movable mirror 33. The user can visually recognize the subject through the viewfinder. When half-press of the release button is detected by the operation switch group 52, focus adjustment according to the phase difference method is executed. Subject light is incident on the distance measuring sensor 37 by the half mirror 31 attached to the movable mirror 33, and the defocus amount is calculated based on the luminance signal from the distance measuring sensor 37.

  The lens CPU 28 controls the lens driving mechanism 26 based on a command from the camera body 30 lens control circuit 56, and the lens driving mechanism 26 moves the focusing lens of the photographing optical system 22 along the optical axis direction in accordance with a control signal from the lens CPU 28. To move. As the release button is pressed halfway, the photometric sensor 38 provided in the viewfinder detects the brightness of the subject, and the system control circuit 40 calculates an exposure value (shutter speed, aperture value, sensitivity, etc.).

  When the release button is fully pressed, the lens control circuit 56 retracts the movable mirror 33 (including the half mirror 31) from the optical path and drives the shutter 35, the diaphragm 24 and the like to control exposure. As a result, light from the subject passing through the photographing optical system 22 forms an image on the image sensor 32, and a subject image is formed on the image sensor 32. Here, the imaging sensor 32 is configured by a two-dimensional single-plate CMOS image sensor having an (M × N) pixel arrangement. A primary color mosaic filter array is provided on-chip.

  When the image sensor driving circuit 36 drives the image sensor 32, a pixel signal for one frame is read from the image sensor 32. The read pixel signal is sent to the image processing circuit 34 via an AFE circuit (not shown). The image processing circuit 34 performs color interpolation processing, gamma correction processing, white balance adjustment, and the like on the read pixel signal for one frame to generate still image data. Still image data is recorded in a removable image memory (memory card or the like) 54 in a compressed or uncompressed state. When the reproduction mode is set, the recorded image is reproduced and displayed on the display 50.

  FIG. 2 is a schematic configuration diagram of the image sensor 32.

  In the imaging sensor 32, an effective pixel area PA composed of a plurality of pixels P arranged in a matrix on a silicon substrate 70 is formed, and a vertical drive circuit 32A, a control circuit 32B, a column signal processing circuit 32C, and a horizontal drive circuit are arranged around the effective pixel area PA. 32D and an output circuit 32E are provided. Each pixel P is provided with a plurality of pixel transistors (not shown here) such as a transfer transistor, a reset transistor, a selection transistor, and an amplification transistor along with the photoelectric conversion unit.

  The control circuit 32B outputs a clock signal or a control signal to the vertical drive circuit 32A, the column signal processing circuit 32C, and the horizontal drive circuit 32D. The vertical drive circuit 32A sequentially selects and reads each pixel P in the vertical direction in units of rows through the horizontal control line HL, and outputs a pixel signal based on the signal charge of each pixel P to the column signal processing circuit 32C through the vertical signal line VL. Supply. The column signal processing circuit 32C arranged for each pixel column performs noise removal, signal amplification processing, and the like by a pixel signal sent from a pixel in an optical black region (not shown). The horizontal drive circuit 32 </ b> D sends the pixel signal to the output circuit 32 </ b> E, and the output pixel signal is read from the image sensor 32. The photometric sensor 38 has the same configuration.

  FIG. 3 is a schematic configuration diagram of the distance measuring sensor. On the silicon substrate 70, the standard pixel array SP and the reference pixel array TP are arranged to face each other. The distance measuring sensor 37 is in the form of a line sensor. The optical image obtained by dividing the pupil from the photographing optical system 22 is imaged and received on a reference pixel column SP and a reference pixel column TP arranged on the same line. The focus detection is performed by calculating the defocus amount (defocus amount) of the lens from the phase shift of these pixel signals. The configuration and operation of the transistor circuit such as the vertical drive circuit 32A are substantially the same as those of the image sensor 32 and the photometric sensor 38.

  FIG. 4 is a schematic cross-sectional view of an arbitrary pixel portion in the distance measuring sensor 37. FIG. 5 is an equivalent circuit diagram of the pixel shown in FIG. Here, one pixel portion is shown.

  The distance measuring sensor 37 is configured as a stacked imaging device in which a photoelectric conversion film (photoconductive film) is stacked on a silicon substrate 70, and here, pixels P are formed based on the p-type silicon substrate 70. The silicon substrate 70 has an impurity concentration profile along the same optical path of light passing through the pixel region centered on the photoelectric conversion film, that is, the photoelectric conversion film.

  Specifically, an n-type well (hereinafter referred to as a first accumulation layer) 74 doped with impurities is formed on the silicon substrate 70 in accordance with the pixel region. A p-type well (hereinafter referred to as a substrate surface layer) 76 is formed on the surface of the n-type well 74. A CIGS photoelectric conversion film 60 is laminated on the substrate surface layer 76.

  The first accumulation layer 74 and the substrate surface layer 76 can be formed by implantation (doping) of impurity ions. For example, ions such as P (phosphorus) are first implanted into the p-type silicon substrate 70, and then B (boron) or the like is implanted thereon. An impurity concentration profile represented by such a stacked structure can be formed by a method other than ion implantation.

The CIGS photoelectric conversion film 60 can be formed by a conventionally known film forming method. Here, a CIGS compound semiconductor composed of a composition (CuGa _0.52 In _0.48 S ₂ ) having sensitivity over the entire visible light region is epitaxially grown in a lattice-matched state. At this time, the film is formed so that the semiconductor type (conductivity) continuously changes in the order of n-type, i-type, and p-type from the silicon substrate 70 side toward the photoelectric conversion film side. The n-type conductivity can be obtained by doping a group 12 element (for example, zinc (Zn)). The p-type conductivity is obtained by setting the ratio of Cu to a group 13 element (Ga, In) to 1 or less. i-type conductivity is obtained without any doping.

  A CIGS p + type well (hereinafter referred to as a p + CIGS layer) 62 is formed on the surface of the CIGS photoelectric conversion film 60 by impurity doping or the like. The p + CIGS layer 62 is connected to the GND potential together with a well contact 75 which is a connection portion for supplying power to the silicon substrate 70.

A pixel P having such an impurity concentration profile is formed in each pixel region. The impurity concentration and thickness in each layer of the pixel P can be determined as follows, for example. In this case, the reset power supply voltage V _DDR corresponds to a voltage at which the first storage layer 74 is depleted, and can be set to about 5 to 10V.

p + CIGS layer 62: impurity concentration of about 10 ¹⁹ to 10 ²⁰ / cm ³ , thickness of about 10 to 30 nm photoelectric conversion film 60: thickness of about 300 to 500 nm substrate surface layer 76: impurity concentration of about 10 ¹⁸ / cm ³ , thickness of 30 About 50 nm First storage layer 74: Impurity concentration of about 10 ¹⁷ / cm ³ , Thickness of about 500 nm Silicon substrate 70: Impurity concentration of about 10 ¹⁷ / cm ³

  A second storage layer 77 is formed on the silicon substrate 70 adjacent to the first storage layer 74. A light shielding film 78 is formed above the second accumulation layer 77 to prevent incident light from entering the second accumulation layer 77 while the electric charge is being held and generating unnecessary charges. In addition, an anti-blooming gate (ABG) 79 is formed adjacent to the first accumulation layer 74, and the photocharge generated in the CIGS photoelectric conversion film 60 is excessive through the ABG 79 so as not to overflow from the first accumulation layer 74. Eliminate unwanted photocharges.

  When photoelectric charges are generated in the CIGS photoelectric conversion film 60 by the light incident on the pixels P, the generated photoelectric charges are transferred to the substrate surface layer 76. A junction portion between the substrate surface layer 76 and the first accumulation layer 74 is a pn junction, and a region (hereinafter referred to as a charge multiplication region) 76A that is charge-multiplied is formed in the junction portion of the substrate surface layer 76. The photocharge that has undergone avalanche multiplication in the charge multiplication region 76 </ b> A is accumulated in the first accumulation layer 74. The accumulated photocharge is transferred to the second accumulation layer 77 through the storage gate (SG) 71.

  Here, it is known that charge multiplication (avalanche multiplication) in a silicon semiconductor is mostly performed by electrons, and it is preferable to use electrons as signal charges (photocharges). That is, it is preferable to configure the first storage layer 74 to have an n-type conductivity. In addition, it is known that noise (excess noise) due to fluctuations in the multiplication factor in the avalanche multiplication process is suppressed to a relatively small level when it is multiplied by either electron or hole carriers. Charge multiplication in the region (avalanche multiplication) is also preferable for suppressing excessive noise.

Further, the photoelectric charge is transferred to the floating diffusion (FD) 80 through the floating diffusion gate (FG) 73 and read out from the distance measuring sensor 37 through the pixel amplifier (AMP) and the selection switch (SEL) 82. After the signal is read out, the charge transferred to the FD 80 is discharged to the reset power supply voltage V _DDR through the reset gate (RG) 83. FIG. 5 shows an equivalent circuit diagram of the pixel shown in FIG. The reset power supply voltage V _DDR and the pixel amplifier power supply voltage V _DDA may be the same value, or only the reset power supply voltage V _DDR may be set to a relatively high voltage.

  4 and 5 show the pixel configuration of the distance measuring sensor 37, the imaging sensor 32 and the photometric sensor 38 have the same configuration. In addition, since the band cap can be arbitrarily set under the condition of the lattice constant a (5.431５) of silicon by adjusting the composition of the chalcopyrite-based material, the photoelectric conversion film corresponding to the red light described above At the same time, a photoelectric conversion film corresponding to green light and a photoelectric conversion film corresponding to blue light are formed and arranged in accordance with a Bayer arrangement method or the like, whereby an image sensor having a structure that does not use a color filter array can be obtained.

  Below, the avalanche multiplication with respect to the photocharge produced | generated in the CIGS type | system | group photoelectric converting film is demonstrated using FIGS.

  FIG. 6 is a diagram schematically showing an energy band in a steady state along the X1-X2 direction of FIG. The silicon substrate 70 and the p + CIGS layer 62 are connected to the GND level.

  As shown in FIG. 6, since the CIGS photoelectric conversion film 60 forms a profile in which the impurity concentration is gradually changed, the energy band is inclined. A potential barrier (band shift) DD due to a difference in electron affinity occurs at the interface (pn junction) between the substrate surface layer (p well) 76 of the silicon substrate 70 and the CIGS photoelectric conversion film 60.

The electron affinity indicates energy from the conduction band CB to the vacuum level, and when there is a difference in electron affinity between the two substances, a band shift DD occurs after bonding. (CuGa _0.52 In _0.48 S ₂ ) is a mixed crystal of CuInS ₂ (electron affinity 4.7 eV) and CuGaS ₂ (electron affinity 4.1 eV), and the composition ratio of In and Ga is about 1: 1. Its electron affinity is about 4.4 eV. Since the electron affinity of silicon is 4.05 eV, when the CIGS photoelectric conversion film 60 and the substrate surface region 76 are bonded, a band shift DD of 0.35 eV is generated in the conduction band CB.

  FIG. 7 shows an energy band along the X1-X2 direction in the process of accumulating photocharges generated by incidence of light in a state where the reset state (ABG = ON) is switched to the accumulation state (ABG = OFF). It is the figure which showed the internal electric field roughly.

  When light is incident, a photoelectron hole pair is generated in the CIGS photoelectric conversion film 60. The holes are discharged to GND through the p + CIGS layer 62 according to the energy band inclination. On the other hand, electrons move to the silicon interface side according to the energy band inclination. The barrier due to the difference in electron affinity between the CIGS compound semiconductor and silicon Si is about 0.35 eV as described above, but by reducing the thickness of the p-type substrate surface layer 76 as described above (50 nm or less), Due to the tunnel effect, electrons can be injected (moved) from the CIGS photoelectric conversion film 60 to the substrate surface layer 76.

As described with reference to FIG. 4, the substrate surface layer 76 has an impurity concentration of about 10 ¹⁸ / cm ³ and a thickness of about ³⁰ to 50 nm, and the first storage layer 74 has an impurity concentration of about 10 ¹⁷ / cm ^3. The impurity concentration profile is formed so as to have a thickness of about 500 nm. As a result, when the reset power supply voltage V _DDR is about 5 to 6 V, the first storage layer 74 can be completely depleted, and the electric field in the charge multiplication region 76A of the pn junction portion causes a charge multiplication of 5 × 10 5. It can be about ⁵ V / cm. Therefore, avalanche multiplication can be caused to electrons moved from the substrate surface layer 76 to the charge multiplication region 76A.

FIG. 8 is a diagram schematically showing an energy band when the CIGS photoelectric conversion film 60 is directly laminated on the silicon substrate 70 by a heterojunction. However, the impurity concentration of the CIGS-based compound semiconductor was constant, the Fermi level E _F of CIGS-based compound semiconductor and silicon Si are the same. As described in FIG. 6, CuGa _0.52 In _0.48 S _{2 has} an electron affinity of 4.4 eV, while silicon has an electron affinity of 4.05 eV. Therefore, when they are joined, as shown on the right side of FIG. A band offset of 0.35 eV occurs in the conduction band.

  Here, when an avalanche multiplication is caused by an energy difference, it is usually said that an energy difference of about three times the energy band gap is required. Therefore, since the difference between the valence band VB and the conduction band CB in silicon Si is 1.12 eV, an energy difference of 3.36 eV is required. However, since the energy difference between the conduction band CB of the CIGS compound semiconductor and the silicon semiconductor is 0.35 eV and the energy on the silicon side is high, the structure in which the CIGS photoelectric conversion film 60 and silicon are simply laminated is not used. It is difficult to cause avalanche multiplication.

Therefore, in the present embodiment, a p-type substrate surface layer 76 is formed between the CIGS photoelectric conversion film 60 that generates photocharges and the n-type first storage layer 74 that stores the generated photocharges. Yes. With the impurity concentration profile, a charge multiplying region 76A to which a high electric field is applied is formed at the pn junction between the first accumulation layer 74 and the substrate surface layer 76. Then, by setting an appropriate reset power supply voltage V _DDR , it is possible to avalanche multiply the photocharge in the charge multiplying region 76A.

  High-sensitivity focus detection can be performed by the distance measuring sensor 37 in which pixels having the semiconductor structure as described above are arranged. In AF adjustment, the distance to the subject must be detected in a relatively short time, and higher sensitivity performance is required than the image sensor 32. In the distance measuring sensor 37, it is not preferable to perform pixel addition for improving sensitivity because resolution is lowered and focus detection accuracy is lowered. In addition, as shown in FIG. 3, a method of increasing the sensitivity by extending in the line orthogonal direction is common, but if this is extended too much, the distance measurement line becomes thick and the distance measurement position becomes unclear. By using the distance measuring sensor 37 having high sensitivity performance of the present embodiment, the focus detection accuracy can be increased.

  In the imaging sensor 32 and the photometric sensor 38, pixels having the semiconductor structure can be arranged. In particular, in the photometric process, unlike an image sensor, long exposure is not allowed, and it is necessary to calculate an exposure value such as a shutter speed in a short time. By using the high-sensitivity photometric sensor 38 of the present embodiment, it is possible to detect appropriate subject brightness in a short time.

  FIG. 9 is a diagram showing a drive timing chart for an image sensor or the like.

  φSHR and φSHS respectively represent a reset signal sampling pulse and an optical signal sampling pulse of a CDS circuit (not shown) provided in the column signal processing circuit for each pixel column. Up to the φSG pulse signal to the storage gate 71 after elapse of t1 to t2 represents the photoelectric conversion time (integration time). t3 to t4 indicate a waiting time until pixel reading of the target row. t4 to t6 indicate the CDS operation period.

  FIG. 10 is a diagram showing a driving timing chart different from FIG. Here, the φSG pulse signal for the storage gate 71 is regularly output at predetermined intervals during the period from t1 to t3. Normally, as charges are accumulated in the first accumulation layer 74, the potential of the first accumulation layer 74 decreases, and the electric field in the charge multiplication region 76A becomes weak. However, the electric field in the charge multiplication region 76A is prevented from weakening by intermittently transferring the charge in the first accumulation layer 74 to the second accumulation layer 77 by outputting the φSG pulse signal in the photoelectric conversion period. Can do.

  Next, a second embodiment will be described with reference to FIG. In the second embodiment, a transparent electrode is provided on the p + CIGS layer. Other configurations are substantially the same as those in the first embodiment.

  FIG. 11 is a schematic cross-sectional view of a distance measuring sensor 37 ′ according to the second embodiment. Here, a transparent electrode (for example, ITO, AZO, etc.) is provided on the upper surface of the p + CIGS layer 62. By providing such a transparent electrode having excellent conductivity, the potential distribution of the entire pixel region can be kept relatively uniform, and the sensitivity becomes uniform.

  Next, a third embodiment will be described with reference to FIG. In the third embodiment, a reverse bias voltage is applied. About another structure, it is the same as 1st Embodiment.

Figure 12 is a schematic sectional view of a distance measuring sensor 37 "in the third embodiment. In this case, the power supply unit 72 for applying a reverse bias voltage V _R between the p + CIGS layer 62 and the GND is provided. This As a result, the electric field in the CIGS photoelectric conversion film 60 is strengthened and the charge traveling speed increases, and as a result, the charge transfer time to the first accumulation layer 74 can be shortened and the operation speed is improved.

  Next, a fourth embodiment will be described with reference to FIG. In the fourth embodiment, a part of the photoelectric conversion film is extended to form a light shielding film. About another structure, it is the same as 1st Embodiment.

  FIG. 13 is a schematic cross-sectional view of a distance measuring sensor 137 according to the fourth embodiment. Here, the p + CIGS layer 162 extends over the entire pixel region and its periphery. A CIGS film extending in the same manner is formed on the lower surface of the CIGS film. By forming a film having a high light absorption rate in this way, it is not necessary to provide a dedicated light-shielding curtain on the second storage layer 77. In addition, since the photoelectric conversion region is widened, external quantum efficiency can be improved, that is, sensitivity can be improved.

  Next, a fifth embodiment will be described with reference to FIG. In the fifth embodiment, a back-illuminated imaging sensor is configured. About another structure, it is the same as 1st Embodiment.

  FIG. 14 is a schematic cross-sectional view of a distance measuring sensor 237 according to the fifth embodiment. A pixel peripheral circuit such as the second storage layer 77 and the floating gate portion 73 is disposed on the opposite side of the CIGS photoelectric conversion film 60 with the insulating layer 275 interposed therebetween. As a result, the photoelectric conversion region of the pixel can be expanded, and external quantum efficiency can be improved, that is, sensitivity can be improved. Further, since the CIGS photoelectric conversion film 60 is above the second storage layer 77 (on the light incident side), it functions as a light shielding film.

  next. The sixth embodiment will be described with reference to FIG. In the sixth embodiment, a CIGS photoelectric conversion film is embedded in a silicon substrate. About another structure, it is the same as 1st Embodiment.

  FIG. 15 is a schematic sectional view of a distance measuring sensor 337 in the sixth embodiment. However, only the vicinity of the photoelectric conversion film is illustrated. Here, the p + CIGS layer 62 ′ is provided so as to cover the upper surface and the side surface of the CIGS photoelectric conversion film 60. If a pn junction appears on the surface near the interface between the CIGS photoelectric conversion film 60 and the silicon substrate 70, dark current may increase through the surface level. By embedding, dark current can be reduced.

  In addition, about 1st-6th embodiment, it is also possible to comprise embodiment by arbitrary combinations each selectively. Further, the silicon substrate can be n-type. In this case, the first accumulation layer may be p-type, the substrate surface layer may be n-type, and the CIGS photoelectric conversion film may be inclined from the substrate side in the order of p-type, i-type, and n-type in order to incline the energy band. . Moreover, as long as it is a chalcopyrite compound semiconductor, the photoelectric conversion film may be formed with a composition other than the above. In either case, an impurity concentration profile that causes charge multiplication may be formed. Furthermore, as a material for forming the photoelectric conversion film, for example, GaAs / InP, CuInGaS / CuInGaSe / AgInGaSe2, FeS2 / Cu2S / SnS2 / BaSi2, GaP, InGaP, or the like can be used.

  In the present embodiment, the single-lens reflex camera is provided with the image sensor, the photometric sensor, and the distance measuring sensor having the above pixel structure, but at least one of them may be used. Also, the present invention can be applied to cameras other than single-lens reflex cameras or other imaging devices.

10 Digital camera (imaging device)
32 Imaging sensor (imaging device)
37 Ranging sensor (image sensor)
38 photometric sensor 60 CIGS photoelectric conversion film (photoelectric conversion film, second type semiconductor)
62 p + CIGS layer 70 Silicon substrate (first type semiconductor, semiconductor substrate)
74 First accumulation layer (first semiconductor region)
76 Substrate surface layer (second semiconductor region)
76A Charge multiplication region

Claims (7)

A first semiconductor region made of a second conductivity type of a first type semiconductor formed in a first conductivity type semiconductor substrate being a first type semiconductor;
A second semiconductor region of the first conductivity type of the first type semiconductor formed on the surface portion of the semiconductor substrate so as to be joined to the first semiconductor region;
A photoelectric conversion film using a second type semiconductor formed so as to be bonded to the second semiconductor region;
The photoelectric conversion film is formed with an energy band inclined so that the generated photocharge moves to the semiconductor substrate side,
The impurity concentration profile of the semiconductor substrate is formed so that when the photocharge is injected into the junction between the first semiconductor region and the second semiconductor region, charge multiplication occurs at the junction. An image sensor characterized by the above. The impurity concentration of the first semiconductor region is about 10 ¹⁷ / cm ³ and the thickness is about 500 nm;
The impurity concentration of the second semiconductor region is about 10 ¹⁸ / cm ³ and the thickness is 30 to 50 nm;
The imaging device according to claim 1, wherein a voltage for resetting the first semiconductor region is at least 5 V or more.   The image pickup device according to claim 1, further comprising a first conductivity type semiconductor region formed so as to cover the photoelectric conversion film. The photoelectric conversion film has a conductive region formed in the order of the second conductivity type, the intrinsic semiconductor type, and the first conductivity type from the semiconductor substrate toward the surface side of the photoelectric conversion film. Item 4. The imaging device according to any one of Items 1 to 3. The first type semiconductor is a silicon semiconductor, the second type semiconductor is a chalcopyrite compound semiconductor,
5. The image sensor according to claim 1, wherein the first conductivity type is p-type and the second conductivity type is n-type. An imaging apparatus comprising the imaging device according to claim 1,
An imaging apparatus comprising the imaging device as at least a distance measuring sensor among an imaging sensor, a photometric sensor, and a distance measuring sensor. An image sensor driving unit for driving the image sensor;
The image sensor driving unit intermittently charges accumulated in the first semiconductor region to a third semiconductor region of a second conductivity type formed adjacent to the first semiconductor region during a photoelectric conversion period. The image pickup apparatus according to claim 6, wherein the image pickup apparatus transfers the data in an automatic manner.

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