JP2010175771A - Plasma display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform high quality image display by generating stable sustaining discharge even in a high-definition plasma display panel. <P>SOLUTION: In this plasma display device, writing discharge is generated selectively by discharge cells in a writing period of a subfield having the writing period and a sustaining period, sustain pulses by the number corresponding to the luminance weight are applied to a display electrode in the sustaining period, and sustaining discharge is generated by the discharge cells made to generate the writing discharge. The rising and falling of the sustain pulses are performed by LC resonance between the inter-electrode capacitance and inductor of the plasma display panel. In the sustaining period of at least one subfield, a first sustain pulse having at least a predetermined rising time and a second sustain pulse having a rising time shorter than the predetermined rising time are applied. The plasma display panel is driven so that the second sustain pulse is included in the period from the start of the sustaining period to the midway of the sustaining period. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a plasma display device used for a wall-mounted television or a large monitor.

  A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front plate and a back plate arranged to face each other. In the front plate, a plurality of pairs of display electrodes made up of a pair of scan electrodes and sustain electrodes are formed on the front glass substrate in parallel with each other, and a dielectric layer and a protective layer are formed so as to cover the display electrodes. The back plate has a plurality of parallel data electrodes on the back glass substrate, an insulating layer so as to cover them, and a plurality of partition walls formed in parallel with the data electrodes on each of the data electrodes. A phosphor layer is formed on the side walls of the barrier ribs. Then, the front plate and the back plate are arranged opposite to each other so that the display electrode and the data electrode are three-dimensionally crossed and sealed, and a discharge gas containing, for example, 5% xenon in a partial pressure ratio is sealed in the internal discharge space. ing. Here, a discharge cell is formed at a portion where the display electrode and the data electrode face each other. In the panel having such a configuration, ultraviolet rays are generated by gas discharge in each discharge cell, and the phosphors of red (R), green (G) and blue (B) colors are excited and emitted by the ultraviolet rays, thereby performing color display. It is carried out.

  As a method of driving the panel, a subfield method, that is, a method of performing gradation display by combining subfields to emit light after dividing one field period into a plurality of subfields is generally used.

  Each subfield has an initialization period, an address period, and a sustain period. In the initializing period, initializing discharge is generated, wall charges necessary for the subsequent address operation are formed on each electrode, and priming particles for generating address discharge stably are generated. In the address period, an address pulse voltage is selectively applied to the discharge cells to be displayed to generate an address discharge to form wall charges (hereinafter, this operation is also referred to as “address”). In the sustain period, a sustain pulse voltage is alternately applied to the display electrode composed of the scan electrode and the sustain electrode, a sustain discharge is generated in the discharge cell in which the address discharge has occurred, and the phosphor layer of the corresponding discharge cell is caused to emit light. The image is displayed.

  In addition, among the subfield methods, initializing discharge is performed using a slowly changing voltage waveform, and further, initializing discharge is selectively performed on discharge cells that have undergone sustain discharge. A driving method is disclosed in which the light emission that is not generated is reduced as much as possible to improve the contrast ratio.

Specifically, among the plurality of subfields, in the initialization period of one subfield, an all-cell initializing operation for generating an initializing discharge in all discharge cells is performed, and in an initializing period of the other subfield. Performs a selective initializing operation in which initializing discharge is generated only in the discharge cells that have undergone sustain discharge in the immediately preceding sustain period. By driving in this way, the luminance of the black display area that changes depending on the light emission not related to the image display (hereinafter abbreviated as “black luminance”) is only weak light emission in the all-cell initialization operation, High-contrast image display is possible (see, for example, Patent Document 1).
JP 2000-242224 A

  In recent years, in order to meet the demand for high definition in plasma display devices, the sustain discharge becomes unstable as the discharge cells become finer, and the sustain discharge does not occur in the discharge cells that have caused the address discharge. The quality may be reduced. The present invention has been made in view of these problems, and provides a plasma display device capable of generating a stable sustain discharge and performing high-quality image display even in a high-definition panel. With the goal.

  The plasma display device of the present invention includes a plasma display panel including a plurality of discharge cells each having a display electrode including a scan electrode and a sustain electrode, and a driving circuit for the plasma display panel, and has a sub-period having an address period and a sustain period. In the address period of the field, in the discharge cell in which the address discharge is selectively generated in the discharge cell, and in the sustain period, the number of sustain pulses corresponding to the luminance weight is applied to the display electrode to generate the address discharge. In the plasma display device for generating the sustain discharge, the sustain pulse rises and falls by LC resonance between the interelectrode capacitance of the plasma display panel and the inductor, and at least a predetermined rise time in the sustain period of at least one subfield. A first maintenance pad having And a second sustain pulse having a rise time shorter than the predetermined rise time, and the second sustain pulse is included in a period from the start of the sustain period to the middle of the sustain period And driving a plasma display panel.

  According to the present invention, unstable discharge variation at the start of the sustain period can be suppressed and the sustain discharge can be stabilized, so that high-quality image display can be performed.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

  Hereinafter, although the plasma display panel by one Embodiment of this invention is demonstrated using FIGS. 1-11, the aspect of this invention is not limited to this.

  First, the overall configuration of a plasma display panel according to an embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 is an exploded perspective view showing a state in which a front plate and a back plate are separated from each other in a plasma display panel according to an embodiment of the present invention. FIG. It is sectional drawing which shows a discharge cell structure. As shown in FIGS. 1 and 2, the panel is configured by disposing a glass front plate 1 and a back plate 2 so as to form a discharge space 3 therebetween.

  The front plate 1 has a display electrode 7 in which a scanning electrode 5 as a conductive first electrode and a sustaining electrode 6 as a second electrode are arranged parallel to each other with a discharge gap therebetween on a glass substrate 4. , A plurality of display electrodes 7 are arranged in the row direction, and a dielectric layer 8 made of a glass material is formed so as to cover the scan electrodes 5 and the sustain electrodes 6, and the dielectric layer 8 A protective film 9 made of MgO is formed on the top.

  The scanning electrode 5 and the sustaining electrode 6 are each composed of only a conductive electrode having a film thickness of about 5 μm made of Ag without using a transparent electrode such as ITO, and the scanning electrode 5 and the sustaining electrode 6 are shown in FIG. As shown in FIG. 4, the substrate 4 side lower layer 5a, 6a is made of a material containing a metal oxide having a low blackness and an upper layer 5b. 6b is composed of a white material having an increased Ag content so that the specific resistance is lower than that of the lower layers 5a and 6a, so that the lower layer 5a and 6a on the substrate 4 side has lower brightness than the upper layers 5b and 6b. It is configured. That is, the display electrode 7 composed of the scan electrode 5 and the sustain electrode 6 is configured such that the brightness of the display electrode 7 composed of the scan electrode 5 and the sustain electrode 6 is low when viewed from the display surface on the substrate 4 side. The light shielding member does not exist between the display electrodes 7 of the adjacent discharge cells. Here, the configuration that the brightness is low is, for example, the lowest brightness “between ideal white having a brightness of 10 and ideal black having a brightness of 0, as known as the Munsell brightness. It means that it is configured so as to be close to 1.0 ".

  Further, the back plate 2 is provided with a plurality of data electrodes 12 made of Ag covered with an insulating layer 11 made of a glass material and arranged in a stripe shape in the column direction on a glass substrate 10 and insulated. On the body layer 11, a grid-like partition wall 13 made of a glass material for partitioning the discharge space 3 between the front plate 1 and the back plate 2 for each discharge cell is provided. Further, red (R), green (G), and blue (B) phosphor layers 14R, 14G, and 14B are provided on the surface of the insulator layer 11 and the side surfaces of the partition walls 13. The front plate 1 and the back plate 2 are arranged to face each other so that the scan electrode 5 and the sustain electrode 6 intersect the data electrode 12, and the scan electrode 5, the sustain electrode 6 and the data electrode 12 intersect each other. As shown in FIG. 3, a discharge cell 15 is provided. The discharge space 3 is filled with, for example, a mixed gas of neon and xenon as a discharge gas.

  Here, as shown in FIG. 2, the cross-shaped barrier ribs 13 forming the discharge cells 15 include the vertical barrier ribs 13a formed in parallel to the data electrodes 12, and the discharges adjacent to each other in the direction intersecting the vertical barrier ribs 13a. The horizontal barrier ribs 13b are formed so as to be present between the display electrodes 7 of the cell and are formed so as to be lower than the vertical barrier ribs 13a so that a gap is formed between the display electrodes 7. Yes. The phosphor layers 14R, 14G, and 14B formed by coating in the barrier ribs 13 are formed of stripes of blue phosphor layers 14B, red phosphor layers 14R, and green phosphor layers 14G along the vertical barrier ribs 13a. They are arranged in order.

  FIG. 3 is an electrode array diagram of the panel shown in FIGS. N scanning electrodes Y1, Y2, Y3... Yn (5 in FIG. 1) and n sustaining electrodes X1, X2, X3... Xn (6 in FIG. 1) are arranged in a row direction. M data electrodes A1... Am (12 in FIG. 1) that are long in the direction are arranged. Discharge cells 15 are formed at portions where the pair of scan electrodes Y1 and sustain electrodes X1 and one data electrode A1 intersect, and m × n discharge cells 15 are formed in the discharge space. Further, as shown in FIG. 3, the scan electrode Y1 and the sustain electrode X1 are formed on the front plate 1 in a pattern that repeats in the arrangement of the scan electrode Y1, the sustain electrode X1, the sustain electrode X2, the scan electrode Y2,. Has been. Each of these electrodes is connected to a connection terminal provided at a peripheral end portion outside the image display area of the front plate 1 and the back plate 2.

  Next, the configuration of the display electrode 7 of the plasma display panel of the present invention will be described in more detail.

  As described above, in the plasma display panel of the present invention, the scan electrode 5 and the sustain electrode 6 constituting the display electrode 7 of the front plate 1 are not made of a transparent electrode such as ITO, but are made of a conductive material such as Ag. It comprises only the conductive electrode which becomes. FIG. 4 shows a layout diagram of the scan electrodes 5 and the sustain electrodes 6, the data electrodes 12, and the partition walls 13 that constitute the display electrode 7. 5A and 5B show examples of the scan electrode 5 and the sustain electrode 6 for one cell.

  As shown in FIG. 4, the scan electrode 5 and the sustain electrode 6 constituting the display electrode 7 each have a ladder shape, and the first portions 51 and 61 that face each other with the discharge gap MG interposed therebetween. Second portions 52 and 62 arranged in parallel with a space from the portions 51 and 61, and the first portions 51 and 61 and the second portions 52 and 62 are connected to each other and provided for each discharge cell 15. 3 portions 53 and 63. Moreover, in the scan electrode 5 and the sustain electrode 6, when the width of the first portions 51 and 61 and the second portions 52 and 62 is LL and the width of the third portions 53 and 63 is Ls, the top of the partition wall 13 is used. The width Lr is configured such that Lr <Ls ≦ LL. Specifically, the width LL of the first portions 51 and 61 and the second portions 52 and 62 is about 60 μm to about 70 μm, the width Ls of the third portions 53 and 63 is about 60 μm, and the width Lr of the top of the partition wall 13 is It is about 50 μm. Discharge gap MG between scan electrode 5 and sustain electrode 6 is 90 μm to 100 μm, and gap LG between first portions 51 and 61 and second portions 52 and 62 of scan electrode 5 and sustain electrode 6 respectively. Is about 80 μm, and is formed to be smaller than the non-discharge gap IPG (about 200 μm) between the adjacent discharge cells 15.

  Here, in FIG. 5A, in the scan electrode 5 and the sustain electrode 6, the widths of the first portions 51, 61 and the second portions 52, 62 and the widths of the third portions 53, 63 are made the same. FIG. 5B is a diagram showing an example in which Lr <Ls ≦ LL configured to be larger than the width Lr of the top of the partition wall 13, and FIG. 5B illustrates the first portions 51, 61 and the scan electrodes 5 and the sustain electrodes 6. It is a figure which shows the example in the case of Lr <Ls <LL comprised larger than the width | variety Lr of the top part of the partition 13, while making the width | variety of the 2nd parts 52 and 62 larger than the width | variety of the 3rd parts 53 and 63.

  Thus, in the scan electrode 5 and the sustain electrode 6, when the width of the first portions 51, 61 and the second portions 52, 62 is LL, and the width of the third portions 53, 63 is Ls, the width of the top of the partition wall 13. By configuring Lr <Ls ≦ LL with respect to Lr, a panel having a display performance that ensures a sufficient contrast ratio without providing a light shielding member between adjacent discharge cells 15 can be obtained at low cost. It becomes possible. That is, in general, in a plasma display panel, since a glass material having a relatively high brightness is used as a material constituting the partition wall 13, it is sufficient to dispose a light shielding member in a non-discharge gap IPG portion of the adjacent discharge cell 15. A structure that ensures a high contrast ratio is employed. However, as in the present invention, the scan electrode 5 and the sustain electrode 6 constituting the display electrode 7 formed so as to have low brightness when viewed from the display surface side are discharged. The first portions 51 and 61 that face each other with the gap MG therebetween, the second portions 52 and 62 that are arranged in parallel with a space from the first portions 51 and 61, the first portions 51 and 61, and the second portions A third portion 53, 63 connected to each of the discharge cells 15 and connected to the portions 52, 62, and the first portion 51 in the scan electrode 5 and the sustain electrode 6. 61 and the second portions 52 and 62 are configured such that Lr <Ls ≦ LL with respect to the width Lr of the top of the partition wall 13 where LL is the width of the third portions 53 and 63 and Ls is the width of the third portions 53 and 63. As a result, a panel having a display performance with a sufficient contrast ratio can be obtained as in the case where the light shielding member is arranged without arranging the light shielding member in the non-discharge gap IPG portion of the adjacent discharge cell 15. It becomes possible.

  Next, the state of the display electrode 7 portion when the front plate 1 and the back plate 2 are bonded together in the plasma display panel of the present invention will be described. FIG. 6 is a schematic enlarged view showing the front plate 1 and the back plate 2 of the discharge cell portion in the plasma display panel of the present invention. FIG. 6 (a) is a plan view and FIG. 6 (b) is a plan view. It is the enlarged view cut | disconnected by the AA line of Fig.6 (a).

  As shown in FIG. 6, in the plasma display panel of the present invention, the front plate 1 and the top of the partition wall 13 of the back plate 2 are configured to abut at portions other than the discharge gap MG. That is, in the present invention, the display electrode 7 composed of the scan electrode 5 and the sustain electrode 6 is composed of only a conductive electrode composed of Ag without using a transparent electrode such as ITO, and the scanning electrode constituting the display electrode 7. The electrode 5 and the sustain electrode 6 include first portions 51 and 61 that are opposed to each other with a discharge gap MG, and second portions 52 and 62 that are arranged in parallel with a space from the first portions 51 and 61, Since the first portions 51, 61 and the second portions 52, 62 are connected and the third portions 53, 63 provided for each discharge cell 15 are provided, the dielectric layer covers the display electrode 7. 8 and the protective film 9, the first portion 51, 61 opposed to the surface of the front plate 1 on the discharge space side via the discharge gap MG, and the first portion 51, 61 Interval from The raised portions 1a are formed so as to correspond to the second portions 52 and 62 arranged in parallel with each other, and thereby the barrier ribs 13 on the back plate 2, particularly the vertical barrier ribs 13a, are raised portions 1a other than the discharge gap MG. Therefore, when the front plate 1 and the back plate 2 are bonded together, it is difficult to apply mechanical stress to the partition wall 13 in the discharge gap MG portion. It is possible to reduce the occurrence of defects by reducing.

  As shown in FIG. 7, in the partition wall 13 on the back plate 2 side, a raised portion 13c is provided at the intersection of the vertical partition wall 13a and the horizontal partition wall 13b, and the raised portion 13c is brought into contact with the front plate 1. As a result, it is possible to further reduce the defects of the barrier ribs 13 in the discharge gap MG portion of the display electrode 7 and to reduce the occurrence of defects due to the cracks of the barrier ribs 13.

  Next, in the plasma display panel according to the present invention, the configuration of the non-display area of the front plate 1 and the configuration of the electrode lead-out portion for connecting the display electrode 7 to an external drive circuit will be described.

  FIG. 8 is a diagram showing a schematic configuration of the entire panel in the plasma display panel according to the present invention. In FIG. 8, 16 is a panel having the configuration shown in FIGS. 1 to 3, and 17 is a display area on the panel 16. In this display area 17, an image corresponding to an input image signal is displayed. Reference numeral 18 denotes a non-display area existing around the display area 17. The non-display area 18 includes a sealing portion (not shown) for sealing the periphery of the front plate 1 and the back plate 2. This is a portion existing between the display area 17 and the display area 17. In the panel 16, a terminal portion (not shown) for connecting to an external drive circuit is provided on the outer portion of the sealing portion.

  Reference numeral 19 denotes a dummy electrode pattern formed in the non-display area 18. The dummy electrode pattern 19 is made of the same material as the scanning electrode 5 and the sustain electrode 6 in the upper and lower non-display areas 18 in the row direction of the front plate 1. In addition, the scanning electrode 5 and the sustain electrode 6 are formed in a solid pattern shape wider than the width in the row direction, and the dummy electrode pattern 19 is formed in an electrically floating state. Further, as shown in FIG. 9A, the dummy electrode pattern 19 has an end on the side of the display area 17 in the width direction, that is, a partition wall 13 in the row direction at the boundary between the display area 17 and the non-display area 18, that is, a horizontal side. It forms so that it may exist in the position which corresponds to the partition 13b. As shown in FIG. 9B, the dummy electrode pattern 19 has a partition wall 13 in the row direction at the boundary between the display area 17 and the non-display area 18 at the end on the display area 17 side in the width direction. The gap g may be formed with the same gap g as the gap g between the scan electrode 5 and the sustain electrode 6 and the horizontal barrier rib 13b.

  As described above, in the plasma display panel of the present invention, the upper and lower non-display regions 18 in the row direction of the front plate 1 are made of the same material as the scan electrode 5 and the sustain electrode 6, and the scan electrode 5 and Since the dummy electrode pattern 19 is formed in a solid pattern shape wider than the width of the sustain electrode 6 in the row direction, and the dummy electrode pattern 19 is formed in an electrically floating state, an image is displayed by discharge light emission. The contrast ratio between the display area 17 and the non-display area 18 is increased, and the display performance of the entire panel can be improved.

  Further, when a panel was actually produced and an image was displayed, the dummy electrode pattern 19 had a partition wall 13 in the row direction at the end of the display region 17 in the width direction at the boundary between the display region 17 and the non-display region 18. That is, it is more preferable to form so as to be present at a position coincident with the horizontal partition wall 13b in order to increase the contrast ratio between the display area 17 and the non-display area 18 and improve the display performance of the entire panel. It turns out to be effective.

  Next, in the plasma display panel according to the present invention, the configuration of the electrode lead-out portion for connecting the display electrode 7 to an external drive circuit will be described.

  FIG. 10 is a plan view showing a state of a non-display area at the electrode lead-out portion side for connecting the display electrode 7 to an external drive circuit, that is, the column end in the column direction, in the plasma display panel according to the present invention. In FIG. 10, only the display electrode 7, the data electrode 12, the partition wall 13, and the dummy electrode pattern 19 described above are shown. As shown in FIG. 10, in the non-display area at the panel end in the column direction, a plurality of data electrodes 12 and barrier ribs 13 are arranged in a repetitive pattern similarly to the display region, and among the plurality of barrier ribs 13, Between the several partition walls 13 (three in the drawing) on the display area side, phosphor layer forming areas are provided in the same arrangement as the display area.

  In addition, as shown in FIG. 10, the first portions 51 and 61 and the second portions 52 and 62 of the scan electrode 5 and the sustain electrode 6 constituting the display electrode 7 are arranged in a state facing each other with a discharge gap therebetween. The third portions 53 and 63 that connect the first portions 51 and 61 and the second portions 52 and 62 are also provided in several places as in the display region. . In addition, the end portions of the first portions 51 and 61 and the second portions 52 and 62 that are extended to the non-display areas are connected to the fourth portions 54 and 54 that connect the first portions 51 and 61 and the second portions 52 and 62, respectively. 64 is provided, and to the fourth portion 54 on the scanning electrode 5 side, the wiring pattern 20 drawn to the end portion outside the sealing portion of the front plate 1 is connected to be connected to an external drive circuit. . Further, the dummy electrode pattern 19 described above is formed such that the end portion of the pattern extends to a position outside the fourth portions 54 and 64 of the scan electrode 5 and the sustain electrode 6. In FIG. 10, only the scan electrode 5 side is shown, but the sustain electrode 6 side has the same configuration.

  FIG. 11 is an enlarged view showing only the terminal portion extended to the non-display area of scan electrode 5 and sustain electrode 6 in FIG. As shown in FIG. 11, in the present invention, the widths of the first portions 51 and 61 and the second portions 52 and 62 of the scan electrode 5 and the sustain electrode 6 are LL, and the width of the wiring pattern 20 is Lp. At this time, Lp is configured to be larger than LL. Specifically, when the width LL of the first portions 51 and 61 and the second portions 52 and 62 is about 60 μm, the width Lp of the wiring pattern 20 is about 80 μm.

  With such a configuration, in the scan electrode 5 and the sustain electrode 6, the fourth portions 54, 64 connecting the end portions extended to the non-display areas of the first portions 51, 61 and the second portions 52, 62. And the wiring pattern 20 having a width larger than the width LL of the first portions 51 and 61 and the second portions 52 and 62 is connected to the fourth portions 54 and 64, so that the scan electrode 5 and the sustain electrode 6 The wiring pattern 20 can be connected with high reliability, and the occurrence of a panel defect can be suppressed.

  In the example shown in FIG. 11, the width Lp of the wiring pattern 20 is configured to be larger than the width LL of the first portions 51 and 61 and the second portions 52 and 62. Even if the width Lp of the wiring pattern 20 and the widths LL of the first portions 51 and 61 and the second portions 52 and 62 are the same, the reliability of the connection portion can be ensured. The width LL of the first portions 51 and 61 and the second portions 52 and 62 may be set to satisfy LL ≦ Lp.

  Next, a driving voltage waveform for driving the panel and an outline of the operation will be described. The plasma display device according to the present embodiment performs gradation display by subfield method, that is, by dividing one field period into a plurality of subfields and controlling light emission / non-light emission of each discharge cell for each subfield. Each subfield has an initialization period, an address period, and a sustain period.

  In each subfield, initializing discharge is generated in the initializing period, and wall charges necessary for subsequent address discharge are formed on each electrode. In addition, it has a function of generating priming particles for reducing discharge delay and generating address discharge stably. The initializing operation at this time is an all-cell initializing operation in which initializing discharge is generated in all discharge cells, and an initializing discharge is selectively generated only in the discharge cells that have undergone sustain discharge in the immediately preceding subfield. There is a selective initialization operation.

  In the address period, an address discharge is selectively generated in the discharge cells to emit light in the subsequent sustain period to form wall charges. In the sustain period, a number of sustain pulses proportional to the luminance weight are alternately applied to the display electrode 7 to generate a sustain discharge in the discharge cells that have generated the address discharge to emit light. The proportionality constant at this time is called “luminance magnification”.

  In this embodiment, one field is composed of 10 subfields (first SF, second SF,..., 10th SF), and each subfield is, for example, (1, 2, 3, 6, 11, 18). , 30, 44, 60, 80). Then, the all-cell initialization operation is performed in the initialization period of the first SF, and the selective initialization operation is performed in the initialization period of the second SF to the tenth SF. As a result, the light emission not related to the image display is only the light emission due to the discharge of the all-cell initialization operation in the first SF, and the black luminance, which is the luminance of the black display area that does not generate the sustain discharge, is weak in the all-cell initialization operation. Only the emission of light makes it possible to display an image with high contrast. In the sustain period of each subfield, the number of sustain pulses obtained by multiplying the luminance weight of each subfield by a predetermined luminance magnification is applied to each display electrode 7.

  However, in the present embodiment, the number of subfields and the luminance weight of each subfield are not limited to the above values, and the subfield configuration may be switched based on an image signal or the like.

  In the present embodiment, the ramp waveform voltage is generated at the end of the sustain period, thereby stabilizing the write operation in the subsequent subfield write period. Hereinafter, the outline of the drive voltage waveform will be described first, and then the configuration of the drive circuit will be described.

  FIG. 12 is a drive voltage waveform diagram applied to each electrode of the panel in the embodiment of the present invention. FIG. 12 shows driving voltage waveforms of two subfields, that is, a subfield that performs an all-cell initializing operation (hereinafter referred to as “all-cell initializing subfield”) and a subfield that performs a selective initializing operation ( Hereinafter, it is referred to as “selective initialization subfield”), but the driving voltage waveforms in the other subfields are substantially the same. In addition, the scan electrode Yi, the sustain electrode Xi, and the data electrode Ak in the following represent electrodes selected from each electrode based on image data.

  First, the first SF, which is an all-cell initialization subfield, will be described.

  In the first half of the initializing period of the first SF, 0 (V) is applied to the data electrodes A1 to Am and the sustain electrodes X1 to Xn, respectively, and the discharge start voltage with respect to the sustain electrodes X1 to Xn is applied to the scan electrodes Y1 to Yn. A first ramp waveform voltage (hereinafter referred to as “up-ramp waveform voltage”) that gradually rises from voltage Vi1 below toward voltage Vi2 that exceeds the discharge start voltage is applied. In the present embodiment, this up-ramp waveform voltage has a slope of about 1.3 V / μsec.

  While the rising ramp waveform voltage rises, weak initializing discharges are continuously generated between the scan electrodes Y1 to Yn, the sustain electrodes X1 to Xn, and the data electrodes A1 to Am. Negative wall voltage is accumulated on scan electrodes Y1 to Yn, and positive wall voltage is accumulated on data electrodes A1 to Am and sustain electrodes X1 to Xn. The wall voltage above the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

  In the latter half of the initialization period, positive voltage Ve1 is applied to sustain electrodes X1 to Xn, 0 (V) is applied to data electrodes A1 to Am, and sustain electrodes X1 to Xn are applied to scan electrodes Y1 to Yn. In contrast, a ramp waveform voltage (hereinafter referred to as a “down-ramp waveform voltage”) that gently falls from a voltage Vi3 that is equal to or lower than the discharge start voltage to a voltage Vi4 that exceeds the discharge start voltage is applied. During this time, weak initializing discharges are continuously generated between the scan electrodes Y1 to Yn, the sustain electrodes X1 to Xn, and the data electrodes A1 to Am. Then, the negative wall voltage above scan electrodes Y1 to Yn and the positive wall voltage above sustain electrodes X1 to Xn are weakened, and the positive wall voltage above data electrodes A1 to Am is adjusted to a value suitable for the write operation. The Thus, the all-cell initializing operation for performing the initializing discharge on all the discharge cells is completed.

  Note that, as shown in the initialization period of the second SF in FIG. 12, a drive voltage waveform in which the first half of the initialization period is omitted may be applied to each electrode. That is, the voltage Ve1 is applied to the sustain electrodes X1 to Xn, 0 (V) is applied to the data electrodes A1 to Am, and the down-ramp waveform voltage that gradually decreases from the voltage Vi3 ′ to the voltage Vi4 to the scan electrodes Y1 to Yn. Apply. As a result, a weak initializing discharge is generated in the discharge cell that has generated the sustain discharge in the sustain period of the previous subfield, and the wall voltage on the scan electrode Yi and the sustain electrode Xi is weakened. Further, in a discharge cell in which a sufficient positive wall voltage is accumulated on the upper part of the data electrode Ak (k = 1 to m) by the last sustain discharge, an excessive portion of the wall voltage is discharged, and the wall voltage suitable for the address operation. Adjusted to On the other hand, the discharge cells that did not cause the sustain discharge in the previous subfield are not discharged, and the wall charges at the end of the initialization period of the previous subfield are maintained as they are. Thus, the initializing operation in which the first half is omitted is a selective initializing operation in which initializing discharge is performed on the discharge cells in which the sustaining operation has been performed in the sustain period of the immediately preceding subfield.

  In the subsequent address period, first, voltage Ve2 is applied to sustain electrodes X1 to Xn, and voltage Vc is applied to scan electrodes Y1 to Yn.

  Then, a negative scan pulse voltage Va is applied to the scan electrode Y1 in the first row, and the data electrode Ak (k = 1 to m) of the discharge cell to be emitted in the first row among the data electrodes A1 to Am is positive. The write pulse voltage Vd is applied. At this time, the voltage difference at the intersection between the data electrode Ak and the scan electrode Y1 is the difference between the wall voltage on the data electrode Ak and the wall voltage on the scan electrode Y1 due to the difference in the externally applied voltage (Vd−Va). It becomes the sum and exceeds the discharge start voltage. As a result, an address discharge occurs between the data electrode Ak and the scan electrode Y1, and between the sustain electrode X1 and the scan electrode Y1, a positive wall voltage is accumulated on the scan electrode Y1, and a negative voltage is accumulated on the sustain electrode X1. A wall voltage is accumulated, and a negative wall voltage is also accumulated on the data electrode Ak.

  In this manner, an address operation is performed in which an address discharge is caused in the discharge cells to be lit in the first row and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection of the data electrodes A1 to Am and the scan electrode Y1 to which the address pulse voltage Vd is not applied does not exceed the discharge start voltage, so that address discharge does not occur. The above address operation is performed until the discharge cell in the nth row, and the address period ends.

  In the subsequent sustain period, first, a positive sustain pulse voltage Vs is applied to scan electrodes Y1 to Yn, and a ground potential serving as a base potential, that is, 0 (V) is applied to sustain electrodes X1 to Xn. Then, in the discharge cell in which the address discharge has occurred, the voltage difference between the scan electrode Yi and the sustain electrode Xi is the difference between the wall voltage on the scan electrode Yi and the wall voltage on the sustain electrode Xi. Exceeding the discharge start voltage. For this reason, a sustain discharge occurs between the scan electrode Yi and the sustain electrode Xi, and the phosphor layers 14R, 14G, and 14B emit light by the ultraviolet rays generated at this time. A negative wall voltage is accumulated on scan electrode Yi, and a positive wall voltage is accumulated on sustain electrode Xi. Further, a positive wall voltage is accumulated on the data electrode Ak. In the discharge cells in which no address discharge has occurred during the address period, no sustain discharge occurs, and the wall voltage at the end of the initialization period is maintained.

  Subsequently, 0 (V) as a base potential is applied to scan electrodes Y1 to Yn, and sustain pulse voltage Vs is applied to sustain electrodes X1 to Xn. Then, in the discharge cell in which the sustain discharge has occurred, since the voltage difference between the sustain electrode Xi and the scan electrode Yi exceeds the discharge start voltage, the sustain discharge occurs again between the sustain electrode Xi and the scan electrode Yi, and the sustain electrode A negative wall voltage is accumulated on Xi, and a positive wall voltage is accumulated on scan electrode Yi. Thereafter, similarly, the sustain period is applied to the scan electrodes Y1 to Yn and the sustain electrodes X1 to Xn alternately by the number obtained by multiplying the luminance weight by the luminance magnification, and a potential difference is given between the electrodes of the display electrode 7, thereby writing period. The sustain discharge is continuously performed in the discharge cell in which the address discharge has occurred in FIG.

  At the end of the sustain period, a second ramp waveform voltage (hereinafter referred to as “erase ramp waveform voltage”) that gradually increases from 0 (V) as the base potential toward the voltage Vers is applied to the scan electrodes Y1 to Yn. Applied). As a result, a weak discharge is continuously generated, and some or all of the wall voltages on the scan electrode Yi and the sustain electrode Xi are erased while leaving the positive wall voltage on the data electrode Ak.

  Specifically, after the sustain electrodes X1 to Xn are returned to 0 (V), the erase is the second ramp waveform voltage that rises from 0 (V), which is the base potential, toward the voltage Vers that exceeds the discharge start voltage. The ramp waveform voltage is generated with a steeper gradient than the up-ramp waveform voltage, which is the first ramp waveform voltage, for example, a gradient of about 10 V / μsec, and is applied to the scan electrodes Y1 to Yn. Then, a weak discharge is generated between the sustain electrode Xi and the scan electrode Yi of the discharge cell in which the sustain discharge has occurred. The weak discharge is continuously generated during a period in which the voltage applied to the sustain electrodes X1 to Xn increases. Then, as soon as the rising voltage reaches the voltage Vers, which is a predetermined potential, the voltage applied to the scan electrodes Y1 to Yn is lowered to 0 (V) as the base potential.

  At this time, the charged particles generated by the weak discharge are always accumulated as wall charges on the sustain electrode Xi and the scan electrode Yi so as to alleviate the voltage difference between the sustain electrode Xi and the scan electrode Yi. It will be done. Thus, the wall voltage between the scan electrodes Y1 to Yn and the sustain electrodes X1 to Xn remains between the voltage applied to the scan electrode Yi and the discharge start voltage while leaving the positive wall charges on the data electrode Ak. The difference is reduced to the extent of (voltage Vers−discharge start voltage). Hereinafter, the last discharge in the sustain period generated by the erase ramp waveform voltage is referred to as “erase discharge”.

In the present embodiment, when the voltage applied to the scan electrodes Y1 to Yn reaches a predetermined voltage Vers, the voltage is immediately lowered to 0 (V) as the base potential. After the rising voltage reaches the predetermined voltage Vers, if this voltage is maintained, the following condition is satisfied:
The cell itself is a non-light emitting discharge cell (a discharge cell not addressed in the subfield).
This is a discharge cell that emits light from an adjacent cell (a discharge cell addressed in the subfield).
A self-sustained discharge occurred in the immediately preceding subfield.
This is because it has been experimentally confirmed that abnormal discharge is likely to occur in discharge cells that meet the above conditions.

  Since this abnormal discharge induces erroneous discharge in the subsequent address period, it is desirable to prevent it from occurring as much as possible. In this embodiment, when the erase ramp waveform voltage is generated, it is applied to the scan electrodes Y1 to Yn. After the voltage to reach the voltage Vers, it is immediately lowered to 0 (V), which is the base potential, so that the addressing operation that continues the wall voltage in the discharge cell is stable while preventing the occurrence of this abnormal discharge. It can be optimally adjusted to do so.

  Subsequent subfield operations are substantially the same as those described above except for the number of sustain pulses in the sustain period, and thus description thereof is omitted. The above is the outline of the drive voltage waveform applied to each electrode of the panel in the present embodiment.

  In this embodiment, the voltage value of the voltage Vers is set to the sustain pulse voltage Vs + 3 (V), for example, about 213 (V), but here the voltage value of the voltage Vers is set to the sustain pulse voltage Vs−. It is desirable to set a voltage range of 10 (V) or more and sustain pulse voltage Vs + 10 (V) or less. If the voltage value of the voltage Vers is larger than the upper limit value, the wall voltage will be excessively adjusted. If the voltage value is smaller than the lower limit value, the wall voltage will be insufficiently adjusted and the subsequent writing operation may not be performed stably. Because.

  In the present embodiment, the configuration in which the gradient of the erase ramp waveform voltage is set to about 10 V / μsec has been described, but this gradient is preferably set to 2 V / μsec or more and 20 V / μsec or less. If the slope is steeper than this upper limit value, the discharge for adjusting the wall voltage will not be weak, and if the slope is made gentler than this lower limit value, the discharge itself will be too weak, This is because the voltage may not be adjusted properly.

  Next, the configuration of the plasma display device in the present embodiment will be described. FIG. 13 is a circuit block diagram of the plasma display device in accordance with the exemplary embodiment of the present invention. The plasma display device 30 includes a panel 21, an image signal processing circuit 22, a data electrode drive circuit 23, a scan electrode drive circuit 24, a sustain electrode drive circuit 25, a timing generation circuit 26, and a power supply circuit that supplies necessary power to each circuit block. (Not shown).

  The image signal processing circuit 22 converts the input image signal sig into image data indicating light emission / non-light emission for each subfield. The data electrode driving circuit 23 converts the image data for each subfield into signals corresponding to the data electrodes A1 to Am, and drives the data electrodes A1 to Am.

  The timing generation circuit 26 generates various timing signals for controlling the operation of each circuit block on the basis of outputs from the horizontal synchronization signal H and the vertical synchronization signal V, and supplies them to the respective circuit blocks. As described above, in the present embodiment, an erase ramp waveform voltage is generated at the end of the sustain period, and a timing signal corresponding to the erase ramp waveform voltage is output to scan electrode drive circuit 24 and sustain electrode drive circuit 25. . As a result, stable initialization discharge is realized, and the address operation is stabilized.

  Scan electrode driving circuit 24 generates an initialization waveform generating circuit for generating an initialization waveform voltage to be applied to scan electrodes Y1 to Yn in the initialization period, and generates a sustain pulse to be applied to scan electrodes Y1 to Yn in the sustain period. And a scan pulse generation circuit for generating a scan pulse voltage to be applied to the scan electrodes Y1 to Yn in the address period, and drives each of the scan electrodes Y1 to Yn based on a timing signal. Sustain electrode drive circuit 25 includes a sustain pulse generating circuit and a circuit for generating voltage Ve1 and voltage Ve2, and drives sustain electrodes X1 to Xn based on a timing signal.

  Next, the scan electrode driving circuit 24 will be described. FIG. 14 is a circuit diagram of scan electrode driving circuit 24 in the embodiment of the present invention. The scan electrode drive circuit 24 includes a sustain pulse generation circuit 70 that generates a sustain pulse, an initialization waveform generation circuit 73 that generates an initialization waveform, and a scan pulse generation circuit 74 that generates a scan pulse. FIG. 14 shows a separation circuit using the switching element Q12 and a separation circuit using the switching element Q13. In the following description, the operation for turning on the switching element is expressed as “on”, the operation for cutting off the switching element is expressed as “off”, the signal for turning on the switching element is expressed as “Hi”, and the signal for turning off is expressed as “Lo”.

  Sustain pulse generation circuit 70 includes a power recovery circuit 71 and a clamp circuit 72. The power recovery circuit 71 includes a power recovery capacitor C1, a switching element Q1, a switching element Q2, a backflow prevention diode D1, a backflow prevention diode D2, and a resonance inductor L1. The power recovery capacitor C1 has a sufficiently large capacity compared to the interelectrode capacity Cp, and is charged to about Vs / 2, which is half of the voltage value Vs, so as to serve as a power source for the power recovery circuit 71. The clamp circuit 72 includes a switching element Q3 for clamping the scan electrodes Y1 to Yn to the voltage Vs, and a switching element Q4 for clamping the scan electrodes Y1 to Yn to 0 (V). Then, based on the timing signal output from the timing generation circuit 26, the switching elements are switched to generate the sustain pulse voltage Vs.

  In the sustain pulse generation circuit 70, for example, when the sustain pulse waveform is raised, the switching element Q1 is turned on to resonate the interelectrode capacitance Cp and the inductor L1, and the switching element Q1 and diode from the power recovery capacitor C1 are resonated. Power is supplied to the scan electrodes Y1 to Yn through D1 and the inductor L1. Then, when the voltage of the scan electrodes Y1 to Yn approaches the voltage Vs, the switching element Q3 is turned on, and the scan electrodes Y1 to Yn are clamped to the voltage Vs. Even when the switching element Q12 is off, a parasitic diode called a body diode is anti-parallel to the portion that performs the switching operation (in parallel to the portion that performs the switching operation, and the current due to the switching operation). Therefore, when the switching element Q3 is turned on, the scan electrodes Y1 to Yn can be clamped to the voltage Vs via the body diode.

  On the contrary, when the sustain pulse waveform is lowered, the switching element Q2 is turned on to resonate the interelectrode capacitance Cp and the inductor L1, and the interelectrode capacitance Cp is used for power recovery through the inductor L1, the diode D2, and the switching element Q2. The power is recovered in the capacitor C1. Then, when the voltage of the scan electrodes Y1 to Yn approaches 0 (V), the switching element Q4 is turned on to clamp the scan electrodes Y1 to Yn to 0 (V).

  In the present embodiment, a ramp waveform generating circuit for generating an erase ramp waveform voltage is provided separately from the ramp waveform generating circuit for generating an up ramp waveform voltage during the initialization operation. . Specifically, the initialization waveform generation circuit 73 includes a switching element Q11, a capacitor C10, and a resistor R10, and generates a rising ramp waveform voltage that gradually rises in a ramp shape up to the voltage Vi2. A first Miller integrating circuit 75, a switching element Q15, a capacitor C11, and a resistor R12, and a second ramp waveform generating circuit that generates an erasing ramp waveform voltage that gradually rises in a ramp shape up to the voltage Vers. The third mirror, which is a third ramp waveform generating circuit 76, which has a Miller integrating circuit 76, a switching element Q14, a capacitor C12, and a resistor R11, and generates a ramp voltage waveform that gradually falls in a ramp shape to a voltage Vi4. An integrating circuit 77 is provided. In FIG. 14, the input terminals of the Miller integrating circuit are shown as an input terminal INa, an input terminal INb, and an input terminal INc.

  In the present embodiment, the erase ramp waveform voltage is compared with a predetermined voltage in order to accurately stop the rise in voltage when the erase ramp waveform voltage is generated at the voltage Vers. A switching circuit for stopping the operation of the second Miller integrating circuit that generates the erase ramp waveform voltage immediately after reaching the predetermined voltage is provided. Specifically, when the voltage output from the diode D13 for backflow prevention, the resistor R13 for adjusting the voltage value of the voltage Vers, and the initialization waveform generation circuit 73 reaches the voltage Vers, the second Miller integration circuit 76 A switching element Q16 for setting the input terminal INc to “Lo”, a protective diode D12, and a resistor R14 are provided.

  The switching element Q16 is formed of a commonly used NPN transistor, and has a base connected to the output of the initialization waveform generating circuit 73, a collector connected to the input terminal INc of the second Miller integrating circuit 76, and an emitter connected in series. The resistor R13 and the diode D13 are connected to the voltage Vs. The resistor R13 has a resistance value set so that the switching element Q16 is turned on when the voltage output from the initialization waveform generation circuit 73 reaches the voltage Vers. Therefore, the resistance R13 is output from the initialization waveform generation circuit 73. When the voltage reaches voltage Vers, switching element Q16 is turned on. Then, the current input to the input terminal INc for operating the second Miller integrating circuit 76 is drawn to the switching element Q16, so that the second Miller integrating circuit 76 stops operating.

  In general, Miller integration circuits are easily affected by variations in the ramp waveform to be generated due to variations in the elements constituting the circuit. Therefore, if waveform generation is performed only during the operation period of the Miller integration circuit, the ramp waveform The maximum voltage value tends to vary. On the other hand, in this embodiment, it has been confirmed that it is desirable to keep the maximum voltage value of the erase ramp waveform voltage within ± 3 (V) with respect to the target voltage value. By using the configuration in this embodiment, Therefore, it can be within a range of about ± 1 (V) with respect to the target voltage value, and the erase ramp waveform voltage can be generated with high accuracy.

  The voltage Vers 'is preferably set to a voltage value higher than the voltage Vers, and in this embodiment, the voltage Vers' is set to the voltage Vs + 30 (V). In this embodiment, the resistance value of the resistor R13 is set so that the voltage Vers becomes the voltage Vs + 3 (V). Specifically, the resistor R13 is set to 100Ω, the voltage Vs is set to 210 (V), and the resistor R14 is set. Is set to 1 kΩ. However, these values are merely values set based on a 42-inch panel having 1080 display electrodes 7 and may be optimally set according to the characteristics of the panel and the specifications of the plasma display device.

  The initialization waveform generation circuit 73 generates the above-described initialization waveform voltage or erase ramp waveform voltage based on the timing signal output from the timing generation circuit 26. For example, when generating an up-ramp waveform voltage in the initialization waveform, a constant current of a predetermined voltage (for example, 15 (V)) is input to the input terminal INa to set the input terminal INa to “Hi”. As a result, a constant current flows from the resistor R10 toward the capacitor C10, the source voltage of the switching element Q11 increases in a ramp shape, and the output voltage of the scan electrode drive circuit 24 also starts to increase in a ramp shape.

  In addition, when generating the down-ramp waveform voltage in the initialization waveform of the all-cell initialization operation and the selection initialization operation, a constant current of a predetermined voltage (for example, 15 (V)) is input to the input terminal INb. The input terminal INb is set to “Hi”. Then, a constant current flows from the resistor R11 toward the capacitor C12, the drain voltage of the switching element Q14 decreases in a ramp shape, and the output voltage of the scan electrode driving circuit 24 also starts decreasing in a ramp shape.

  Further, when the erase ramp waveform voltage is generated at the end of the sustain period, a constant current of a predetermined voltage is input to the input terminal INc, and the input terminal INc is set to “Hi”. As a result, a constant current flows from the resistor R12 toward the capacitor C11, the source voltage of the switching element Q15 increases in a ramp shape, and the output voltage of the scan electrode drive circuit 24 also starts to increase in a ramp shape. In the present embodiment, the resistance value of the resistor R12 is made smaller than the resistance value of the resistor R10, whereby the erase ramp waveform voltage, which is the second ramp waveform voltage, is changed to the first ramp waveform voltage. It is generated with a steeper slope than some up-ramp waveform voltage.

  When the drive voltage waveform output from the initialization waveform generating circuit 73 gradually increases and becomes higher than the voltage Vers, the switching element Q16 is turned on and the constant current input to the input terminal INc is drawn to the switching element Q16. As a result, the second Miller integrating circuit 76 stops operating. As a result, the drive voltage waveform output from the initialization waveform generation circuit 73 immediately drops to 0 (V), which is the base potential. Thus, in the present embodiment, the rise in voltage when the erase ramp waveform voltage is generated is accurately stopped at the voltage Vers that is the predetermined potential, and then immediately lowered to 0 (V) that becomes the base potential.

  The scan pulse generation circuit 74 includes switch circuits OUT1 to OUTn that output scan pulse voltages to the scan electrodes Y1 to Yn, a switching element Q21 for clamping the low voltage side of the switch circuits OUT1 to OUTn to the voltage Va, Control circuits IC1 to ICn for controlling the switch circuits OUT1 to OUTn, and a diode D21 and a capacitor C21 for applying a voltage Vc obtained by superimposing the voltage Vscn on the voltage Va to the high voltage side of the switch circuits OUT1 to OUTn. ing. Each of the switch circuits OUT1 to OUTn includes switching elements QH1 to QHn for outputting the voltage Vc and switching elements QL1 to QLn for outputting the voltage Va. Then, based on the timing signal output from the timing generation circuit 26, the scan pulse voltage Va to be applied to the scan electrodes Y1 to Yn is sequentially generated in the address period. Scan pulse generation circuit 74 outputs the voltage waveform of initialization waveform generation circuit 73 during the initialization period and the voltage waveform of sustain pulse generation circuit 70 as it is during the sustain period.

  Since a very large current flows through switching element Q3, switching element Q4, switching element Q12, and switching element Q13, a plurality of FETs, IGBTs, etc. are connected in parallel to these switching elements to reduce impedance. .

  The scan pulse generation circuit 74 includes an AND gate AG that performs an AND operation and a comparator CP that compares the magnitudes of input signals input to two input terminals. The comparator CP compares a voltage (Va + Vset2) obtained by superimposing the voltage Vset2 on the voltage Va and the drive voltage waveform. If the drive voltage waveform is higher than the voltage (Va + Vset2), “0” is set. Then, “1” is output. Two input signals, that is, an output signal CEL1 of the comparator CP and a switching signal CEL2 are input to the AND gate AG. For example, a timing signal output from the timing generation circuit 26 can be used as the switching signal CEL2. The AND gate AG outputs “1” when any of the input signals is “1”, and outputs “0” otherwise. The output of the AND gate AG is input to the control circuits IC1 to ICn. If the output of the AND gate AG is “0”, the drive voltage waveform is output via the switching elements QL1 to QLn, and the output of the AND gate AG is “1”. If there is, the voltage Vc in which the voltage Vscn is superimposed on the voltage Va is output via the switching elements QH1 to QHn.

  In the present embodiment, a Miller integration circuit using FETs that are practical and have a relatively simple configuration for the first ramp waveform generation circuit, the second ramp waveform generation circuit, and the third ramp waveform generation circuit. However, the ramp waveform generating circuit is not limited to this configuration, and any circuit can be used as long as it can generate an up-ramp waveform voltage and a down-ramp waveform voltage. Good.

  Next, the sustain electrode drive circuit 25 will be described. FIG. 15 is a circuit diagram of sustain electrode drive circuit 25 in the embodiment of the present invention. In FIG. 15, the interelectrode capacitance of the panel 21 is shown as Cp.

  Sustain pulse generation circuit 80 of sustain electrode drive circuit 25 has substantially the same configuration as sustain pulse generation circuit 70 of scan electrode drive circuit 24, and collects and reuses power when driving sustain electrodes X1 to Xn. Power recovery circuit 81 and a clamp circuit 82 for clamping sustain electrodes X1 to Xn to voltages Vs and 0 (V), and sustain electrodes X1 to X1 are one end of interelectrode capacitance Cp of panel 21. Connected to Xn.

  The power recovery circuit 81 includes a power recovery capacitor C30, a switching element Q31, a switching element Q32, a backflow prevention diode D31, a diode D32, and a resonance inductor L30. Then, the interelectrode capacitance Cp and the inductor L30 are LC-resonated, and the sustain pulse rises and falls. The clamp circuit 82 includes a switching element Q33 for clamping the sustain electrodes X1 to Xn to the voltage Vs, and a switching element Q34 for clamping the sustain electrodes X1 to Xn to 0 (V). Then, sustain electrodes X1 to Xn are connected to power supply VS via switching element Q33 and clamped to voltage Vs, and sustain electrodes X1 to Xn are grounded and switched to 0 (V) via switching element Q34.

  The sustain electrode drive circuit 25 also includes a power source VE1 for generating the voltage Ve1, a switching element Q36 for applying the voltage Ve1 to the sustain electrodes X1 to Xn, a switching element Q37, a power source ΔVE for generating the voltage ΔVe, and a backflow prevention A diode D33, a pump-up capacitor C31 for accumulating the voltage ΔVe on the voltage Ve1, a switching element Q38 for accumulating the voltage ΔVe on the voltage Ve1 to obtain the voltage Ve2, and a switching element Q39 are provided.

  For example, at the timing of applying the voltage Ve1 shown in FIG. 12, the switching element Q36 and the switching element Q37 are turned on, and the positive voltage Ve1 is connected to the sustain electrodes X1 to Xn via the diode D33, the switching element Q36, and the switching element Q37. Apply. At this time, the switching element Q38 is turned on and charged so that the voltage of the capacitor C31 becomes the voltage Ve1. In addition, at the timing of applying the voltage Ve2 shown in FIG. 12, the switching element Q36 and the switching element Q37 are kept conductive, the switching element Q38 is cut off and the switching element Q39 is turned on so that the voltage ΔVe is applied to the voltage of the capacitor C31. The voltage (Ve1 + ΔVe), that is, the voltage Ve2 is applied to the sustain electrodes X1 to Xn. At this time, the current from the capacitor C31 to the power source VE1 is cut off by the action of the backflow preventing diode D33.

  Next, details of the drive voltage waveform in the sustain period will be described. FIG. 16 is a timing chart for explaining an example of operations of scan electrode driving circuit 24 and sustain electrode driving circuit 25 in the embodiment of the present invention, and is a detailed timing chart of a portion surrounded by a broken line in FIG. is there. First, one period of the sustain pulse repetition period is divided into six periods indicated by T1 to T6, and each period will be described. The repetition period is an interval between sustain pulses repeatedly applied to the display electrodes in the sustain period, and represents, for example, a period repeated by the periods T1 to T6. In FIG. 16, description is made using the positive electrode waveform, but the present invention is not limited to this. For example, although the embodiment in the negative waveform is omitted, what is expressed as “rising” in the positive waveform in the following description is “falling” in the negative waveform, and “ By replacing the expression “falling” with “rising” in the negative waveform, the same effect can be obtained even in the negative waveform. In the drawing, a signal for turning on the switching element is represented as “ON”, and a signal for turning off is represented as “OFF”.

(Period T1)
At time t1, switching element Q2 is turned on. Then, the charges on the scan electrodes Y1 to Yn side start to flow to the capacitor C1 through the inductor L1, the diode D2, and the switching element Q2, and the voltage of the scan electrodes Y1 to Yn starts to decrease. Since the inductor L1 and the interelectrode capacitance Cp form a resonance circuit, the voltage of the scan electrodes Y1 to Yn drops to near 0 (V) at time t2 after the time ½ of the resonance period has elapsed. However, the voltage of the scan electrodes Y1 to Yn does not decrease to 0 (V) due to power loss due to the resistance component of the resonance circuit. During this period, the switching element Q34 is kept on.

(Period T2)
At time t2, switching element Q4 is turned on. Then, since the scan electrodes Y1 to Yn are directly grounded through the switching element Q4, the voltages of the scan electrodes Y1 to Yn are forcibly lowered to 0 (V).

  Further, switching element Q31 is turned on at time t2. Then, current begins to flow from the power recovery capacitor C30 through the switching element Q31, the diode D31, and the inductor L30, and the voltages of the sustain electrodes X1 to Xn begin to rise. Since the inductor L30 and the interelectrode capacitance Cp form a resonance circuit, the voltage of the sustain electrodes X1 to Xn rises to the vicinity of the voltage Vs at time t3 after a time ½ of the resonance period has elapsed. Therefore, the voltage of the sustain electrodes X1 to Xn does not rise up to the voltage Vs.

(Period T3)
At time t3, switching element Q33 is turned on. Then, since sustain electrodes X1 to Xn are directly connected to power supply VS through switching element Q33, the voltages of sustain electrodes X1 to Xn are forcibly increased to voltage Vs. Then, in the discharge cell in which the address discharge has occurred, the voltage between the scan electrode Yi and the sustain electrode Xi exceeds the discharge start voltage, and a sustain discharge occurs.

(Period T4-T6)
The sustain pulse applied to scan electrodes Y1 to Yn and the sustain pulse applied to sustain electrodes X1 to Xn have the same waveform, and the operation from period T4 to period T6 scans the operation from period T1 to period T3. Since the operation is the same as the operation in which the electrodes Y1 to Yn and the sustain electrodes X1 to Xn are switched, description thereof will be omitted.

  Switching element Q2 may be turned off after time t2 and before time t5, and switching element Q31 may be turned off after time t3 and before time t4. Further, the switching element Q32 may be turned off by the next time t2 after the time t5, and the switching element Q1 may be turned off by the next time t1 after the time t6. In order to lower the output impedance of sustain pulse generating circuits 70 and 80, switching element Q34 is preferably turned off immediately before time t2, switching element Q3 is preferably turned off immediately before time t1, and switching element Q4 is turned off immediately before time t5. Switching element Q33 is preferably turned off immediately before time t4.

  In the sustain period, the operations in the above periods T1 to T6 are repeated according to the required number of pulses. In this manner, the sustain pulse voltage that is displaced from the base potential 0 (V) to the voltage Vs that is a potential for generating a sustain discharge is alternately applied to each of the display electrodes 7 to cause the discharge cells to sustain discharge.

  Next, an operation when the erase ramp waveform voltage is generated at the end of the sustain period will be described.

(Period T7)
This period is the fall of the sustain pulse applied to the sustain electrodes X1 to Xn, and is the same as the period T4. That is, by turning off the switching element Q33 immediately before time t7 and turning on the switching element Q32 at time t7, the charges on the sustain electrodes X1 to Xn side start to flow to the capacitor C30 through the inductor L30, the diode D32, and the switching element Q32. The voltage of sustain electrodes X1 to Xn starts to drop. Further, the switching element Q4 is kept on, and the scan electrodes Y1 to Yn are maintained at 0 (V) which is the base potential.

(Period T8)
At time t8, switching element Q34 is turned on to forcibly reduce the voltages of sustain electrodes X1 to Xn to 0 (V). At time t8, the input terminal INc is set to “Hi”. As a result, a constant current flows from the resistor R12 toward the capacitor C11, the source voltage of the switching element Q15 rises in a ramp shape, and the output voltage of the scan electrode drive circuit 24 has a steeper slope than the up-ramp waveform voltage. It begins to rise like a ramp. In this way, the erase ramp waveform voltage which is the second ramp waveform voltage rising from 0 (V) as the base potential toward the voltage Vers is generated. Then, the voltage difference between the scan electrode Yi and the sustain electrode Xi exceeds the discharge start voltage while the erase ramp waveform voltage rises. At this time, in the present embodiment, each numerical value is set so that discharge is generated only between the scan electrode Yi and the sustain electrode Xi. For example, the sustain pulse voltage Vs is about 210 (V), and the voltage Vers is about 213 (V), and the gradient of the erase ramp waveform voltage is about 10 V / μsec. As a result, a weak discharge can be generated between the scan electrode Yi and the sustain electrode Xi, and this weak discharge can be continued for a period during which the erase ramp waveform voltage rises.

  At this time, if a momentary strong discharge due to a sudden voltage change is generated, a large amount of charged particles generated by the strong discharge form a large wall charge so as to relieve the sudden voltage change, The wall voltage formed by the sustain discharge is excessively erased. In addition, in a panel with a large screen, high definition, and increased driving impedance, waveform distortion such as ringing is likely to occur in the driving waveform generated from the driving circuit. Then, there is a risk of generating strong discharge due to waveform distortion.

  However, in the present embodiment, a weak erase discharge is continuously generated between the scan electrode Yi and the sustain electrode Xi by the erase ramp waveform voltage that gradually increases the applied voltage. Even in a panel with high definition and increased driving impedance, the erase discharge can be generated stably, and the wall voltage on the scan electrode Yi and the sustain electrode Xi can be generated stably. It can be adjusted to the optimum state.

  Although not shown in the drawing, since the data electrodes A1 to Am are held at 0 (V) at this time, a positive wall voltage is formed on the data electrodes A1 to Am.

(Period T9)
When the drive voltage waveform output from the initialization waveform generation circuit 73 reaches the voltage Vers at time t9, the switching element Q16 is turned on and is input to the input terminal INc to operate the second Miller integration circuit 76. The current is drawn to the switching element Q16, and the second Miller integrating circuit 76 stops operating.

  As described above, after the voltage applied to the scan electrodes Y1 to Yn reaches the voltage Vers, if the voltage is maintained, an abnormal discharge may be generated that induces an erroneous discharge in the subsequent address period. However, in this embodiment, since the voltage applied to the scan electrodes Y1 to Yn reaches the voltage Vers and immediately drops to 0 (V), which is the base potential, the occurrence of this abnormal discharge is prevented. can do.

  Then, after time t10, which is the initialization period of the next subfield, the initialization operation of the subsequent subfield, for example, if the subsequent subfield is a selective initialization subfield, the down ramp waveform is applied to the scan electrodes Y1 to Yn. A voltage is applied, and a voltage Ve1 is applied to the sustain electrodes to start a selective initialization operation.

  Next, details of the drive voltage waveform in the initialization period will be described. FIG. 17 is a timing chart for explaining an example of the operation of scan electrode driving circuit 24 in the all-cell initializing period in the embodiment of the present invention. In the drawing, the drive waveform during the all-cell initialization operation is described as an example, but the down-ramp waveform voltage can be generated by the same control in the selective initialization operation.

  In FIG. 17, the drive voltage waveform for performing the all-cell initialization operation is divided into five periods indicated by periods T10 to T14, and each period will be described. In the following description, it is assumed that the voltages Vi1 and Vi3 are equal to the voltage Vs, the voltage Vi2 is equal to the voltage Vr, and the voltage Vi4 is equal to a voltage (Va + Vset2) obtained by superimposing the voltage Vset2 on the negative voltage Va. In the drawing, the input signals CEL1 and CEL2 to the AND gate AG are similarly expressed as “Hi” and “0” as “Lo”.

  In FIG. 17, in order to show the difference between the generation of the erasing ramp waveform voltage and the generation of the rising ramp waveform voltage, the operations in the periods T8 to T9 for generating the erasing ramp waveform voltage are also shown.

  Here, in order to change the voltage Vi4 to a voltage (Va + Vset2) obtained by superimposing the voltage Vset2 on the negative voltage Va, the switching signal CEL2 is maintained at “1” in the periods T10 to T14. Although not shown, the switching element Q21 is kept off during the periods T10 to T14. Although not shown, a signal having a reverse polarity to the signal input to the input terminal INa is input to the switching element Q12 constituting the separation circuit, and the input terminal is connected to the switching element Q13 constituting the separation circuit. A signal having a polarity opposite to that of the signal input to INb is input.

(Period T8)
In the period T8, the input terminal INc is set to “Hi”. As a result, a constant current flows from the resistor R12 toward the capacitor C11, the source voltage of the switching element Q15 rises in a ramp shape, and the output voltage of the scan electrode drive circuit 24 has a steeper slope than the up-ramp waveform voltage. It begins to rise like a ramp.

(Period T9)
When the drive voltage waveform output from the initialization waveform generating circuit 73 reaches the voltage Vers, the switching element Q16 is turned on, and the current input to the input terminal INc for operating the second Miller integrating circuit 76 is the switching element. Pulled out by Q16, the second Miller integrating circuit 76 stops its operation.

  Thus, the erase ramp waveform voltage, which is the second ramp waveform voltage rising from 0 (V) as the base potential toward the voltage Vers, is generated.

(Period T10)
Then, switching element Q1 of sustain pulse generating circuit 70 is turned on. Then, the interelectrode capacitance Cp and the inductor L1 resonate, and the voltage of the scan electrodes Y1 to Yn starts to rise from the power recovery capacitor C1 through the switching element Q1, the diode D1, and the inductor L1.

(Period T11)
Next, switching element Q3 of sustain pulse generating circuit 70 is turned on. Then, voltage Vs is applied to scan electrodes Y1 to Yn via switching element Q3 and switching element Q12, and the potential of scan electrodes Y1 to Yn becomes voltage Vs (equal to voltage Vi1 in the present embodiment).

(Period T12)
Next, the input terminal INa of the Miller integrating circuit that generates the up-ramp waveform voltage is set to “Hi”. Specifically, for example, a voltage of 15 (V) is applied to the input terminal INa. Then, a constant current flows from the resistor R10 toward the capacitor C10, the source voltage of the switching element Q11 increases in a ramp shape, and the output voltage of the scan electrode driving circuit 24 also starts to increase in a ramp shape. This voltage increase continues while the input terminal INa is “Hi”.

  When this output voltage rises to the voltage Vr (equal to the voltage Vi2 in this embodiment), the input terminal INa is then set to “Lo”. Specifically, for example, a voltage of 0 (V) is applied to the input terminal INa.

  In this way, the voltage Vs (equal to the voltage Vi1 in the present embodiment) that is equal to or lower than the discharge start voltage gradually decreases toward the voltage Vr (equal to the voltage Vi2 in the present embodiment) that exceeds the discharge start voltage. An up-ramp waveform voltage that rises to 1 is applied to the scan electrodes Y1 to Yn.

(Period T13)
When the input terminal INa is set to “Lo”, the voltages of the scan electrodes Y1 to Yn are reduced to the voltage Vs (equal to the voltage Vi3 in this embodiment). Thereafter, the switching element Q3 is turned off.

(Period T14)
Next, the input terminal INb of the Miller integrating circuit that generates the down-ramp waveform voltage is set to “Hi”. Specifically, for example, a voltage of 15 (V) is applied to the input terminal INb. Then, a constant current flows from the resistor R11 toward the capacitor C12, the drain voltage of the switching element Q14 decreases in a ramp shape, and the output voltage of the scan electrode driving circuit 24 also starts decreasing in a ramp shape. Then, immediately before the initialization period ends, the input terminal INb is set to “Lo”. Specifically, for example, a voltage of 0 (V) is applied to the input terminal INb.

  In the period T14, the switching element Q13 is turned off, but the Miller integrating circuit that generates the down-ramp waveform voltage can lower the output voltage of the scan electrode driving circuit 24 via the body diode of the switching element Q13.

  In the comparator CP, the down-ramp waveform voltage is compared with the voltage (Va + Vset2) obtained by adding the voltage Vset2 to the voltage Va. The output signal from the comparator CP has the down-ramp waveform voltage equal to the voltage ( Va + Vset2) At time t14 when the time becomes equal to or less than “0”, “0” is switched to “1”. Since the switching signal CEL2 is “1”, the inputs of the AND gate AG are both “1”, and “1” is output from the AND gate AG, and the scan pulse generation circuit 74 outputs the negative voltage Va. A voltage Vc in which the voltage Vscn is superimposed on is output. Accordingly, the scan pulse generation circuit 74 outputs a down-ramp waveform voltage obtained by setting the voltage Vi4 to the voltage (Va + Vset2).

  As described above, the scan electrode driving circuit 24 generates the up-ramp waveform voltage that is the first ramp waveform voltage that gradually increases from the voltage Vi1 that is equal to or lower than the discharge start voltage toward the voltage Vi2 that exceeds the discharge start voltage. And applied to the scan electrodes Y1 to Yn, and then a down-ramp waveform voltage that gently falls from the voltage Vi3 toward the voltage Vi4 is applied.

  Although not shown, the switching element Q21 is kept on in the subsequent writing period after the end of the initialization period. As a result, the voltage input to one terminal of the comparator CP becomes the negative voltage Va, and the output signal CEL1 from the comparator CP is maintained at “1”. As a result, the output from the AND gate AG is maintained at “1”, and the scan pulse generation circuit 74 outputs the voltage Vc in which the voltage Vscn is superimposed on the negative voltage Va. Then, by setting the switching signal CEL2 to “0” at the timing of generating the negative scan pulse voltage, the output signal of the AND gate AG becomes “0”, and the scan pulse generation circuit 74 outputs the negative voltage Va. The In this way, a negative scanning pulse voltage in the address period can be generated.

  In this embodiment, when the voltage applied to the scan electrodes Y1 to Yn reaches a predetermined voltage Vers at the end of the sustain period, the voltage is immediately lowered to 0 (V) as the base potential. In this configuration, after reaching Vers, the potential is held for a certain period and then lowered to 0 (V).

  FIG. 18 is a waveform diagram showing an outline of the sustain pulse waveform in the embodiment of the present invention.

  In the embodiment, the sustain pulses having different waveform shapes are generated by switching. However, each sustain pulse controls the switching timing of each switching element of sustain pulse generating circuit 70 and sustain pulse generating circuit 80. Thus, the drive time of each power recovery circuit and each voltage clamp circuit is merely generated. In FIG. 18, the ground potential is denoted as “GND”.

  As shown in FIG. 18, in the present embodiment, sustain pulses having different waveform shapes, that is, a first sustain pulse serving as a reference, a second sustain pulse whose rise is steeper than the first sustain pulse, The third sustain pulse, which makes the rise more gradual than the one sustain pulse, is switched and generated.

  Specifically, the first sustain pulse as a reference sustain pulse is generated with a pulse width of about 2.7 μsec, a rising period length of about 1200 nsec, and a falling period length of about 1200 nsec. Let Further, in the second sustain pulse, the length of the rising period is about 900 nsec shorter than that of the first sustain pulse, the rise is made steeper than the first sustain pulse, and the pulse width is equal to that of the first sustain pulse. It is generated at about 2.7 μsec. Further, the third sustain pulse is generated with the length of the rising period being about 1300 nsec, which is slightly longer than the first sustain pulse, and the pulse width being about 2.7 μsec, which is the same as the first sustain pulse. Here, the length of the rising period of the sustain pulse is defined as the rising time, and the length of the falling period of the sustain pulse is defined as the falling time.

  Note that the resonance cycle of LC resonance between the inductor L1 of the power recovery circuit 71 and the interelectrode capacitance Cp of the panel 21 and the resonance cycle of LC resonance between the inductor L30 of the power recovery circuit 81 and the interelectrode capacitance Cp are the inductor L1. If the inductance of the inductor L30 is L, it can be obtained by the calculation formula “2π√ (LCp)”. In this embodiment, the inductor L1 and the inductor L30 are set so that the resonance period in the power recovery circuit 71 and the power recovery circuit 81 is about 1250 nsec. The resonance period is also referred to as resonance time.

  FIG. 19 is a schematic diagram showing a state of the sustain pulse in which the rising period is fixed at the start of the sustain period in the embodiment of the present invention. In the present embodiment, in the sustain period, the first sustain pulse and the second sustain pulse serving as a reference are switched and generated and applied to the display electrode 7. Specifically, as shown in FIG. 19, the second sustain pulse is generated at the start of the sustain period and applied to the scan electrodes Y1 to Yn and the sustain electrodes X1 to Xn which are display electrodes.

  In this embodiment, with such a configuration, it is possible to stably generate a sustain discharge. This is due to the following reason.

  Since the wall charge formed in the sustain period depends on the intensity of the sustain discharge, when a weak sustain discharge occurs, the wall charge formed in the discharge cell also remains insufficient. Alternatively, if the sustain discharge has a variation for each discharge cell, the wall charge also varies for each discharge cell. One of the causes of the occurrence of the sustain discharge with insufficient discharge intensity and the variation of the sustain discharge for each discharge cell is as follows.

  Since the lighting / non-lighting of the discharge cells varies depending on the display image, the driving load for each display electrode 7 varies depending on the display image. For this reason, variations occur in the rising waveform of the sustain pulse, which may cause variations in the timing (discharge start time) at which discharge occurs between the discharge cells.

  Further, in a panel in which the xenon partial pressure is increased in order to improve the light emission efficiency, the discharge start voltage between the display electrodes 7 is also increased, and therefore, the variation in timing at which discharge occurs tends to be further increased.

  At this time, if there is a difference in the timing at which discharge occurs between adjacent discharge cells, the discharge cells where the discharge occurred earlier and the discharge cells where the discharge occurred later may have different discharge intensities. This was initiated once, for example, due to the influence of the discharge cell that discharges first, and the wall charge of the discharge cell that is discharged later decreases and the discharge becomes weak, or it is affected by the discharge of the adjacent discharge cell. This is because the discharge is temporarily stopped and the discharge is weakened because the discharge is generated again by the increase of the applied voltage.

  Thus, when a discharge cell with a weakened discharge occurs due to variations in sustain discharge among discharge cells, wall charges formed in the discharge cell remain insufficient. In particular, at the start of the sustain period, the sustain discharge varies greatly from discharge cell to discharge cell, and a discharge cell with a weakened discharge is generated, and the wall charges formed in such a discharge cell are further insufficient.

  It is desirable to make the discharge intensity of the sustain discharge uniform so as not to cause variations among discharge cells, and to make the wall charges formed in the sustain discharge as uniform as possible.To achieve this, the sustain discharge is performed with a sharp voltage change. It is effective to make it occur. This is because if discharge is generated in a state where the voltage change is steep, the variation in the discharge start voltage is absorbed, and the variation in the timing at which discharge occurs between the discharge cells can be reduced. Further, since the sustain discharge generated in a state where the voltage change is steep becomes a strong discharge, it not only reduces the variation in the timing at which the discharge occurs, but also has a function of forming sufficient wall charges in the discharge cells.

  Therefore, by generating a sustain pulse with a steep rise, a sustain discharge can be generated in a state where the change in the voltage applied to the display electrode 7 is steep. The timing at which the discharge occurs can be made uniform.

  That is, at the beginning of the sustain period, the sustain discharge is generated by the second sustain pulse whose rise is steeper than the first sustain pulse as a reference, so that the wall charge necessary in the discharge cell is changed for each discharge cell. The wall charges can be formed with reduced variations.

  In order to investigate the relationship between the rise time of the sustain pulse and the Vs voltage necessary for the sustain discharge, the present inventors first show the result of measuring the Vs voltage while changing the rise time of the sustain pulse. The horizontal axis of FIG. 20 shows the ratio of the rise time of the sustain pulse to the resonance time, and represents how much the rise time is changed with respect to the resonance time, with 0% when the rise time is equal to the resonance time. ing. The vertical axis represents the Vs voltage at which the sustain discharge is stabilized. As shown in FIG. 20, when the rise time is shortened, the Vs voltage necessary for the sustain discharge becomes stable, and conversely, when the rise time is lengthened, the sustain discharge starts from the time when the rise time approaches the resonance time. It has been experimentally confirmed that the Vs voltage required for the increase is high.

  Next, FIG. 21 shows the result of measuring the Vs voltage necessary for stable sustain discharge when the second sustain pulse is continuously applied from the beginning of the sustain period in panel 21 according to the embodiment of the present invention. It is. The horizontal axis of FIG. 21 represents the number of sustain pulses applied to the display electrode 7 continuously from the beginning of the sustain period, and the vertical axis represents the Vs voltage at which the sustain discharge is stabilized. From this experiment, it was found that the sustain discharge can be stably performed without increasing the Vs voltage by increasing the number of the second sustain pulses having a steep rising edge applied continuously.

  Increasing the number of continuous application of sustain pulses with sharp rises increases the afterimage phenomenon (when a scene is switched after displaying a still image etc. for a long time, the still image immediately before that is recognized as an afterimage) ) Worsened. It is desirable to set the number of continuous application of the sustain pulse with a steep rise in a range in which the above-described effect can be sufficiently obtained without deteriorating the afterimage phenomenon. In the present embodiment, the number is continuously set to 2 to 10 times. It is desirable to set. Furthermore, it is desirable to set according to the total number of sustain pulses in the sustain period.

  Next, a configuration in which the second sustain pulse is continuously applied from the second start of the sustain period will be described. In the sustain period, the first sustain pulse applied to the display electrode 7 is referred to as the first sustain pulse, and the Nth sustain pulse applied to the display electrode 7 is referred to as the sustain Nth pulse. The discharge at the first sustaining applied at the beginning of the sustaining period has the largest variation and is difficult to stabilize during the sustaining period. In order to suppress the variation in the discharge, for example, the pulse width of the first sustaining pulse is widened to increase the discharge stability. At this time, if the rising edge of the first sustaining pulse is steep, the sustaining current flowing through the scan electrode driving IC increases. Flow, spec over. Therefore, by generating the second sustain pulse from the second sustain pulse, the sustain current flowing through the scan electrode driving IC can be suppressed and the sustain discharge can be stably generated.

  Further, a configuration in which the second sustain pulse is continuously applied from the third maintenance pulse excluding the first maintenance and second maintenance pulses in the sustain period will be described. As described above, the reason for the first sustain pulse is to suppress the sustain current flowing through the scan electrode driving IC, but the second sustain pulse is also used for the second sustain pulse to increase the discharge stability for the same reason. When the width is widened, if the rise is steep, the sustain current flowing through the scan electrode driving IC will flow greatly. Therefore, by generating the second sustain pulse from the third sustain pulse, the sustain current flowing through the scan electrode driving IC is generated. The current can be suppressed and the sustain discharge can be generated stably.

  As described above, according to the present embodiment, the sustain discharge can be stably generated by continuously applying the sustain pulse with a steep rise at the start of the sustain period in which the sustain discharge is difficult to stabilize. Even in panels with larger screens and higher definition, sustain discharge can be generated stably without increasing the voltage necessary to generate sustain discharge, and image display quality can be improved. It becomes possible.

  In the present embodiment, the configuration in which the second sustain pulse is generated regardless of the total number of sustain pulses has been described. However, this is merely an example. For example, the total number of sustain pulses is 70 or more. In the sustain period, the second sustain pulse may be generated continuously eight times, and in the sustain period where the total number of sustain pulses is less than 70, the second sustain pulse may be generated four times continuously. A threshold value of the total number of sustain pulses for changing the number of continuous occurrences of the second sustain pulse, such as changing the number of continuous occurrences of the second sustain pulse between the sustain period of 50 or more and the sustain period of less than 50 , It may be changed to other numerical values. Alternatively, the number of consecutive occurrences of the second sustain pulse may be changed to another numerical value, such as switching between the number of consecutive occurrences of the second sustain pulse between 6 and 10. Or it is good also as a structure which switches the continuous generation frequency of a 2nd sustain pulse by 3 or more different numerical values, such as switching the continuous generation frequency of a 2nd sustain pulse between 2 times, 6 times, and 8 times. These specific numerical values may be set optimally according to the specifications of the plasma display device, the characteristics of the panel, and the like.

  This “total number of sustain pulses” is not the total number of sustain pulses in one field period, but the total number of sustain pulses in the sustain period of each subfield (total number excluding the erase ramp waveform).

  Further, in the present embodiment, the configuration in which the second sustain pulse is continuously applied in the predetermined subfield has been described. However, this is merely an example, and for example, the first first reference pulse is used. It is not applied to a subfield composed of sustain pulses, and is composed of a sustain period of a subfield using a recovery time longer than the resonance time, that is, a third sustain pulse, in which the Vs voltage required for stable sustain discharge is higher. A configuration in which the second sustain pulse is continuously applied only to the subfields that have been performed may be employed. The recovery time is a time during which power recovery is performed by the power recovery circuits 71 and 81, and is the same as the rise time or the fall time of the sustain pulse.

  In the present embodiment, the rise time of the second sustain pulse is fixed at 900 nsec. However, this is just an example, and if the sustain discharge is generated stably, For example, it may be configured to be fixed at the minimum value of the usage recovery time of other maintenance periods, or may be configured to be fixed at a time shorter than the average recovery time of the usage recovery times of other maintenance periods. Further, it may be configured to be fixed within a certain ratio with respect to the resonance time (90% or less of the resonance time).

  In addition, when the rising time of the second sustain pulse was fixed at a rising time shorter than 900 nsec, the same result was obtained even in a configuration in which the number of times of continuous application was reduced. Further, when the rising time of the second sustain pulse is fixed at a slower rising time than 900 nsec, the same result was obtained even in the configuration in which the number of times of continuous application is increased.

  In the embodiment of the present invention, the scan electrode drive circuit 24 and the sustain electrode drive circuit 25 shown in FIGS. 14 and 15 are merely examples of the configuration, and the same operation can be realized. Any circuit configuration may be used as long as it is present. For example, the circuit that applies the voltage Ve1 and the voltage Ve2 is not limited to the circuit shown in FIG. 15, and for example, a power source that generates the voltage Ve1 and a power source that generates the voltage Ve2 and the respective voltages are maintained electrodes. A plurality of switching elements for applying to X1 to Xn may be used to apply each voltage to sustain electrodes X1 to Xn at a necessary timing. Further, the circuit for generating the erase ramp waveform voltage shown in FIG. 14 is merely a configuration example, and can be replaced with another circuit capable of realizing the same operation.

  In the embodiment of the present invention, the scan electrodes Y1 to Yn are divided into a first scan electrode group and a second scan electrode group, and an address period is set for each of the scan electrodes belonging to the first scan electrode group. The first address period in which the scan pulse is sequentially applied to the first scan period and the second address period in which the scan pulse is sequentially applied to each of the scan electrodes belonging to the second scan electrode group. In at least one of the two address periods, the scan electrodes belonging to the scan electrode group to which the scan pulse is applied are scanned from the second voltage higher than the scan pulse voltage to the scan pulse voltage and again to the second voltage. For the scan electrodes belonging to the scan electrode group to which the pulse is sequentially applied and the scan pulse is not applied, either the third voltage higher than the scan pulse voltage, the second voltage, or the fourth voltage higher than the third voltage. Kanden Can be applied to a panel driving method by so-called two-phase driving in which a third voltage is applied at least while a scanning pulse voltage is applied to adjacent scanning electrodes. Can be obtained.

  In the embodiment of the present invention, the configuration in which the erase ramp waveform voltage is applied to the scan electrodes Y1 to Yn has been described. However, when the last sustain pulse is applied to the scan electrodes Y1 to Yn, the erase lamp is applied. A waveform voltage may be applied to the sustain electrodes X1 to Xn. However, in the embodiment of the present invention, it is desirable to adopt a configuration in which the electrode to which the last sustain pulse is applied is the sustain electrodes X1 to Xn, and the erase ramp waveform voltage is applied to the scan electrodes Y1 to Yn.

  In the embodiment of the present invention, in the power recovery circuits 71 and 81, the configuration in which one inductor is commonly used for the rise and fall of the sustain pulse has been described. However, the rise of the sustain pulse is performed using a plurality of inductors. Alternatively, different inductors may be used for the falling and falling edges. In this case, the configuration in which the inductor is set so that the resonance period is about 1250 nsec in the power recovery circuit 71 and the power recovery circuit 81 described above is applied to the inductor used for the falling. Further, the inductor used for the rising may be set to have a resonance period different from the falling, for example, about 1200 nsec.

  The scan electrodes and sustain electrodes of the plasma display panel described in the present embodiment are made of conductive electrodes that do not use transparent electrodes, compared to scan electrodes and sustain electrodes that use transparent electrodes. Some have low resistance values and are 30-40% lower. As the resistance value decreases as described above, the discharge current tends to flow and the discharge variation tends to increase. Therefore, the present invention is particularly useful for a plasma display panel including conductive electrodes that do not use transparent electrodes. It is.

  The specific numerical values shown in the embodiment of the present invention are set based on the characteristics of a 42-inch panel with 1080 display electrodes 7 used in the experiment. This is just an example. Embodiments of the present invention are not limited to these numerical values, and are desirably set to optimum values in accordance with panel characteristics, plasma display device specifications, and the like. Each of these numerical values is allowed to vary within a range where the above-described effect can be obtained.

  Since the present invention can suppress unstable discharge variation at the start of the sustain period and stabilize the sustain discharge, it is possible to perform high-quality image display, and as a plasma display device with good image display quality. Useful.

1 is an exploded perspective view showing a plasma display panel according to an embodiment of the present invention. Sectional drawing which shows the structure of the discharge cell part of the panel Electrode arrangement of the panel The top view which shows the arrangement | positioning relationship between the scanning electrode which comprises the display electrode of the panel, a sustain electrode, a data electrode, and a partition A plan view showing a configuration example of scan electrodes and sustain electrodes of the panel An explanatory diagram schematically showing a configuration example of the scan electrode and the sustain electrode of the panel, and a front plate and a back plate of the discharge cell portion. Explanatory drawing which expands and shows typically the front board and back board by other examples of the discharge cell part of the panel The top view which shows schematic structure of the whole panel of the panel The top view which shows the example of arrangement | positioning of the dummy electrode pattern of the panel The top view which shows schematic structure of the non-display area | region of the edge part of the panel The top view which shows schematic structure of the termination | terminus part of the scanning electrode and sustain electrode of the panel Drive voltage waveform diagram applied to each electrode of the panel Circuit block diagram of plasma display device in accordance with exemplary embodiment of the present invention Circuit diagram of scan electrode driving circuit in an embodiment of the present invention Circuit diagram of sustain electrode driving circuit according to an embodiment of the present invention Timing chart for explaining an example of operation of scan electrode drive circuit and sustain electrode drive circuit in the embodiment of the present invention Timing chart for explaining an example of the operation of the scan electrode driving circuit in the all-cell initializing period in the embodiment of the present invention Waveform diagram showing an outline of the sustain pulse waveform in the embodiment of the present invention Schematic showing the state of the sustain pulse generated at the start of the sustain period in the embodiment of the present invention The figure which showed the voltage required for the stable sustain discharge in embodiment of this invention The figure which showed the voltage required for the continuous application frequency of the pulse which made the rising period steep in embodiment of this invention, and the stable sustain discharge

DESCRIPTION OF SYMBOLS 1 Front plate 1a, 13c Raised part 2 Back plate 3 Discharge space 4, 10 Substrate 5 Scan electrode 5a, 6a Lower layer 5b, 6b Upper layer 6 Sustain electrode 7 Display electrode 8 Dielectric layer 9 Protective film 11 Insulator layer 12 Data electrode 13 Partition 14R, 14G, 14B Phosphor layer 15 Discharge cell 17 Display area 18 Non-display area 19 Dummy electrode pattern 20 Wiring pattern 21 Panel 22 Image signal processing circuit 23 Data electrode drive circuit 24 Scan electrode drive circuit 25 Sustain electrode drive circuit 26 Timing Generation circuit 30 Plasma display device 51, 61 First part 52, 62 Second part 53, 63 Third part 54, 64 Fourth part 70, 80 Sustain pulse generation circuit 71, 81 Power recovery circuit 72, 82 Clamp circuit 73 Initial Waveform generation circuit 74 scan pulse generation circuit 75 first Miller integrating circuit 76 the second Miller integrating circuit 77 a third Miller integrating circuit

Claims (8)

A plasma display panel having a plurality of discharge cells each having a display electrode including a scan electrode and a sustain electrode, and a driving circuit for the plasma display panel, wherein the discharge is performed in the address period of a subfield having an address period and a sustain period. Plasma display apparatus for generating address discharge selectively in a cell, and generating sustain discharge in a discharge cell in which the address discharge is generated by applying a number of sustain pulses corresponding to luminance weight to the display electrode in the sustain period The sustain pulse rises and falls by LC resonance between the interelectrode capacitance of the plasma display panel and the inductor, and the first sustain pulse has at least a predetermined rise time in the sustain period of at least one subfield. Than the predetermined rise time And applying a second sustain pulse having a high rise time, and driving the plasma display panel so that the second sustain pulse is included in a period from the start of the sustain period to the middle of the sustain period. A characteristic plasma display device. At least in the sustain period of the subfield including a sustain pulse having a rise time longer than the resonance time of the LC resonance, the second sustain pulse is included in a period from the start of the sustain period to the middle of the sustain period. 2. The plasma display device according to claim 1, wherein the plasma display panel is driven. The plasma display apparatus of claim 1, wherein a rising time of the second sustain pulse is shorter than an average value of rising times of the sustain pulses included in the sustain period. The plasma display apparatus of claim 1, wherein a rising time of the second sustain pulse is shorter than a resonance time of the LC resonance. The plasma display apparatus as claimed in claim 4, wherein a rising time of the second sustain pulse is 90% or less of a resonance time of the LC resonance. 2. The plasma display apparatus according to claim 1, wherein the second sustain pulse is not used as a sustain pulse applied to the display electrode at the beginning of the sustain period. 2. The plasma display apparatus according to claim 1, wherein the second sustain pulse is not used as a sustain pulse to be applied to the display electrode in the first and second sustain periods. The plasma display panel includes a front plate in which a conductive scan electrode and a sustain electrode are disposed on a substrate to form a display electrode by disposing a discharge gap therebetween, and a plurality of display electrodes are arranged in a row direction. A back plate provided with a discharge space between the front plates and arranged opposite to each other and forming a plurality of data electrodes in a column direction intersecting with the display electrodes and providing discharge cells at intersections, The plasma display device according to any one of claims 1 to 7, wherein the display electrode is configured such that brightness of the scan electrode and the sustain electrode is low when viewed from the display surface on the substrate side.

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