JP2010175770A - Plasma display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve display quality and luminous efficiency in a plasma display panel. <P>SOLUTION: A plasma display device has a plasma display panel which is provided with a plurality of discharge cells having a display electrode pair composed of a scan electrode and a sustain electrode, and a sustaining pulse generating circuit which applies a sustaining pulse to each of the display electrode pair using a power recovery circuit which causes rising or falling edge of the sustaining pulse by resonating inter-electrode capacitance and inductor of the display electrode pair and a clamp circuit which clamps a voltage of the sustaining pulse to a power source voltage or base potential. The sustaining pulse generating circuit generates sustaining pulses, wherein a time point of starting of a rising edge of the sustaining pulse applied to one electrode of the display electrode pair and a time point of starting of falling edge of the sustaining pulse applied to another electrode coincide each other, and the time of rising of the sustaining pulse applied to one electrode of the display electrode pair, and the time of the falling of edge of the sustaining pulse applied to another electrode are different. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a plasma display device used for a wall-mounted television or a large monitor.

  A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front plate and a back plate arranged to face each other. In the front plate, a plurality of display electrode pairs each consisting of a pair of scan electrodes and sustain electrodes are formed in parallel with each other on the front glass substrate, and a dielectric layer and a protective layer are formed so as to cover the display electrode pairs. Yes. The back plate has a plurality of parallel data electrodes on the back glass substrate, a dielectric layer so as to cover them, and a plurality of barrier ribs in parallel with the data electrodes formed on the back glass substrate. A phosphor layer is formed on the side walls of the barrier ribs. Then, the front plate and the back plate are arranged opposite to each other so that the display electrode pair and the data electrode are three-dimensionally crossed and sealed, and a discharge gas containing, for example, 5% xenon is enclosed in the internal discharge space. Has been. Here, a discharge cell is formed at a portion where the display electrode pair and the data electrode face each other. In the panel having such a configuration, ultraviolet rays are generated by gas discharge in each discharge cell, and the phosphors of red (R), green (G) and blue (B) colors are excited and emitted by the ultraviolet rays, thereby performing color display. It is carried out.

  As a method of driving the panel, a subfield method, that is, a method of performing gradation display by combining subfields to emit light after dividing one field period into a plurality of subfields is generally used.

  Each subfield has an initialization period, an address period, and a sustain period. In the initializing period, initializing discharge is generated, and wall charges necessary for the subsequent address operation are formed on each electrode. In the address period, an address pulse voltage is selectively applied to the discharge cells to be displayed to generate an address discharge to form wall charges. In the sustain period, a sustain pulse voltage is alternately applied to the display electrode pair composed of the scan electrode and the sustain electrode, and a sustain discharge is generated in the discharge cell that has caused the address discharge, and the phosphor layer of the corresponding discharge cell emits light. To display an image.

In an electrode drive circuit for applying a sustain pulse to a display electrode pair, a power recovery circuit is provided on each of the scan electrode side and the sustain electrode side. For example, Patent Document 1 discloses a scan electrode and a sustain electrode. A sustain pulse is applied to the display electrode pair by collecting the charge charged in the panel between the electrodes via the power recovery circuit (so-called self-recovery), thereby making one power recovery circuit. It is disclosed that the cost can be reduced by using a circuit configuration.
JP 2001-272945 A

  FIG. 14 shows a sustain pulse waveform when a sustain pulse is applied to the display electrode pair by self-recovering the charge charged in the panel between the scan electrode and the sustain electrode via the power recovery circuit. Is. Since the self-recovery is performed, the rising start time of the sustain electrode voltage (sustain electrode voltage) and the falling start time of the scan electrode voltage (scan electrode voltage) are the same time (time t1), and the scan electrode voltage rises. The start time and the falling start time of the sustain electrode voltage are the same time (time t3). The time when the sustain electrode voltage is clamped to the predetermined voltage Vs and the time when the scan electrode voltage is clamped to the ground potential (0 V) are the same time (time t2), and the scan electrode voltage is clamped to the predetermined voltage Vs. The time and the time when the sustain electrode voltage is clamped to the ground potential are the same time (time t4). That is, the rising period of the sustain pulse applied to the sustain electrode (period in which the ground potential is changed to the predetermined voltage Vs) and the falling period of the sustain pulse applied to the scan electrode (period in which the predetermined voltage Vs is changed to the ground potential). Are exactly overlapped in time, and the rising period of the sustain pulse applied to the scan electrode (period in which the ground potential is changed to the predetermined voltage Vs) and the falling period of the sustain pulse applied to the sustain electrode (from the predetermined voltage Vs to the ground) The period during which the potential changes) overlaps in time.

  In such a case, when the sustain discharge is generated during the rising period of the sustain pulse, the distortion of the sustain pulse waveform increases. Thereby, compared with the case where the rising period of the sustaining pulse applied to one of the sustaining electrode and the scanning electrode is not temporally overlapped with the falling period of the sustaining pulse applied to the other electrode, There are problems that the generation timing of the sustain discharge varies and the display luminance becomes non-uniform so that the display quality is deteriorated and the light emission efficiency of the panel is lowered.

  The present invention has been made to solve these problems, and improves display quality and light emission efficiency when a sustain pulse is applied such that most of the rising and falling periods of the sustain pulse overlap. It is an object of the present invention to provide a plasma display device that can be used.

  The plasma display apparatus of the present invention resonates a plasma display panel having a plurality of discharge cells each having a display electrode pair composed of a scan electrode and a sustain electrode, a capacitance between the electrode of the display electrode pair and an inductor, and generates a sustain pulse. A power recovery circuit that rises or falls and a sustain pulse generation circuit that applies a sustain pulse to each of the display electrode pairs using a clamp circuit that clamps the sustain pulse voltage to a power supply voltage or a base potential, and The sustain pulse generating circuit generates a sustain pulse in which a sustain pulse rising start time applied to one electrode of the display electrode pair coincides with a sustain pulse falling start time applied to the other electrode, and the display electrode Rise time of sustain pulse applied to one electrode of the pair and sustain applied to the other electrode Luz fall time and are different from each other.

  ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to provide the plasma display apparatus which can improve display quality and luminous efficiency.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1)
First, the overall configuration of the plasma display panel according to Embodiment 1 of the present invention will be described with reference to FIGS.

  FIG. 1 is an exploded perspective view showing a state in which a front plate and a back plate are separated from each other in a plasma display panel according to an embodiment of the present invention. FIG. It is sectional drawing which shows a discharge cell structure. As shown in FIGS. 1 and 2, the panel is configured by disposing a glass front plate 1 and a back plate 2 so as to form a discharge space 3 therebetween.

  The front plate 1 has a display electrode 7 in which a scanning electrode 5 as a conductive first electrode and a sustaining electrode 6 as a second electrode are arranged parallel to each other with a discharge gap therebetween on a glass substrate 4. , A plurality of display electrodes 7 are arranged in the row direction, and a dielectric layer 8 made of a glass material is formed so as to cover the scan electrodes 5 and the sustain electrodes 6, and the dielectric layer 8 A protective film 9 made of MgO is formed on the top.

  The scanning electrode 5 and the sustaining electrode 6 are each composed of only a conductive electrode having a film thickness of about 5 μm made of Ag without using a transparent electrode such as ITO, and the scanning electrode 5 and the sustaining electrode 6 are shown in FIG. As shown in FIG. 4, the substrate 4 side lower layer 5a, 6a is made of a material containing a metal oxide having a low blackness and an upper layer 5b. 6b is composed of a white material having an increased Ag content so that the specific resistance is lower than that of the lower layers 5a and 6a, so that the lower layer 5a and 6a on the substrate 4 side has lower brightness than the upper layers 5b and 6b. It is configured. That is, the display electrode 7 composed of the scan electrode 5 and the sustain electrode 6 is configured such that the brightness of the display electrode 7 composed of the scan electrode 5 and the sustain electrode 6 is low when viewed from the display surface on the substrate 4 side. The light shielding member does not exist between the display electrodes 7 of the adjacent discharge cells. Here, the configuration that the brightness is low is, for example, the lowest brightness “between ideal white having a brightness of 10 and ideal black having a brightness of 0, as known as the Munsell brightness. It means that it is configured so as to be close to 1.0 ".

  Further, the back plate 2 is provided with a plurality of data electrodes 12 made of Ag covered with an insulating layer 11 made of a glass material and arranged in a stripe shape in the column direction on a glass substrate 10 and insulated. On the body layer 11, a grid-like partition wall 13 made of a glass material for partitioning the discharge space 3 between the front plate 1 and the back plate 2 for each discharge cell is provided. Further, red (R), green (G), and blue (B) phosphor layers 14R, 14G, and 14B are provided on the surface of the insulator layer 11 and the side surfaces of the partition walls 13. The front plate 1 and the back plate 2 are arranged to face each other so that the scan electrode 5 and the sustain electrode 6 intersect the data electrode 12, and the scan electrode 5, the sustain electrode 6 and the data electrode 12 intersect each other. As shown in FIG. 3, a discharge cell 15 is provided. The discharge space 3 is filled with, for example, a mixed gas of neon and xenon as a discharge gas. Note that the structure of the panel is not limited to the above-described structure, and for example, a structure having a stripe-shaped partition may be used.

  Here, as shown in FIG. 2, the cross-shaped barrier ribs 13 forming the discharge cells 15 include the vertical barrier ribs 13a formed in parallel to the data electrodes 12, and the discharges adjacent to each other in the direction intersecting the vertical barrier ribs 13a. The horizontal barrier ribs 13b are formed so as to be present between the display electrodes 7 of the cell and are formed so as to be lower than the vertical barrier ribs 13a so that a gap is formed between the display electrodes 7. Yes. The phosphor layers 14R, 14G, and 14B formed by coating in the barrier ribs 13 are formed of stripes of blue phosphor layers 14B, red phosphor layers 14R, and green phosphor layers 14G along the vertical barrier ribs 13a. They are arranged in order.

  FIG. 3 is an electrode array diagram of the panel shown in FIGS. N scanning electrodes Y1, Y2, Y3... Yn (5 in FIG. 1) and n sustaining electrodes X1, X2, X3... Xn (6 in FIG. 1) are arranged in a row direction. M data electrodes A1... Am (12 in FIG. 1) that are long in the direction are arranged. Discharge cells 15 are formed at portions where the pair of scan electrodes Y1 and sustain electrodes X1 and one data electrode A1 intersect, and m × n discharge cells 15 are formed in the discharge space. Further, as shown in FIG. 3, the scan electrode Y1 and the sustain electrode X1 are formed on the front plate 1 in a pattern that repeats in the arrangement of the scan electrode Y1, the sustain electrode X1, the sustain electrode X2, the scan electrode Y2,. Has been. Each of these electrodes is connected to a connection terminal provided at a peripheral end portion outside the image display area of the front plate 1 and the back plate 2.

  Next, the configuration of the display electrode 7 of the plasma display panel of the present invention will be described in more detail.

  As described above, in the plasma display panel of the present invention, the scan electrode 5 and the sustain electrode 6 constituting the display electrode 7 of the front plate 1 are not made of a transparent electrode such as ITO, but are made of a conductive material such as Ag. It comprises only the conductive electrode which becomes. FIG. 4 shows a layout diagram of the scan electrodes 5 and the sustain electrodes 6, the data electrodes 12, and the partition walls 13 that constitute the display electrode 7. 5A and 5B show examples of the scan electrode 5 and the sustain electrode 6 for one cell.

  As shown in FIG. 4, the scan electrode 5 and the sustain electrode 6 constituting the display electrode 7 each have a ladder shape, and the first portions 51 and 61 that face each other with the discharge gap MG interposed therebetween. Second portions 52 and 62 arranged in parallel with a space from the portions 51 and 61, and the first portions 51 and 61 and the second portions 52 and 62 are connected to each other and provided for each discharge cell 15. 3 portions 53 and 63. Moreover, in the scan electrode 5 and the sustain electrode 6, when the width of the first portions 51 and 61 and the second portions 52 and 62 is LL and the width of the third portions 53 and 63 is Ls, the top of the partition wall 13 is used. The width Lr is configured such that Lr <Ls ≦ LL. Specifically, the width LL of the first portions 51 and 61 and the second portions 52 and 62 is about 60 μm to about 70 μm, the width Ls of the third portions 53 and 63 is about 60 μm, and the width Lr of the top of the partition wall 13 is It is about 50 μm. Discharge gap MG between scan electrode 5 and sustain electrode 6 is 90 μm to 100 μm, and gap LG between first portions 51 and 61 and second portions 52 and 62 of scan electrode 5 and sustain electrode 6 respectively. Is about 80 μm, and is formed to be smaller than the non-discharge gap IPG (about 200 μm) between the adjacent discharge cells 15.

  Here, in FIG. 5A, in the scan electrode 5 and the sustain electrode 6, the widths of the first portions 51, 61 and the second portions 52, 62 and the widths of the third portions 53, 63 are made the same. FIG. 5B is a diagram showing an example in which Lr <Ls = LL configured to be larger than the width Lr of the top of the partition wall 13, and FIG. 5B illustrates the first portions 51, 61 and the scan electrodes 5 and the sustain electrodes 6. It is a figure which shows the example in the case of Lr <Ls <LL comprised larger than the width | variety Lr of the top part of the partition 13, while making the width | variety of the 2nd parts 52 and 62 larger than the width | variety of the 3rd parts 53 and 63.

  Thus, in the scan electrode 5 and the sustain electrode 6, when the width of the first portions 51, 61 and the second portions 52, 62 is LL, and the width of the third portions 53, 63 is Ls, the width of the top of the partition wall 13. By configuring Lr <Ls ≦ LL with respect to Lr, a panel having a display performance that ensures a sufficient contrast ratio without providing a light shielding member between adjacent discharge cells 15 can be obtained at low cost. It becomes possible. That is, in general, in a plasma display panel, since a glass material having a relatively high brightness is used as a material constituting the partition wall 13, it is sufficient to dispose a light shielding member in a non-discharge gap IPG portion of the adjacent discharge cell 15. A structure that ensures a high contrast ratio is employed. However, as in the present invention, the scan electrode 5 and the sustain electrode 6 constituting the display electrode 7 formed so as to have low brightness when viewed from the display surface side are discharged. The first portions 51 and 61 that face each other with the gap MG therebetween, the second portions 52 and 62 that are arranged in parallel with a space from the first portions 51 and 61, the first portions 51 and 61, and the second portions A third portion 53, 63 connected to each of the discharge cells 15 and connected to the portions 52, 62, and the first portion 51 in the scan electrode 5 and the sustain electrode 6. 61 and the second portions 52 and 62 are configured such that Lr <Ls ≦ LL with respect to the width Lr of the top of the partition wall 13 where LL is the width of the third portions 53 and 63 and Ls is the width of the third portions 53 and 63. As a result, a panel having a display performance with a sufficient contrast ratio can be obtained as in the case where the light shielding member is arranged without arranging the light shielding member in the non-discharge gap IPG portion of the adjacent discharge cell 15. It becomes possible.

  As shown in FIGS. 1 to 5, the scanning electrodes Yi (i = 1 to n) and the sustaining electrodes Xi (i = 1 to n) are formed in parallel with each other, so that scanning is performed. A large interelectrode capacitance Cp exists between the electrode Yi and the sustain electrode Xi.

  Next, a driving voltage waveform for driving the panel and an outline of the operation will be described. The driving method of the plasma display panel in the present embodiment is a subfield method, that is, gradation display by dividing one field period into a plurality of subfields and controlling light emission / non-light emission of each discharge cell for each subfield. I do. Each subfield has an initialization period, an address period, and a sustain period.

  In each subfield, initializing discharge is generated in the initializing period, and necessary wall charges are formed on each electrode in the subsequent address period. In the address period, an address discharge is selectively generated in the discharge cells to emit light in the subsequent sustain period to form wall charges. In the sustain period, a number of sustain pulses proportional to the luminance weight are alternately applied to the display electrode 7 to generate a sustain discharge in the discharge cells that have generated the address discharge to emit light. The proportionality constant at this time is called “luminance magnification”.

  In this embodiment, one field is composed of 10 subfields (first SF, second SF,..., 10th SF), and each subfield is, for example, (1, 2, 3, 6, 11, 18). , 30, 44, 60, 80). By doing so, the luminance level in each discharge cell can be adjusted in a total of 256 steps from 0 to 255.

  FIG. 6 is a drive voltage waveform diagram applied to each electrode of the panel in the first exemplary embodiment of the present invention. FIG. 6 shows drive voltage waveforms of two subfields (first SF and second SF), but drive voltage waveforms in other subfields are substantially the same. In addition, scan electrodes Yi (i = 1 to n), sustain electrodes Xi (i = 1 to n), and data electrodes Ak (k = 1 to m) in the following were selected based on image data. Represents an electrode.

  First, the first SF will be described. In the first half of the initializing period of the first SF, 0 (V) is applied to the data electrodes A1 to Am and the sustain electrodes X1 to Xn, respectively, and the discharge start voltage with respect to the sustain electrodes X1 to Xn is applied to the scan electrodes Y1 to Yn. A first ramp waveform voltage (hereinafter referred to as “up-ramp waveform voltage”) that gradually rises from voltage Vi1 below toward voltage Vi2 that exceeds the discharge start voltage is applied. The slope of this up-ramp waveform voltage is about 1.3 V / μsec.

  While the rising ramp waveform voltage rises, weak initializing discharges are continuously generated between the scan electrodes Y1 to Yn, the sustain electrodes X1 to Xn, and the data electrodes A1 to Am. Negative wall voltage is accumulated on scan electrodes Y1 to Yn, and positive wall voltage is accumulated on data electrodes A1 to Am and sustain electrodes X1 to Xn. The wall voltage above the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

  In the latter half of the initialization period, positive voltage Ve1 is applied to sustain electrodes X1 to Xn, 0 (V) is applied to data electrodes A1 to Am, and sustain electrodes X1 to Xn are applied to scan electrodes Y1 to Yn. In contrast, a ramp waveform voltage (hereinafter referred to as a “down-ramp waveform voltage”) that gently falls from a voltage Vi3 that is equal to or lower than the discharge start voltage to a voltage Vi4 that exceeds the discharge start voltage is applied. During this time, weak initializing discharges are continuously generated between the scan electrodes Y1 to Yn, the sustain electrodes X1 to Xn, and the data electrodes A1 to Am. Then, the negative wall voltage above scan electrodes Y1 to Yn and the positive wall voltage above sustain electrodes X1 to Xn are weakened, and the positive wall voltage above data electrodes A1 to Am is adjusted to a value suitable for the write operation. The Thus, the all-cell initializing operation for performing the initializing discharge on all the discharge cells is completed.

  Note that, as shown in the initialization period of the second SF in FIG. 6, a drive voltage waveform in which the first half of the initialization period is omitted may be applied to each electrode. That is, the voltage Ve1 is applied to the sustain electrodes X1 to Xn, 0 (V) is applied to the data electrodes A1 to Am, and the down-ramp waveform voltage that gradually decreases from the voltage Vi3 ′ to the voltage Vi4 to the scan electrodes Y1 to Yn. Apply. As a result, a weak initializing discharge is generated in the discharge cell that has generated the sustain discharge in the sustain period of the previous subfield, and the wall voltage on the scan electrode Yi and the sustain electrode Xi is weakened. Further, in a discharge cell in which a sufficient positive wall voltage is accumulated on the upper part of the data electrode Ak (k = 1 to m) by the last sustain discharge, an excessive portion of the wall voltage is discharged, and the wall voltage suitable for the address operation. Adjusted to On the other hand, the discharge cells that did not cause the sustain discharge in the previous subfield are not discharged, and the wall charges at the end of the initialization period of the previous subfield are maintained as they are. Thus, the initializing operation in which the first half is omitted is a selective initializing operation in which initializing discharge is performed on the discharge cells in which the sustaining operation has been performed in the sustain period of the immediately preceding subfield.

  In the subsequent address period, first, voltage Ve2 is applied to sustain electrodes X1 to Xn, and voltage Vc is applied to scan electrodes Y1 to Yn. Then, a negative scan pulse voltage Va is applied to the scan electrode Y1 in the first row, and a positive address pulse voltage Vd is applied to the data electrode Ak of the discharge cell to be emitted in the first row among the data electrodes A1 to Am. To do. At this time, the voltage difference at the intersection between the data electrode Ak and the scan electrode Y1 is the difference between the wall voltage on the data electrode Ak and the wall voltage on the scan electrode Y1 due to the difference in the externally applied voltage (Vd−Va). It becomes the sum and exceeds the discharge start voltage. As a result, an address discharge occurs between the data electrode Ak and the scan electrode Y1, and between the sustain electrode X1 and the scan electrode Y1, a positive wall voltage is accumulated on the scan electrode Y1, and a negative voltage is accumulated on the sustain electrode X1. A wall voltage is accumulated, and a negative wall voltage is also accumulated on the data electrode Ak.

  In this manner, an address operation is performed in which an address discharge is caused in the discharge cells to be lit in the first row and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection of the data electrodes A1 to Am and the scan electrode Y1 to which the address pulse voltage Vd is not applied does not exceed the discharge start voltage, so that address discharge does not occur. The above address operation is performed until the discharge cell in the nth row, and the address period ends.

  In the subsequent sustain period, first, a positive sustain pulse voltage Vs is applied to scan electrodes Y1 to Yn, and a ground potential serving as a base potential, that is, 0 (V) is applied to sustain electrodes X1 to Xn. In the discharge cell in which the address discharge has occurred at this time, the voltage difference between the scan electrode Yi and the sustain electrode Xi is the difference between the wall voltage on the scan electrode Yi and the wall voltage on the sustain electrode Xi in the sustain pulse voltage Vs. It becomes the sum and exceeds the discharge start voltage. A sustain discharge occurs between the scan electrode Yi and the sustain electrode Xi, and the phosphor layers 14R, 14G, and 14B emit light by the ultraviolet rays generated at this time. A negative wall voltage is accumulated on scan electrode Yi, and a positive wall voltage is accumulated on sustain electrode Xi. Further, a positive wall voltage is accumulated on the data electrode Ak. In the discharge cells in which no address discharge has occurred during the address period, no sustain discharge occurs, and the wall voltage at the end of the initialization period is maintained.

  Subsequently, 0 (V) as a base potential is applied to scan electrodes Y1 to Yn, and sustain pulse voltage Vs is applied to sustain electrodes X1 to Xn. Then, in the discharge cell in which the sustain discharge has occurred, since the voltage difference between the sustain electrode Xi and the scan electrode Yi exceeds the discharge start voltage, the sustain discharge occurs again between the sustain electrode Xi and the scan electrode Yi, and the sustain electrode A negative wall voltage is accumulated on Xi, and a positive wall voltage is accumulated on scan electrode Yi. In the same manner, writing is performed by applying a number of sustain pulses obtained by alternately multiplying the luminance weight to the luminance magnification to the scan electrodes Y1 to Yn and the sustain electrodes X1 to Xn, and applying a potential difference between the electrodes of the display electrode pair 7. The sustain discharge is continuously performed in the discharge cell that has caused the address discharge in the period.

  At the end of the sustain period, a second ramp waveform voltage (hereinafter referred to as “erase ramp waveform voltage”) that gradually increases from 0 (V) as the base potential toward the voltage Vers is applied to the scan electrodes Y1 to Yn. Applied). As a result, a weak discharge is continuously generated, and some or all of the wall voltages on the scan electrode Yi and the sustain electrode Xi are erased while leaving the positive wall voltage on the data electrode Ak.

  Specifically, after the sustain electrodes X1 to Xn are returned to 0 (V), the erase is the second ramp waveform voltage that rises from 0 (V), which is the base potential, toward the voltage Vers that exceeds the discharge start voltage. The ramp waveform voltage is generated with a steeper gradient than the up-ramp waveform voltage, which is the first ramp waveform voltage, for example, a gradient of about 10 V / μsec, and is applied to the scan electrodes Y1 to Yn. Then, a weak discharge is generated between the sustain electrode Xi and the scan electrode Yi of the discharge cell in which the sustain discharge has occurred. This weak discharge is continuously generated during the period when the applied voltage to the scan electrodes Y1 to Yn increases. Then, after the rising voltage reaches the voltage Vers which is a predetermined potential, the voltage applied to the scan electrodes Y1 to Yn is lowered to 0 (V) as the base potential.

  At this time, the charged particles generated by the weak discharge are always accumulated as wall charges on the sustain electrode Xi and the scan electrode Yi so as to alleviate the voltage difference between the sustain electrode Xi and the scan electrode Yi. It will be done. Thus, the wall voltage between the scan electrodes Y1 to Yn and the sustain electrodes X1 to Xn remains between the voltage applied to the scan electrode Yi and the discharge start voltage while leaving the positive wall charges on the data electrode Ak. The difference is reduced to the extent of (voltage Vers−discharge start voltage). Hereinafter, the last discharge in the sustain period generated by the erase ramp waveform voltage is referred to as “erase discharge”.

  Subsequent subfield operations are substantially the same as those described above except for the number of sustain pulses in the sustain period, and thus description thereof is omitted. The above is the outline of the drive voltage waveform applied to each electrode of the panel in the present embodiment.

  Next, the configuration of the plasma display device in the present embodiment will be described. FIG. 7 is a circuit block diagram of the plasma display device in accordance with the first exemplary embodiment of the present invention. The plasma display apparatus includes a panel 21, image signal processing circuit 71, data electrode drive circuit 72, scan electrode drive circuit 73, sustain electrode drive circuit 74, timing generation circuit 75, and a power supply circuit that supplies power necessary for each circuit block ( (Not shown).

  The image signal processing circuit 71 converts the input image signal sig into image data indicating light emission / non-light emission for each subfield. The data electrode driving circuit 72 converts the image data for each subfield into signals corresponding to the data electrodes A1 to Am, and drives the data electrodes A1 to Am.

  The timing generation circuit 75 generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal H and the vertical synchronization signal V, and supplies them to the respective circuit blocks.

  Scan electrode drive circuit 73 is an initialization waveform generating circuit (not shown) for generating an initialization waveform voltage to be applied to scan electrodes Y1 to Yn in the initialization period, and is applied to scan electrodes Y1 to Yn in the sustain period. A sustain pulse generating circuit 80 for generating a sustain pulse and a scan pulse generating circuit (not shown) for generating a scan pulse voltage to be applied to the scan electrodes Y1 to Yn in an address period are provided, and based on a timing signal. Each scanning electrode Y1-Yn is each driven. Sustain electrode drive circuit 74 includes sustain pulse generation circuit 90 and Ve voltage generation circuit (not shown) for generating voltages Ve1 and Ve2, and drives sustain electrodes X1 to Xn based on a timing signal.

  Next, details and operation of sustain pulse generating circuit 80 and sustain pulse generating circuit 90 will be described. FIG. 8 is a circuit diagram of sustain pulse generation circuit 80 and sustain pulse generation circuit 90 in the first exemplary embodiment of the present invention. In FIG. 8, the interelectrode capacitance of the panel 21 is shown as Cp, and the scan pulse generation circuit, the initialization waveform generation circuit, and the Ve voltage generation circuit are omitted.

  Sustain pulse generation circuit 80 includes a power recovery circuit 81 and a clamp circuit 82. Power recovery circuit 81 and clamp circuit 82 include a scan pulse generation circuit (not shown because it is in a short-circuit state during the sustain period). To the scanning electrodes Y1 to Yn which are one end of the interelectrode capacitance Cp of the panel 21. The power recovery circuit 81 is connected to the clamp circuit 92 of the sustain pulse generation circuit 90.

  The power recovery circuit 81 includes a switching element Q11, a switching element Q12, a backflow prevention diode D11, a backflow prevention diode D12, and a resonance inductor L10. Then, the interelectrode capacitance Cp and the inductor L10 are LC-resonated to cause the sustain pulse to rise and fall. Thus, since the power recovery circuit 81 drives the scan electrodes Y1 to Yn and the sustain electrodes X1 to Xn by LC resonance without being supplied with power from the power supply, the power consumption is ideally zero. The power recovery circuit 81 provided between the scan electrodes Y1 to Yn and the sustain electrodes X1 to Xn recovers the charges charged in the panel (so-called self recovery).

  The clamp circuit 82 includes a switching element Q13 for clamping the scan electrodes Y1 to Yn to the voltage Vs, and a switching element Q14 for clamping the scan electrodes Y1 to Yn to 0 (V). Then, the scanning electrodes Y1 to Yn are connected to the power source VS via the switching element Q13 and clamped to the voltage Vs, and the scanning electrodes Y1 to Yn are grounded and clamped to 0 (V) via the switching element Q14. Therefore, the impedance at the time of voltage application by the clamp circuit 82 is small, and a large discharge current due to strong sustain discharge can flow stably.

  Sustain pulse generation circuit 80 is connected to power recovery circuit 81 by clamping switching element Q11, switching element Q12, switching element Q13, and switching element Q14 in accordance with the timing signal output from timing generation circuit 75. The circuit 82 is operated to generate a sustain pulse waveform. Details of this will be described later. Note that these switching elements can be configured using generally known elements such as MOSFETs and IGBTs.

  Sustain pulse generation circuit 90 operates clamp circuit 92 by switching between conduction and cutoff of switching element Q21 and switching element Q22 according to the timing signal output from timing generation circuit 75, and generates a sustain pulse waveform. Details of this will be described later. Note that these switching elements can be configured using generally known elements such as MOSFETs and IGBTs.

  Note that the period of LC resonance between the inductor L10 of the power recovery circuit 81 and the interelectrode capacitance Cp of the panel 21 (hereinafter referred to as “resonance period”) is expressed by the formula “2π√ (LCp) ". In this embodiment, the inductor L10 is set so that the resonance period in the power recovery circuit 81 is about 2500 nsec. However, this numerical value is only an example in the embodiment, and the characteristics of the panel and the plasma display device are set. What is necessary is just to set to the optimal value according to the specification etc.

  Next, details of the drive voltage waveform in the sustain period will be described. FIG. 9 is a timing chart for explaining operations of sustain pulse generating circuit 80 and sustain pulse generating circuit 90 in the first embodiment of the present invention. Here, one cycle of the sustain pulse repetition cycle (hereinafter abbreviated as “sustain cycle”) is divided into four periods indicated by T1 to T4, and each period will be described.

  In the following description, the operation for conducting the switching element is expressed as ON and the operation for blocking is expressed as OFF. In the drawing, the signal for turning on the switching element is expressed as “ON”, and the signal for turning off is expressed as “OFF”. In FIG. 9, the description is made using the positive electrode waveform, but the present invention is not limited to this. For example, although the embodiment in the negative waveform is omitted, the expression “rising” in the positive waveform in the following description is replaced with “falling” in the negative waveform. The same effect can be obtained even with this waveform.

(Period T1)
At time t1, switching element Q12 is turned on. Then, the charges on the scan electrodes Y1 to Yn side start to flow to the sustain electrode side through the inductor L10, the diode D12, and the switching element Q12. As a result, the voltage on the scan electrodes Y1 to Yn decreases and the voltage on the sustain electrodes X1 to Xn It rises. Since the inductor L10 and the interelectrode capacitance Cp form a resonance circuit, the voltage of the scan electrodes Y1 to Yn decreases to near 0 (V) and the sustain electrode X1 after a half time of the resonance period has elapsed. The voltage of .about.Xn rises to almost the voltage Vs. However, the voltage of the scan electrodes Y1 to Yn does not drop to 0 (V) due to power loss due to the resistance component of the resonance circuit and the like even after lapse of half the resonance period. Similarly, the voltage of the sustain electrodes X1 to Xn does not increase up to Vs. In the present embodiment, switching element Q14 is turned on at time t2a that is earlier than time t2 by a predetermined time. Then, since the scan electrodes Y1 to Yn are directly grounded through the switching element Q14, the voltages of the scan electrodes Y1 to Yn are clamped to 0 (V) which is the ground potential.

(Period T2)
Subsequently, at time t2, switching element Q21 is turned on. Since sustain electrodes X1 to Xn are directly connected to power supply Vs through switching element Q21, the voltage of sustain electrodes X1 to Xn is clamped to voltage Vs and forcibly rises to voltage Vs. As a result, in the discharge cell in which the address discharge has occurred, the voltage between the scan electrode Yi and the sustain electrode Xi exceeds the discharge start voltage, and a sustain discharge occurs. Since the resonance period of the inductor L10 and the interelectrode capacitance Cp is set to about 2500 nsec, after about 1250 nsec from the time t1, the voltage of the scan electrodes Y1 to Yn drops to near the ground potential 0 (V), and the sustain electrode The voltages X1 to Xn rise to almost the voltage Vs. However, since the length of the period T11 from time t1 to time t2a, that is, the falling period of the sustain pulse using the power recovery circuit 81 is set to 800 nsec or 900 nsec, the scan electrodes Y1 to Yn at time t2a The voltage is clamped to the ground potential of 0 (V). Further, since the length of the period T1 from time t1 to time t2, that is, the rising period of the sustain pulse using the power recovery circuit 81 is set to 1000 nsec or 1100 nsec, the voltages of the sustain electrodes X1 to Xn at time t2. Is clamped to voltage Vs and forcibly rises to voltage Vs.

  In the period T2, the voltages of the sustain electrodes X1 to Xn are maintained at the voltage Vs, and the voltages of the scan electrodes Y1 to Yn are maintained at 0 (V). The period T2 is maintained for a sufficient time (in this embodiment, approximately 1300 to 1700 nsec), it is possible to stably generate a sustain discharge.

  Here, conventionally, since the time t2a and the time t2 coincide with each other, the length of the rising period T1 and the length of the falling period T11 are the same value. However, in the first embodiment, as shown in FIG. By turning on the switching element Q14 at a time t2a that is a predetermined time earlier than the time t2, the falling period T11 is made shorter than the rising period T1.

  In the first embodiment, with respect to two types of rising periods having a rising period length of 1000 nsec or 1100 nsec, the falling period is set to 800 nsec or 900 nsec, which is 200 nsec shorter than the rising period. As a result, it is possible to improve display quality and light emission efficiency by suppressing variations in the occurrence timing of the sustain discharge and making the display luminance of each discharge cell uniform.

(Period T3)
At time t3, switching element Q11 is turned on. Then, the charges on the sustain electrodes X1 to Xn side start to flow to the scan electrodes Y1 to Yn side through the switching element Q11, the diode D11, and the inductor L10. As a result, the voltage of the sustain electrodes X1 to Xn decreases and the scan electrodes Y1 to Yn The voltage rises. Since the inductor L10 and the interelectrode capacitance Cp form a resonance circuit, the voltage of the sustain electrodes X1 to Xn drops to near 0 (V) after the time ½ of the resonance period has elapsed, and the scan electrode Y1. The voltage of .about.Yn rises to almost the voltage Vs. However, the voltage of the sustain electrodes X1 to Xn does not drop to 0 (V) due to power loss due to the resistance component of the resonance circuit and the like even after lapse of half the resonance period. Similarly, the voltages of the scan electrodes Y1 to Yn do not increase up to Vs. In the present embodiment, switching element Q22 is turned on at time t4a that is earlier than time t4 by a predetermined time. Then, since sustain electrodes X1 to Xn are directly grounded through switching element Q22, the voltages of sustain electrodes X1 to Xn are clamped to 0 (V) which is the ground potential.

(Period T4)
Subsequently, switching element Q13 is turned on at time t4. Then, since the scan electrodes Y1 to Yn are directly connected to the power source Vs through the switching element Q13, the voltage of the scan electrodes Y1 to Yn is clamped to the voltage Vs and forcibly rises to the voltage Vs. As a result, in the discharge cell in which the address discharge has occurred, the voltage between the sustain electrode Xi and the scan electrode Yi exceeds the discharge start voltage, and a sustain discharge occurs. Since the resonance period of the inductor L10 and the interelectrode capacitance Cp is set to about 2500 nsec, the voltage of the sustain electrodes X1 to Xn drops to near 0 (V) of the ground potential after about 1250 nsec from time t3. The voltages Y1 to Yn rise to almost the voltage Vs. However, since the length of the period T31 from time t3 to time t4a, that is, the sustain pulse falling period using the power recovery circuit 81 is set to 800 nsec or 900 nsec, the sustain electrodes X1 to Xn at time t4a are set. The voltage is clamped to the ground potential of 0 (V). Further, since the length of the period T3 from time t3 to time t4, that is, the rising period of the sustain pulse using the power recovery circuit 81 is set to 1000 nsec or 1100 nsec, the voltages of the scan electrodes Y1 to Yn at time t4. Is clamped to voltage Vs and forcibly rises to voltage Vs.

  In the period T4, the voltages of the scan electrodes Y1 to Yn are maintained at the voltage Vs, and the voltages of the sustain electrodes X1 to Xn are maintained at 0 (V). The period T4 is maintained for a sufficient time (in this embodiment, approximately 1300 to 1700 nsec), it is possible to stably generate a sustain discharge.

  Here, since the time t4a coincides with the time t4 in the related art, the length of the rising period T3 and the length of the falling period T31 are the same value. However, in the present embodiment, switching is performed as shown in FIG. By turning on the element Q22 at a time t4a earlier than the time t4 by a predetermined time, the falling period T31 is made shorter than the rising period T3.

  Here, the length of the sustain pulse rising period T1 is the sustain pulse rise time tT1, the length of the sustain pulse rise period T3 is the sustain pulse rise time tT3, and the length of the sustain pulse fall period T11 is The sustain pulse fall time tT11 is set, and the length of the sustain pulse fall period T31 is set as the sustain pulse fall time tT31.

  In the first embodiment, for two types of rising periods with a rising time of 1000 nsec or 1100 nsec, the falling time is set to 800 nsec or 900 nsec, which is 200 nsec shorter than the rising time. As a result, it is possible to improve display quality and light emission efficiency by suppressing variations in the occurrence timing of the sustain discharge and making the display luminance of each discharge cell uniform.

  In order to lower the output impedance of sustain pulse generating circuit 80 and sustain pulse generating circuit 90, switching element Q11, switching element Q13, and switching element Q22 are preferably turned off immediately before time t1, and switching element Q12 and switching element Q12 are switched off. Q14 and switching element 21 are preferably turned off immediately before time t3.

  In the sustain period, the operations in the above periods T1 to T4 are repeated according to the required number of pulses. In this manner, the sustain pulse voltage that is displaced from the base potential 0 (V) to the voltage Vs that is the potential for generating the sustain discharge is alternately applied to each of the display electrodes 7 to cause the discharge cells to sustain discharge.

  Next, as in the first embodiment, the display pulse and the light emission can be increased by setting the rise time tT1 of the sustain pulse applied to the sustain electrode and the fall time tT11 of the sustain pulse applied to the scan electrode to different values. The reason why the efficiency can be improved will be described. The same applies to the case where the rise time tT3 of the sustain pulse applied to the scan electrode and the fall time tT31 of the sustain pulse applied to the sustain electrode have different values.

  The display quality and the light emission efficiency are closely related to the light emission intensity in the discharge cell, and the light emission intensity greatly changes depending on the waveform of the sustain pulse. That is, the emission intensity varies greatly depending on the rise time of the sustain pulse, the time for maintaining the sustain pulse at the voltage Vs, and the like. However, the start time of the rise period T1 of the sustain pulse applied to the sustain electrode and the start time of the fall period T11 of the sustain pulse applied to the scan electrode are the same time, and the rise period T1 and the fall period T11 are temporally different. In the case of overlapping, it has been found that the emission intensity varies greatly depending on the fall time of the sustain pulse applied to the scan electrode. This is because by making the fall time tT11 longer or shorter than the length of the rise time tT1, the waveform at the time of the occurrence of the sustain discharge in the rise period T1 can be changed, resulting in a great change in the emission intensity. is there. For example, when self-collection is not performed and the sustain pulse applied to the scan electrode and the sustain pulse applied to the sustain electrode do not overlap in time, the next pulse can be changed even if the fall time of the sustain pulse is changed. The change in the sustain pulse waveform at the time of the occurrence of the sustain discharge in the rising period of the sustain pulse to be applied to was small, and the light emission intensity was not greatly changed.

  Therefore, we conducted an experiment to confirm how the display quality and luminous efficiency change when the rising and falling periods of the sustain pulse are changed. Here, the display quality improved in the present invention indicates a difference in luminance due to an afterimage phenomenon and a lighting load. The afterimage phenomenon is a phenomenon in which a still image immediately before switching is recognized as an afterimage when an image is switched after a still image or the like is displayed for a long time. Both the afterimage phenomenon and the luminance difference due to the lighting load degrade the image display quality.

  The difference in luminance due to the afterimage phenomenon and lighting load is considered to be caused by the difference in emission intensity caused by the difference in waveform distortion due to the difference in discharge start voltage between the discharge cells and lighting load caused by displaying a still image, It is considered that a variation in emission intensity in the discharge cell is one of the causes. Therefore, in order to reduce the luminance difference due to the afterimage phenomenon and the lighting load, it is considered effective to make the emission intensity as uniform as possible.

  First, the examination result of the afterimage phenomenon will be described. FIG. 10 is a diagram showing a change in the afterimage level when the fall time of the sustain pulse is changed in the first embodiment of the present invention. In FIG. 10, the vertical axis represents the afterimage level, and the horizontal axis represents the difference between the rise time and the fall time (rise time−fall time). In this experiment, in consideration of the number of subfields in one field period, the total number of sustain pulses, the stability of sustain discharge, and the power recovery rate, the rise times tT1 and tT3 of the sustain pulses are set to 1000 nsec, and the voltage Vs is set. While the length of the sustaining period (period T2, period T4) is kept constant at about 1700 nsec, only the sustain pulse falling time tT11, tT31) is changed from 800 nsec to 1200 nsec at 50 nsec intervals, and the afterimage phenomenon at that time is changed. Evaluation was performed in a lighting state in which the lighting rate of the discharge cells that were discharged simultaneously was 80% or more. In addition, the afterimage level on the vertical axis shows the appearance of the afterimage divided into six stages of 0 to 5 by subjective evaluation by the evaluator, and the afterimage level indicated by each numerical value is as follows.

  5: The afterimage can be clearly seen, and the afterimage has a color.

  4: An afterimage is visible, and the afterimage has a color.

  3: The afterimage appears thin and the afterimage of the character can be recognized as a character.

  2: The afterimage is very thin and it is difficult to recognize the afterimage of the character as a character.

  1: The afterimage is hardly visible.

  0: No afterimage is visible.

  And when it was evaluated as the afterimage level between the above six stages, a numerical value of the afterimage level was determined using a decimal. Here, if the afterimage level is 1.5 or less, the level is practically satisfactory.

  As shown in FIG. 10, the afterimage level is higher when the difference between the rise time and the fall time is larger than when the difference between the rise time and the fall time is set to 0 nsec (rise time = fall time). There is a tendency to improve, especially when the difference between the rise time and the fall time is −100 nsec or less or 100 nsec or more, and the afterimage level becomes 1.5 or less and the afterimage becomes a level with no problem. It was. That is, it is experimentally possible to improve the afterimage phenomenon by setting the rise time and the fall time to different values so that the difference between the rise time and the fall time is equal to or greater than a predetermined value. Was confirmed.

  Next, the evaluation result of the luminance difference due to the lighting rate load will be described. FIG. 11 is a diagram showing a change in luminance difference when the falling time of the sustain pulse is changed in the first embodiment of the present invention. In FIG. 11, the vertical axis represents the luminance difference, and the horizontal axis represents the difference between the rise time and the fall time as in FIG. In this experiment, the sustain pulse rising times tT1 and tT3 are maintained at 1000 ns and the voltage Vs in consideration of the number of subfields in one field period, the total number of sustain pulses, the stability of sustain discharge, and the power recovery rate. Discharge for lighting in the same subfield by changing only the sustain pulse falling times tT11 and tT31 at intervals of 50 nsec from 800 nsec to 1200 ns while keeping the length of the period (period T2, period T4) constant at about 1700 nsec. In a lighting state in which the lighting rate of the cell is 80% or more, the luminance difference was evaluated at different locations of the lighting area on the same display electrode pair. Here, if the luminance difference is 10% or less, the level is practically satisfactory.

  As shown in FIG. 11, the rise time and the fall time are compared with the difference between the rise time and the fall time (rise time−fall time) set to 0 nsec (rise time = fall time). The larger the difference, the smaller the luminance difference. In particular, when the difference between the rising period and the falling period is -100 nsec or less or 100 nsec or more, the luminance difference becomes 10% or less and the luminance difference is improved. I understood it. That is, it has been experimentally confirmed that the deterioration in display quality due to the luminance difference can be greatly improved by setting different values for the rise time and the fall time.

  Next, the evaluation result of luminous efficiency will be described. FIG. 12 is a diagram showing the relationship between the falling period of the sustain pulse and the light emission efficiency in the first embodiment of the present invention. In FIG. 12, the vertical axis represents the rate of change with respect to the light emission efficiency when the difference between the rise period and the fall period of the light emission efficiency is 0 nsec (rise time = fall time), and the horizontal axis represents the rise time and the fall as in FIG. Expresses the difference from time. In this experiment, sustain pulse rise times tT1 and tT3 are maintained at 1000 nsec and voltage Vs in consideration of the number of subfields in one field period, the total number of sustain pulses, the stability of sustain discharge, and the power recovery rate. Discharging for lighting in the same subfield by changing only the sustain pulse falling times tT11 and tT31 at intervals of 50 nsec from 800 nsec to 1200 nsec, while keeping the length of the period (period T2, period T4) constant at about 1700 nsec. The light emission efficiency in the lighting state where the lighting rate of the cell is 80% or more was measured.

  As shown in FIG. 12, the rise time and the fall time are different from those when the difference between the rise time and the fall time (rise time−fall time) is set to 0 nsec (rise time = fall time). It was found that the larger the difference, the better the luminous efficiency, and the greater the difference between the rise time and the fall time, the better. That is, it has been experimentally confirmed that the luminous efficiency can be improved by setting the rise time and the fall time to different values.

  In the above description, the experimental results are shown in which the sustain pulse rise times tT1 and tT3 are set to 1000 nsec and the length of the period (period T2 and period T4) for maintaining the voltage Vs is constant at about 1700 nsec. The same effect was obtained when tT3 was set to 1100 nsec and the length of the period (period T2, period T4) for maintaining the voltage Vs was constant at about 1600 nsec. Therefore, in this embodiment, the difference between the rise time and the fall time (rise time−fall time) is set to, for example, 200 nsec so that the afterimage phenomenon, the luminance difference, and the light emission efficiency are all effective. With respect to two types of rise times with a pulse rise period of 1000 nsec or 1100 nsec, the fall time is set to 800 nsec or 900 nsec, which is 200 nsec shorter than the rise time. Thereby, in the case where the sustain pulse is applied in the self-collection circuit configuration, it is possible to improve display quality and light emission efficiency.

  As described above, according to the first embodiment, the rise time of the sustain pulse applied to one electrode of the display electrode pair is different from the fall time of the sustain pulse applied to the other electrode. This makes it possible to improve display quality and light emission efficiency.

  The experiment shown in the first embodiment is performed using a 42-inch panel having 768 display electrode pairs, and the above-described numerical values are set based on the panel. The present embodiment is not limited to these numerical values, and specific numerical values such as the sustain pulse rise time and fall time are optimally set according to the specifications of the plasma display device and the panel characteristics. It is desirable to do.

  In the first embodiment, the description has been made within one subfield within one field period. However, the present invention is not limited to these numerical values, and all subfields within one field period and some subfields are included. The same effect can be obtained by setting to an optimal value as appropriate based on the specifications of the plasma display device, the characteristics of the panel, the characteristics of the drive circuit, etc.

  In the first embodiment, the rising period is set to two types of 1000 nsec and 1100 nsec, and the difference between the rising period and the falling period (rising period−falling period) is set to 200 nsec, so that the falling period Is set to two types of 800 nsec and 900 nsec, but is not limited to these numerical values. By setting one type of rise time and two types of differences between the rise time and the fall time, Two types of falling time may be set, three or more types of rising time and falling time may be set, or the falling time may be set longer than the rising time. Based on the specifications of the plasma display device, panel characteristics, drive circuit characteristics, etc. Similar effects can be obtained by setting the a value.

  Here, as another example of the first embodiment, the effectiveness of setting two types of differences between the rise time and the fall time (rise time−fall time) will be described. In the first embodiment, the rise time is set to two types of 1000 nsec and 1100 nsec as described above, but a shorter rise time is set depending on the specifications of the plasma display device, the panel characteristics, the drive circuit characteristics, and the like. There may be cases. For example, when two types of settings of 800 nsec and 1100 nsec are required, if the difference between the rise time and the fall time (rise time-fall time) is set to 200 nsec, the fall time is 600 nsec and 900 nsec. Become. Here, setting the fall time to be shorter than the relative rise time is the direction in which the rise waveform of the sustain pulse is changed to increase the reactive power. When the rise time is set shorter than 1/2 of the resonance period, the reactive power tends to increase. However, when the fall time relative to the rise time is set shorter, the reactive power is further increased. Therefore, when the rise time is set to 800 nsec and the corresponding fall time is set to 600 nsec with respect to 1250 nsec, which is 1/2 of the resonance period of 2500 nsec shown in the first embodiment, the power recovery efficiency at the rise time of 800 nsec is The reactive power further decreases with the relative fall time of 600 nsec, and the reactive power increases rapidly. Therefore, as another example of the first embodiment of the present invention, the difference between the rise time and the fall time relative to the rise time is set to be larger when the rise time is shorter than when the rise time is short. Thus, display quality and luminous efficiency can be improved while suppressing an increase in reactive power as much as possible. For example, as described above, when two types of rise times of 800 nsec and 1100 nsec are required, the fall times relative to the respective rise times are set to two types of 750 nsec and 900 nsec, and the rise time is long. The difference (200 nsec) between (1100 nsec) and the corresponding fall time (900 nsec) is set longer than the difference (50 nsec) between the short rise time (800 nsec) and the corresponding fall time (750 nsec). Like that. By setting in this way, display quality and luminous efficiency can be improved while suppressing an increase in reactive power as much as possible.

  The scan electrodes and sustain electrodes of the panel in this embodiment are composed of conductive electrodes that do not use transparent electrodes, and have lower resistance values than the scan electrodes and sustain electrodes that use transparent electrodes. Some may be 30-40% lower. In such a panel having a low resistance value, a discharge current tends to flow, and the discharge variation tends to be larger than a panel using transparent electrodes for the scan electrode and the sustain electrode. Therefore, for a panel having a structure as in this embodiment, in order to improve display quality and luminous efficiency, the rise time of the sustain pulse applied to one electrode of the display electrode pair and the other It is particularly effective to set the fall time of the sustain pulse applied to the electrodes to a different value.

(Embodiment 2)
Next, a second embodiment of the present invention will be described. In the second embodiment of the present invention, in setting the fall time, different fall times are set for the fall time of the sustain pulse applied to the scan electrode and the fall time of the sustain pulse applied to the sustain electrode. Each sustain pulse is generated only by controlling the switching timing of each switching element of the sustain pulse generating circuit 80 and the sustain pulse generating circuit 90, and other operations and configurations of the respective circuits are performed. Therefore, the effectiveness of setting different fall time values for the sustain pulse fall time applied to the scan electrode and the sustain pulse fall time applied to the sustain electrode is here. Only will be described.

  As described above, the circuit configuration for self-recovering the charge charged in the panel between the scan electrode and the sustain electrode via the power recovery circuit is as shown in the circuit diagram of the sustain pulse generating circuit in FIG. In addition, the power recovery circuit 81 is included in the scan electrode driving circuit 73 and is not included in the sustain electrode driving circuit 74. In other words, in the circuit configuration that self-recovers the charge charged in the panel, the power recovery circuit is included in either the scan electrode drive circuit 73 or the sustain electrode drive circuit 74, thereby minimizing the circuit configuration and reducing the cost. I am trying. However, in such a circuit configuration, an impedance difference occurs between the scan electrode drive circuit 73 and the sustain electrode drive circuit 74, and even if the sustain pulse is generated at the same control timing, the scan electrode end or the sustain electrode end , The desired sustain pulse may not be output because the distortion of the sustain pulse waveform varies depending on the difference in circuit impedance. If a circuit configuration is designed so that this circuit impedance difference can be eliminated by the scan electrode drive circuit 73 and the sustain electrode drive circuit 74, there is no problem, but it is very difficult to eliminate the impedance difference. Will increase costs.

  Therefore, in the second embodiment of the present invention, the sustain pulse waveform distortion due to the difference in circuit impedance is suppressed between the sustain pulse fall time applied to the scan electrode and the sustain pulse fall time applied to the sustain electrode. By setting the falling time suitable for each direction, the distortion of the sustain pulse waveform due to the difference in circuit impedance is suppressed without increasing the cost, and the display quality and luminous efficiency are improved as described in the first embodiment. Can be realized.

  For example, in the first embodiment, the rise time is set to two types of 1000 nsec and 1100 nsec, and the difference between the rise time and the fall time (rise time−fall time) is set to −200 nsec. Although the time is set to two types of 800 nsec and 900 nsec, as shown in FIG. 8, when the power recovery circuit 81 is in the scan electrode drive circuit 73, the impedance of the scan electrode drive circuit 73 is the sustain electrode drive circuit. Since the rise time and fall time of the sustain pulse applied to the sustain electrode are set to be shorter by 50 nsec, the sustain pulse applied to the scan electrode is set to be shorter by 50 nsec. 1 rise time of sustain pulse to be applied 00nsec and 1100nsec, the sustain pulse rise time applied to the scan electrode is 950nsec and 1050nsec, the sustain pulse fall time applied to the sustain electrode is 800nsec and 900nsec, and the sustain pulse fall time applied to the scan electrode is By setting 750 nsec and 950 nsec, display quality and luminous efficiency can be improved while suppressing distortion of the sustain pulse waveform due to the circuit impedance difference.

  In the second embodiment, the power recovery circuit 81 is included in the scan electrode drive circuit 73. However, the power recovery circuit 81 may be included in the sustain electrode drive circuit 74. The rising period and the falling period may be set by the sustain pulse applied to the sustain electrode in the reverse direction and the sustain pulse applied to the scan electrode.

  In the second embodiment, the rise time and fall time of the sustain pulse applied to the sustain electrode are set to be shorter by 50 nsec than the rise time and fall time of the sustain pulse applied to the scan electrode. Not limited to these values, distortion is suppressed not only in the impedance difference due to the power recovery circuit 81 but also in the sustain pulse waveform distortion due to the impedance difference due to other circuit configurations or the impedance difference due to the panel structure. The fall time may be set to a different value between the sustain pulse applied to the sustain electrode and the sustain pulse applied to the scan electrode, so that the fall time can be set based on the specifications of the plasma display device, the panel characteristics, the drive circuit characteristics, etc. A similar effect can be obtained by appropriately setting the optimum value.

(Embodiment 3)
The third embodiment is different from the first and second embodiments in that it includes a lighting rate detection circuit that detects a lighting rate of a discharge cell that is lit in the same subfield among a plurality of discharge cells, and is detected by the lighting rate detection circuit. The fall time is controlled in accordance with the lighting rate. Hereinafter, the configuration of the apparatus will be described first, and then the fall time controlled according to the lighting rate will be described.

  A configuration of the plasma display device according to the third embodiment will be described. FIG. 13 is a circuit block diagram of the plasma display device in accordance with the third exemplary embodiment of the present invention. This plasma display device has a configuration in which a lighting rate detection circuit 76 is added to the plasma display device described in the first embodiment. Since the configuration is the same as that described in Embodiment 1 except for the lighting rate detection circuit 76, only the lighting rate detection circuit 76 will be described here.

  The lighting rate detection circuit 76 detects the ratio of the number of lighting discharge cells to the total number of discharge cells, that is, the lighting rate of the discharge cells for each subfield, based on the image data for each subfield. Then, the detected lighting rate for each subfield is compared with a predetermined lighting rate threshold value, and a signal representing the result of the determination is output to the timing generation circuit 75. Timing generation circuit 75 outputs a timing signal corresponding to the determination result to scan electrode drive circuit 73 and sustain electrode drive circuit 74 to drive scan electrodes Y1 to Yn and sustain electrodes X1 to Xn. Thereby, the fall time can be controlled according to the lighting rate detected by the lighting rate detection circuit 76, the display quality can be improved according to the lighting rate, and the increase in reactive power can be suppressed. . Next, the effectiveness of controlling the fall time according to the lighting rate will be described.

  As described in the first embodiment, the display quality and the light emission efficiency are closely related to the light emission intensity in the discharge cell, and the light emission intensity greatly varies depending on the sustain pulse waveform. In other words, the emission intensity varies greatly depending on the rise time of the sustain pulse waveform, the period during which the sustain pulse is maintained at the voltage Vs, etc., but also varies greatly depending on the lighting rate of the discharge cells to be lit in the same subfield. In particular, when the lighting rate of discharge cells to be lit in the same subfield is high, the number of discharge cells to be lit in the same subfield is large throughout the panel surface. Therefore, since the sustain pulse waveform distortion increases due to the lighting load, the variation in the timing of the occurrence of the sustain discharge is likely to increase, resulting in non-uniform display brightness and worse display quality than when the lighting rate is low. There is a tendency. That is, when the lighting rate of the discharge cells to be lit in the same subfield is high, the display quality is likely to deteriorate. Therefore, the difference (rise time-fall time) between the rise time and the fall time of the sustain pulse waveform is increased. Therefore, it is necessary to improve the display quality, and the fall time is set short. For example, when the lighting rate of the discharge cells to be lit in the same subfield is 80% or more, the difference between the rise time and the fall time of the sustain pulse waveform (rise time−fall time) is set to 200 nsec. When the lighting rate is less than 80%, the difference between the rise time and the fall time of the sustain pulse waveform is set to 150 nsec. Conversely, when the lighting rate of the discharge cells to be lit in the same subfield is low, the deterioration in display quality tends to be smaller than when the lighting rate is high. Even if it is set longer, it can be equal to or better than the display quality when the lighting rate is high. That is, when the lighting rate is high, the difference between the rising time and the falling time of the sustain pulse waveform may be larger than when the lighting rate is low.

  The present invention is useful as a plasma display device because it can improve the display quality and luminous efficiency of the plasma display.

The disassembled perspective view which shows the panel in Embodiment 1 of this invention. Sectional drawing which shows the structure of the discharge cell part of the panel Electrode arrangement of the panel The top view which shows the arrangement | positioning relationship between the scanning electrode which comprises the display electrode of the panel, a sustain electrode, a data electrode, and a partition A plan view showing a configuration example of scan electrodes and sustain electrodes of the panel The figure which shows the drive waveform impressed to each electrode of the panel Configuration diagram of plasma display device in Embodiment 1 of the present invention Circuit diagram of sustain pulse generating circuit according to the first embodiment of the present invention Timing chart for explaining the operation of the sustain pulse generation circuit The figure which shows the relationship between fall time and afterimage level in Embodiment 1 of this invention The figure which shows the relationship between the fall time and luminance difference in Embodiment 1 of this invention The figure which shows the relationship between fall time and luminous efficiency in Embodiment 1 of this invention Configuration diagram of plasma display device according to embodiment 3 of the present invention A diagram for explaining a conventional sustain pulse waveform

DESCRIPTION OF SYMBOLS 1 Front plate 2 Back plate 3 Discharge space 4, 10 Substrate 5 Scan electrode 5a, 6a Lower layer 5b, 6b Upper layer 6 Sustain electrode 7 Display electrode 8 Dielectric layer 9 Protective film 11 Insulator layer 12 Data electrode 13 Partition 14R, 14G, 14B Phosphor layer 15 Discharge cell 51, 61 First part 52, 62 Second part 53, 63 Third part 71 Image signal processing circuit 72 Data electrode drive circuit 73 Scan electrode drive circuit 74 Sustain electrode drive circuit 75 Timing generation circuit 76 Lighting rate detection circuit 80, 90 Sustain pulse generation circuit 81 Power recovery circuit 82, 92 Clamp circuit Q11, Q12, Q13, Q14, Q21, Q22 Switching element
L10 Inductor D11, D12 Diode

Claims (5)

A plasma display panel having a plurality of discharge cells each having a display electrode pair composed of a scan electrode and a sustain electrode, and power recovery for causing a sustain pulse to rise or fall by resonating the interelectrode capacitance of the display electrode pair and an inductor. A sustain pulse generating circuit that applies a sustain pulse to each of the display electrode pairs using a circuit and a clamp circuit that clamps a voltage of the sustain pulse to a power supply voltage or a base potential,
The sustain pulse generating circuit generates a sustain pulse in which a sustain pulse rising start time applied to one electrode of the display electrode pair coincides with a sustain pulse falling start time applied to the other electrode, and the display A plasma display device, wherein a rising time of a sustain pulse applied to one electrode of an electrode pair is different from a falling time of a sustain pulse applied to the other electrode. The sustain pulse is applied to the display electrode pair by performing self-collection of the charge charged in the plasma display panel through a power recovery circuit between the scan electrode and the sustain electrode. Item 2. The plasma display device according to Item 1. A lighting rate detection circuit for detecting a lighting rate of a discharge cell to be lit in the same subfield among the plurality of discharge cells is provided, and a fall time is changed according to the lighting rate detected by the lighting rate detection circuit. The plasma display device according to claim 1, wherein the plasma display device is a plasma display device. When the lighting rate detection circuit determines that the lighting rate is smaller than a predetermined threshold value, the fall time is set longer than when the lighting rate is determined to be equal to or higher than the threshold value. The plasma display device according to claim 3. A plasma display panel comprises a front plate in which a conductive scan electrode and a sustain electrode are arranged on a substrate to form a display electrode by disposing a discharge gap therebetween, and a plurality of the display electrodes are arranged in a row direction, A back plate provided with a discharge space between the front plates and arranged opposite to each other and forming a plurality of data electrodes in a column direction crossing the display electrodes and providing discharge cells at the intersections; and 4. The plasma display device according to claim 1, wherein the display electrode is configured such that brightness of the scan electrode and the sustain electrode is low when viewed from the display surface on the substrate side.

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