JP2010173313A - Color image formation apparatus and image processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To allow storage means such as a SDRAM to be accessed at a high speed and also a color image to be formed at a high speed even if a scan periodic signal is fluctuated in a polygon drive system or the like. <P>SOLUTION: A tandem color image formation apparatus includes: a laser index sensor for detecting the scan period of a laser beam light to be scanned on an Y color photoreceptor drum; a reference signal generation unit 110 for generating an ACV signal for memory control based on a RIND signal obtained from the sensor; the SDRAM 303 for storing image data with the amount of delay set for each image formation unit; and a SDRAM control unit 113 for executing writing of image data only in a main scanning effective image region into the SDRAM 303 and reading thereof from the SDRAM 303 based on the ACV signal obtained from the reference signal generation unit 110. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  According to the present invention, an image forming unit that has a polygon drive system and forms a color image on a photosensitive drum is provided for each image forming color, and the color image formed by each image forming unit is displayed on the image carrier. The present invention relates to a color image forming apparatus and an image processing method suitable for application to a tandem color printer, a color copying machine, a color complex machine, and the like.

  In recent years, tandem color printers, color copiers, and these color multifunction devices have been increasingly used. According to this type of color image forming apparatus, when reproducing R (red), G (green), and B (blue) colors of a color image, for example, LED light sources are arranged in a line, and a photoconductor An LPH (LED Print Head) unit that performs batch exposure on the drum line by line is provided for each image forming color, and each toner image of each color of yellow (Y), magenta (M), cyan (C), and black (BK) is provided. The image forming color is formed by a photosensitive drum, and the toner images of the respective colors formed by the photosensitive drums for the respective colors are superimposed on the intermediate transfer belt. The color toner images superimposed on the intermediate transfer belt are transferred to a desired sheet, and then fixed and discharged.

  According to such a tandem color image forming apparatus, in order to superimpose toner images of each color on the intermediate transfer belt with good reproducibility, the photosensitive drum for one color and the photosensitive drum for the other color A write control method is taken into consideration, taking into account the delay amount set according to the distance between the two. According to this writing control method, a storage device such as an SDRAM capable of functioning as a line memory is provided for each image forming color of Y, M, C, and BK, and simultaneous writing timing is provided for each color SDRAM. A write operation of image data for forming a color image is performed.

  Further, when data is read from the SDRAM as the line memory, a read access timing signal is generated by adding a line delay amount (inter-drum delay amount) corresponding to the distance between the drums, and the read access timing signal is used for each color. A read operation of image data of the image forming color is performed from the SDRAM.

  According to the SDRAM access method using the read access timing signal to which the line delay amount is added, the precharge (PRE) command → the active (ACT) command → the write (WRITE) command → the PRE command → the ACT command → the read (READ) command. Etc. are sequentially issued and these command issuances are repeated to cope with image data writing and reading processing using different banks and row addresses.

  The reason that the PRE command and the ACT command are issued between the READ command (read operation) and the WRITE command (write operation) is that when the SDRAM is used for inter-drum delay control, the read address and write address banks or row addresses are different. Because it comes. It is well known that a refresh operation is required in a storage device such as an SDRAM. The refresh operation is an operation in which data is periodically rewritten by applying a charge to prevent data loss in an SDRAM or the like.

  In relation to an apparatus that handles this type of line delay amount (memory read delay control), Patent Document 1 discloses a delay circuit. The delay circuit includes a delay time setting means, a counting means, a comparison means, and a DRAM storage means. The delay time setting means sets the delay time and outputs a first signal corresponding to the set delay time. . The counting means counts the clock signal and outputs a second signal corresponding to the count value. The comparison means compares the first and second signals and resets the counting means when both signals have a predetermined relationship. After the DRAM storage means reads the address corresponding to the second signal, an operation of writing new data to the same address is performed to obtain a delay time in arbitrary bit units. By configuring the delay circuit in this way, a wide range of delay times can be set.

Japanese Patent No. 2641329 (FIG. 1 on page 4)

Incidentally, the tandem type color image forming apparatus in which the SDRAM or the like having a refresh operation is mounted has the following problems.
i. With the recent increase in processing clock speed of color image forming apparatuses, it has become necessary to increase the operating frequency during SDRAM access. High-speed memories such as DDR SDRAM are also commercially available, but higher frequency (higher speed) of the memory clock is required, and if the same memory access method as described above is adopted, the PRE command, the ACT command, etc. are written. In addition, there is a problem that the target SDRAM access speed cannot be expected in the tandem type color image forming apparatus without fail during the read operation.

  ii. In the tandem color image forming apparatus, for each color superposition, writing control is performed in consideration of the delay amount between the color drums. According to the memory read delay control described in Patent Document 1, only the case of a fixed delay amount is supported. When a write method such as a polygon drive system in which the delay amount varies is adopted, the memory read delay control is performed. It becomes difficult to adopt. Incidentally, when the scanning cycle signal (index signal cycle) fluctuates as in the polygon writing method, the width of the image formed on the photosensitive drum outside the effective image region fluctuates, and the effective image region is delayed. The amount will fluctuate.

  iii. When the delay amount of the above-mentioned effective image area fluctuates, as a countermeasure, according to the memory access method according to the conventional example, the read address and the write address are used for different addresses using separate counters. There is a method of performing read / write processing. However, when the SDRAM is used for inter-drum delay control, the read command and the write address require different PRE and ACT commands between the read and write cycles because the bank address or row address of the read address is different. For this reason, according to the conventional method, there is a problem that the performance is deteriorated when the PRE command and the ACT command are inserted between the read / write cycles.

  iv. In order to prevent the performance of the SDRAM from being deteriorated, there is an address tracking method for performing read / write with respect to the same address. However, in this method, the delay amount is fixed and the delay amount is changed. In such a writing method, it becomes difficult to apply the address tracking method without any ingenuity.

  Therefore, the present invention solves the above-described problem, and devise writing and reading control of image information for color image formation, and even when the scanning cycle signal fluctuates in a polygon driving system or the like, It is an object of the present invention to provide a color image forming apparatus and an image processing method capable of accessing a storage means such as an SDRAM at a high speed and forming a color image at a high speed.

  In order to solve the above-described problem, a color image forming apparatus according to claim 1 is configured such that an image forming unit that forms a color image by scanning light based on image information on a photosensitive drum having a rotation axis is provided for each image forming color. In a tandem type color image forming apparatus provided on the image carrier for superimposing color images formed by the respective image forming units on an image carrier, scanning light for detecting a scanning period of light scanned on the photosensitive drum A detection unit; a signal generation unit that generates a reference signal for memory control based on a scanning cycle signal obtained from the scanning light detection unit; and a delay amount is set for each image forming unit to store the image information The storage means for inter-drum delay and the direction along the rotation axis of the photosensitive drum is the main scanning direction, and the area that restricts image writing in the main scanning direction is the main scanning effective image area. Control means for writing the image information of only the scanning effective image area into the storage unit based on a reference signal obtained from the signal generation unit and executing reading from the storage unit .

  According to the color image forming apparatus of the first aspect, the scanning light detector detects the scanning period of the light scanned on the photosensitive drum and generates a scanning period signal. The signal generation unit creates a reference signal for memory control based on the scanning cycle signal obtained from the scanning light detection unit. On the other hand, a delay amount is set for each image forming unit and image information is stored in the inter-drum delay storage means. On the premise of this, the control means writes the image information of only the main scanning effective image area to the storage means based on the reference signal obtained from the signal generation unit, and executes reading from the storage means. Therefore, in a polygon driving system or the like, even when the scanning cycle signal fluctuates, it becomes possible to access storage means such as SDRAM at high speed and to form a color image at high speed.

  A color image forming apparatus according to a second aspect is the color image forming apparatus according to the first aspect, wherein the image forming unit is provided with a writing unit for scanning the photosensitive drum with light based on image information, and the control means is the storage means. The memory control is executed by accessing the address of the image information read from the writing unit to the writing unit and writing the next image information at the address.

  According to a third aspect of the present invention, in the color image forming apparatus according to the second aspect, the writing unit is provided with a light source that scans the light so as to face the photosensitive drum, and scanning exposure processing based on image information of one line unit. A polygon drive unit capable of the above is provided.

  According to a fourth aspect of the present invention, there is provided the color image forming apparatus according to the first aspect, wherein the control unit executes a refresh process of the storage unit during a period when the reading and writing of the image information are not performed. It is.

  In the image processing method according to claim 5, an image forming unit that forms a color image by scanning light based on image information on a photosensitive drum having a rotation axis is provided for each image forming color. In the image processing method in the tandem type color image forming apparatus that superimposes the color image formed by the unit on the image carrier, the step of detecting the scanning period of the light scanned on the photosensitive drum, and the detected Creating a reference signal for memory control based on a scanning cycle signal; setting a delay amount for each image forming unit; storing the image information; and direction along a rotation axis of the photosensitive drum Is the main scanning direction, the area that restricts image writing in the main scanning direction is the main scanning effective image area, and the image information of only the main scanning effective image area is the reference signal. And writing to the storage means based, it is characterized in that a step of reading from the storage means.

  According to the color image forming apparatus according to claim 1 and the image processing method according to claim 5, the control means for controlling writing and reading of the image information is provided, and the control means is a memory created based on the scanning cycle signal. Based on the control reference signal, the image information of only the main scanning effective image area is written into the storage means, and the image information is read out from the storage means.

  With this configuration, even when the scanning cycle signal fluctuates, it becomes possible to access storage means such as SDRAM at high speed based on the reference signal for memory control and to form a color image at high speed. . As a result, a color image based on the image information can be formed on the photosensitive drum at a high speed, so that the color image processing can be speeded up without increasing the operating frequency or depending on the next high-speed DRAM. In addition, the number of times the PRE command and the ACT command are generated can be reduced, and even when the amount of delay varies as in the polygon driving system writing method, it can be used for reading and writing image information. It becomes like this.

  According to the color image forming apparatus of the second aspect of the present invention, the control unit accesses the address of the image information read from the storage unit to the writing unit, and writes the next image information at the address (memory tracking access method). Therefore, the PRE command, the ACT command, etc. can be omitted from the writing operation and the reading operation of the image information, and the SDRAM repeats the PRE command → ACT command → WRITE command → PRE command → ACT command → READ command in order. Compared to the access method, the access speed between the storage means such as SDRAM and the control means can be improved (improved).

  According to the color image forming apparatus of the third aspect, the writing unit includes the polygon driving unit capable of performing the scanning exposure processing based on the image information of one line unit, and the LED light source is arranged in a line facing the photosensitive drum. The cost can be reduced compared to an LPH (LED Print Head) unit capable of performing batch exposure based on image information for each line.

  According to the color image forming apparatus of the fourth aspect, since the refresh process of the storage unit is executed during a period when the reading and writing of the image information is not performed, the storage unit such as the SDRAM is compared with the SDRAM access method described above. And the access speed between the control means and the control means can be improved (improved).

1 is a conceptual diagram illustrating a configuration example of a color printer 100 as an embodiment of the present invention. It is a conceptual diagram which shows the structural example of the writing unit 3Y for Y color. It is a block diagram which shows the example of an internal structure of the writing units 3Y, 3M, 3C, and 3K. It is a block diagram which shows the example of internal structure of the line memory part 81 grade | etc., For Y color. FIGS. 5A to 5H are time charts showing examples of control signals in the line memory unit 81 and the like. FIG. 6 is a state transition diagram illustrating an operation example of the SDRAM control unit 113. (A) to (P) are operation timing charts showing examples of read and write operations in the SDRAM 303. (A)-(N) are operation | movement timing charts which show the example of precharge bank active operation | movement in SDRAM303. (A)-(L) are operation | movement timing charts which show the refresh operation example in SDRAM303. (A)-(M) are the operation time charts which show the example of the delay process in the line memory part 81 (the 1). (A)-(M) are the operation | movement time charts which show the example of a delay process in the line memory part 81 (the 2). (A)-(M) are operation | movement time charts which show the example of a delay process in the line memory part 81 (the 3). 6 is an operation flowchart showing a delay processing example (part 1) using the SDRAM 303; 12 is an operation flowchart illustrating a delay processing example (part 2) using the SDRAM 303;

  A color image forming apparatus according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a conceptual diagram showing a configuration example of a color printer 100 as an embodiment of the present invention. A color printer 100 shown in FIG. 1 constitutes an example of a tandem color image forming apparatus, and an image forming unit is provided for each image forming color. Each image forming unit is based on image data Din (image information). The formed color image is superimposed on the color on the intermediate transfer belt 6 (image carrier). The image data Din is supplied from an external device such as a personal computer to the color printer 100 and transferred to the image forming unit 80.

  The image forming unit 80 includes an image forming unit 10Y having a photosensitive drum 1Y for yellow (Y), an image forming unit 10M having a photosensitive drum 1M for magenta (M), and a cyan (C) color. The image forming unit 10 </ b> C having the photosensitive drum 1 </ b> C, the image forming unit 10 </ b> K having the black (K) photosensitive drum 1 </ b> K, and the endless intermediate transfer belt 6 are configured.

  In the image forming unit 80, image formation processing is performed for each of the photosensitive drums 1Y, 1M, 1C, and 1K. They are superimposed on the intermediate transfer belt 6 to form a color image. The photosensitive drums 1Y, 1M, 1C, and 1K and the intermediate transfer belt 6 constitute an example of an image carrier.

  In this example, the image forming unit 10Y includes, in addition to the photosensitive drum 1Y, a charger 2Y, a polygon driving type writing unit 3Y, a developing unit 4Y, and an image forming body cleaning unit 8Y. ) A color image is formed. The photosensitive drum 1Y has a rotation shaft and is rotatably provided, for example, near the upper right portion of the intermediate transfer belt 6 so as to form a Y-color toner image. In this example, the photosensitive drum 1Y is rotated counterclockwise. A charger 2Y is provided on the lower right side of the photosensitive drum 1Y so as to charge the surface of the photosensitive drum 1Y to a predetermined potential.

  The writing unit 3Y is provided so as to face (opposite) substantially beside the photosensitive drum 1Y, and includes a laser light source and a polygon mirror. The writing unit 3Y scans a preliminarily charged photosensitive drum 1Y with a Y color laser beam having a predetermined intensity based on Y color image data. The laser beam light is, for example, writing of so-called Y color image data in the main scanning direction that is deflected and scanned by rotating a polygon mirror for Y color.

  Here, the main scanning direction refers to a direction parallel to the rotation axis of the photosensitive drum 1Y. The photosensitive drum 1Y rotates in the sub-scanning direction. The sub-scanning direction is a direction orthogonal to the rotation axis of the photosensitive drum 1Y. The photosensitive drum 1Y rotates in the sub-scanning direction, and an electrostatic latent image for Y color is formed on the photosensitive drum 1Y by the deflection scanning of the laser beam light in the main scanning direction.

  The above-mentioned laser beam light is scanned onto the photosensitive drum 1Y with a reference period of a reference index signal (hereinafter referred to as a reference IDX signal) as a control target. The scanning period of the laser beam light scanned by the polygon mirror 34 is detected by a laser index sensor 49 as shown in FIG. 2, and is an index signal for Y color (hereinafter referred to as a Y-IDX signal) as an example of a scanning period signal. And output to the polygon drive control system.

  Here, the index signal is a signal for detecting that the mirror surface of the polygon mirror 34 is phase-adjusted at a predetermined angle by the laser index sensor 49 in each of the image forming units 10Y, 10M, 10C, and 10K. For example, in the polygon drive control system for Y color, polygon phase control is performed such that the Y-IDX signal maintains the target phase difference with respect to the reference-IDX signal. By providing such a writing unit 3Y, a Y color image based on the image data Dout = Wy can be formed on the photosensitive drum 1Y for each line.

  A developing unit 4Y is provided above the writing unit 3Y and operates to develop an electrostatic latent image for Y formed on the photosensitive drum 1Y. The developing unit 4Y has a Y-color developing roller (not shown). In the developing unit 4Y, a Y color toner agent and a carrier are stored.

  The Y-color developing roller has a magnet disposed therein, and rotates and conveys the two-component developer obtained by stirring the carrier and the Y-color toner agent in the developing unit 4Y to the opposite part of the photosensitive drum 1Y. The electrostatic latent image is developed by the color toner agent. The Y color toner image formed on the photosensitive drum 1Y is transferred to the intermediate transfer belt 6 by operating the primary transfer roller 7Y (primary transfer). A cleaning unit 8Y is provided below the left side of the photosensitive drum 1Y so as to remove (clean) the toner remaining on the photosensitive drum 1Y in the previous writing.

  In this example, an image forming unit 10M is provided below the image forming unit 10Y. The image forming unit 10M includes a photosensitive drum 1M, a charger 2M, a writing unit 3M, a developing unit 4M, and an image forming body cleaning unit 8M, and forms a magenta (M) color image. . An image forming unit 10C is provided below the image forming unit 10M. The image forming unit 10C includes a photosensitive drum 1C, a charger 2C, a writing unit 3C, a developing unit 4C, and a cleaning unit 8C for an image forming body, and forms a cyan (C) color image. .

  An image forming unit 10K is provided below the image forming unit 10C. The image forming unit 10K includes a photosensitive drum 1K, a charger 2K, a writing unit 3K, a developing unit 4K, and a cleaning unit 8K for an image forming body, and forms a black (BK) color image. . An organic photoconductor (OPC) drum is used as the photoconductor drums 1Y, 1M, 1C, and 1K. Note that the functions of the members of the image forming units 10M to 10K can be applied by replacing Y with M, C, and K for the same reference numerals of the image forming unit 10Y, and thus description thereof is omitted.

  A primary transfer bias voltage having a polarity opposite to that of the toner agent to be used (positive polarity in this embodiment) is applied to the above-described primary transfer roller 7Y and the like. The intermediate transfer belt 6 superimposes the toner image transferred by the primary transfer roller 7Y or the like to form a color toner image (color image). The color image formed on the intermediate transfer belt 6 is conveyed toward the secondary transfer roller 7A as the intermediate transfer belt 6 rotates clockwise. The secondary transfer roller 7A is located below the intermediate transfer belt 6 and transfers the color toner image formed on the intermediate transfer belt 6 onto the paper P in a lump (secondary transfer). The secondary transfer roller 7A is configured to remove (clean) the toner agent remaining on the secondary transfer roller 7A in the previous transfer.

  In this example, a cleaning unit 8A is provided on the upper left side of the intermediate transfer belt 6 and operates to clean the toner agent remaining on the intermediate transfer belt 6 after transfer. The cleaning unit 8 </ b> A has a neutralization unit (not shown) that neutralizes the charge of the intermediate transfer belt 6 and a pad that removes toner remaining on the intermediate transfer belt 6. The intermediate transfer belt 6 after the belt surface is cleaned by the cleaning unit 8A and discharged by the discharging unit enters the next image forming cycle. As a result, a color image can be formed on the paper P.

  In addition to the image forming unit 80, the color printer 100 includes a paper feeding unit 20 and a fixing device 17. A sheet feeding unit 20 is provided below the image forming unit 10K and includes a plurality of sheet feeding trays (not shown). A paper P of a predetermined size is accommodated in each paper feed tray. Conveying rollers 22A and 22C, a loop roller 22B, a registration roller 23, and the like are provided on a sheet conveying path from the sheet feeding unit 20 to the lower side of the image forming unit 10K. For example, the registration roller 23 holds a predetermined sheet P fed from the sheet feeding unit 20 in front of the secondary transfer roller 7A and sends it to the secondary transfer roller 7A in accordance with the image timing. The secondary transfer roller 7A is configured to transfer the color image carried on the intermediate transfer belt 6 onto a predetermined paper P whose paper conveyance is controlled by the registration roller 23.

  A fixing device 17 is provided on the downstream side of the secondary transfer roller 7A described above, and the paper P on which the color image is transferred is fixed. The fixing device 17 includes a fixing roller, a pressure roller, a heating (IH) heater, a fixing cleaning part 17A, and the like (not shown). In the fixing process, the paper P is heated and pressed by passing the paper P between a fixing roller heated by a heater and a pressure roller. The fixed sheet P is nipped by the sheet discharge roller 24 and discharged onto a sheet discharge tray (not shown) outside the apparatus. The fixing cleaning portion 17A removes (cleans) the toner agent remaining on the fixing roller or the like by the previous fixing.

  In this example, the writing units 3Y, 3M, 3C, and 3K are connected to a control unit 15 that constitutes an example of a control unit, and controls input / output of the writing unit 3Y to transfer image data Wy to the photosensitive drum 1Y. The write timing is controlled. Similarly, the control unit 15 controls the input / output of the writing unit 3M to control the writing timing of the image data Wm to the photosensitive drum 1M, and controls the input / output of the writing unit 3C to the photosensitive drum 1C. The control unit 15 controls the input / output of the writing unit 3K to control the writing timing of the image data Wk to the photosensitive drum 1K (see FIG. 3). .

  FIG. 2 is a conceptual diagram showing a configuration example of the Y color writing unit 3Y. The Y color writing unit 3Y shown in FIG. 2 is arranged to face the photosensitive drum 1Y, and has a collimator lens 32, an auxiliary lens 33, a polygon mirror 34, a polygon motor 35, an f (θ) lens 36, a mirror surface connection. The image forming apparatus includes a CY1 lens 37 for image formation, a CY2 lens 38 for drum surface image formation, a reflection plate 39, a polygon motor drive substrate 45, an LD drive substrate 46, a line memory unit 81, and an LD & drive unit 82. The LD & drive unit 82 includes the semiconductor laser light source 31 and the LD drive substrate 46.

  The semiconductor laser light source 31 is connected to a Y-color LD drive substrate 46. Image data Wy = write data Wy is supplied from the line memory unit 81 to the LD drive substrate 46. In the LD drive substrate 46, the write data Wy is PWM-modulated, and a laser drive signal SLy having a predetermined pulse width after PWM modulation is output to the semiconductor laser light source 31. The semiconductor laser light source 31 generates laser beam light based on the Y color laser drive signal SLy. The laser beam light emitted from the semiconductor laser light source 31 is shaped into a predetermined beam light by the collimator lens 32, the auxiliary lens 33, and the CY1 lens 37.

  The laser beam is deflected and scanned in the main scanning direction by the polygon mirror 34, and the intermediate transfer belt 6 is moved in the sub-scanning direction at a constant linear velocity. When the photosensitive drum 1Y rotates in the sub-scanning direction and the writing unit 3Y deflects and scans the laser beam light in the main scanning direction based on the reference IDX signal, the photosensitive drum 1Y is Y-colored by exposure for each line. An electrostatic latent image is formed. In this example, hereinafter, an area that restricts image writing in the main scanning direction is referred to as a main scanning effective image area, and an area that restricts image writing in the sub scanning direction is referred to as a sub main scanning effective image area.

  In this example, the polygon mirror 34 is driven by a polygon motor 35. A polygon motor drive board 45 is connected to the polygon motor 35, and a polygon drive clock signal for Y color (hereinafter referred to as YP-CLK signal) is supplied to the polygon motor drive board 45 from the controller 15 described above. . The polygon motor drive board 45 is configured to rotate the polygon motor 35 at a predetermined rotation speed based on the YP-CLK signal.

  After the polygon phase control, the rotation control is locked so that the polygon motor 35 rotates at a constant speed. The laser beam light deflected and scanned by the polygon mirror 34 is imaged toward the photosensitive drum 1Y by the f (θ) lens 36 and the CY2 lens 38. By this operation, an electrostatic latent image such as an original image or a registration mark for color misregistration is formed in the image area of the photosensitive drum 1Y in the normal operation mode or the color misregistration correction mode.

  A reflecting plate 39 is provided at a predetermined fixed portion of the writing unit 3Y, and a laser index sensor 49 is attached at a position facing the reflecting plate 39. The laser index sensor 49 constitutes an example of a scanning light detection unit, detects the laser beam light deflected and scanned by the polygon mirror 34, and outputs a Y-IDX signal to the control unit 15 shown in FIG. The Although not shown in FIG. 2, the other M, C, K color writing units 3M, 3C, 3K are configured in the same manner, and the other M, C, K color writing units 3M, 3C. The 3K laser index sensor 49 outputs an M-IDX signal, a C-IDX signal, and a K-IDX signal to the control unit 15, respectively.

  Next, an internal configuration example of the writing unit 3Y and the like will be described. FIG. 3 is a block diagram illustrating an internal configuration example of the writing units 3Y, 3M, 3C, and 3K. FIG. 4 is a block diagram illustrating an internal configuration example of the line memory unit 81 for Y color. The writing unit 3 </ b> Y shown in FIG. 3 includes a line memory unit 81 for Y color and an LD & driving unit 82 for Y color, and is connected to the control unit 15.

  The line memory unit 81 for Y color constitutes an example of a storage means for inter-drum delay, and stores the image data Din with a delay amount set for each of the image forming units 10Y, 10M, 10C, and 10K. . The line memory unit 81 includes, for example, an address counter comparison value (hereinafter referred to as a DLY signal), a writing side sub-scanning effective image area signal (hereinafter referred to as a WVV signal), and a writing side main scanning effective image area signal (hereinafter referred to as a WHV signal). The image data Din (= Dy) is written and read out on the basis of the read side index signal (hereinafter referred to as RIND signal) and the read side main scanning effective image area signal (hereinafter referred to as RHV signal).

  This RIND signal is an index signal on the read side, and in the case of the writing unit 3Y, is a Y-IDX signal output from the LD & drive unit 82 for Y color. Similarly, in the case of the writing unit 3M, the M-IDX signal is output from the LD & driving unit 84 for M color. In the case of the writing unit 3 </ b> C, this is a C-IDX signal output from the LD & driving unit 86 for C color. In the case of the writing unit 3K, this is a K-IDX signal output from the LD & driving unit 88 for BK color. For the line memory unit 81, an SDRAM (Synchronous DRAM) is used.

  The control unit 15 is connected to the line memory unit 81, and the image data Din of only the main scanning effective image region is written to the line memory unit 81, and the image data Dout = Wy is read from the line memory unit 81 to the LD & drive unit 82. And the refresh process of the line memory unit 81 is executed in a period in which the reading and writing of the image data Dout are not executed.

  Further, the control unit 15 accesses the address ADR of the image data Dout = Wy read from the line memory unit 81 to the LD & driving unit 82, and writes the next image data Din = Dy to the address ADR. Execute memory control by. When the control unit 15 performs memory control by the read address tracking access method, the number of occurrences of a precharge (PRE) command, an active (ACT) command, and the like can be reduced.

  Accordingly, the PRE command, the ACT command, and the like can be reduced between the write operation of the image data Din = Dy and the read operation of the image data Dout = Wy, and the PRE command → ACT command → write (WRITE) command → PRE command. The access speed between the line memory unit 81 such as an SDRAM and the control unit 15 can be improved (improved) as compared with an SDRAM access method in which an ACT command → a read command is sequentially repeated. The other M, C, and K color writing units 3M, 3C, and 3K are similarly configured.

  The line memory unit 81 includes, for example, a reference signal generation unit 110, a read / write control counter 111, a storage capacity determination unit 112, an SDRAM control unit 113, an address generation unit 301, an SDRAM 303, a write processing unit 304, a signal, as shown in FIG. A separation unit 305 and a read processing unit 306 are included.

  The reference signal generator 110 constitutes an example of a signal generator, and generates a write-side reference access valid signal (hereinafter referred to as an ACV signal) based on the RIND signal. The RIND signal (= Y-IDX signal) is input from the laser index sensor 49 of the writing unit 3Y to the reference signal generation unit 110 via the control unit 15. The reference signal generation unit 110 raises the ACV signal to a high level (hereinafter referred to as Hi) when writing the image data Din.

  The period of the RIND signal is not necessarily constant and varies. The reason why the cycle of the RIND signal fluctuates is that a polygon driving method is used for writing an image on the photosensitive drum 1Y. The RIND signal of the writing unit 3Y is a Y-IDX signal. The RIND signal of the other writing unit 3M is an M-IDX signal, the RIND signal of the writing unit 3C is a C-IDX signal, and the RIND signal of the writing unit 3K is a K-IDX signal.

  The reference signal generation unit 110 is connected to a read / write control counter 111, counts an ACV signal, generates a read / write control signal (hereinafter referred to as a CNT signal), and outputs the CNT signal to the SDRAM control unit 113. . The read / write control counter 111 increments the CNT signal when the ACV signal is Hi. The read / write control counter 111 further generates a carry signal C0 when the ACV signal is counted and counted up, and outputs the carry signal C0 to the column address counter 105.

  In addition to the read / write control counter 111, a storage capacity determination unit 112 is connected to the reference signal generation unit 110. A write processing unit 304 is connected to the storage capacity determination unit 112. The write processing unit 304 includes a two-input AND circuit 99, a data packing unit 101, and a FIFO memory 102 for write timing.

  The 2-input AND circuit 99 inputs a main scanning effective image area signal (hereinafter referred to as a WHV signal) and a sub-scanning effective image area signal (hereinafter referred to as a WVV signal) on the writing side, and logically outputs the WHV signal and the WVV signal. An effective image area signal (write enable signal: hereinafter referred to as a WEN signal) obtained by the product operation is generated.

  A data packing unit 101 is connected to the 2-input AND circuit 99. The data packing unit 101 transfers image data Din inputted in synchronization with the WEN signal to a clock signal of a transfer processing system (hereinafter referred to as a transfer clock) and an SDRAM operation system. Are packed according to the frequency ratio to the clock signal (hereinafter referred to as SDRAM clock).

  For example, when the image data Din = Dy in which one pixel is expressed by 8 bits is input, the data packing unit 101 performs packing processing on the 8-bit image data Din = Dy every two pixels. In this example, as shown in FIG. 7, when the read and write operations are 0 to 18 CLK, it is sufficient that the SDRAM clock frequency is 2.25 times the transfer clock frequency. 2. Set to 25 times.

  In this case, the image data Din is not packed. Alternatively, the data packing unit 101 sets the SDRAM clock to 1.125 times the transfer clock and packs two pixels as one data. When packing two pixels into one data, the WEN signal to the FIFO memory 102 may be changed to a signal that becomes Hi once every two clocks. Note that the number of pixels to be packed according to the image bit width, the data bus width, and the frequency is not limited.

  A FIFO memory 102 is connected to the data packing unit 101, and image data that has been subjected to packing processing (hereinafter also referred to as packing data DQ) is stored in the FIFO memory 102. The FIFO memory 102 operates to write the packing data DQ obtained by packing the image data Wy into the SDRAM 303 via the signal separation unit 305 based on the write timing signal WV.

  The FIFO memory 102 has a frequency conversion function. Here, the frequency conversion function refers to a function for converting the frequency of the transfer clock of the transfer processing system of the image data Din into the frequency of the SDRAM clock of the SDRAM operation system. The FIFO memory 102 detects the amount of image data Din stored in its own FIFO memory 102 and writes a write address signal (data accumulation amount detection signal: hereinafter referred to as a WFWAD signal) indicating the amount of the image data Din. ) Is output to the storage capacity determination unit 112.

  The storage capacity determination unit 112 described above determines the amount of data stored in the FIFO memory 102 in response to the ACV signal, and generates a reference access flag signal (hereinafter referred to as an ACF signal). For example, when the ACV signal becomes Hi, the storage capacity determination unit 112 receives the WFWAD signal from the FIFO memory 102, and sets the maximum image data amount setting value corresponding to one cycle of the reference IDX signal as the Y-IDX signal. When the maximum shake (shake) amount set value reflected in the above is set, the signal indicating the maximum shake amount set value is compared with the WWFAD signal.

  If the storage capacity determination unit 112 determines that the image data Din greater than the maximum blur amount setting value is stored in the FIFO memory 102, the storage capacity determination unit 112 raises the ACF signal to Hi. If it is determined that only image data Din less than the maximum blur amount setting value is stored, the ACF signal is kept at the low level (hereinafter referred to as Lo).

  If it is determined that image data Din greater than the maximum blur amount setting value is stored in the FIFO memory 102, the ACF signal is raised to Hi based on the next ACV signal. The ACF signal is output to the SDRAM control unit 113. As a result, the storage capacity determination unit 112 can determine whether or not the FIFO memory 102 stores image data Din that is equal to or greater than the maximum blur amount setting value corresponding to the reference IDX signal period.

  In this example, when image data Din that is equal to or greater than the maximum blur amount setting value is not stored in the FIFO memory 102, a delay of one line occurs in the FIFO memory 102. For this reason, the address count comparison unit 108 sets and initializes a value “−1” for the inter-drum delay amount to be compared with the row address ROW, and compares it with the inter-drum delay amount “−1” with the row address ROW. To be made.

  An address generation unit 301 is connected to the read / write control counter 111 described above. The address generator 301 receives the DLY signal and the carry signal C0 and generates an address ADR, carry signals C1 and C2, and a bank address BA. The address generation unit 301 includes, for example, a column (row) address counter 105, a bank counter 106, a row (column) address counter 107, an address count comparison unit 108, and a multiplexer 109.

  The address count comparison unit 108 inputs a DLY signal (set value of inter-drum delay amount), a column address COL (count value), a bank address BA and a row address ROW (count value), and receives these column address COL, bank The address BA (count value) and the row address ROW (count value) are compared with a predetermined set value. Here, the inter-drum delay amount is a value for setting the writing timing of the image data Din to be written on the other photosensitive drums 1M, 1C, and 1K with reference to the photosensitive drum 1Y, for example. The DLY signal is supplied from the upper control unit 15 to the address count comparison unit 108.

  For example, the address count comparison unit 108 compares the values of the column address COL and the bank address BA with the data amount for one line, and if they match, generates the RST0 signal and the RST1 signal and also generates the carry signal C2. To do. The RST0 signal is a signal for resetting the column address counter 105, and is output from the address count comparison unit 108 to the column address counter 105. The RST1 signal is a signal that resets the bank counter 106 and is output from the address count comparison unit 108 to the bank counter 106.

  The address count comparison unit 108 further compares the ROW value input from the row address counter 107 with the inter-drum delay amount, and generates an RST2 signal when they match. The RST2 signal is a signal for resetting the row address counter 107, and is output from the address count comparison unit 108 to the row address counter 107. The address count comparison unit 108 outputs the carry signal C2 to the row address counter 107 and simultaneously to the SDRAM control unit 113.

  As described above, the RST0 to RST2 signals are generated when the counter provided in the address count comparison unit 108 transitions to the read request confirmation operation excluding the transition from the memory initial state. Are compared and output. When accessing the SDRAM 303, the address count comparison unit 108 counts up from the column address COL because the PRE command and the ACT command are not required in the bank address BA and the row address ROW.

  A column address counter 105 is connected to the address count comparison unit 108, is reset by the RST0 signal, counts the carry signal C0, and generates a carry signal C1 and a 9-bit column address COL. When the column address counter 105 counts up “512”, it overflows and returns to “0”. The carry signal C0 is output from the read / write control counter 111 to the column address counter 105. The column address counter 105 counts up eight addresses when transitioning to the read request confirmation operation excluding transition from the memory initial setting state. The reason for counting up eight addresses is that eight burst transfers are being executed.

  In this example, when the column address counter 105 counts up 512, which depends on the SDRAM 303, the carry signal C1 is output to the bank counter 106 and the SDRAM control unit 113. The column address COL is output from the column address counter 105 to the multiplexer 109 and the address count comparison unit 108. The counter that counts up next to the column address counter 105 may be either the bank counter 106 or the row address counter 107.

  A bank counter 106 is connected to the column address counter 105 and generates a 2-bit bank address BA based on the RST1 signal and the carry signal C1. When the bank counter 106 counts up “4” times, it returns to “0”. For example, the bank counter 106 receives the carry signal C 1 and counts up, and counts up four times depending on the SDRAM 303. The bank address BA (count value) is output from the bank counter 106 to the address count comparison unit 108 and the SDRAM 303.

  In addition to the column address counter 105 and the bank counter 106, a row address counter 107 is connected to the address count comparison unit 108, and a 13-bit row address ROW is generated based on the RST2 signal and the carry signal C2. The row address counter 107 is reset by the RST2 signal, and counts up the row address ROW based on the carry signal C2. The row address ROW is output from the row address counter 107 to the address count comparison unit 108 and the multiplexer 109. The row address ROW is initialized when it reaches a preset value (inter-drum delay amount).

  A multiplexer 109 is connected to the row address counter 107 and the column address counter 105. The column address COL is input based on a timing signal (hereinafter referred to as an ACT-T signal) that receives the column address COL and the row address ROW and generates an ACT command. Alternatively, the row address ROW is selected. Then, the multiplexer 109 outputs the address ADR to the SDRAM 303. The ACT-T signal is output from the SDRAM control unit 113 to the multiplexer 109.

  For example, the multiplexer 109 selects the output value of the row address counter 107 based on the ACT-T signal, and selects the column address counter value otherwise. With this ACT-T signal, the address ADR of the row address ROW or the column address COL output to the SDRAM 303 can be selected.

  The above-mentioned column address counter 105 is connected to the SDRAM control unit 113 (control means), and a refresh operation is inserted outside the main scanning effective image area where no read (read) operation or write (write) operation is performed. The As described above, when the refresh operation is inserted outside the main scanning effective image area where the read operation or the write operation is not performed, high-speed access can be realized between the SDRAM control unit 113 and the SDRAM 303.

  The SDRAM control unit 113 receives an ACV signal, a CNT signal, an ACF signal, and carry signals C1 and C2, inputs an ACT command generation timing signal (hereinafter referred to as ACT-T signal), a row address strobe signal (hereinafter referred to as RAS signal), A column address strobe signal (hereinafter referred to as a CAS signal), a write enable signal (hereinafter referred to as a WE signal), a write timing signal (hereinafter referred to as a WV signal), and a read timing signal (write enable signal: hereinafter referred to as an RV signal) are generated. Data writing and reading are controlled.

  The command is composed of a RAS signal, a CAS signal, and a WE signal. The write command is composed of a RAS signal = Hi, a CAS signal = Lo, and a WE signal = Lo, and the SDRAM control unit 113 writes data to the address ADR input simultaneously with the read command. The read command is composed of a RAS signal = Hi, a CAS signal = Hi, and a WE signal = Lo, and the SDRAM control unit 113 reads data from the address ADR input simultaneously with the read command.

  For example, the SDRAM control unit 113 generates a read command, a write command, an RV signal, and a WV signal from the value of the CNT signal when the ACF signal is Hi. When the ACT-T signal is Hi, the RV signal is not Hi. The ACT-T signal is output from the SDRAM control unit 113 to the multiplexer 109. The RAS signal, CAS signal, and WE signal are output from the SDRAM control unit 113 to the SDRAM 303. The WV signal is output from the SDRAM control unit 113 to the FIFO memory 102. The RV signal is output from the SDRAM control unit 113 to the input / output signal separation unit 305 and the read timing FIFO memory 103.

  The SDRAM control unit 113 receives the carry signal C1, holds the carry signal C1 until the write operation is completed, asserts the ACT-T signal, and issues an ACT command, whereby the bank address BA and the row address ROW are obtained. To change. Further, after asserting the RV signal and outputting the read command to the SDRAM 303, the SDRAM control unit 113 waits for CAS latency (3CLK), and outputs the RV signal to the signal separation unit 305 and the FIFO memory 103 for read timing. .

  Further, the SDRAM control unit 113 is initialized when the CNT signal reaches a set value (the number of clocks required for reading / writing). When the SDRAM control unit 113 initializes the CNT signal, the address count comparison unit 108 increments the column address COL eight times, and if it overflows, increments the bank address BA.

  When the address count comparison unit 108 increments the bank address BA, the SDRAM control unit 113 sends a PRE command and an ACT command to the SDRAM 303. When sending an ACT command to the SDRAM 303, the SDRAM control unit 113 sends an ACT-T signal to the multiplexer 109 that selects the column address COL and the row address ROW, and outputs the row address ROW.

  When the above-described column address COL and bank address BA become the set values (image data amount for one main scan) and the SDRAM control unit 113 performs read / write, the column address COL and bank address BA are initialized, The address ROW is incremented. At this time, the reference signal generation unit 110 causes the ACV signal to fall from Hi to Lo.

  The timing signal for generating the maximum value of the CNT signal, the read command, the write command, RV, and WV varies depending on the type of the SDRAM 303 to be used and its operation frequency. In this example, an example of control in the SDRAM control unit 113 is shown in an operation timing chart of FIG. 5, a state transition diagram thereof is shown in FIG. 6, and an example of control of the SDRAM 303 is shown in operation flowcharts of FIGS.

  An SDRAM 303 is connected to the SDRAM control unit 113. The SDRAM 303 writes the image data Wy to the SDRAM 303 based on the address ADR, bank address BA, RAS signal, CAS signal, and WE signal, and the image data Wy based on the address ADR, bank address BA, RAS signal, and CAS signal. Control is performed to read from the SDRAM 303.

  The SDRAM 303 has a data bus width of 32 bits, a row address width of 13 bits, and a bank address BA of 2 bits. In this example, the maximum value of the main scanning effective image region is 7500 pixels, and one line is written in 100 μsec. Data writing / reading processing is performed on 1 pixel of the image data Din with a 1CLK signal.

  The image data Din (packing data DQ) is written to and read from the SDRAM 303 by 8-burst transfer in which 8 data (D1 to D8) are transferred continuously. In this example, the frequency of the data processing clock (CLK) signal of the line memory unit 81 and the operating frequency of the SDRAM 303 are set to the same 80 MHz.

  Further, since the packing data DQ handled by the line memory unit 81 is image data Din = Dy of the main scanning effective image area, it is not necessary to perform read and write operations outside the main scanning effective image area. It is not necessary to operate the bank counter 106 and the row address counter 107. In this example, the column address counter 105 and the like are not operated during a period in which the WHV signal and the RHV signal fall to Lo. An example of read and write operations in the SDRAM 303 is shown in FIG. 7, an example of precharge bank active operation is shown in FIG. 8, and an example of refresh operation is shown in FIG.

  A signal separator 305 is connected to the FIFO memory 102 and operates to separate the image data Dy at the time of writing and the image data Wy at the time of reading based on the RV signal. A read processing unit 306 is connected to the signal separation unit 305. The RV signal is output from the SDRAM control unit 113 to the signal separation unit 305.

  The read processing unit 306 is configured to include a FIFO memory 103 and a data unpacking unit 104. The FIFO memory 103 receives an RV signal and an output enable signal (hereinafter referred to as a REN signal) and operates to write packing data DQ (image data Dout = Wy) read from the SDRAM 303 into the data unpacking unit 104.

  The REN signal is a signal generated by delaying the RHV signal by the delay circuit 114. Thereby, the packing data DQ can be read to the data unpacking unit 104 based on the RV signal and the REN signal. The RV signal is output from the SDRAM control unit 113 to the FIFO memory 103 in addition to the signal separation unit 305.

  The data unpacking unit 104 operates so that image data Dout = Wy obtained by unpacking the packing data DQ read from the FIFO memory 103 is divided into pixels and supplied to the LD & driving unit 82 all at once. The unpacking process is a process for solving and outputting packed data.

  A Y-color LD & drive unit 82 is connected to the Y-color line memory unit 81, and the polygon drive system is based on the image data Dout read from the FIFO memory 103 of the line memory unit 81. Is exposed to light, and an electrostatic latent image for Y color is formed.

  The writing unit 3Y shown in FIG. 3 includes a Y-color line memory unit 81 and a Y-color LD & driving unit 82. The writing unit 3M includes a line memory unit 83 for M color and a LD & drive unit 84 for M color. The writing unit 3 </ b> C includes a line memory unit 85 for C color and an LD & drive unit 86 for C color. The writing unit 3K includes a line memory unit 87 for BK color and an LD & drive unit 88 for BK color.

  The writing units 3Y to 3K are connected to the control unit 15 described above. For the writing unit 3Y, the control unit 15 writes the image data Din = Dy of only the main scanning effective image region to the line memory unit 81 of the writing unit 3Y, and the image data Dout from the line memory unit 81 to the LD & driving unit 82. = Wy is read, and the refresh process of the line memory unit 81 of the writing unit 3Y is executed in a period in which the reading and writing of the image data Dout are not executed.

  Similarly, with respect to the writing unit 3M, the control unit 15 writes the image data Din = Dm of only the main scanning effective image region to the line memory unit 83 of the writing unit 3M, and the line memory unit 83 to the LD & driving unit 84. The image data Dout = Wm is read out, and the refresh process of the line memory unit 83 of the writing unit 3M is executed during the period when the reading and writing of the image data Dout are not executed.

  Further, the control unit 15 writes the image data Din = Dc of only the main scanning effective image region to the line memory unit 85 of the writing unit 3C and the image from the line memory unit 85 to the LD & driving unit 86 regarding the writing unit 3C. The data Dout = Wm is read, and the refresh process of the line memory unit 85 of the writing unit 3C is executed during a period when the reading and writing of the image data Dout are not executed.

  Further, with respect to the writing unit 3K, the control unit 15 writes the image data Din = Dk of only the main scanning effective image region to the line memory unit 87 of the writing unit 3K, and the image from the line memory unit 87 to the LD & driving unit 88. The data Dout = Wk is read, and the refresh process of the line memory unit 87 of the writing unit 3K is executed during a period when the reading and writing of the image data Dout are not executed.

  The refresh process (operation) is performed for every row address at a rate of once every 64 msec. In this example, the refresh process may be performed only 8192 times within 64 msec. Here, assuming that the exposure time of one line is 100 μsec, there are 640 lines in 64 msec), so the refresh process is performed only 8192/640 = 12.8≈13 times in one line. Since the exposure time for one line is 100 μsec, the interval of the synchronization signal (Y-IDX signal) used for timing of writing the image data Wy to the photosensitive drum 1Y is 8000 CLK when the SDRAM clock is 80 MHz.

  5A to 5H are time charts showing examples of control signals in the line memory unit 81 and the like. The CLK signal shown in FIG. 5A is not shown in FIG. 4, but the reference signal generation unit 110, the read / write control counter 111, the storage capacity determination unit 112, the SDRAM control unit 113, the address generation unit 301, the SDRAM 303, the write This is an SDRAM clock supplied to the processing unit 304, the signal separation unit 305, and the read processing unit 306. In this example, the SDRAM clock is 80 MHz.

  The RIND signal shown in FIG. 5B is an index signal on the read side, and in the case of the writing unit 3Y, is a Y-IDX signal output from the LD & drive unit 82 for Y color. The RIND signal is output from the laser index sensor 49 to the reference signal generation unit 110 via the control unit 15 at the head of the deflection scanning of the laser beam light by the polygon drive system.

  The ACV signal shown in FIG. 5C is a write-side reference access valid signal, and is a signal generated by the reference signal generation unit 110 with reference to the RIND signal (= Y-IDX signal). The reference signal generator 110 raises the ACV signal to Hi when writing the image data Din.

  The WFWADR signal shown in FIG. 5D is a write address signal (data accumulation amount detection signal) indicating the amount of image data Din, and is a signal output from the FIFO memory 102 to the accumulation capacity determination unit 112. The WWFAD signal is a signal indicating the amount of image data Din when the amount of image data Din stored in the FIFO memory 102 is detected by the FIFO memory 102. The WWFAD signal is output from the FIFO memory 102 to the storage capacity determination unit 112. The WFWADR signal is indicated by write address signals “2” to “3213” in the drawing.

  The WEN signal shown in FIG. 5E is an effective image area signal (write enable signal), and is a signal obtained by performing an AND operation on the write side WHV signal and the WVV signal by the 2-input AND circuit 99. The WEN signal is output from the 2-input AND circuit 99 to the data packing unit 101.

  The ACF signal shown in FIG. 5F is a reference access flag signal, and is a signal generated when the storage capacity determination unit 112 determines the amount of data stored in the FIFO memory 102 in response to the ACV signal. For example, when the ACV signal becomes Hi, the WFWAD signal is output from the FIFO memory 102 to the storage capacity determination unit 112, and the signal indicating the maximum shake amount setting value reflected in the Y-IDX signal is compared with the WFWAD signal. The The maximum blur amount setting value is set by the maximum value of the period shift amount predicted in the reference IDX signal by the polygon driving system writing method.

  If it is determined by the storage capacity determination unit 112 that the FIFO memory 102 stores image data Din that is greater than or equal to the maximum blur amount setting value, the ACF signal is raised to Hi. If it is determined that only image data Din less than the maximum blur amount setting value is stored, the ACF signal is kept at the low level (hereinafter referred to as Lo). If it is determined that image data Din greater than the maximum blur amount set value is stored in the FIFO memory 102, the ACF signal is raised to Hi based on the next ACV signal. The ACF signal is output from the storage capacity determination unit 112 to the SDRAM control unit 113.

  The CNT signal = clock “0” shown in FIG. 5G is a read / write control signal, and the read / write control counter 111 counts the ACV signal and outputs it to the SDRAM control unit 113. “0” is incremented when the ACV signal is Hi. In this example, the CNT signal is incremented every 0-18 CLK.

  The carry signal C0 shown in FIG. 5H is a signal generated every time the read / write control counter 111 counts up the ACV signal. In this example, the carry signal C0 is output to the column address counter 105 when the CNT signal is counted up at 18 CLK. Even when the signal period of the RIND signal fluctuates, the line memory unit 81 and the like are controlled by these control signals, so that the writing and reading of the image data Din in the SDRAM 303 can be executed without excess or deficiency (failure). .

  In the above example, even if the ACV signal shown in FIG. 5C rises to Hi and the ACF signal shown in FIG. 5F falls to Lo, the specified amount of data is not stored in the FIFO memory 102 (I ). When the ACV signal shown in FIG. 5C rises to Hi and the ACF signal shown in FIG. 5F rises to Hi, the specified amount of data is stored in the FIFO memory 102 (II).

  FIG. 6 is a state transition diagram showing an operation example of the SDRAM control unit 113. According to the state transition of the SDRAM control unit 113 shown in FIG. 6, the initial state is the standby state, and when the ACV signal becomes “1”, the standby state is changed to the read cycle.

  When the read / write control counter 111 counts the ACV signal in the read cycle and the CNT signal becomes the clock “11”, the read cycle shifts to the write cycle. In the write cycle, the read / write control counter 111 counts the ACV signal and the CNT signal = clock “18”. At this time, if the carry signal C1 is “0”, the read cycle is entered. If carry signal C1 is “1”, transition is made to bank switching. If the carry signal C2 is “1”, a transition is made to a refresh cycle (operation).

  When the bank is switched, the read / write control counter 111 counts the ACV signal, and “0” becomes the clock “3”, and a transition is made to the read cycle. In the refresh cycle, the read / write control counter 111 counts the ACV signal and becomes REF-CNT signal = clock “13”. If the ACT-T signal is “1”, the state shifts to the standby state.

  As a result, the first cycle of returning from the standby state of the SDRAM control unit 113 to the read cycle → write cycle → refresh cycle → standby state can be executed. Further, from the standby state, the read cycle → write cycle → bank switching → read cycle → write cycle → bank switching → read cycle → write cycle → refresh cycle → second cycle to return to the standby state or from the standby state to the read cycle → Write cycle-> Read cycle-> Write cycle-> Bank switch-> Read cycle-> Write cycle-> Read cycle-> Write cycle-> Refresh cycle-> Third cycle to return to standby state, and read cycle-> Write cycle-> Read cycle-> from the standby state Write cycle-> bank switch-> read cycle-> write cycle-> bank switch-> read cycle-> write cycle-> refresh cycle-> 4th cycle to return to standby state can be executed .

Next, an operation example in the SDRAM 303 will be described. In this example, the description will be divided into three parts: a read and write operation, a precharge bank active operation, and a refresh operation.
[Read and write operation example]
7A to 7P are operation timing charts showing an example of read and write operations in the SDRAM 303. FIG. According to the SDRAM 303 of this example, the ACV signal shown in FIG. 7A, the column address COL + bank address BA shown in FIG. 7B, the row address shown in FIG. 7C, the carry signal C2 shown in FIG. 7D, and the CLK signal (CLK) shown in FIG. 7F, CAS signal shown in FIG. 7G, WE signal shown in FIG. 7H, CNT signal shown in FIG. 7I, carry signal C0 shown in FIG. 7J, carry signal C1 shown in FIG. 7K, ACT shown in FIG. Based on the -T signal, the WV signal shown in FIG. 7M, the RV signal shown in FIG. 7N, and the address ADR shown in FIG. 7O, the packing data DQ shown in FIG. 7P is read. The packing data DQ becomes image data Dout = Wy after the unpacking processing.

  In this example, the read operation is started based on the ACV signal shown in FIG. 7A and the CLK signal shown in FIG. 7E. One cycle of the ACV signal is 100 μsec. In the column address COL + bank address BA shown in FIG. 7B, the address is incremented every “8” in order to execute 8-burst transfer for updating the column address COL.

  In this example, when the column address COL + bank address BA is “3192”, the carry signal C1 shown in FIG. 7D rises, the carry signal C2 shown in FIG. 7D (Lo in the initial state) rises, and the column address COL and the bank The address BA is initialized. The row address shown in FIG. 7C is incremented from “0” to “1” when the column address COL + bank address BA is “3192”. The carry signal C1 shown in FIG. 7K remains Lo.

  In this example, when the column address COL + bank address BA is “8”, a read command (READ) is issued in synchronization with the rising edge of the CLK signal shown in FIG. 7E. In the read command, the RAS signal shown in FIG. 7F is Hi, the WE signal shown in FIG. 7H is Hi, and the CAS signal shown in FIG. 7G is Lo. The read command is issued when the CNT signal shown in FIG. 7I is the clock “0” and the ACT-T signal shown in FIG. 7J is Lo.

  Thereafter, when the RV signal shown in FIG. 7N transitions to “1” in the period of CNT signal = clock “3” to clock “10” shown in FIG. 7I with a delay of 3 clocks, the address ADR shown in FIG. Based on the above, the packing data DQ shown in FIG. The packing data DQ (D1 to D8) is read only during the period when the RV signal shown in FIG. 7N is Hi.

  In the write operation of this example, when the column address COL + bank address BA is “8”, a write command (WRITE) is issued in synchronization with the rise of the CLK signal shown in FIG. 7E. In the write command, the RAS signal shown in FIG. 7F is Hi, the WE signal shown in FIG. 7H falls from Hi to Lo, the WV signal shown in FIG. 7M is Lo, and the CAS signal shown in FIG. 7G is Lo. It is. The write command is issued when the CNT signal shown in FIG.

  In the period of CNT signal = clock “11” to “18” shown in FIG. 7I, packing data DQ shown in FIG. 7P is written into the SDRAM 303 based on the address ADR shown in FIG. In this example, the carry signal C1 (Lo in the initial state) shown in FIG. 7K rises with the CNT signal = clock “18”.

  The packing data DQ (D1 to D8) is written during the period when the RV signal shown in FIG. 7N is Lo. The packing data DQ is obtained by packing image data Din = Dy. Accordingly, eight packing data DQ (= D1 to D8) can be sequentially burst transferred to the SDRAM 303 based on the output of the write command.

[Example of precharge bank active operation]
8A to 8N are operation timing charts showing an example of the precharge bank active operation in the SDRAM 303. FIG. According to the SDRAM 303 of this example, the ACV signal shown in FIG. 8A, the column address COL + bank address BA shown in FIG. 8B, the CLK signal shown in FIG. 8C, the RAS signal shown in FIG. 8D, the CAS signal shown in FIG. 8G, CNT signal shown in FIG. 8H, carry signal C0 shown in FIG. 8H, carry signal C1 shown in FIG. 8I, ACT-T signal shown in FIG. 8J, WV signal shown in FIG. 8K, RV signal shown in FIG. The precharge bank active operation is executed based on the address ADR shown in FIG. 8M.

  In this example, in the period in which the column address COL + bank address BA shown in FIG. 8B shifts from “1016” to “1024”, the precharge bank active operation is started based on the CLK signal shown in FIG. The At this time, the RV signal shown in FIG. 8E and the WV signal shown in FIG. 8K remain Lo. Regarding the column address COL + bank address BA, when the column address COL overflows, the bank address BA is incremented.

  In this example, the CNT signal shown in FIG. 8G = clock “18”, and the write operation ends. Then, when carry signal C0 shown in FIG. 8H (Lo in the initial state) and carry signal C1 shown in FIG. 8I (Lo in the initial state) rise to Hi, a pre-command (PRE) is issued.

  The ACT command (ACT) is issued 2 CLK after the rising edge of the CLK signal at the time when the pre-command (PRE) is issued. With the CNT signal = clocks “1” to “3” shown in FIG. 8G, the RAS signal shown in FIG. 8D transitions from Lo → Hi again, and the address ADR shown in FIG. 8M is generated and output to the SDRAM 303. The address ADR is the row address ROW. Based on the row address ROW, the SDRAM 303 can be activated in a precharge bank.

  Thereafter, a read command (READ) is issued. In the read operation, the packing data DQ shown in FIG. 8N is read from the SDRAM 303 based on the address ADR (COL) shown in FIG. 8M. Packing data DQ (D1 to D8) is read only during a period when the RV signal shown in FIG. 8L is Hi. Accordingly, the packing data DQ write operation and the packing data DQ read operation shown in FIG. 8N based on the address ADR shown in FIG. 8M based on the ACV signal, the CLK signal, the ACT-T signal, and the CNT signal = clock “0”. In the meantime, the precharge bank active operation can be executed.

[Example of refresh operation]
9A to 9L are operation timing charts showing an example of the refresh operation in the SDRAM 303. FIG. According to the SDRAM 303 of this example, the CLK signal shown in FIG. 9B, the RAS signal shown in FIG. 9C, the CAS signal shown in FIG. 9D, the WE signal shown in FIG. 9E, the CNT signal shown in FIG. 9F = clock “0”, FIG. The refresh operation is executed based on the ACT-T signal shown in FIG. 9 and the REF-CENT signal shown in FIG. 9L. FIG. 9K shows address ADR = row address ROW.

  In this example, when the ACV signal shown in FIG. 9A transitions to Lo, the refresh operation is started based on the CLK signal shown in FIG. 9B. At this time, the WV signal shown in FIG. 9H and the RV signal shown in FIG. 9I remain Lo, and the address ADR shown in FIG. 9J is not generated. The pre-command (PRE) is issued when the RAS signal = Lo, the CAS signal = Hi, and the WE signal = Lo.

  A refresh command (REF) shown in FIG. 9B is issued 2 CLK after the rising edge of the CLK signal shown in FIG. 9B when the above-described PRE command is issued. The REF command is RAS signal = Lo, CAS signal = Lo, and WE signal = Hi. Thereafter, the REF command is issued every 5 CLK from the rising edge of the CLK signal shown in FIG. 9B. In this example, 13 refresh operations are executed with CNT signal = clock “0” and REF−CNT = clock “1” to “13” shown in FIG. 9F.

  In this example, when the ACT-T signal shown in FIG. 9G becomes Hi, the precharge bank active operation is started. Address ADR shown in FIG. 9J is generated and output to SDRAM 303. In the precharge bank active operation, the address ADR is the row address ROW. A refresh operation can be inserted outside the main scanning effective image area, and loss during the access of the SDRAM 303 can be reduced. In addition, the control unit 15, the SDRAM control unit 113, and the like can access the SDRAM 303 at high speed.

  Next, an example of delay processing in the line memory unit 81 will be described. In this example, the Y-IDX signal is generated based on the reference IDX signal, the WHV signal is generated according to the Y-IDX signal, and when the Y-IDX signal varies, the WHV signal and the RHV signal also vary. Based on these assumptions, the SDRAM control unit 113 sends a read command to the SDRAM 303 and stores the packing data DQ in the read timing FIFO memory 103 using the RV signal.

  The FIFO memory 103 reads the packing data DQ as read data Dout to the data unpacking unit 104 using a signal obtained by delaying the RHV signal. In this SDRAM 303, the delay amount of the RHV signal is determined by the number of clocks required for sending the read command to the SDRAM 303 and the packing data DQ being output from the SDRAM 303 to the FIFO memory 103, and the time difference (distance) between the RIND signal and the RHV signal. ).

  10A to 10M are operation time charts showing a delay processing example (part 1) in the line memory unit 81. FIG. According to the first delay processing example in the line memory unit 81 shown in FIG. 4, the main scanning effective image area signal (RHV signal) on the read side shown in FIG. 10F and the main scanning effective image on the write side shown in FIG. 10A. The control example in the case where the phase with the region signal (WHV signal) is in phase (synchronization) is shown.

  In this example, according to the first delay processing example in the line memory unit 81, there is no phase difference between the reference IDX signal and the Y-IDX signal (RIND signal). In the case of a system in which the WHV signal and the RHV signal are synchronized, the ACV signal is raised in synchronization with the rise of the WHV (RHV) signal. For example, this is a case where 5-line image data is delayed by 3 lines in the sub-scanning direction.

  In this example, the period in which the WHV signal shown in FIG. 10A is Hi is the image effective area in the main scanning direction. During the period when WVV shown in FIG. 10B is Hi, the WHV signal shown in FIG. 10A is Hi five times. The WEN signal shown in FIG. 10C is Hi five times in synchronization with the WHV signal during the period when the WVV signal is Hi.

  In the write operation in this example, the write timing FIFO memory 102 delays one line and writes to the SDRAM 303. The ACV signal shown in FIG. 10D rises in synchronization with the reference (rise) of the WHV signal and falls when the image data for one line is read / written.

  In the ACF signal shown in FIG. 10E, the rising timing of the WHV signal and the ACV signal is the same, and therefore, the image data of the specified amount or more is not stored in the write timing FIFO memory 102. Stand up in sync with. Therefore, the write timing FIFO memory 102 delays one line. Therefore, the delay amount in the SDRAM 303 is two lines.

  The row address ROW shown in FIG. 10L repeats 0 → 1 → 0 → 1 because the delay amount in the SDRAM 303 is two lines. The RHV signal shown in FIG. 10F is synchronized with the WHV signal. Since the RVV signal shown in FIG. 10G is delayed in the 3-line sub-scanning direction, it rises at a timing delayed by 3 lines from the WVV signal. The REN signal shown in FIG. 10H is Hi five times in synchronization with the RHV signal during the period when the RVV signal is Hi.

  The bank address BA + column address COL shown in FIG. 10M counts one line of packing data. In this example, since the image data of the first line is stored in the SDRAM 303 when the address ADR is the row address ROW = “1”, next, from the SDRAM 303 when the address ADR is the row address ROW = “1”. Image data is read out. Image data delayed by three lines can be obtained in the period in which the RVV signal is Hi and the RHV signal is Hi in FIG. 10G.

  The write operation and the read operation are performed only when the ACV signal is Hi, and the refresh operation is performed while the ACV signal is Lo. As a result, when the RHV signal on the read side and the WHV signal on the write side are in phase (synchronization), the line memory unit 81 can execute control of writing / reading the image data Din in the SDRAM 303 (first). 1 delay processing).

  11A to 11M are operation time charts showing a delay processing example (part 2) in the line memory unit 81. FIG. According to the second delay processing example in the line memory unit 81 shown in FIG. 4, when the read-side RHV signal and the write-side WHV signal have different phases (with phase difference), This is an example of control when it is confirmed that the image data Din is stored in the timing FIFO memory 102 and the specified amount of image data Din is stored.

  In this example, according to the second delay processing example in the line memory unit 81, a phase difference is generated between the reference IDX signal and the Y-IDX signal (RIND signal). For example, this is a case where 5-line image data is delayed by 3 lines in the sub-scanning direction. A period in which the WHV signal shown in FIG. 11A is Hi is an image effective area in the main scanning direction. In this example, the WHV signal shown in FIG. 11A is Hi five times during the period when the WVV signal shown in FIG. 11B is Hi. The WEN signal shown in FIG. 11C is Hi five times in synchronization with the WHV signal during the period when the WVV signal is Hi.

  In the write operation in this example, the write timing FIFO memory 102 delays one line and writes to the SDRAM 303. The ACV signal shown in FIG. 11D rises in synchronization with the reference (rise) of the WHV signal, and falls when the read / write operation is performed on image data for one line.

  The ACF signal shown in FIG. 11E rises in synchronization with the rise of the ACV signal on the second day because the difference in the rise timing of the WHV signal and the ACV signal is less than the specified amount. In the write timing FIFO memory 102, a one-line delay occurs, so the delay amount in the SDRAM 303 is two lines.

  The row address ROW shown in FIG. 11L repeats 0 → 1 → 0 → 1 because the delay amount in the SDRAM 303 is two lines. The RHV signal (which depends on the RIND signal) shown in FIG. 11F is different in phase from the WHV signal and rises. Since the RVV signal shown in FIG. 11G is delayed in the 3-line sub-scanning direction, it rises at a timing delayed by 3 lines from the WVV signal.

  The REN signal shown in FIG. 11H is Hi five times in synchronization with the RHV signal during the period when the RVV signal is Hi. The bank address BA + column address COL shown in FIG. 11M counts packing data for one line. Since the image data of the first line is stored in the SDRAM 303 when the address ADR is the row address ROW = “1”, the image data is read from the SDRAM 303 when the address ADR is next the row address ROW = “1”. .

  Image data delayed by three lines can be obtained in a period in which the RVV signal shown in FIG. 10G is Hi and the RHV signal is Hi. The write operation and the read operation are performed only when the ACV signal is Hi, and the refresh operation is performed while the ACV signal is Lo. As a result, when there is a phase difference between the read-side RHV signal and the write-side WHV signal, the line memory unit 81 can execute the read / write control of the image data Din in the SDRAM 303 (first step). 2 delay processing).

  12A to 12M are operation time charts showing a delay processing example (part 3) in the line memory unit 81. FIG. According to the third delay processing example in the line memory unit 81 shown in FIGS. 12A to 12M, the phase of the read-side RHV signal and the write-side WHV signal are different (there is a phase difference). This is an example of control when image data Din is stored in the FIFO memory 102 but a specified amount of image data Din is not stored.

  In this example, according to the second delay processing example in the line memory unit 81, a phase difference is generated between the reference IDX signal and the Y-IDX signal (RIND signal). For example, this is a case where 5-line image data is delayed by 3 lines in the sub-scanning direction. A period in which the WHV signal shown in FIG. 12A is Hi is an image effective area in the main scanning direction. In this example, the WHV signal shown in FIG. 12A is Hi five times during the period when the WVV signal shown in FIG. 12B is Hi. The WEN signal shown in FIG. 12C is Hi five times in synchronization with the WHV signal during the period when the WVV signal is Hi.

  In the write operation in this example, the write timing FIFO memory 102 delays one line and writes to the SDRAM 303. The ACV signal shown in FIG. 12D rises in synchronization with the reference (rise) of the WHV signal, and falls when the read / write operation is performed on image data for one line.

  The ACF signal shown in FIG. 12E rises in synchronization with the second rise of the ACV signal because the difference between the rise timings of the WHV signal and the ACV signal is less than the specified amount. In the write timing FIFO memory 102, a one-line delay occurs, so the delay amount in the SDRAM 303 is two lines.

  The row address ROW shown in FIG. 12L repeats 0 → 1 → 0 → 1 because the delay amount in the SDRAM 303 is two lines. The RHV signal (which depends on the RIND signal) shown in FIG. 12F is different in phase from the WHV signal and rises. Since the RVV signal shown in FIG. 12G is delayed in the 3-line sub-scanning direction, it rises at a timing delayed by 3 lines from the WVV signal.

  The REN signal shown in FIG. 12H is Hi five times in synchronization with the RHV signal during the period when the RVV signal is Hi. The bank address BA + column address COL shown in FIG. 12M counts one line of packing data. Since the image data of the first line is stored in the SDRAM 303 when the address ADR is the row address ROW = “1”, the image data is read from the SDRAM 303 when the address ADR is next the row address ROW = “1”. .

  Image data delayed by three lines can be obtained in a period in which the RVV signal shown in FIG. 10G is Hi and the RHV signal is Hi. The write operation and the read operation are performed only when the ACV signal is Hi, and the refresh operation is performed while the ACV signal is Lo. Thus, when there is a phase difference between the read-side RHV signal and the write-side WHV signal, and the FIFO memory 102 stores only less than the specified amount of image data Din, the line memory The unit 81 can execute writing / reading control of the image data Din in the SDRAM 303 (third delay processing).

  Next, a control example in the SDRAM 303 will be described. FIGS. 13 and 14 are operation flowcharts showing delay processing examples (Nos. 1 and 2) using the SDRAM 303. In this example, assuming that the SDRAM control unit 113 shown in FIG. 6 controls the SDRAM 303, the first cycle from the standby state to return to the read cycle → write cycle → bank switching → refresh cycle → standby state is executed. An example is given below. As for the level of each signal, Hi is “1” and Lo is “0”.

  With this as a control condition, first, the SDRAM control unit 113 initially sets the FIFO memories 102 and 103 and the SDRAM 303 in step ST1 of the flowchart shown in FIG. For example, the SDRAM control unit 113 executes a process of clearing each counter and setting “0”.

  Next, in step ST2, the SDRAM control unit 113 determines whether the ACF signal is “1” or the ACF signal is “0”. If the ACF signal is “0”, the process proceeds to step ST3 to determine whether the ACV signal has become “1”. If the ACV signal is not “1”, it waits until the ACV signal becomes “1”.

  When the ACV signal becomes “1”, the process proceeds to step ST4, and the SDRAM control unit 113 determines whether or not the designated amount of image data Din is stored in the FIFO memory 102 on the writing side. In this example, the storage capacity determination unit 112 determines WFWADR> A. WFWADR is an address on the writing side. A is a maximum shake amount setting value set by the maximum value of the period shift amount predicted in the reference IDX signal by the polygon driving system writing method.

  If the storage capacity determination unit 112 determines that image data Din greater than or equal to the maximum blur amount setting value is stored in the FIFO memory 102, the ACF signal is raised to “1”. If it is determined that only image data Din less than the maximum blur amount setting value is stored, the ACF signal is kept lowered to “0” (see FIG. 5F).

  When WFWADR> A, the process proceeds to step ST5, and the SDRAM control unit 113 executes a read cycle. According to this read cycle, as shown in FIGS. 7A to 7P, a read operation is started based on the ACV signal shown in FIG. 7A and the CLK signal shown in FIG. 7E. One cycle of the ACV signal is 100 μsec. In the column address COL + bank address BA shown in FIG. 7B, the address is incremented every “8” in order to execute 8-burst transfer for updating the column address COL.

  In this example, when the column address COL + bank address BA is “3192”, the carry signal C1 shown in FIG. 7K rises, the carry signal C2 shown in FIG. 7D (“0” in the initial state) rises, and the column address COL The bank address BA is initialized. The row address ROW shown in FIG. 7C is incremented from “0” to “1” when the column address COL + bank address BA is “3192”. The carry signal C1 shown in FIG. 7K remains “0”.

  In this example, when the column address COL + bank address BA is “8”, a read command (READ) is issued in synchronization with the rising edge of the CLK signal shown in FIG. 7E. In the read command, the RAS signal shown in FIG. 7F is “1”, the WE signal shown in FIG. 7H is “1”, and the CAS signal shown in FIG. 7G is “0”.

  When the read command is issued, counting up starts from the CNT signal = clock “0” shown in FIG. 7I, and the address ADR shown in FIG. 7O is generated and output to the SDRAM 303. When the RV signal shown in FIG. 7N transitions to “1” in the period from the CNT signal = clock “3” to the clock “10” shown in FIG. 7I with a delay of 3 clocks, the address ADR shown in FIG. Based on the above, the packing data DQ shown in FIG. The packing data DQ (D1 to D8) is read only during the period when the RV signal shown in FIG. 7N is “1”.

  Thereafter, the process proceeds to step ST6, and the SDRAM control unit 113 executes a write cycle. In this write cycle, when the column address COL + bank address BA is “8” as shown in FIGS. 7A to 7P, a write command (WRITE) is issued in synchronization with the rise of the CLK signal shown in FIG. 7E. In the write command, the RAS signal shown in FIG. 7F is “1”, the WE signal shown in FIG. 7H is “0”, and the CAS signal shown in FIG. 7G is “0”.

  When the write command is issued, the count-up continues from the CNT signal = clock “11” shown in FIG. 7I, and the address ADR shown in FIG. 7O is generated and output to the SDRAM 303. In this example, when the CNT signal shown in FIG. 7I = clock “11” to “18” and the RV signal shown in FIG. 7N transitions from “1” to “0”, the address ADR shown in FIG. Based on this, packing data DQ shown in FIG. In this example, the carry signal C1 (“0” in the initial state) shown in FIG. 7K rises with the CNT signal = clock “18”.

  The packing data DQ (D1 to D8) is written during a period in which the RV signal shown in FIG. 7N is “0”. The packing data DQ is obtained by packing image data Din = Dy. Thus, eight packing data DQ (= D1 to D8) can be sequentially burst transferred to the SDRAM 303 based on the issuance of the write command.

  Thereafter, the process proceeds to step ST7, where it is determined whether the column address counter 105 + bank counter 106 has counted one line of packing data. When the packing data for one line is counted, the carry signal C2 becomes 1, and this can be determined by comparing with the reference level.

  If the column address counter 105 + bank counter 106 has not counted one line of packing data, the process proceeds to step ST8, and the SDRAM control unit 113 determines whether the column address counter 105 has overflowed. When the column address counter 105 overflows, the carry signal C1 becomes “1”, which may be determined by comparing it with the reference level. If the column address counter 105 does not overflow, the process returns to step ST2 and the above-described step processing is repeated.

  When the column address counter 105 overflows, the process moves to step ST9, and the SDRAM control unit 113 executes bank switching processing. According to this bank switching process, as shown in FIGS. 8A to 8N, for example, in the period in which the column address COL + bank address BA shown in FIG. 8B shifts from “1016” to “1024”, the write operation is continued. Based on the CLK signal shown in FIG. 8C, the precharge bank active operation is started.

  At this time, the WV signal shown in FIG. 8E and the RV signal shown in FIG. 8E remain “0”. Regarding the column address COL + bank address BA, when the column address COL overflows, the bank address BA is incremented.

  In this example, the CNT signal shown in FIG. 8G = clock “18”, and the write operation ends. Then, when carry signal C1 (“0” in the initial state) shown in FIG. 8H rises to “1”, a precharge command (PRE) is issued. The ACT command is issued 2 CLK after the rising edge of the CLK signal at the time when the precharge command (PRE) is issued.

  Simultaneously with the ACT command, the row address ROW is passed to the address ADR shown in FIG. 8M. Thereafter, the process returns to step ST2. When the column address counter 105 + bank counter 106 counts one line of packing data, the process proceeds to step ST10 and the SDRAM control unit 113 sets ACV = “0”.

  Then, in step ST11, the SDRAM control unit 113 executes a fresh cycle. According to this refresh cycle, as shown in FIGS. 9A to 9L, when the ACV signal transitions to “0”, the refresh operation is started based on the CLK signal shown in FIG. 9B. At this time, the WV signal shown in FIG. 9H and the RV signal shown in FIG. 9I remain “0”, and the address ADR shown in FIG. 9J is not generated. The PRE command is RAS signal = “0”, CAS signal = “1”, and WE signal = “0”.

  A refresh command (REF) shown in FIG. 9B is issued 2 CLK after the rising edge of the CLK signal shown in FIG. 9B when the above-described PRE command is issued. The REF command is RAS signal = “0”, CAS signal = “0”, and WE signal = “1”. Thereafter, the REF command is issued every 5 CLK from the rising edge of the CLK signal shown in FIG. 9B. In this example, 13 refresh operations are executed with CNT signal = clock “0” and REF−CNT = clock “1” to “13” shown in FIG. 9F. Thereafter, the process returns to step ST2.

  When the ACF signal is “0” in the above-described step ST2, the process proceeds to step ST12, and the SDRAM control unit 113 determines whether the ACV signal is “1”. If the ACV signal is not “1”, the SDRAM control unit 113 waits until the ACV signal becomes “1”. When the ACV signal becomes “1”, the process proceeds to step ST5, and the read / write cycle and the refresh cycle shown in steps ST5 to ST11 are repeated as described above.

  If WFWADR> A is not satisfied in step ST4 described above, the process proceeds to step ST13, where the SDRAM control unit 113 stores the specified amount of image data Din in the write side FIFO memory 102 (whether WFWADR> 0). ). When WFWADR> 0, the process proceeds to step ST14, and the SDRAM control unit 113 calculates the delay amount−1. Thereafter, the process proceeds to step ST15, and the SDRAM control unit 113 sets a one-line delay amount.

  Thereafter, the process returns to step ST2. Then, as described above, step ST2 to step ST4 or step ST2 to step ST11 are repeated. As a result, a write / read cycle, a fresh cycle, and the like can be executed based on the ACF signal and the ACV signal.

  As described above, according to the color printer 100 as the embodiment, the laser index sensor 49 detects the scanning period of the laser beam light scanned on the photosensitive drum 1Y and generates the Y-IDX signal. The IDX signal is output to the control unit 15. The controller 15 outputs the Y-IDX signal to the reference signal generator 110 as a RIND signal. The reference signal generation unit 110 generates an ACV signal for memory control based on the RIND signal.

  On the other hand, in the SDRAM 303 for inter-drum delay, the delay amount is set for each image forming unit and the image data Din is stored. On the premise of this, the SDRAM control unit 113 writes the image data Din of only the main scanning effective image region into the SDRAM 303 based on the ACV signal output from the reference signal generation unit 110, and executes the reading from the SDRAM 303. .

  Therefore, in the polygon driving system, even when the cycle of the Y-IDX signal fluctuates, the SDRAM 303 can be accessed at high speed and a color image can be formed at high speed. In addition, the number of times the PRE command and the ACT command are generated can be reduced, and even when the delay amount fluctuates as in the polygon driving system writing unit 3Y, the reading and writing processing of the image data Din is performed. Can be applied to.

  In the above-described embodiment, the case where the polygon drive type writing unit 3Y is used as the image forming unit has been described. However, the present invention is not limited to this, and an LPH (LED Print Head) unit is used instead of the writing unit 3Y. May be adopted. In the LPH unit, LED light sources are arranged in a line so as to face the photosensitive drum 1Y, and batch exposure based on image information is possible in units of lines.

  According to the present invention, an image forming unit that has a polygon drive system and forms a color image on a photosensitive drum is provided for each image forming color, and the color image formed by each image forming unit is displayed on the image carrier. The present invention is extremely suitable when applied to tandem color printers, color copiers, and these color multi-function machines.

1Y, 1M, 1C, 1K Photosensitive drum (image carrier)
2Y, 2M, 2C, 2K charger 3Y, 3M, 3C, 3K Writing unit (image forming unit)
4Y, 4M, 4C, 4K Development unit (image forming unit)
6 Intermediate transfer belt (image carrier)
10Y, 10M, 10C, 10K Image forming unit (image forming unit)
15 Control unit (control means)
49 Laser index sensor (scanning light detector)
81, 83, 85, 87 Line memory unit 82, 84, 86, 88 LD & drive unit 80 Image forming unit 99 2-input AND circuit 100 Color printer 101 Data packing unit 102 FIFO memory for write timing 103 FIFO for read timing Memory 104 Data unpacking section
105 column address counter 106 bank counter 107 row address counter 108 address count comparison unit 109 multiplexer 110 reference signal generation unit (signal generation unit)
111 Read / Write Control Counter 112 Storage Capacity Determination Unit 113 SDRAM Control Unit 114 Delay Circuit 301 Address Generation Unit 303 SDRAM (Storage Unit)
304 Write processing unit 305 Signal separation unit 306 Read processing unit

Claims (5)

An image forming unit for forming a color image by scanning light based on image information on a photosensitive drum having a rotation axis is provided for each image forming color, and the color image formed by each of the image forming units is image-supported. In a tandem color image forming apparatus that is superimposed on the body,
A scanning light detector for detecting a scanning period of light scanned on the photosensitive drum;
A signal generation unit that creates a reference signal for memory control based on a scanning cycle signal obtained from the scanning light detection unit;
A storage means for inter-drum delay for storing the image information in which a delay amount is set for each image forming unit;
A direction along the rotation axis of the photosensitive drum is a main scanning direction, an area that restricts image writing in the main scanning direction is a main scanning effective image area, and the image information of only the main scanning effective image area is the signal. A color image forming apparatus comprising: a control unit that writes to and reads from the storage unit based on a reference signal obtained from a generation unit. In the image forming unit,
A writing unit that scans light based on image information is provided on the photosensitive drum,
The control means includes
2. The color image forming apparatus according to claim 1, wherein a memory control for accessing the address of the image information read from the storage unit to the writing unit and writing the next image information at the address is executed. . The writing unit includes
3. The color image according to claim 2, further comprising a polygon driving unit that is disposed opposite to the photosensitive drum and that scans light and that can perform scanning exposure processing based on image information in units of one line. Forming equipment. The control means includes
2. The color image forming apparatus according to claim 1, wherein a refresh process of the storage unit is executed during a period in which the reading and writing of the image information are not executed. An image forming unit for forming a color image by scanning light based on image information on a photosensitive drum having a rotation axis is provided for each image forming color, and the color image formed by each of the image forming units is image-supported. In an image processing method in a tandem color image forming apparatus for superimposing on a body,
Detecting a scanning period of light scanned on the photosensitive drum;
Creating a reference signal for memory control based on the detected scanning cycle signal;
Storing a delay amount for each image forming unit and storing the image information;
A direction along the rotation axis of the photosensitive drum is a main scanning direction, an area that restricts image writing in the main scanning direction is a main scanning effective image area, and the image information of only the main scanning effective image area is the reference. An image processing method comprising: writing to the storage unit based on a signal and reading from the storage unit.

Images