JP2010171384A - Simulation device and method for designing semiconductor device, semiconductor device, and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a simulation method for designing a semiconductor device estimating or reproducing the operation of the semiconductor device in practically acceptable time and with high precision. <P>SOLUTION: In the simulation method, between the source and the drain, at least a portion of a difference between a carrier density described in a quasi-static steady state at a first time, and a carrier density described in a transient state at a second time preceding the first time, is added to the carrier density described in a transient state at the second time, depending on a carrier's delay between the first time and the second time, and the carrier density of the first time is described in a transient state. A transient current between the source and the drain is described as the total of a steady-state current and a displacement current regarding as a time variation proportion of a quasi-static carrier density between the source and the drain. Assuming that the quasi-static carrier density satisfies the transient current, the quasi-static carrier density is described as a non-quasi-static model. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device design technique, and more particularly, to a semiconductor device design simulation device and a semiconductor device design in which the reproducibility of transient carrier behavior in a source / drain and a channel when a transistor operates at high speed is improved. The present invention relates to a simulation method, a semiconductor device designed using these methods, and a manufacturing method thereof.

  Usually, prior to manufacturing a semiconductor device, the operation of the designed semiconductor device is generally predicted in advance by simulation. In addition, it is also common to reproduce (confirm) by simulation whether or not an actually manufactured semiconductor device can exhibit the desired performance. As a semiconductor device, for example, a high-speed operation of a metal-oxide-semiconductor field-effect transistor (MOSFET) is reproduced by simulation. In this case, in order to increase the accuracy of the simulation, a simulation model that can analyze and reproduce the behavior of carriers in the source / drain and the channel with high accuracy is required. In order to obtain such a simulation model, it is necessary to consider the transit time (passage delay) of carriers traveling from the source to the drain via the channel. Many simulation models called non-quasi-static models (NQS models) have been proposed as simulation models for semiconductor device design in consideration of the carrier delay through the channel. (For example, refer nonpatent literature 1).

  For example, as a first non-quasi-static model, there is a model that expresses a carrier travel delay by virtually dividing an actual transistor into a plurality of small transistors and sandwiching a resistor between the transistors. In addition, as a second non-quasi-static model, there is a model that expresses carrier travel delay by virtually arranging resistors of different values between a source and a gate and between a gate and a drain. Furthermore, as a third non-quasi-static model, there is a model in which relaxation time is introduced in the formation of charge in the channel and this is solved using a virtual equivalent device. A typical example of this third non-quasi-static model is a so-called BSIM (The Berkeley Short-Channel IGFET Model), which is one of the most commonly used non-quasi-static models in the world. .

Jpn. J. Appl. Phys. Vol. 42 (2003) pp. 2132-2136 Part 1, No. 4B, April 2003

  As described above, various non-quasi-static models have been proposed in order to predict or reproduce the high-speed operation of the MOSFET with high accuracy by simulation. However, most of them have not obtained satisfactory results in practical use. For example, in the first non-quasi-static model described above, the number of transistors to be considered increases, so that the calculation time becomes enormous. At the same time, in this first non-quasi-static model, the channel length varies depending on the number of divisions of the channel. Therefore, whether all the transistors obtained by integrating the divided transistors have the same characteristics as the whole transistors before division. Is unknown. Further, in the second non-quasi-static model described above, the estimation of each resistance value is unclear. Furthermore, in the third non-quasi-static model described above, it is difficult to obtain device convergence. At the same time, this third non-quasi-static model cannot explain the charge deficiency in the channel region caused by the NQS effect taking into account the delay of carrier travel in the channel region.

  As described above, in the conventional non-quasi-static simulation models, the behavior of carriers in the semiconductor device is predicted or reproduced with high accuracy within a time that is practically acceptable regardless of a steady state or a transient state. It is difficult. In particular, it is virtually impossible to predict or reproduce the behavior of carriers in a semiconductor device operating at high speed with high accuracy using such a simulation model. Of course, it is apparent that it is difficult to perform simulation with high accuracy within a time that allows the operation of the semiconductor device to be practically acceptable in a simulation apparatus or a simulation method using such a simulation model. As a result, a semiconductor device designed or manufactured using the simulation model, the simulation apparatus, and the simulation method may be significantly inferior in performance to a desired semiconductor device.

  The present invention has been made in order to solve the problems described above, and the object of the present invention is to investigate the behavior of carriers in the source / drain and channel of a transistor including not only a steady state but also a transient state. An object of the present invention is to provide a simulation model for designing a semiconductor device that can be predicted or reproduced with high accuracy within a time that allows the operation of the semiconductor device to be practically possible by improving the analysis accuracy. Also, by using such a simulation model for designing a semiconductor device, a semiconductor device design simulation device and a semiconductor device design simulation capable of simulating the operation of the semiconductor device within a time that is practically acceptable and with high accuracy. It is to provide a method. Furthermore, a semiconductor that can exhibit substantially desired performance by performing at least one of design and inspection using the simulation model for semiconductor device design, the simulation device for semiconductor device design, or the simulation method for semiconductor device design. An object of the present invention is to provide a device and a method of manufacturing a semiconductor device that can easily manufacture such a semiconductor device.

  In order to solve the above problem, a simulation model for designing a semiconductor device according to one embodiment of the present invention is described in a quasi-static steady state at a predetermined first time between a source and a drain of a transistor. At least part of the difference between the carrier density and the carrier density described in a transient state at a predetermined second time prior to the first time is expressed as the first time and the second time. In addition to describing the carrier density at the first time in a transient state by adding to the carrier density described in the transient state at the second time according to the delay of the carrier between the time and , A steady current that constantly flows between the source and the drain, and the quasi-static carrier density between the source and the drain. Describing the transient current flowing between the source and the drain as the sum of the displacement current as the rate of change due to, and the quasi-static carrier density satisfying the current flowing between the source and the drain The assumption is that the quasi-static carrier density is described as a non-quasi-static model.

  In this simulation model for semiconductor device design, the carrier density and current between the source and drain of a transistor are described universally regardless of whether they are steady state, transient state, static state, or quasi-static state. it can. In addition, there is no need to distinguish between the source and drain due to the delay mechanism. Thereby, it is possible to improve the analysis accuracy of the behavior of carriers in the source / drain and channel of the transistor including not only the steady state but also the transient state. At the same time, it is possible to almost eliminate the possibility of increasing the time required for predicting or reproducing the operation of the semiconductor device.

In order to solve the above problem, a simulation model for designing a semiconductor device according to another aspect of the present invention provides a transient density at a predetermined time t _i of carriers traveling between a source and a drain of a transistor. and q (t _i), a transient density of the carriers in the time t _i given time t _i-1 prior to the q (t _i-1), a quasi-static state at the time t _i Q (t _i ) is the carrier density between the source and the drain in the assumed steady state, and τ is the time taken for the carriers to reach the drain from the source, and the q (t _i ) the q (t _i-1), wherein Q (t _i), and wherein τ is the time t from said _i-1 t _i the time until the time (t _i -t _i-1) first shown below in Q (t _i ) = q (t _i-1 ) + (t _i −t _i-1 ) / τ [Q (t _i ) -q (t _i-1 )], and the transient current flowing between the source and the drain at time t _i is expressed as I (t _i ). The conduction current that constantly flows between the source and the drain is I _DC, and the displacement current that flows between the source and the drain is dQ (t _i ) / dt, and I (t _i ) and I _DC, and the second equation that the dQ (t _i) / dt is shown below in the t _i the time, I (t _i) = assuming satisfy _{I DC + dQ (t i)} / dt, the first by substituting the obtained from the equation Q (t _i) in the second equation, is characterized in that to describe the Q a (t _i) as a non-quasi-static model.

  In this simulation model for semiconductor device design, the carrier density and current between the source and drain of a transistor are described universally regardless of whether they are steady state, transient state, static state, or quasi-static state. it can. In addition, there is no need to distinguish between the source and drain due to the delay mechanism. Thereby, it is possible to improve the analysis accuracy of the behavior of carriers in the source / drain and channel of the transistor including not only the steady state but also the transient state. At the same time, it is possible to almost eliminate the possibility of increasing the time required for predicting or reproducing the operation of the semiconductor device.

  In order to solve the above-mentioned problem, a semiconductor device design simulation apparatus according to another aspect of the present invention is characterized in that the semiconductor device design simulation model according to the present invention is incorporated.

  In this semiconductor device design simulation apparatus, since the simulation model for semiconductor device design according to the present invention is incorporated, the behavior of the carrier in the source / drain and channel of the transistor including not only the steady state but also the transient state is analyzed. The accuracy has been improved. At the same time, there is almost no possibility of increasing the time required for predicting or reproducing the operation of the semiconductor device.

  In order to solve the above problem, a simulation device for designing a semiconductor device according to another aspect of the present invention includes a step of analyzing electrical characteristics of the semiconductor device using a simulation model for designing a semiconductor device according to the present invention. It is characterized by this.

  In this semiconductor device design simulation method, the simulation model for semiconductor device design according to the present invention is incorporated, so that the behavior of carriers in the source / drain and channel of the transistor including not only the steady state but also the transient state is analyzed. Accuracy can be improved. At the same time, it is possible to almost eliminate the possibility of increasing the time required for predicting or reproducing the operation of the semiconductor device.

  In order to solve the above problems, a semiconductor device according to another aspect of the present invention is characterized in that at least one of transistor design and inspection is performed using the simulation model for semiconductor device design according to the present invention. It is what.

  In order to solve the above problems, a semiconductor device according to another aspect of the present invention is characterized in that at least one of transistor design and inspection is performed by the semiconductor device design simulation apparatus according to the present invention. Is.

  In order to solve the above-described problem, a semiconductor device according to another aspect of the present invention is characterized in that at least one of transistor design and inspection is performed by the semiconductor device design simulation method according to the present invention. Is.

  In these semiconductor devices, at least one of design and inspection is performed using any one of the simulation model for designing a semiconductor device, the simulation device for designing a semiconductor device, and the simulation method for designing a semiconductor device according to the present invention. This improves the analysis accuracy of the carrier behavior in the source / drain and channel of the transistor including not only the steady state but also the transient state. At the same time, such analysis is performed within a time that is practically acceptable.

  In order to solve the above problems, a method of manufacturing a semiconductor device according to another aspect of the present invention includes a step of performing at least one of transistor design and inspection using the simulation model for semiconductor device design according to the present invention. It is characterized by including.

  In order to solve the above problems, a method for manufacturing a semiconductor device according to another aspect of the present invention includes a step of performing at least one of transistor design and inspection by the semiconductor device design simulation apparatus according to the present invention. It is characterized by.

  Furthermore, in order to solve the above problems, a method for manufacturing a semiconductor device according to still another aspect of the present invention includes a step of performing at least one of transistor design and inspection by the semiconductor device design simulation method according to the present invention. It is characterized by this.

  According to these semiconductor device manufacturing methods, at least one of design and inspection is performed using any one of the semiconductor device design simulation model, the semiconductor device design simulation device, and the semiconductor device design simulation method according to the present invention. . Thereby, it is possible to improve the analysis accuracy of the behavior of carriers in the source / drain and channel of the transistor including not only the steady state but also the transient state. At the same time, such analysis can be performed within a time that is practically acceptable.

  According to the simulation model for designing a semiconductor device according to one aspect and the other aspect of the present invention, by improving the analysis accuracy of the carrier behavior in the source / drain and channel of the transistor including not only the steady state but also the transient state. The operation of the semiconductor device can be predicted or reproduced with high accuracy within a time that is practically acceptable.

  Further, according to the simulation apparatus for designing a semiconductor device and the simulation method for designing a semiconductor device according to another aspect of the present invention, the operation of the semiconductor device is practically performed by using the simulation model for designing a semiconductor device according to the present invention. It can be simulated within an acceptable time and with high accuracy.

  In addition, in a semiconductor device according to another aspect of the present invention, design and inspection can be performed using any of the simulation model for semiconductor device design, the simulation device for semiconductor device design, or the simulation method for semiconductor device design according to the present invention. When at least one of them is performed, the performance almost as desired can be exhibited.

  Furthermore, according to the method for manufacturing a semiconductor device according to another aspect of the present invention, any one of the simulation model for designing a semiconductor device, the simulation device for designing a semiconductor device, or the simulation method for designing a semiconductor device according to the present invention is used. By including a step of performing at least one of design and inspection, a semiconductor device capable of exhibiting substantially desired performance can be easily manufactured.

The figure which shows typically the origin of the NQS effect of the simulation model for semiconductor device design concerning 1st Embodiment. The figure which shows the simulation result of each voltage application of the simulation model and 2D device simulation apparatus which concern on 1st Embodiment as a graph. The figure which shows the simulation result of each displacement current of the simulation model and 2D device simulation apparatus which concern on 1st Embodiment as a graph. The figure which shows the simulation result of each transient drain current of the simulation model which concerns on 1st Embodiment, and a two-dimensional device simulation apparatus as a graph. The figure which shows the effect | action of each delay model in transient carrier transport as a graph in the simulation model which concerns on 1st Embodiment. The figure which shows the calculation result of each carrier concentration of a transient state and a quasi-static approximation in a graph. FIG. 6 is a graph showing the lateral carrier speed in a transient state and a quasi-static approximation in a high-speed switch-on state. The figure which shows the carrier state of each of the transient state in the source side of MOSFET with a design rule of 0.5 micrometer, and a quasi-static approximation in a graph. The figure which shows the carrier injection delay with respect to different several rise time, and the velocity distribution of each carrier of the transient state and quasi-static approximation in different several rise time. The figure which shows as a graph the case where the effect of the carrier injection delay is included in the simulation model which concerns on 2nd Embodiment, and the case where it does not include, respectively. The figure which shows typically the analysis in the quasi-static state of the delay mechanism of MOSFET as a comparative example with respect to 2nd Embodiment. The figure which shows the relationship between a gate voltage and conduction | electrical_connection delay as a graph. The figure which shows the carrier density distribution by each of two-dimensional device simulation and circuit simulation using the quasi-static state approximation as a graph. The figure which shows the response of the potential of two types of switching speed with respect to the rise time of several different gate voltages in a graph, respectively. The figure which shows typically the transient carrier density distribution in each case where the transient carrier density in the drain side edge part of a channel is 0 and the case where it is not 0. The figure which shows typically the origin of the NQS effect as a comparative example with respect to 2nd Embodiment using two models of a conduction delay and an injection delay. The figure which shows each calculation result of passage time, conduction delay, and injection | pouring delay on a graph. The figure which shows three types of simulation results of the charge density with respect to several different rise time as a graph. The figure which shows the result of the two-dimensional device simulation of the electric field distribution of the direction along a channel. The figure which shows the delay time estimated from conduction | electrical_connection delay and two-dimensional device simulation as a graph, respectively. The figure which shows the calculation result of the charge density in the drain side edge part of a channel. The figure which shows the simulation result of the drain current by the approximation which makes a quasi-static state, and the approximation which makes a non-quasi-static state, respectively. The figure which shows the relationship between each of the passage delay, injection | pouring delay, and two types of conduction delay as a delay model which concerns on 3rd Embodiment, and a voltage. The figure which shows the calculation result of each carrier driving time which concerns on 3rd Embodiment as a graph, respectively. The figure which shows the calculation result of each transient carrier density by the simulation model which concerns on 3rd Embodiment as a graph, respectively. The figure which shows the calculation result of the conduction current by the simulation model which concerns on 3rd Embodiment, and a two-dimensional device simulation as a graph, respectively. The figure which shows the calculation result of the displacement current by the simulation model which concerns on 3rd Embodiment, and a two-dimensional device simulation as a graph, respectively. The figure which shows the dependence with respect to the injection delay of the displacement current by the simulation model which concerns on 3rd Embodiment, and the calculation result of the displacement current by two-dimensional device simulation as a graph, respectively. The figure which shows the characteristic with respect to the minimum value of the conduction delay by the simulation model which concerns on 3rd Embodiment as a graph, respectively. The figure which shows the dependence with respect to the conduction delay of the displacement current by the simulation model which concerns on 3rd Embodiment, and the calculation result of the displacement current by two-dimensional device simulation as a graph, respectively. The block diagram which shows typically the simulation apparatus for semiconductor device design and the simulation method for semiconductor device design which incorporated the simulation model for semiconductor device design concerning 4th Embodiment. The figure which shows the circuit for transient analysis by the simulation apparatus for semiconductor device design concerning 4th Embodiment, and its turn-on input voltage. The figure which shows the dependence with respect to the injection delay of the turn-on-drain current by the simulation apparatus for semiconductor device design concerning 4th Embodiment, and the calculation result of the turn-on-drain current by two-dimensional device simulation, respectively. The figure which shows the dependence with respect to the conduction delay of the turn-on-drain current by the simulation apparatus for semiconductor device design concerning 4th Embodiment, and the calculation result of the turn-on-drain current by two-dimensional device simulation as a graph, respectively. The figure which shows the circuit for transient analysis by the simulation apparatus for semiconductor device design concerning 4th Embodiment, and its turn-off input voltage. The figure which shows the calculation result of the turn-off drain current by the simulation apparatus for semiconductor device design concerning 4th Embodiment, and a two-dimensional device simulation as a graph, respectively. The figure which shows the calculation result of the displacement current in the turn-off by the simulation apparatus for semiconductor device design concerning 4th Embodiment, and two-dimensional device simulation as a graph, respectively.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings.

(First embodiment)
First, a first embodiment according to the present invention will be described with reference to FIGS. FIG. 1 is a diagram schematically showing the origin of the NQS effect of the simulation model for designing a semiconductor device according to the present embodiment. FIG. 2 is a graph showing simulation results of voltage application of the simulation model and the two-dimensional device simulation apparatus according to the present embodiment. FIG. 3 is a graph showing the simulation results of the displacement currents of the simulation model and the two-dimensional device simulation apparatus according to this embodiment. FIG. 4 is a graph showing simulation results of transient drain currents of the simulation model and the two-dimensional device simulation apparatus according to the present embodiment. FIG. 5 is a graph showing the action of each delay model in transient carrier transport in the simulation model according to the present embodiment.

  In the present embodiment, as a simulation model for designing a semiconductor device, a non-quasi-static model (Non-Quasi-Static Model) for designing a semiconductor circuit for MOSFET based on a carrier passage delay (τ) between a source and a drain : NQS Model).

A general two-dimensional simulation device (2D device simulator) for designing a semiconductor device (not shown) solves three basic device equations simultaneously: Poisson distribution, current density equation, and current continuity equation. However, this method is very time consuming and is not suitable for practical circuit simulation. Therefore, simplification is achieved so that a large circuit can be simulated within a time that is practically acceptable. Conventionally, circuit simulation is generally based on a quasi-static (QS) approximation, and the transit time of the carrier through the channel is ignored. However, as shown in FIG. 6, the QS approximation causes a great deal of error in simulation for high-speed circuit operation (fast switching) of the MOSFET. FIG. 6 shows a graph comparing the quasi-static electron density and the non-quasi-static electron density when the gate voltage V _gs is switched on. In order to accurately predict or reproduce the circuit performance of such a MOSFET that operates at high speed, a non-quasi-static (NQS) model that considers the delay of carrier passage between the source and the drain is required. This will be described in detail below.

  Of the basic device equations, the current continuity equation (1) explains the NQS effect. This current continuity equation (1) is solved together with the current density equation (2).

  Here, I (y, t), n (y, t), and ψ (y, t) are the current, electron density, and surface potential at time t at the y position along the channel, respectively. Further, q, W, and μ are charge, transistor width (channel width), and carrier mobility, respectively. The current continuity equation (1) is integrated from the origin (y = 0), which is the source side end of the channel, to a position y along the longitudinal direction of the channel, and is then substituted into the current density equation (2). Thereby, the following expression (3) is obtained.

  Equation (3) is integrated again from the origin (y = 0) to the drain end of the channel (y = L). Thereby, the following expressions (4a) and (4b) are obtained.

Here, L represents the length of the channel. Ψ _s0 and ψ _sL represent surface potentials at the source side end and the drain side end of the channel, respectively. Furthermore, q _c (t) is the total amount of channel charge in the time evolution t. Equation (4b) shows that the transient current flowing through the channel consists of a conduction current (first term on the right side) and a displacement current (second term). The conduction current is guided under steady state by following a change in potential almost immediately following the change in voltage applied. Further, in the QS approximation, q _c (t) is described as the following equation (5).

Similar to the general NQS model, the present inventors aim to increase the accuracy of the analytical description regarding q _c (t). This is consistent with the result obtained by solving the current continuity equation (1).

Next, a carrier passage delay model developed by the present inventors in order to verify the NQS effect according to the present embodiment will be described with reference to FIG. As shown in FIG. 1, the present inventors have developed a model based on a carrier passage delay τ by three types of carrier delay structures consisting of τ _chrg , τ _cndt , and τ _dsch . FIG. 1 shows a delay structure that is the origin of the NQS effect. The carrier passage delay τ represents the change time of carriers from the source to the drain.

First, the delay (injection delay) when carriers are injected from the source into the channel is modeled by τ _chrg . Second, the delay (conduction delay) when the carrier passes through the channel is modeled by τ _cndt . In this case, τ _cndt is further distinguished into two different conduction delays. The first conduction delay determines the delay required for the head of the carrier injected into the source to reach the drain side end (drain contact) of the channel. We identify this delay as τ _cndt1 . When the head of the carriers injected into the source reaches the drain, τ _cndt1 is governed by the electric field of the channel. At this time, τ _cndt is determined by the transit time of carriers moving from the source to the drain. We identify this delay as τ _cndt2 . _Thirdly , the delay (release delay) caused by the carrier discharging the charge to the drain contact when the carrier enters the drain from the channel is modeled by τ _dsch . However, according to research conducted by the present inventors, this τ _dsch hardly contributed to the NQS effect. Therefore, the description regarding τ _dsch will be omitted below.

First, the injection delay τ _chrg will be described. This delay τ _chrg satisfies the carrier concentration at the source side end of the channel, which is determined by the applied voltage V (t). Therefore, the density of passing carriers at the source side end of the channel in the time evolution t _i , q _n (0, t _i ) is described as the following equation (6).

Here, q _n (0, t) indicating a transient passing carrier density and Q _n (0, t) indicating a carrier density under a steady state are distinguished. The basic idea, charge Q _n required in time evolution t _i (0, t _i) -q _n only a portion of the (0, t _i-1) is the previous time by the delay tau _chrg development t _{i -1} is added to the charge q _n (0, t _i-1 ). A part of this charge Q _n (0, t _i ) −q _n (0, t _i−1 ) is represented by (t _i −t _i−1 ) / τ _chrg . Note that (t _i −t _i−1 ) ≦ τ _chrg .

Next, the first conduction delay τ _cndt1 will be described. By using this first conduction delay τ _cndt1 , the position of the head of the carrier in the channel is described as in the following equation (7).

The carrier density in the channel decreases substantially linearly from the position q _n (0, t _i ) in the channel toward q _n (y _f , t _i ). When 0 <y _f (t _i ) <L, the total charge q _c (t) in the channel is described as the following equation (8).

After the head of the carrier reaches the drain, the transient carrier density q _n (L, t _i ) at the drain side end of the channel is _expressed by the following equation (9) using the second conduction delay τ _cndt2. It is described as follows.

Here, Q _n (L, t) represents the carrier density at the drain side end of the channel under a steady state. Under this condition, q _c (t) is described as the following equation (10).

The second conduction delay τ _cndt2 determines the time (delay time) required for carriers to move from the source to the drain.

  The NQS simulation model of the present embodiment described above is included in a surface-potential-based MOSFET simulation model HiSIM described in the fourth embodiment later. Then, this HiSIM is incorporated into a so-called SPICE, which is a typical example of a semiconductor device design simulation device (semiconductor circuit design simulator), and a SPICE simulation is executed.

FIG. 3 is a graph showing the simulation results of the respective displacement currents dq _c (t _i ) / dt _{i using} the NQS simulation model of this embodiment and so-called MEDICI, which is a typical 2D device simulator. Thereby, the NQS simulation model of this embodiment is evaluated by comparing the simulation results of both displacement currents dq _c (t _i ) / dt _i . According to the NQS simulation model of this embodiment, implantation is performed under the conditions of a gate length L _g = 0.5 μm, a drain voltage V _ds = 1.0 V, and a gate voltage V _gs = 1.5 V at a rise time of 20 ps. The delay τ _chrg was extracted along with the 2D simulation results. This result is very dependent on the rise time of the gate voltage. Note that the analytical equation for the second conduction delay τ _cndt2 is derived by integrating the velocity through the channel, and the result is a function of the surface potential based on the applied voltage. The value of the first conduction delay τ _cndt1 is determined by the saturation speed. As described above, according to the NQS simulation model of the present embodiment, a good agreement with the result of the 2D simulation was obtained based on the estimated delay value.

FIG. 4 is a graph showing the simulation result of each transient drain current I (L, t _i ) based on the NQS simulation model and MEDICI of this embodiment. This compares the simulation results of the transient drain currents I (L, t _i ) of both. According to the graph shown in FIG. 4, the NQS simulation model of the present embodiment and MEDICI are in good agreement even with the transient drain current I (L, t _i ).

Furthermore, FIG. 5 shows the function of each modeled delay in transient carrier movement, that is, transient drain current arrangement, according to the NQS simulation model of the present embodiment. The injection delay τ _chrg indicates the condition that the carrier injection from the source to the channel decreases as the channel is formed. If this delay is not taken into account, the transient current response occurs in the same manner as the transient current response by the QS approximation. Also, if the first conduction delay τ _cndt1 is not taken into account, the carriers move only diffusively at an early stage of switch-on and slowly fill the channel. As a result, the displacement current decreases.

Thus, in the NQS simulation model (NQS-MOSFET model) of the present embodiment, the importance of three different delay structures including carrier delay reaction could be shown. This NQS simulation model shows both the time dependency and the position dependency of the arrangement of the carrier density through the channel as a delay function. Further, the NQS simulation model of the present embodiment is based on the delay of carrier passage that causes the channel arrangement when the switch is turned on, and determines the time dependence of the distribution of carriers through the channel. By examining two different delay structures, injection delay τ _chrg and conduction delay τ _cndt , the carrier distribution calculated by this NQS simulation model can clearly solve the continuous equation. Thereby, the NQS simulation model of this embodiment can reproduce carrier distribution with the same high accuracy as the simulation result by the 2D simulation model device. Further, the NQS simulation model of the present embodiment can be easily incorporated into a general circuit simulator. It was possible to obtain good agreement with the simulation result of the transient drain current by the 2D simulation model device.

  Further, as a result of further studies by the present inventors on the NQS simulation model of the present embodiment described above, the carrier density at a predetermined time in the channel is expressed by the following equation ( 11) It was found that it can be described. At the same time, it was found that the current at a predetermined time flowing in the MOSFET can be described by the following equation (12).

  That is, first, in equation (11), the carrier density between the source and drain of a MOSFET (transistor) is described in a quasi-static steady state at a predetermined first time. At the same time, the carrier density is described in a transient state at a predetermined second time before the first time. Then, at least a part of the difference between the carrier densities is added to the carrier density described in the transient state at the second time according to the carrier delay between the first time and the second time. . Thus, the carrier density at the first time is described in a transient state.

  Next, in the expression (12), the current flowing between the source and the drain is changed with the steady current flowing between the source and the drain and the quasi-static density of the carrier between the source and the drain with time. It is described as the sum of the displacement current as a ratio.

  Then, assuming that the density of the quasi-static carrier in Expression (11) satisfies the current in Expression (12), the density of the quasi-static carrier in Expression (11) is described as a non-quasi-static model. To do. That is, the carrier density described in the transient state in Equation (11) is solved assuming the QS state, and the solution is opened by Equation (12). As a result, the carrier density described in the transient state is finally obtained as the NQS state.

More specifically, first, let q (t _i ) be the transient density of carriers traveling between the source and drain of the transistor at a predetermined time t _i . Moreover, the transient density of the carrier at a predetermined time t _i-1 before time t _i and q (t _i-1). Also, let Q (t _i ) be the carrier density between the source and drain in the steady state assuming a quasi-static state at time t _i . Further, τ is the time required for carriers to reach the drain from the source. _{Then, q (t i), q} (t i-1), Q (t i), and τ is the time t _i-1 to t _i the time period (t _i -t _i-1) In the above first It is assumed that equation (11) is satisfied.

Next, let the transient current flowing between the source and drain at time t _{i be} I (t _i ). Further, I _DC is a conduction current that constantly flows between the source and the drain. Further, the displacement current flowing between the source and the drain is dQ (t _i ) / dt. It is assumed that I (t _i ), I _DC , and dQ (t _i ) / dt satisfy the second equation (12) at time t _i .

Then, Q (t _i ) is described as a non-quasi-static model by substituting Q (t _i ) obtained from the first equation (11) into the second equation (12).

  In the NQS simulation model of the present embodiment, the carrier density and current between the source and drain of the transistor are general-purpose regardless of whether they are steady state, transient state, static state, or quasi-static state. Can be described. In addition, there is no need to distinguish between the source and drain due to the delay mechanism. Thereby, it is possible to improve the analysis accuracy of the behavior of carriers in the source / drain and channel of the transistor including not only the steady state but also the transient state. At the same time, it is possible to almost eliminate the possibility of increasing the time required for predicting or reproducing the operation of the semiconductor device.

  FIG. 2A is a graph showing the simulation result of the limit state by the NQS simulation model of the present embodiment. In addition, FIG. 2B is a graph showing the numerical simulation results of the extreme state by MEDICI. As is clear from FIGS. 2A and 2B, according to the NQS simulation model of the present embodiment, it is possible to obtain a simulation result with the same high accuracy as MEDICI even in an extreme state. In general, numerical simulation is high in accuracy but requires a large amount of calculation time, and is not suitable for practical use. On the other hand, according to the NQS simulation model of this embodiment, as described above, the same accuracy as the numerical simulation can be obtained within a practically acceptable time.

  As described above, according to the first embodiment, it is possible to improve the analysis accuracy of the carrier behavior in the source / drain and channel of the MOSFET including not only the steady state but also the transient state. As a result, the operation of the MOSFET (semiconductor device) that operates at high speed can be predicted or reproduced within a time that is practically acceptable and with high accuracy.

(Second Embodiment)
Next, a second embodiment according to the present invention will be described with reference to FIGS. FIG. 7 is a graph showing the lateral carrier speeds in the transient state and the quasi-static approximation in the high-speed switch-on state. FIG. 8 is a graph showing the carrier concentrations in the transient state and the quasi-static approximation on the source side of the MOSFET having the design rule of 0.5 μm. FIG. 9 is a graph showing carrier injection delays for a plurality of different rise times and carrier velocity distributions of the transient state and the quasi-static approximation at different rise times. FIG. 10 is a graph showing a case where the effect of the carrier injection delay is included and a case where it is not included in the simulation model according to the present embodiment.

In the present embodiment, among the three delay structures τ _chrg , τ _cndt (τ _cndt1 , τ _cndt2 ), and τ _dsch described in the first embodiment, the importance of τ _cndt for the τ _chrg estimation method and the simulation result Will be described.

  First, a non-quasi-static MOSFET model (NQS-MOSFET Model) with no self-contradiction regarding circuit simulation based on transient carrier response will be described.

  The inventors have developed the basic concept of the NQS-MOSFET model for device simulation. This model is based on carrier response delay and incorporates the time and position dependence of carrier density along the channel. That is, the delay due to the traveling of the carrier, which is the origin of the NQS effect, is considered. Then, the present inventors clearly solved the continuity equation while comparing the result of this model with the result of the two-dimensional device simulation (2D device simulation), so that the carrier response delay is reduced to the conductive delay and the charge. It was found that it consists of charging delay. In addition, according to research conducted by the present inventors, the developed model has been successfully applied to the verification of the transient behavior of the drain current. Hereinafter, a new NQS model for device simulation that captures the channel transit time of the carrier with high accuracy by a self-consistent method proposed by the present inventors will be described in detail.

  First, prior to the description of the NQS simulation model of the present embodiment, basic equations relating to the transient current used in the NQS simulation model of the present embodiment will be described. As described in the first embodiment, in order to include the NQS effect in the NQS simulation model, the current continuity equation (1) is solved together with the current density equation (2). From these current continuity equation (1) and current density equation (2), a closed form solution for the drain current and the source current under a gentle channel approximation is derived. First, the current continuity equation (1) is integrated from the boundary (y = 0) between the source region and the channel region to a predetermined position (y = y) along the channel region. Then, by substituting the integrated value into the current density equation (2), the above equation (3) is derived. Further, by integrating the equation (3) from the boundary between the source region and the channel region (y = 0) to the boundary between the channel region and the drain region (y = L), the above equations (4a) and ( 4b) is obtained.

In these formulas (4a) and (4b), L is the length of the channel region. Ψ _s0 and ψ _sL are the surface potentials at the source region side end and the drain region side end of the channel region, respectively. Equation (4b) indicates that the transient current is composed of a conduction current (first term on the right side) and a displacement current (second term on the right side). And the conduction current is explained under steady state.

  A circuit simulator (not shown) solves the equation (4b) under the quasi-static approximation (QS-approx.), And derives the following equation (13).

In this equation (13), q∂n (y, t) / ∂V _{(G, S, D)} determines the capacitance of each of the gate, source, and drain.

  The inventors have studied for the purpose of developing an analytical explanation for electron density at n (y, t), i.e., position y and time t along the length of the channel region. This analytical explanation regarding n (y, t) satisfies the current continuity equation (1). Further, the validity of the n (y, t) model is verified by comparing the following calculated transient drain current equation (14) with the result of a two-dimensional device simulation (2D device simulation).

Next, a new n (y, t) model according to this embodiment will be described. Developing a new n (y, t) model reduces leading to a closed form solution of charge density q _n (y, t) = qn (y, t), usually performed on a trigonometric series it can. However, this requires a very large calculation time, and it is difficult to determine the coefficients of the series independently.

13, the present inventors have carried out, and the carrier density was calculated by 2D device simulation distribution q _n (y, t), the carrier density distribution was calculated by device simulation using QS approximation q _n (y, t) The result of comparing with is shown in a graph. A graph indicated by a solid line in FIG. 13 is a calculation result by 2D device simulation, and a graph indicated by a broken line in FIG. 13 is a calculation result by device simulation using QS approximation. In each of these simulations, the drain voltage (V _ds ) was fixed at 1 V, and the gate voltage (V _gs ) was switched on with a rise time of 20 ps. The results of 2D device simulation are exact solutions and are not approximated. According to the results of the 2D simulation, up to 15 ps, the carriers are not completely filled in the channel region until reaching the drain region. On the other hand, the device simulation using the QS approximation showed a natural carrier response, and the result was that the channel region was completely and completely satisfied even after 5 ps.

Next, a potential that immediately responds to a change in the gate voltage (V _gs ) is approximated. The validity of this approximation is shown in FIG. 14 by comparing the respective potential responses simulated by the 2D device simulator (MEDICI) for two different switch-on speeds. The graph shown by the solid line in FIG. 14 is the result when the switching speed τ _R = 20 ps, and the graph shown by the broken line in FIG. 14 is the result when the switching speed τ _R = 40 ps. As is clear from the graphs shown in FIG. 14, the validity of this approximation is proved because the potential distribution at each time step for two different velocities is approximately equal. In each graph shown in FIG. 2, the slight difference observed in the central part of the channel region is due to different carrier responses.

Here, it distinguishes between q _n representing the transient carrier density, and a Qn representing the carrier density in the steady state. The modeling of q _n is performed separately for the following two conditions. On the other hand, as shown in FIG. 15A, the top of the carrier flow does not reach the drain region at time step t _i (q _n (L, t _i ) = 0). The other is the case where the beginning of the carrier flow reaches the drain region at the time step t _i (q _n (L, t _i )> 0) as shown in FIG. Under these two conditions, the channel charge density Q _n (0, t _i ) in the steady state on the source region side of the channel region and the channel charge density Q _n (L in the steady state on the drain region side of the channel region) , T _i ) are distinguished from each other. In addition, an approximation is introduced in which the transient carrier density q _n (0, t _i ) on the source region side of the channel region is equal to the carrier density Q _n (0, t _i ) in the steady state on the source region side of the channel region. To do. This means that there is no response delay on the source region side of the channel region. Hereinafter, the two conditions described above will be individually described.

First, a case where q _n (L, t _i ) = 0 is described.

In this case, it is approximated that the carrier density q _n (y, t _i ) in the channel decreases approximately linearly from Q _n (0, t _i ) to zero along the channel region. A position y _f (t _i ) moving from the source region to the drain region where the carrier density is equal to zero is modeled as shown in the following equation (15).

In this equation (15), τ (t _i ) represents the carrier passage delay required to move from the source region to the drain region at time step t _i . Thus, the carrier density between y = 0 and y _f (t _i ) is described as in the following equation (16).

Here, if the potential distribution from the source region side end of the channel region to the drain region side end of the channel region is linearly changed from ψ _s0 (t _i ) to ψ _sL (t _i ), y The potential ψ (t _i ) at _f (t _i ) is expressed as the following equation (17).

By using ψ (t _i ) obtained by the equation (17), the equation (14) can be analytically expressed as the following equation (18) using Q _n (0, t _i ). Can be solved.

Next, a case where q _n (L, t _i )> 0 will be described.

In this case, it is necessary to consider both the linear condition including the pinch-off region in the channel region and the saturation condition. The change in carrier density from the time step t _i-1 to t _i at the pinch-off position y _p (t _i ) is expressed by the following equation (19) in consideration of the passage delay.

  The final carrier density is expressed by two different equations depending on the position, as shown in the following equations (20a) and (20b).

  By using these equations (20a) and (20b), the equation (14) is analytically described as the following equation (21).

In this equation (21), ψ _sp (t _i ) is the surface potential at the pinch-off position y _p (t _i ).

  Next, an NQS simulation model considering the carrier transit time will be described.

The present inventors have developed an NQS simulation model based on the carrier transit time in order to consider the charge deficiency in the channel region caused by the NQS effect. First, as shown in FIG. 16, the explanation about the conduction delay τ _cndt caused by the transit time of carriers from the source region to the drain region was developed. The conduction delay τ _cndt is calculated from the averaged carrier velocity in the channel region and expressed as a function of the surface potential as shown in the following equation (22).

In this formula (22), v (y), I _D , C _OX , k, T, N _A , and L _D are carrier velocity, drain current, oxide film capacity, Boltzmann constant, absolute temperature, acceptor concentration, respectively. And Debye length. In FIG. 17, the conduction delay τ _cndt calculated by the equation (22) is shown by a dashed line graph. Using the calculated τ = τ _cndt , the carrier density q _n (y, t) is calculated. At this time, the calculation of q _n (y, t) includes the above-described Q _n (0, t), Q _n (L, t), ψ _s0 (t), ψ _sL (t), and ψ _sp (t )Is required. Those numerical values are obtained by the NQS simulation model HiSIM based on the description of the surface potential described above in the first embodiment. Thereby, the consistency in the description of the NQS model considering the carrier transit time is maintained through the surface potential. The result is shown by a broken line graph in FIG. As is apparent from FIG. 6, the calculated carrier distribution at the beginning of the switch-on cannot reproduce the 2D simulation result. Even after 15 ps, carriers do not reach the drain. This is because the calculated τ _cndt is too small compared to the 2D simulation result. The calculated τ _cndt is derived from theory. In that theory, carriers gain inertia from transport principles based on drift-diffusion.

As carriers are injected from the source into the channel, an additional force must be included that pushes the carriers in the channel to the drain. FIG. 19 shows a 2D simulation result of the electric field distribution along the channel. The electric field in the channel direction is maximized at the source-side end of the channel, giving the carrier inertia to enter the channel. The transit time crossing the carrier depletion region l _d is roughly calculated as in the following equation (23).

  In this equation (23), μ is the carrier mobility.

In FIG. 20, the passage delay τ estimated from the 2D simulator MEDICI is shown by a solid line graph. According to FIG. 20, since the electric field distribution at the source side end of the channel shown in FIG. 19 hardly depends on the applied voltage, the characteristic of the passage delay τ that hardly depends on time is observed. As described above in the first embodiment, this inertia is the charging delay (injection delay) τ _chrg and approximated to be substantially constant. Further, since the value τ obtained in the equation (23) depends on the source / channel junction condition, the value of τ _chrg is obtained as about 13 ps by fitting to the 2D simulation result of the carrier distribution of t = 5 ps and 10 ps. It is done. The final passage delay τ is expressed by the following equation (24) by integrating the two components τ _cndt and τ _chrg of the passage delay τ described in the first embodiment.

In FIG. 17, the calculated τ _chrg and τ are plotted. By using the calculated τ, the carrier density distribution is calculated. The result is shown by a broken line in FIG. As is clear from FIG. 18, according to the NQS simulation model of the present embodiment, a carrier distribution substantially similar to the 2D simulation result could be obtained.

FIG. 21 shows the calculation result of the carrier density at the drain side end portion of the channel, q _n (L, t), in order to verify the validity of the NQS simulation model of the present embodiment. The modeled q _n (L, t) shows a clear response delay by comparison with Q _n (L, t). Even after V _gs reaches steady state, q _n (L, t) converges smoothly to the final value as expected. The drain current is calculated by Equation (18), Equation (20a), and Equation (20b) using the calculated q _n (L, t). The calculation result is shown in FIG. For comparison, the calculated drain current and simulation results under the QS approximation are also shown in FIG. According to FIG. 22, it can be seen that the NQS simulation model of the present embodiment reproduces the 2D numerical simulation result very well. In addition, the initial rise response of the NQS simulation model of the present embodiment is due to the calculation excluding the capacity. The negative I _ds of the 2D simulation result is also due to the charging capacitance from the drain. However, the charging capacity from the drain is excluded in this calculation.

As described above, according to the NQS simulation model of the present embodiment, an NQS-MOSFET model including a carrier response delay can be developed by a self-consistent method. The NQS simulation model of this embodiment explains both the time and position dependence of the carrier in the channel direction as a function of the carrier passage delay τ. This passage delay τ is modeled by a carrier passage time integrating the conduction delay τ _cndt and the charging delay τ _chrg . And the calculated carrier density distribution in the channel direction reproduces the 2D simulation result very well. At the same time, it was confirmed that the current calculated using the developed carrier distribution reproduces the result of 2D simulation.

  Next, the delay mechanism for transient carrier transport in MOSFETs under very fast switching will be described.

  The inventors have studied a delay mechanism that governs the transport of carriers in the MOSFET channel under conditions where the gate input is fast and time-varying. According to this study, it has been found that carriers receive great force to enter the channel. This has been found to constitute a new type of carrier delay mechanism that relies on the time derivative of the carrier concentration induced on the source side of the channel. And it has been found that introducing a new delay mechanism into the circuit simulation model is necessary to accurately predict the MOSFET drain current in RF operation. This will be described in detail below.

  First, a carrier delay component in high-speed MOSFET switching will be described.

With the recent development of integrating MOSFETs in circuits operating in the RF region, a delay mechanism that accounts for the transport of carriers in the channel has become a first challenge. In general, channel-carrier transport is described by the time a carrier travels in a section of the channel. The delay time (τ _{y2, y1} ) is calculated by the following equation (25).

Here, v is the carrier velocity in the sections y ₁ and y ₂ . Equation (25) is schematically illustrated in FIG. 11 for a MOSFET. Here, the integration is performed from the source (y ₁ = 0) to the drain (y ₂ = L _eff ). In quasi-static (QS) analysis, the delay (τ _Leff , 0) is simply due to the steady conduction of carriers. In the following, this is called the conduction delay (τ _cndt ). As the gate voltage (V _g ) increases, τ _cndt decreases due to the contribution of increasing drift as shown in FIG. However, it is well known that when applying a time-varying input very quickly, the carrier behaves differently than in a quasi-static state. As shown in FIG. 6 used in the first embodiment, this is also proved in a simulation using a 2D device simulator MEDICI for high-speed switch-on. In the quasistatic approximation, the carriers are assumed to reach equilibrium instantaneously once a bias voltage is applied. In this case, the calculated τ _cndt does not, of course, accurately represent the generation of carriers in the channel at a fast time-varying bias voltage. Therefore, simply applying the conventional delay mechanism in which carriers move by conduction proves to be insufficient to model the carrier response in such high frequency operation. . As shown in FIG. 1 used in the first embodiment, an additional delay mechanism is necessary to fully explain the carrier behavior. The injection delay τ _chrg and the ejection delay τ _dsch that govern the carrier entering and exiting the channel, respectively, are considered particularly important. Here we focus on the analysis of the injection delay of carriers that receive excessive force to enter the channel. In particular, it clarifies how this delay mechanism affects the carrier transport required to build transient delay modeling for circuit simulation.

  First, a transient delay model related to analysis by 2D simulation and circuit simulation will be described.

In FIG. 7, when attention is paid to the lateral (lateral) carrier velocity characteristic between the high-speed switch and the on-state, an initial bump is observed near the source region. A very short rise time (t _r ) is used for the purpose of demonstrating important effects. As revealed by the increase in velocity as the carriers are injected into the channel, the carriers contain additional moments. The effect of the additional moment, i.e. the increased speed, reaches approximately L _eff / 2. On the drain side, the speed predicted by the quasi-static approximation dominates. The additional moment is induced by the rising force required to preserve the carrier distribution necessary to satisfy the continuity equation. The inventors have modeled the delay due to charge injection with a delay time τ _chrg called charging delay to reach a quasi-static approximate carrier concentration on the source side of the channel in a transient case.

FIG. 8 shows the carrier concentration results for a 0.5 μm MOSFET and, as an example, a rise time of 20 ps. As shown in the inset of FIG. 8, τ _chrg is assumed to be a time delay required for the carrier density in the transient simulation to reach the value of the carrier density predicted by the QS simulation.

Figure 9a is a summary of the tau _chrg determined for different t _r. It can be seen that τ _chrg decreases as the switch-on is faster. This tends to have a larger additional moment when the carrier enters the channel, and reaches the carrier density required to satisfy the continuity equation under fast changes in the gate-source voltage (V _gs ). This means that it is injected quickly. As V _gs further increases to V _{gs, max} , the additional moment relaxes and the velocity distribution in the channel relaxes to a steady state. Figures 9 (b)-(d) show that the corresponding bumps in the velocity distribution near the source region increase with decreasing switch-on time, demonstrating that the injected carriers behave as described above. ing.

FIG. 8 shows the influence of τ _chrg in the calculation of the drain current when the transient delay model is executed in HiSIM, which is a circuit simulation model based on the surface potential related to the MOSFET. τ _chrg is included as a delay governing the carrier concentration in the source, and the passing carrier delay in the channel is determined by τ _cndt according to equation (25). Both delay contributions cause a delay in carrier concentration at the drain. τ _cndt further prevents a shortage of carriers in the channel. Other important observation in FIG. 8, tau _chrg is that affect the transport of the whole carrier in particular to a short t _r. T _r of 20ps, since already too early, even after the V _{gs, max} has reached the 20ps, it has not yet been alleviated additional charging moment. This results in a smooth current transfer at V _{gs, max} . The corresponding velocity distribution is given in Fig. 7c.

  Thus, the delay model relating to the circuit simulation described here reproduces accurate movement characteristics as implemented by the current continuity equation (1).

As described above, according to the second embodiment, the same effects as those of the first embodiment described above can be obtained. In addition, a more appropriate estimation method for τ _chrg could be obtained. Furthermore, the importance of τ _cndt for the simulation results was confirmed.

(Third embodiment)
Next, a third embodiment according to the present invention will be described with reference to FIGS. FIG. 23 is a graph showing the relationship between the voltage and each of the passing delay, the injection delay, and the two types of conduction delays as the delay model according to the present embodiment. FIG. 24 is a graph showing the calculation results of each carrier travel time according to the present embodiment. FIG. 25 is a graph showing calculation results of each transient carrier density by the simulation model according to the present embodiment. FIG. 26 is a graph showing the calculation results of the conduction current by the simulation model according to the present embodiment and the two-dimensional device simulation. FIG. 27 is a graph showing displacement current calculation results obtained by the simulation model and the two-dimensional device simulation according to the present embodiment. FIG. 28 is a graph showing the dependency of the displacement current on the injection delay by the simulation model according to the present embodiment and the calculation result of the displacement current by the two-dimensional device simulation. FIG. 29 is a graph showing the characteristics of the conduction delay with respect to the minimum value by the simulation model according to the present embodiment. FIG. 30 is a graph showing the dependence of the displacement current on the conduction delay by the simulation model according to the present embodiment and the calculation result of the displacement current by the two-dimensional device simulation.

  In the present embodiment, more specific and detailed research and consideration conducted by the present inventors will be described for the NQS simulation model described in each of the first and second embodiments. This will be described in detail below.

First, the injection delay τ _chrg will be described. This τ _chrg must include an additional force that pushes carriers from the channel toward the drain as carriers are injected from the source into the channel. FIG. 19 used in the second embodiment shows the electric field distribution along the channel by two-dimensional simulation. The maximum electric field at the source side end of the channel gives the force to flow carriers into the channel. The travel time crossing the depletion region l _d can be roughly explained by the equation (23). Here, in the case where the gate length is 0.5 μm and V _ds = 1.0 V, τ _chrg modeled from the analysis by the two-dimensional simulator MEDICI is expressed as the following equation (26).

In this equation (26), τ _chrg determines the transient carrier density at the source side end of the channel. For this reason, the transient carrier density at the source side end of the channel is expressed as in the above equation (6).

Next, the first conduction delay τ _cndt1 will be described. As described above, this τ _cndt1 indicates that the carrier tip position y _f changes from the source to the drain when the channel is not formed because the source side end and the drain side end of the channel are not filled with carriers. Represents the time required to reach. Studies conducted by the present inventors, the moving speed of the tip position y _f of the carrier was found to be substantially constant regardless of the time. Therefore, the leading end position y _{f of the} carrier is expressed as the above formula (7).

Next, the second conduction delay τ _cndt2 will be described. As described above, τ _cndt2 represents the conduction delay in the case where the source side end and the drain side end of the channel are filled with carriers and a channel is formed. This second conduction delay τ _cndt2 is calculated from the average velocity of the carriers in the channel and is a function of the surface potential. The second conduction delay tau _Cndt2, in the formula (22) can be represented by the formula by replacing tau _CNDT to _τ cndt2. τ _cndt2 represents the time required for the carriers emitted from the source to reach the drain, and directly affects the transient carrier density of the drain. For this reason, the equation expressing the transient carrier density of the drain can be expressed by an equation in which τ (t _i ) in the equation (19) is replaced with τ _cndt2 .

In calculating the actual carrier density changes from tau _Cndt1 before and after the leading end of the carrier reaches the drain _τ cndt2. In view of this, τ _cndt1 and τ _cndt2 are represented by τ _cndt coupled in the relationship of the following equation (27) so that the change is smooth in calculation.

Therefore, the transient carrier density is calculated by replacing τ (t _i ) and τ _cndt2 (t _i ) in the equations (22) and (19) with τ _cndt1 (t _i ). Further, by combining the equation (27) and the equation (24), the three types of carrier delay models used in the NQS simulation model of the present embodiment can be expressed as the following equation (28). it can.

  FIG. 23 is a graph showing the relationship between the three types of delay models of carriers used in the NQS simulation model of this embodiment.

  Next, verification of the validity of the transient carrier density distribution model based on the conduction current using the NQS simulation model of the present embodiment will be described.

  The displacement current of the equation (4a) is ignored, and the conduction current of the equation (14) is described by a transient carrier density distribution model. Then, the following equations (29) and (30) can be obtained in accordance with the state of the tip of the carrier in the MOSFET.

Expression (29) is applied to a state where the carrier tip does not reach the drain. Expression (30) is applied to a state where the carrier tip reaches the drain. In the calculation in this verification, the steady state carrier densities Q _n (0, t _i ) and Q _n (L, t _i ), the surface potentials ψ _s0 (t _i ), ψ _sL (t _i ), And ψ _sp (t _i ) are based on the assumption that the calculation result of the steady state at time t _i of HiSIM is used.

First, the case where the carrier tip does not reach the drain, that is, the case where q _n (L, t _i ) = 0 is described. In this case, the integration of equation (14) corresponds to a triangular area having the carrier density on the vertical axis and the potential on the horizontal axis in FIG. 15A used in the second embodiment. This is represented by the formula (29). In the equation (29), ψ (t _i ) is calculated by the equation (17).

Next, a state where the carrier tip reaches the drain, that is, a case where q _n (L, t _i )> 0 will be described. In this case, the integration of equation (14) is the sum of the area of the left trapezoid and the area of the right triangle, with the vertical axis of FIG. 15B used in the second embodiment as the carrier density and the horizontal axis as the potential. Equivalent to. This is represented by the formula (30).

In this verification, the Charging delay τ _chrg was calculated by the equation (26). In addition, according to the research conducted by the present inventors, the first conductive delay τ _cndt1 is determined such that the carrier tip y _f starts moving at t = 2.5 ps and reaches the drain at t = 13.5 ps. I found out. Thus, in this verification, τ _cndt1 = (13.5−2.5) ps = 11.0 ps was made substantially constant. The second Conductive delay tau _Cndt2 has a tau _CNDT In the formula (22) was calculated according to the case is replaced with _τ cndt2.

FIG. 24 shows the calculation result of the carrier travel delay described above. Further, while using the carrier travel time shown in FIG. 24, the transient source carrier density q _n (0, t), the carrier tip position y _f (t) by the above equations (6), (7), and (19). , And the transient drain carrier density q _n (L, t), respectively. The result is shown in FIG. For comparison, the steady-state source carrier density Q _n (0, t) and the steady-state drain carrier density Q _n (L, t) are also plotted in FIG. Carrier tip position y _f is increased as expected linearly, it reaches the drain in the vicinity 13 ps. Also, the value of q _n (L, t) is 0 until about 13 ps, but has increased since then, and this well represents a state in which no channel is formed. In comparison with Q _n (L, t), the modeled q _n (0, t) and q _n (L, t) show clear response delays. Even after the gate voltage V _gs has reached a steady state, q _n (0, t) and q _n (L, t) are smoothly agile toward the expected final value.

FIG. 26 shows the conduction current calculated by the two equations (29) and (30). For comparison, FIG. 26 also shows the source current, drain current, and conduction current by two-dimensional simulation. The reason why the current values are different at a time point close to the steady state of 35 ps is that tuning of the two-dimensional device simulator is not complete. In the NQS simulation model of this embodiment, it can be seen that the current is delayed as much as the carrier delay is considered with respect to the conduction current I _do by the two-dimensional simulation. However, as an overall trend, it can be seen that the NQS simulation model of the present embodiment reproduces a two-dimensional simulation well. The difference between Q _n (0, t _i ) and q _n (0, t _i ) shown in FIG. 25 represents the influence of Charging delay τ _chrg . The effect is represented by the difference between the absence of τ _chrg indicated by the thick dashed line in FIG. 26 and the presence of τ _chrg indicated by the thick solid line. As is apparent from FIG. 25, the effect of τ _{chrg on} q _n (0, t _i ) increases as the gate voltage increases. This effect appears in FIG. 26 in that the conduction current delay increases after 13 ps.

  Next, verification of the validity of the transient carrier density distribution model based on the displacement current using the NQS simulation model of the present embodiment will be described.

  The equation (4b) is described only for the displacement current. Then, the following formula (31) can be obtained.

In this equation (31), q _c (t) represents the amount of carrier charge in the MOSFET at time t. The calculation of q _c (t) in this equation (31) with the transient carrier density distribution model is as follows: the vertical axis in FIGS. 15 (a) and 15 (b) is the carrier density, and the horizontal axis is the distance in the channel direction. This corresponds to finding the area of a triangle or trapezoid. When q _c (t _i ) at time t _i is described by a transient carrier density distribution model, the following two equations (32) and (33) are obtained according to the state of the carrier tip in the MOSFET.

  Expression (32) is applied to a state where the carrier tip does not reach the drain. Equation (33) is applied to the state where the carrier tip reaches the drain.

First, the case where the carrier tip does not reach the drain, that is, the case where q _n (L, t _i ) = 0 is described. In this case, q _c (t _i ) is the carrier density q _n (0, t _i ) in FIG. 15A used in the second embodiment, and the height is the carrier tip y _f (t _i ). It corresponds to the area of a triangle. This is represented by the formula (32).

Next, a state where the carrier tip reaches the drain, that is, a case where q _n (L, t _i )> 0 will be described. In this case, q _c (t _i ) is the carrier density q _n (0, t _i ) on the lower side of FIG. 15A used in the second embodiment, the carrier density q _n (L, t _i ) on the upper side, The area of the left trapezoid whose height is the pinch-off distance y _p (t _i ), the lower side is the carrier density q _n (L, t _i ), and the height is (L−y _p (t _i )). It corresponds to the sum of the areas of the right triangle. This is represented by the formula (33).

  In this verification, the final formula of the formula (31) was calculated as the following formula (34).

In this equation (34), t _i-1 represents a time before t _i .

FIG. 27 shows a calculation result of the displacement current when the drain voltage V _ds = 1.0 V (constant) and the gate voltage V _gs is applied from 0 V to 1.5 V over 20 ps. Charging delay τ _chrg and Conductive delays τ _cndt1 and τ _cndt2 are assumed to be the conditions shown in FIG. In FIG. 27, the calculation result by the two-dimensional simulator is also plotted for comparison. The reason why the current value differs between the NQS simulation model and the two-dimensional simulation of the present embodiment within about 3 ps after the start of the gate voltage application is that the overlap capacitance differs between the HiSIM model parameter and the two-dimensional simulator.

Up to 13 ps, the displacement current increases linearly with the carrier tip not reaching the drain. However, the slope of the NQS simulation model of this embodiment is slightly gentler than that of the two-dimensional simulator. The current value of the NQS simulation model of the present embodiment is smaller than the current value of the two-dimensional simulation at 13 ps after the carrier tip reaches the drain and after 20 ps until the increase of the gate voltage is completed. According to research conducted by the present inventors, the electron density distribution after 14 ps is rounded upward in the two-dimensional simulation, whereas the NQS simulation model of the present embodiment approximates it with a straight line. It depends on. Thereby, in the NQS simulation model of this embodiment, the amount of change in charge is calculated smaller than in the two-dimensional simulation. After 20 ps when the gate voltage is constant, the NQS simulation model of the present embodiment agrees very well with the two-dimensional simulation. That is, the validity of introducing the _conductive delays τ _cndt1 and τ _cndt2 in the NQS simulation model of the present embodiment is supported.

FIG. 28 shows the result of the influence of the Charging delay τ _chrg on the displacement current together with the result of the two-dimensional simulation. to alter the value of tau _chrg, adding the parameter m to change the value of tau _chrg the model equation (26) of the tau _chrg. This can be expressed as the following equation (35).

In this equation (35), the value of m is _{set to} 1/3, 1 and 2, which are the gate voltage V _gs = 1.5V and the values of τ _chrg are about 0.9 ps, 2.6 ps, 5 respectively. .2 ps is supported. When τ _chrg is small, carriers are instantaneously injected into the channel corresponding to the gate voltage V _gs , so that a large displacement current flows while the gate voltage V _gs rises. When the rise of the gate voltage V _gs stops, the carrier injection in the channel does not increase any more and the carrier outflow from the drain takes effect, so the displacement current decreases rapidly. On the other hand, if tau _chrg is large, the displacement current for the rise of the gate voltage V _gs is the carrier behind rise of the gate voltage V _gs is injected is reduced. However, it can be seen that even when the increase in the gate voltage V _gs stops, carriers continue to be injected into the channel, so that the displacement current decreases gradually.

Next, the inventors examined the influence of the _conductive delay τ _cndt2 on the displacement current. At this time, the equation (22) for the drain voltage V _ds = 1.0 V was approximated by the following equation (36).

In this equation (36), the minimum value τ _min of τ _cndt2 at the gate voltage V _gs = 1.5 V can be changed. In the present embodiment, as the value of τ _min, a value of 2 ps and 10 ps was used in addition to the original 4.5 ps obtained by the equation (22). FIG. 29 is a graph showing the change in τ _cndt2 with respect to the value of τ _min used this time.

FIG. 30 shows the displacement current when τ _min is used as a parameter. τ _cndt2 has a role of determining the response of the carrier density of the drain after the channel is formed. For this reason, as intended, before 13 ps before channel formation, there is no effect on the displacement current due to the change in τ _cndt2 . The fact that τ _min is large, that is, τ _cndt2 is large, means that the increase in carrier density at the drain side end of the channel is small, as can be seen from the equation (19). This means that if the gate voltage V _gs is increasing, the carrier density increases at the drain side end of the channel due to the inflow of charge into the channel, and the drain side of the channel due to the carrier flowing out of the channel. This means that the decrease in carrier density at the end is substantially equal. As a result, the change in the charge amount of all carriers in the channel is reduced. Therefore, as can be seen in the broken line graph between 13 ps and 20 ps in FIG. 30, the displacement current is smaller in the case of τ _min = 10 ps than in the other cases.

On the other hand, when there is almost no change in the gate voltage V _gs and it becomes substantially constant, the inflow of the charge amount into the channel becomes constant, and only the outflow of carriers from the drain appears as the change amount of the entire carrier. In this case, τ _cndt2 is large, that is, suppressing the change in carrier density at the end of the drain side of the channel to a small value means that the outflow of carriers is suppressed or the carriers stay in the channel for a long time. ing. This is why it takes time for the graph in the case of τ _min = 10 ps to become a substantially constant value, as can be seen in the broken line graph after 20 ps in FIG.

As described above, according to the third embodiment, the same effects as those of the first and second embodiments described above can be obtained. Further, as shown in FIG. 23 and Expression (28), the validity of the Charging delay τ _chrg and the Conductive delays τ _cndt1 and τ _cndt2 used in the NQS simulation model of this embodiment has been sufficiently confirmed. The validity of each of the transient carrier density distribution model based on the conduction current and the transient carrier density distribution model based on the displacement current using the NQS simulation model of the present embodiment was sufficiently verified.

(Fourth embodiment)
Next, a fourth embodiment according to the present invention will be described with reference to FIGS. FIG. 31 is a block diagram schematically showing a semiconductor device design simulation apparatus and a semiconductor device design simulation method incorporating the semiconductor device design simulation model according to the present embodiment. FIG. 32 is a diagram showing a transient analysis circuit and its turn-on input voltage by the semiconductor device design simulation apparatus according to this embodiment. FIG. 33 is a graph showing the dependency of the turn-on / drain current on the injection delay by the semiconductor device design simulation apparatus according to this embodiment and the calculation result of the turn-on / drain current by two-dimensional device simulation. It is. FIG. 34 is a graph showing the dependence of the turn-on / drain current on the conduction delay by the simulation apparatus for designing a semiconductor device according to the present embodiment and the calculation result of the turn-on / drain current by two-dimensional device simulation. It is. FIG. 35 is a diagram showing a transient analysis circuit and its turn-off input voltage by the semiconductor device design simulation apparatus according to this embodiment. FIG. 36 is a graph showing turn-off / drain current calculation results obtained by the semiconductor device design simulation apparatus and the two-dimensional device simulation according to this embodiment. FIG. 37 is a graph showing the calculation results of the displacement current at turn-off by the semiconductor device design simulation apparatus and the two-dimensional device simulation according to this embodiment.

  In the present embodiment, a semiconductor device design simulation apparatus and a semiconductor device design simulation method using the NQS simulation model described in each of the first to third embodiments will be described. This will be described in detail below.

  First, the case where HiSIM, which is the above-described NQS simulation model, is incorporated into SPICE 3, which is a typical circuit simulator, will be described. Further, input / output information of the NQS simulation model HiSIM for SPICE 3 will be described. FIG. 31 shows the relationship between the NQS simulation model HiSIM developed by the present inventors and the circuit simulator SPICE3. A portion surrounded by a broken-line frame is HiSIM1 (MOSFET model HiSIM1). By combining this HiSIM1 with the circuit simulator SPICE3, a circuit simulator 2 as a semiconductor device design simulation apparatus according to the present embodiment is configured. The circuit simulator 2 executes the semiconductor device design simulation method according to the present embodiment.

  In the transient analysis of the circuit simulator SPICE3, a voltage condition is set for each time step, and a MOSFET model calculation result for the condition is obtained. The MOSFET model HiSIM1 receives from the SPICE 3 a flag indicating a time interval and a convergence state in the previous circuit simulator together with the voltage condition. In HiSIM1, first, the steady state is calculated under the input voltage condition. Next, the previously converged flag is checked. This flag indicates whether or not the previous circuit matrix calculation in the circuit simulator has converged normally, and when the abnormal convergence is indicated, it means that the previous calculation is invalid. If the flag indicates abnormal convergence, the previous voltage condition and the transient charge density state are reset so that they can be used as the previous state. The current transient charge density is calculated using the previous transient charge density. If the previous calculation is invalid, the previous state is invalid and cannot be used. For this reason, it is necessary to set the previous state as the previous state. If the flag indicates normal convergence, NQS is calculated. Next, the previous state is set as the previous state, and the newly calculated state is set as the previous state, and a save for use in the next calculation is performed. After the NQS calculation, the conduction current and the transient charge of each electrode are returned to the circuit simulator. In the circuit simulator SPICE3, the current and voltage of the entire circuit are obtained by matrix calculation using information obtained from the MOSFET model HiSIM1. Next, a convergence flag is set and circuit characteristics are saved, and the next time step is calculated.

Next, the charge amount and charge partitioning of the transistor electrode will be described. In the transient analysis of the circuit simulator 2 of this embodiment, the charge amount Q _a0 and the conduction current I _a0 possessed by each electrode calculated by the transistor model are received, and the current flowing through each electrode is calculated according to a predetermined formula. The gate charge Q _G is represented by the sum of the channel charge Q _c and the substrate charge Q _B. However, the channel charge Q _c corresponds to the channel charge q _c calculated by the equations (32) and (33) of the NQS simulation model of the present embodiment described above. Therefore, the gate charge Q _G can be expressed as the following formula (37).

Further, the channel charge q _c is the sum of the source charge q _s and the drain charge q _D, and can be expressed as the following formula (38).

Therefore, it is necessary to divide the channel charge q _c obtained by the NQS simulation model of the present embodiment into the source charge q _s and the drain charge q _D and pass them to the circuit simulator SPICE 3. In the circuit simulator BSIM3 described in the background art, as a default setting of the MOSFET, the division is set to 60/40 and is passed to the circuit simulator. In the present embodiment, for the sake of simplicity, the division ratio is calculated as 60/40. Further, assuming that the substrate charge Q _B has little transient influence on the gate voltage V _gs , the charge calculated in the steady state is passed to the circuit simulator as it is.

  Next, turn-on transient calculation of NMOSFET by SPICE3 using the NQS simulation model HiSIM1 of this embodiment will be described.

Using the NQS simulation model of the present embodiment, the transient analysis of the circuit shown in FIGS. 32A and 32B was performed by SPICE3. At this time, the gate length of the MOSFET was set to about 0.5 μm, the drain voltage V _DS = 1.0 V (constant), and the source voltage V _S = bulk voltage V _B = 0 V (constant). Then, the turn-on characteristic when the gate voltage V _GS was increased from 0 V to about 1.5 V over about 20 ps was calculated.

FIG. 33 shows the output result of the drain current by SPICE3. FIG. 33 also shows the drain current using m defined in the equation (35) as a parameter and the drain current obtained by the two-dimensional simulator in order to see the influence of the Charging delay τ _{chrg on} the drain current. The negative current up to about 14 ps by the two-dimensional simulator indicates that the current flows from the drain to the MOSFET through the overlap capacitance. The NQS simulation model HiSIM1 also has a negative current flowing up to about 14 ps, but its characteristics are rounded down. This is presumably because the junction capacitance model incorporated in HiSIM1 has a gate voltage dependency. In the NQS simulation model HiSIM1, the current jumps at about 20 ps. The jump width increases when τ _chrg is small. This corresponds to the jump also seen in the displacement current shown in FIG. 30 used in the third embodiment. The cause of this jump has not yet been elucidated, but is thought to be due to a calculation problem of the circuit simulator SPICE3. Such a sudden change may affect the convergence of the circuit simulation, but it is generally recognized that the circuit simulation is not affected.

Also in FIG. The channel is not formed up to about 14 ps, and carriers are only stored in the transistor. The larger τ _chrg is, the larger the drain current is. From about 14 ps to about 20 ps, a channel is formed and carrier inflow from the source and carrier outflow from the drain occur simultaneously. As a result, it can be seen that the influence of τ _{chrg on} the drain current is small. From about 20 ps after the rise of the gate voltage V _GS is stopped, the carrier supply from the source is delayed as τ _chrg increases, so that it takes time for each simulation result to reach a steady state. As is apparent from FIG. 33, it can be seen that the simulation results of the NQS simulation model HiSIM1 generally agree well with the two-dimensional simulation when m = 1.

Next, in FIG. 34, in order to _examine the influence of the _conductive delay τ _{cndt2 on} the drain current, the drain current by the NQS simulation model HiSIM1 using τ _min defined by the equation (36) as a parameter, the drain current by the two-dimensional simulator, Are shown repeatedly. Since τ _cndt2 is a delay effective in the region where the channel is formed, a difference in τ _min appears after about 14 ps. In particular, the difference appears largely immediately before about 20 ps. When τ _min is small at this time, as shown in FIG. 30 used in the third embodiment, this corresponds to a case where the change in carriers accumulated in the channel is large, and the drain is smaller than in other cases. It means that there are few careers flowing out of it. After about 20 ps after the rise of the gate voltage V _GS is stopped, the transient charge density at the drain end is set closer to the steady state as τ _min is smaller, as seen in the equation (19). The drain current also approaches the steady state earlier as τ _min is smaller.

  Next, turn-off transient calculation of NMOSFET by SPICE3 using the NQS simulation model HiSIM1 of this embodiment will be described.

It is important in model evaluation to look at the turn-off characteristic together with the turn-on characteristic described above. Here, the transient analysis of the circuit shown in FIGS. 35A and 35B was performed by SPICE 3 using the NQS simulation model HiSIM1 of the present embodiment. At this time, the gate length of the MOSFET was set to about 0.5 μm, the drain voltage V _DS = 1.0 V (constant), and the source voltage V _S = bulk voltage V _B = 0 V (constant). Then, turn-off characteristics were calculated when the gate voltage V _GS was lowered from about 1.5 V to 0 V over about 20 ps.

FIG. 36 shows the drain current turn-off characteristics of the NQS simulation model HiSIM1 of this embodiment, together with the results of the QS model and the two-dimensional simulation. At about 5 ps, the gate voltage V _GS starts to decrease, and at the same time, a jump is seen in the drain currents of the NQS model HiSIM1 and the QS model. Such a jump is also seen in the two-dimensional simulation, but is smaller than the HiSIM1 and QS models. Similarly, a jump occurs at about 25 ps when the decrease in the gate voltage V _GS stops. Such a phenomenon is generally known. In either case, a jump occurs, which is considered to be caused by a problem specific to numerical calculation. In comparison NQS model HiSIM1 and 2-dimensional simulation, a peak appears in the vicinity about 7ps the gate voltage V _GS begins to descend. At this time, the current decreases smoothly in the two-dimensional simulation from about 17 ps to about 25 ps as the value of the NQS model HiSIM1 increases. On the other hand, in the NQS model HiSIM1, the current decreases once and then decreases rapidly. FIG. 37 shows the displacement current at the turn-on of the NQS model HiSIM1 superimposed on the result of the two-dimensional simulation in order to see the state of this time zone corresponding to the displacement current.

  As is clear from FIG. 37, the NQS model HiSIM1 has a rapid increase from about 7 ps to a constant, and a constant from about 17 ps to a rapid decrease. However, the two-dimensional simulation shows a smooth increase and a smooth decrease at each time. The cause is considered as follows. In general, the carrier density distribution during turn-off by two-dimensional simulation is set to a distribution with a rounded top. On the other hand, the NQS model HiSIM1 of the present embodiment approximates a distribution in which the charge density at the source end and the drain end is connected by a straight line. As a result, the channel charge amount having a distribution with a rounded top has a larger value than the channel charge amount approximated by a straight line. Therefore, it can be considered that the amount of change in channel charge with the next time step is linearly approximated, that is, the amount of change in the NQS model HiSIM1 of this embodiment is large, and shows a rapid change. From the above considerations, it was found that when various carrier density distributions appearing with respect to turn-off deviate from the linear approximation, an appropriate approximation according to the distribution should be applied.

  As described above, according to the fourth embodiment, the same effects as those of the first to third embodiments described above can be obtained. In addition, according to the NQS simulation model HiSIM1 and the simulation apparatus 2 and the simulation method using the HiSIM1 of this embodiment, the analysis accuracy of the carrier behavior in the source / drain and channel of the transistor including not only the steady state but also the transient state Can be improved. At the same time, it is possible to almost eliminate the possibility of increasing the time required for predicting or reproducing the operation of the semiconductor device. Therefore, the operation of the semiconductor device can be simulated with high accuracy within a time that is practically acceptable.

  In addition, it was confirmed that the NQS simulation model HiSIM1 of the present embodiment agrees very well with the simulation result of the two-dimensional simulation, which is a numerical simulation with high accuracy. In particular, the NQS simulation model HiSIM1 of the present embodiment can analytically derive such a highly accurate simulation result within a time that is practically acceptable.

  As described above, according to the NQS simulation model HiSIM1 of the present embodiment, the carrier density distribution satisfying the current continuity equation and the current density equation is modeled, and combined with the carrier travel delay, the transient phenomenon of the MOSFET is reduced. For the first time, it was clarified that it can be expressed by an analytical expression. Moreover, the carrier delay which should be considered regarding the carrier travel of MOSFET was able to be clarified. This is expected to be used very effectively as a guide for future fine device design and circuit design. Furthermore, it was confirmed that the NQS simulation model HiSIM1 of this embodiment can be used sufficiently for transient analysis of a high-speed circuit by incorporating it into a general general-purpose circuit simulator SPICE3.

(Fifth embodiment)
Next, a fifth embodiment according to the present invention will be described with the illustration omitted.

  In the present embodiment, a semiconductor device and a method for manufacturing the semiconductor device according to the present invention will be described with their illustration omitted.

  The semiconductor device according to the present embodiment is designed and / or inspected by using any one of the aforementioned semiconductor device design simulation model, semiconductor device design simulation device, or semiconductor device design simulation method. This improves the analysis accuracy of the carrier behavior in the source / drain and channel of the transistor including not only the steady state but also the transient state. At the same time, such analysis is performed within a time that is practically acceptable.

  In addition, the semiconductor device manufacturing method of the present embodiment performs at least one of design and inspection using any of the above-described semiconductor device design simulation model, semiconductor device design simulation device, or semiconductor device design simulation method. . Thereby, it is possible to improve the analysis accuracy of the behavior of carriers in the source / drain and channel of the transistor including not only the steady state but also the transient state. At the same time, such analysis can be performed within a time that is practically acceptable.

  As described above, according to the fifth embodiment, the same effects as those of the first to fourth embodiments described above can be obtained. In addition, the semiconductor device according to the present embodiment is designed and / or inspected by using any one of the aforementioned semiconductor device design simulation model, semiconductor device design simulation device, or semiconductor device design simulation method. Thereby, the performance as desired can be exhibited. In addition, such a semiconductor device has improved performance, quality, and reliability, and improved yield. As a result, production efficiency is improved, and production can be performed at low cost.

  Similarly, the semiconductor device manufacturing method of the present embodiment performs at least one of design and inspection using any of the above-described semiconductor device design simulation model, semiconductor device design simulation device, or semiconductor device design simulation method. Do. As a result, a semiconductor device capable of exhibiting substantially desired performance can be easily manufactured.

  As described above, the reason why the NQS simulation model according to the present invention has to be taken into account is that, in the conventional NQS simulation model and the QS simulation model, the carrier response almost follows the voltage operation of the MOSFET operating at high speed. That is not. In order to design a semiconductor device that can exhibit the desired performance, it is necessary to design the device while avoiding such a situation. To that end, studies conducted by the present inventors have shown that a quick and good carrier response can be realized, for example, by shortening the channel length. However, it is actually extremely difficult to simply shorten the channel length. Since the channel length greatly affects the performance of the semiconductor device, extremely careful consideration is required for setting the length. In designing a semiconductor device, such a difficulty can be overcome by performing a simulation using the NQS simulation model according to the present invention. That is, in order to design a semiconductor device that can perform as desired by performing a simulation using the NQS simulation model according to the present invention before actually manufacturing the semiconductor device, the channel length is set to what extent. It can be known whether the carrier response can be quickly and satisfactorily shortened. Thereby, it becomes possible to easily manufacture a semiconductor device including a transistor having an appropriate channel length capable of exhibiting substantially desired performance.

  The semiconductor device according to the present invention is not limited to the first to fifth embodiments described above. Without departing from the spirit of the present invention, a part of the configuration or manufacturing process can be changed to various settings, or various settings can be appropriately combined and used. .

  For example, the circuit simulator that can incorporate the NQS simulation model HiSIM1 according to one aspect of the present invention is not limited to the SPICE 3 described in the fourth embodiment. The NQS simulation model HiSIM1 according to one embodiment of the present invention can be used in combination with other various circuit simulators. Further, in the turn-off transient calculation of the MOSFET, it is not always necessary to linearly approximate the carrier density distribution. When various carrier density distributions appearing with respect to turn-off deviate from the linear approximation, appropriate approximation may be appropriately performed accordingly.

DESCRIPTION OF SYMBOLS 1 ... NQS simulation model HiSIM (simulation model for semiconductor device design) 2 ... Simulator for semiconductor circuit design (simulation device for semiconductor device design)

Claims (12)

A semiconductor device design simulation method used in a semiconductor device design simulation device,
The semiconductor device design simulation device inputs a voltage condition for each time step from the circuit simulator, a time interval, and a flag indicating a convergence state in the previous circuit simulator,
The semiconductor device design simulation device performs a steady state calculation based on the input voltage condition,
The semiconductor device design simulation device checks the input flag,
When the flag indicates abnormal convergence by the semiconductor device design simulation device, the voltage condition and the transient charge density state of the previous time are set as the previous voltage condition and the transient charge density state,
If the flag indicates normal convergence by the semiconductor device design simulation device, a non-quasi-static model is calculated,
By the semiconductor device design simulation device, the previous voltage condition and transient charge density state are set as the previous voltage condition and transient charge density state, and the voltage condition and transient newly calculated by the non-quasi-static model are set. Set the charge density state as the previous voltage condition and transient charge density state,
Returning the conduction current and the transient charge of each electrode to the circuit simulator after the calculation of the non-quasi-static model by the simulation device for semiconductor device design,
The non-quasi-static model is
Transient density at a given time t _i of a carrier running between the source and the drain of the transistor and q (t _i), the transient of the carrier at a predetermined time t _i-1 prior to the time t _i Q (t _i-1 ), the density of the carrier between the source and the drain in the steady state assuming a quasi-static state at time t _i is Q (t _i ), and The time taken for the carrier to reach the drain from the source is denoted by τ, and q (t _i ), q (t _i-1 ), Q (t _i ), and τ are the time t _i−. the first equation which satisfies the time from ₁ to the t _i the time _{(t i -t i-1)} , q (t i) = q (t i-1) + (t i -t i-1) / τ [Q (t _i ) −q (t _i−1 )],
The current that flows between the source and the drain at the time t _i is I (t _i ), the conduction current that constantly flows between the source and the drain is I _DC, and the displacement that flows between the source and the drain A current is dQ (t _i ) / dt, and I (t _i ), I _DC , and dQ (t _i ) / dt satisfy a second equation that satisfies the time t _i , where I (t _i ) = I _DC + dQ (t _i ) / dt,
A simulation method for designing a semiconductor device, which is obtained by substituting Q (t _i ) obtained from the first equation into the second equation. Τ _cndt is the time taken for the head of the carrier to reach the drain from the source, and τ _chrg is the time τ _{chrg taken} for the carrier to be injected between the source and the drain. _2. The semiconductor device design simulation method according to claim 1, wherein _cndt and τ _{chrg satisfy} the following third expression: 1 / τ = 1 / τ _cndt + 1 / τ _chrg . In a state where no channel is formed between the source and the drain, a time required for the head of the carrier injected between the source and the drain from the source to reach the drain is τ _cndt1 , The time taken for the carriers injected between the source and the drain to move from the source to the drain in a state where a channel is formed by filling the space between the source and the drain with the carrier. ₃ , wherein τ _cndt , τ _cndt1 , and τ _{cndt2 satisfy} the following fourth expression: 1 / τ _cndt = 1 / τ _cndt1 + 1 / τ _cndt2 The simulation method for semiconductor device design as described. Wherein the semiconductor device design simulation apparatus for the semiconductor device design simulation method according to claim 2 or 3, characterized in that setting the tau _chrg so as to follow the rise time t _r of the gate voltage as a pulse signal .   A simulation apparatus for designing a semiconductor device, wherein a simulation model based on the simulation method for designing a semiconductor device according to claim 1 is incorporated.   A simulation method for designing a semiconductor device, comprising a step of analyzing electrical characteristics of the semiconductor device by the simulation method for designing a semiconductor device according to claim 1.   5. A semiconductor device, wherein at least one of transistor design and inspection is performed using the simulation method for designing a semiconductor device according to claim 1.   6. A semiconductor device, wherein at least one of transistor design and inspection is performed by the semiconductor device design simulation apparatus according to claim 5.   A semiconductor device, wherein at least one of transistor design and inspection is performed by the semiconductor device design simulation method according to claim 6.   A method for manufacturing a semiconductor device, comprising the step of performing at least one of transistor design and inspection using the simulation method for semiconductor device design according to claim 1.   6. A method of manufacturing a semiconductor device, comprising a step of performing at least one of transistor design and inspection by the semiconductor device design simulation apparatus according to claim 5.   A method for manufacturing a semiconductor device, comprising a step of performing at least one of transistor design and inspection by the semiconductor device design simulation method according to claim 6.

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