JP2010171126A - High-frequency semiconductor device - Google Patents

High-frequency semiconductor device Download PDF

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Publication number
JP2010171126A
JP2010171126A JP2009010996A JP2009010996A JP2010171126A JP 2010171126 A JP2010171126 A JP 2010171126A JP 2009010996 A JP2009010996 A JP 2009010996A JP 2009010996 A JP2009010996 A JP 2009010996A JP 2010171126 A JP2010171126 A JP 2010171126A
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Japan
Prior art keywords
drain
gate
wire
frame
cavity
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Granted
Application number
JP2009010996A
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Japanese (ja)
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JP5083229B2 (en
Inventor
Keiichi Kawashima
慶一 川嶋
Go Hosomi
剛 細見
Toshikazu Hirayama
敏和 平山
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2009010996A priority Critical patent/JP5083229B2/en
Priority to TW098112996A priority patent/TWI393222B/en
Priority to CN2009101511018A priority patent/CN101783326B/en
Priority to CN201110317683.XA priority patent/CN102339802B/en
Publication of JP2010171126A publication Critical patent/JP2010171126A/en
Application granted granted Critical
Publication of JP5083229B2 publication Critical patent/JP5083229B2/en
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13064—High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
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    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/181—Encapsulation

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high-frequency semiconductor device that can increase wire lengths of a gate wire and a drain wire. <P>SOLUTION: The high-frequency semiconductor device includes a package having a cavity, a semiconductor chip disposed on a cavity bottom surface and having a gate electrode, a source electrode and a drain electrode on an upper surface, a gate frame, a drain frame and a source frame disposed on the cavity bottom surface, the gate wire connecting the gate electrode and gate frame to each other, the drain wire connecting the drain electrode and drain frame to each other, and a source wire connecting the source electrode and source frame to each other. Then the semiconductor chip is disposed a predetermined offset away from the center part of the cavity bottom surface so as to have longer lengths of the gate wire and drain wire than when disposed at the center part of the cavity bottom surface. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、パッケージ内に半導体チップを備える高周波半導体装置に関する。   The present invention relates to a high-frequency semiconductor device including a semiconductor chip in a package.

半導体チップを保護するために半導体チップをパッケージが備えるキャビティ底面に配置する場合がある。前述のキャビティには半導体チップの外部との高周波電気信号の授受を可能にするためのフレーム（リードフレーム）の一部が配置される。このフレームの他の部分はパッケージ外部に伸びる。そして、半導体チップは金線ワイヤなどで前述のフレームと接続され、パッケージに覆われた状態で高周波電気信号の授受が可能な高周波半導体装置が製造される。このように実装されることが多い半導体チップの一例としてはＨＥＭＴ(High electron mobility transistor)を挙げることができる。   In order to protect the semiconductor chip, the semiconductor chip may be disposed on the bottom surface of the cavity included in the package. A part of a frame (lead frame) for enabling transmission / reception of high-frequency electrical signals to / from the outside of the semiconductor chip is disposed in the cavity. The other part of the frame extends outside the package. Then, the semiconductor chip is connected to the above-described frame with a gold wire or the like, and a high-frequency semiconductor device capable of transmitting and receiving a high-frequency electric signal in a state covered with a package is manufactured. An example of a semiconductor chip that is often mounted in this manner is a HEMT (High Electron Mobility Transistor).

なお、上述した高周波半導体装置はパッケージに半導体チップを搭載し所望のワイヤ配線を行った後にパッケージ上面にキャップを取り付け、半導体チップを密閉するタイプのものが多い。   The high-frequency semiconductor device described above is often of a type in which a semiconductor chip is mounted on a package, a desired wire wiring is performed, a cap is attached to the upper surface of the package, and the semiconductor chip is sealed.

一般に高周波半導体装置のパッケージ外部形状および外部寸法は標準化されているため、高周波半導体装置の形状および寸法は制限されている。また、製造コストの観点からも上述の標準化されたパッケージを用いることが好ましい。従ってパッケージが備えるキャビティの容積もこの制限を受けて一定の容積以下となる。   Generally, since the package external shape and external dimensions of a high-frequency semiconductor device are standardized, the shape and dimensions of the high-frequency semiconductor device are limited. From the viewpoint of manufacturing cost, it is preferable to use the standardized package described above. Therefore, the volume of the cavity included in the package is also less than a certain volume due to this limitation.

さらに、組み立て容易性の観点から半導体チップはパッケージのキャビティ底面の中央部に配置される。また、半導体チップとフレームを接続するワイヤの一端は、フレームのワイヤ接続可能領域の中央に接続されることが一般的である。   Further, from the viewpoint of ease of assembly, the semiconductor chip is arranged at the center of the bottom surface of the cavity of the package. Further, one end of the wire connecting the semiconductor chip and the frame is generally connected to the center of the wire connectable region of the frame.

特開２００３−００７７２７号公報JP 2003-007727 A 実開平０３−００３７３７号公報Japanese Utility Model Publication No. 03-003737 特開昭６３−０８６５５５号公報JP 63-086555 A 特開平１０−０７０１５９号公報Japanese Patent Laid-Open No. 10-070159 特開平０４−１９９５４３号公報Japanese Patent Laid-Open No. 04-199543 特開平０８−１５３８１７号公報Japanese Patent Laid-Open No. 08-153817

半導体チップとフレームの接続に用いられるワイヤのワイヤ長は高周波半導体装置の組み立て容易性およびワイヤ接続容易性の観点からパッケージのタイプに応じて一義的に定められるものであった。しかしながら、後述する通り、本願の発明者はゲート、ドレイン、ソースを備える半導体チップにおいてゲートワイヤおよびドレインワイヤそれぞれのワイヤ長を延長することが高周波半導体装置の周波数特性改善に効果的であることを見出している。そして、上述した通りワイヤ長はパッケージのタイプに応じて一義的に定められるため、ゲートワイヤおよびドレインワイヤのワイヤ長を延長できない問題があった。   The wire length of the wire used for connecting the semiconductor chip and the frame is uniquely determined according to the package type from the viewpoint of ease of assembly and wire connection of the high-frequency semiconductor device. However, as will be described later, the inventors of the present application have found that extending the wire lengths of the gate wire and the drain wire in a semiconductor chip having a gate, a drain, and a source is effective in improving the frequency characteristics of the high-frequency semiconductor device. ing. Since the wire length is uniquely determined according to the package type as described above, there is a problem that the wire length of the gate wire and the drain wire cannot be extended.

また、ゲートワイヤおよびドレインワイヤのワイヤ長を延長するために大型のパッケージを用いることは前述の標準に準ずることを妨げたり製造コストの増大を伴ったりする問題があった。   In addition, the use of a large package for extending the wire length of the gate wire and the drain wire has a problem in that it does not comply with the above-mentioned standard and increases the manufacturing cost.

本発明は、上述のような課題を解決するためになされたもので、パッケージのタイプ（外部形状および外部寸法）を大型化することなく、ゲートワイヤおよびドレインワイヤのワイヤ長を延長できる高周波半導体装置を提供することを目的とする。   The present invention has been made to solve the above-described problems, and a high-frequency semiconductor device capable of extending the wire length of a gate wire and a drain wire without increasing the package type (external shape and external dimensions). The purpose is to provide.

本願の発明にかかる高周波半導体装置は、キャビティを有するパッケージと、該キャビティ底面に配置され、上面にゲート電極、ソース電極、ドレイン電極を有する半導体チップと、該キャビティ底面に配置されたゲートフレームと、該キャビティ底面に配置されたドレインフレームと、該キャビティ底面に配置されたソースフレームと、該ゲート電極と該ゲートフレームを接続するゲートワイヤと、該ドレイン電極と該ドレインフレームを接続するドレインワイヤと、該ソース電極と該ソースフレームを接続するソースワイヤとを備える。そして、該半導体チップは、該半導体チップが該キャビティ底面の中央部に配置された場合と比較して該ゲートワイヤおよび該ドレインワイヤの長さが長くなるように該中央部から所定のオフセットだけ離間して配置されたことを特徴とする。   A high-frequency semiconductor device according to the invention of the present application includes a package having a cavity, a semiconductor chip disposed on the bottom surface of the cavity and having a gate electrode, a source electrode, and a drain electrode on the top surface, a gate frame disposed on the bottom surface of the cavity, A drain frame disposed on the bottom surface of the cavity; a source frame disposed on the bottom surface of the cavity; a gate wire connecting the gate electrode and the gate frame; a drain wire connecting the drain electrode and the drain frame; A source wire connecting the source electrode and the source frame; The semiconductor chip is separated from the central portion by a predetermined offset so that the lengths of the gate wire and the drain wire are longer than when the semiconductor chip is disposed at the central portion of the bottom surface of the cavity. It is characterized by being arranged.

本願の発明にかかる高周波半導体装置は、キャビティを有するパッケージと、該キャビティ底面に配置され、上面にゲート電極、ソース電極、ドレイン電極を有する半導体チップと、該キャビティ底面に配置されたゲートフレームと、該キャビティ底面に配置されたドレインフレームと、該キャビティ底面に配置されたソースフレームと、該ゲート電極と該ゲートフレームを接続するゲートワイヤと、該ドレイン電極と該ドレインフレームを接続するドレインワイヤと、該ソース電極と該ソースフレームを接続するソースワイヤとを備える。そして、該ゲート電極は、該ゲート電極が該ゲートフレームと最近接して配置された場合と比較して該ゲートワイヤの長さを長くするように、該半導体チップ上面のうち該ゲートフレームと最近接せず該ゲートフレームと離間した位置に配置され、該ドレイン電極は、該ドレイン電極が該ドレインフレームと最近接して配置された場合と比較して該ドレインワイヤの長さを長くするように、該半導体チップ上面のうち該ドレインフレームと最近接せず該ドレインフレームと離間した位置に配置されていることを特徴とする。   A high-frequency semiconductor device according to the invention of the present application includes a package having a cavity, a semiconductor chip disposed on the bottom surface of the cavity and having a gate electrode, a source electrode, and a drain electrode on the top surface, a gate frame disposed on the bottom surface of the cavity, A drain frame disposed on the bottom surface of the cavity; a source frame disposed on the bottom surface of the cavity; a gate wire connecting the gate electrode and the gate frame; a drain wire connecting the drain electrode and the drain frame; A source wire connecting the source electrode and the source frame; Then, the gate electrode is disposed on the upper surface of the semiconductor chip closest to the gate frame so as to increase the length of the gate wire as compared with the case where the gate electrode is disposed closest to the gate frame. The drain electrode is disposed at a position spaced apart from the gate frame, and the drain electrode is formed so as to increase the length of the drain wire as compared with the case where the drain electrode is disposed closest to the drain frame. It is characterized in that the semiconductor chip is disposed at a position apart from the drain frame without being closest to the drain frame on the upper surface of the semiconductor chip.

本願の発明にかかる高周波半導体装置は、キャビティを有するパッケージと、該キャビティ底面に配置され、上面にゲート電極、ソース電極、ドレイン電極を有する半導体チップと、該キャビティ底面に配置されたゲートフレームと、該キャビティ底面に配置されたドレインフレームと、該キャビティ底面に配置されたソースフレームと、該ゲート電極と該ゲートフレームを接続するゲートワイヤと、該ドレイン電極と該ドレインフレームを接続するドレインワイヤと、該ソース電極と該ソースフレームを接続するソースワイヤとを備える。そして、該ゲートワイヤと該ドレインワイヤは該ソースワイヤよりも該キャビティ底面に対して垂直方向に高く伸びることを特徴とする。   A high-frequency semiconductor device according to the invention of the present application includes a package having a cavity, a semiconductor chip disposed on the bottom surface of the cavity and having a gate electrode, a source electrode, and a drain electrode on the top surface, a gate frame disposed on the bottom surface of the cavity, A drain frame disposed on the bottom surface of the cavity; a source frame disposed on the bottom surface of the cavity; a gate wire connecting the gate electrode and the gate frame; a drain wire connecting the drain electrode and the drain frame; A source wire connecting the source electrode and the source frame; The gate wire and the drain wire extend higher in the direction perpendicular to the bottom surface of the cavity than the source wire.

本発明によりパッケージを大型化することなくゲートワイヤとドレインワイヤを延長することができる。   According to the present invention, the gate wire and the drain wire can be extended without increasing the size of the package.

実施の形態
本実施形態は図１〜図７を参照して説明する。なお、同一材料または同一、対応する構成要素には同一の符号を付して複数回の説明を省略する場合がある。 Embodiment This embodiment will be described with reference to FIGS. In some cases, the same material or the same and corresponding components are denoted by the same reference numerals and the description thereof is omitted.

図１は本実施形態の高周波半導体装置１０を説明する正面図であり、説明の便宜上パッケージの有するキャビティ内も表示する図である。パッケージ１２は例えばモールド樹脂などの非導電体である。パッケージ１２はキャビティ１６を備え、その容積はパッケージ１２およびその蓋であるキャップ１４により規定される。   FIG. 1 is a front view for explaining the high-frequency semiconductor device 10 of the present embodiment, and also shows the inside of the cavity of the package for convenience of explanation. The package 12 is a nonconductor such as a mold resin. The package 12 includes a cavity 16 whose volume is defined by the package 12 and a cap 14 which is its lid.

そして、キャビティ１６底面にはソースフレーム２０が配置されている。ソースフレーム２０は後述の半導体チップを高周波半導体装置の外部と電気的に接続するための導電体である。ソースフレーム２０の所定位置には接着剤１５を介して半導体チップ１３が配置される。半導体チップ１３は、図１から把握されるように、キャビティ１６底面の中央部ではなく中央部から所定のオフセット（所定の距離）だけ離間して配置されている。本実施形態でこのオフセットは１００μｍ以上である。つまり、半導体チップ１３はキャビティ１６底面の中央部よりもキャビティ１６側壁側へ１００μｍ以上離間している。   A source frame 20 is disposed on the bottom surface of the cavity 16. The source frame 20 is a conductor for electrically connecting a semiconductor chip described later to the outside of the high-frequency semiconductor device. A semiconductor chip 13 is disposed at a predetermined position of the source frame 20 via an adhesive 15. As can be understood from FIG. 1, the semiconductor chip 13 is arranged not at the center of the bottom surface of the cavity 16 but at a predetermined offset (predetermined distance) from the center. In this embodiment, this offset is 100 μm or more. That is, the semiconductor chip 13 is separated from the central portion of the bottom surface of the cavity 16 by 100 μm or more toward the side wall of the cavity 16.

半導体チップ１３はその上面にゲート電極、ソース電極、ドレイン電極を有する。キャビティ１６底面の平面図である図３には上述のゲート電極、ソース電極、ドレイン電極がゲート電極６０、ソース電極６４、ドレイン電極６２として示されている。前述のソースフレーム２０はこのソース電極６４と高周波半導体装置外部とを接続するためのリードフレームである。   The semiconductor chip 13 has a gate electrode, a source electrode, and a drain electrode on its upper surface. In FIG. 3, which is a plan view of the bottom surface of the cavity 16, the above-described gate electrode, source electrode, and drain electrode are shown as a gate electrode 60, a source electrode 64, and a drain electrode 62. The aforementioned source frame 20 is a lead frame for connecting the source electrode 64 and the outside of the high-frequency semiconductor device.

ソースフレーム２０と同様に、ゲートフレーム１８とドレインフレーム２２もキャビティ１６底面に配置されている。ゲートフレーム１８とドレインフレーム２２はそれぞれゲート電極６０とドレイン電極６２を高周波半導体装置外部と接続するためのリードフレームであり、ソースフレーム２０と同様に高周波半導体装置外部へ伸びる部分を有する。ゲートフレーム１８とドレインフレーム２２は、図１の側面図である図２に示されている。   Similar to the source frame 20, the gate frame 18 and the drain frame 22 are also arranged on the bottom surface of the cavity 16. The gate frame 18 and the drain frame 22 are lead frames for connecting the gate electrode 60 and the drain electrode 62 to the outside of the high-frequency semiconductor device, respectively, and have portions extending to the outside of the high-frequency semiconductor device, like the source frame 20. The gate frame 18 and the drain frame 22 are shown in FIG. 2, which is a side view of FIG.

半導体チップ１３の各電極と前述の各フレームとの接続は金線ワイヤを用いて行われる。前述の金線ワイヤによる接続は図３を参照して説明する。まず、ソースワイヤ３０は、一端が半導体チップ１３のソース電極６４と接続され、他端がソースフレーム２０に接続される。   Connection between each electrode of the semiconductor chip 13 and each of the above-described frames is performed using a gold wire. The connection using the gold wire described above will be described with reference to FIG. First, the source wire 30 has one end connected to the source electrode 64 of the semiconductor chip 13 and the other end connected to the source frame 20.

ゲートワイヤ３２は、一端が半導体チップ１３のゲート電極６０と接続され、他端がゲートパッド１９に接続される。ゲートパッド１９とはゲートフレーム１８の一部であってワイヤ接続可能な領域のことをいう。ここで、ゲートワイヤ３２とゲートパッド１９との接続点はゲートパッド１９の中央部ではなく、当該接続点をゲートパッド中央部に設けた場合と比較してゲートワイヤ３２の長さが長くなるように、ゲートパッド１９の中央部から離間した位置に設けられる。具体的にはゲートパッド１９のなかで、ゲートパッド１９の中央部よりも半導体チップ１３と離間した位置にゲートワイヤ３２が接続される。   The gate wire 32 has one end connected to the gate electrode 60 of the semiconductor chip 13 and the other end connected to the gate pad 19. The gate pad 19 is a part of the gate frame 18 that can be connected to the wire. Here, the connection point between the gate wire 32 and the gate pad 19 is not the central portion of the gate pad 19, but the length of the gate wire 32 is longer than that when the connection point is provided in the central portion of the gate pad 19. The gate pad 19 is provided at a position separated from the center portion. Specifically, in the gate pad 19, the gate wire 32 is connected to a position farther from the semiconductor chip 13 than the central portion of the gate pad 19.

ドレインワイヤ３４は、一端が半導体チップ１３のドレイン電極６２と接続され、他端がドレインパッド２３に接続される。ドレインパッド２３とはドレインフレーム２２の一部であってワイヤ接続可能な領域のことをいう。ここで、ドレインワイヤ３４とドレインパッド２３との接続点はドレインパッド２３の中央部ではなく、当該接続点をドレインパッド中央部に設けた場合と比較してドレインワイヤ３４の長さが長くなるように、ドレインパッド２３の中央部から離間した位置に設けられる。具体的にはドレインパッド２３のなかで、ドレインパッド２３の中央部よりも半導体チップ１３と離間した位置にドレインワイヤ３４が接続される。   The drain wire 34 has one end connected to the drain electrode 62 of the semiconductor chip 13 and the other end connected to the drain pad 23. The drain pad 23 is a part of the drain frame 22 and can be connected to a wire. Here, the connection point between the drain wire 34 and the drain pad 23 is not the central portion of the drain pad 23, but the length of the drain wire 34 is longer than that in the case where the connection point is provided in the central portion of the drain pad. The drain pad 23 is provided at a position separated from the center of the drain pad 23. Specifically, in the drain pad 23, the drain wire 34 is connected to a position farther from the semiconductor chip 13 than the central portion of the drain pad 23.

本実施形態の高周波半導体装置は上述の構成を備える。以後、本実施形態の高周波半導体装置の作用効果について説明する。   The high-frequency semiconductor device of this embodiment has the above-described configuration. Hereinafter, functions and effects of the high-frequency semiconductor device of this embodiment will be described.

高周波半導体装置においては装置の安定性を表す安定係数Ｋを良好な値とすることが求められる。安定係数とは高周波半導体装置が不安定動作を起こすかを示す重要なファクタであり以下の式１により算出される。   In a high-frequency semiconductor device, it is required that the stability coefficient K representing the stability of the device be a good value. The stability coefficient is an important factor indicating whether the high-frequency semiconductor device causes an unstable operation, and is calculated by the following formula 1.

Figure 2010171126
Figure 2010171126

ここで、Ｋは安定係数であり、Ｓ１１は入力電力反射係数であり、Ｓ２２は出力電力反射係数であり、Ｓ２１は電力利得であり、Ｓ１２は逆方向電力利得である。 Here, K is a stability coefficient, S 11 is an input power reflection coefficient, S 22 is an output power reflection coefficient, S 21 is a power gain, and S 12 is a reverse power gain.

上述のＳ１２は高周波信号の通過損失を表し、この値を低減することが安定係数Ｋの改善に効果的である。そこで本願の発明者は鋭意研究を行った結果、金線ワイヤ長を変化させる試験を行い、ゲートワイヤとドレインワイヤのワイヤ長を延長することでＳ１２（逆方向電力利得）を低減できることを見出した。その結果を図４に示す。図４は本実施形態におけるＳ１２（逆方向電力利得）の周波数特性と、比較例におけるＳ１２（逆方向電力利得）の周波数特性とを比較するグラフである。 S 12 described above represents the transmission loss of high-frequency signals, is effective in improving the stability factor K to reduce this value. Therefore, the inventors of the present application have conducted intensive research and found that it is possible to reduce S 12 (reverse power gain) by extending the wire length of the gate wire and the drain wire by performing a test to change the gold wire length. It was. The result is shown in FIG. FIG. 4 is a graph comparing the frequency characteristic of S 12 (reverse power gain) in this embodiment with the frequency characteristic of S 12 (reverse power gain) in the comparative example.

ここで、比較例の構成は、図３で示されるパッケージのキャビティ底面の構成とほぼ同等であるが、半導体チップがキャビティ底面の中央部に配置され、かつ、ゲートワイヤとゲートパッドとはゲートパッドの中央部において接続され、ドレインワイヤとドレインパッドとはドレインパッドの中央部において接続される構成である。   Here, the configuration of the comparative example is almost the same as the configuration of the bottom surface of the cavity of the package shown in FIG. 3, but the semiconductor chip is arranged at the center of the bottom surface of the cavity, and the gate wire and the gate pad are the gate pad. The drain wire and the drain pad are connected at the central portion of the drain pad.

図４から把握されるように、比較例の高周波半導体装置の周波数特性は高周波側でＳ１２（逆方向電力利得）が悪化する。一方、本実施形態の高周波半導体装置の周波数特性は高周波側であってもＳ１２（逆方向電力利得）の劣化がなくＳ１２の低減が可能であることが示されている。 As can be seen from FIG. 4, in the frequency characteristics of the high-frequency semiconductor device of the comparative example, S 12 (reverse power gain) deteriorates on the high-frequency side. On the other hand, the frequency characteristics of the high-frequency semiconductor device of this embodiment is shown to be possible to reduce the deterioration without S 12 of S 12 be high frequency side (reverse power gain).

このようにゲートワイヤとドレインワイヤのワイヤ長を延長することは、Ｓ１２の低減に有効なものではあるが、標準によって定められたパッケージ外形および寸法の制約がある中でワイヤ長を延長することは困難であるという問題があった。 Thus to extend the wire length of the gate wires and the drain wire, albeit those effective in reducing the S 12, to extend the wire length among other constraints package outline and dimensions defined by the standard Had the problem of being difficult.

しかしながら、本実施形態の構成によれば半導体チップ１３がキャビティ１６底面の中央部に配置された場合と比較してゲートワイヤ３２およびドレインワイヤ３４の長さが長くなるように中央部から所定のオフセット（１００μｍ以上）だけ離間して配置される。よって、ゲートワイヤ３２とドレインワイヤ３４の延長が可能であり、Ｓ１２の低減、すなわち安定係数の改善を行うことができる。 However, according to the configuration of the present embodiment, the gate wire 32 and the drain wire 34 have a predetermined offset from the central portion so that the lengths of the gate wire 32 and the drain wire 34 are longer than when the semiconductor chip 13 is disposed at the central portion of the bottom surface of the cavity 16. They are spaced apart by (100 μm or more). Therefore, it is possible to extend the gate wires 32 and the drain wire 34, it is possible to perform the reduction of S 12, namely the improvement of the stability factor.

さらに、前述の通り、ドレインワイヤ３４とドレインパッド２３との接続点はドレインパッド２３の中央部ではなく、当該接続点をドレインパッド中央部に設けた場合と比較してドレインワイヤ３４の長さが長くなるように、ドレインパッド２３の中央部から離間した位置に設けられる。また、ゲートワイヤ３２も同様の方法で延長されている。よって半導体チップ１３をキャビティ１６底面の中央部から離間させることに加えて、更にゲートワイヤ３２とドレインワイヤ３４を延長することができるから、本発明の効果を高めることができる。   Furthermore, as described above, the connection point between the drain wire 34 and the drain pad 23 is not the central portion of the drain pad 23, but the length of the drain wire 34 is longer than that when the connection point is provided in the central portion of the drain pad. The drain pad 23 is provided at a position separated from the center portion so as to be long. The gate wire 32 is also extended in the same manner. Therefore, in addition to separating the semiconductor chip 13 from the center of the bottom surface of the cavity 16, the gate wire 32 and the drain wire 34 can be further extended, so that the effect of the present invention can be enhanced.

上述のように半導体チップの位置および金線ワイヤの接続点を変更することは、キャビティ容積の増大を伴わずに実施できるので、パッケージ外形および寸法の変更は不要でありコストの増加などの弊害はない。   As described above, changing the position of the semiconductor chip and the connection point of the gold wire can be carried out without increasing the cavity volume. Therefore, it is not necessary to change the package external shape and dimensions, and there are problems such as an increase in cost. Absent.

本実施形態の主要な特徴はパッケージ外形および寸法の変更なく、ゲートワイヤとドレインワイヤの延長を可能とする構成を提供できる点にある。従って、本発明の範囲内で様々な変形が可能である。   The main feature of this embodiment is that it is possible to provide a configuration that allows extension of the gate wire and the drain wire without changing the package outline and dimensions. Accordingly, various modifications are possible within the scope of the present invention.

図５はそのような変形の一例を説明するための図である。図５は図３に対応する図であり、キャビティ底面を表す平面図である。図５では半導体チップ１３が図３の場合と比べて９０°回転して配置される。すなわち、半導体チップ１３上におけるゲート電極６０は、ゲート電極６０がゲートパッド１９と最近接して配置された場合と比較してゲートワイヤの長さを長くするように、半導体チップ１３上面のうちゲートパッド１９と最近接せずゲートパッド１９と離間した位置に配置される。また、半導体チップ１３上におけるドレイン電極６２は、ドレイン電極６２がドレインパッド２３と最近接して配置された場合と比較してドレインワイヤ７３の長さを長くするように、半導体チップ１３上面のうちドレインパッド２３と最近接せずドレインパッド２３と離間した位置に配置されている。このような構成とすると、半導体チップ１３をキャビティ底面の中央部に配置しても、パッケージの変更を伴わずゲートワイヤおよびドレインワイヤの延長が可能であり、本発明の効果を得ることができる。   FIG. 5 is a diagram for explaining an example of such a modification. FIG. 5 corresponds to FIG. 3 and is a plan view showing the cavity bottom surface. In FIG. 5, the semiconductor chip 13 is rotated by 90 ° as compared to the case of FIG. That is, the gate electrode 60 on the semiconductor chip 13 has a gate pad on the upper surface of the semiconductor chip 13 so that the length of the gate wire is longer than that in the case where the gate electrode 60 is disposed closest to the gate pad 19. The gate pad 19 is disposed at a position that is not closest to the gate pad 19 and is separated from the gate pad 19. Further, the drain electrode 62 on the semiconductor chip 13 has a drain electrode 73 on the upper surface of the semiconductor chip 13 so that the length of the drain wire 73 is longer than that in the case where the drain electrode 62 is disposed closest to the drain pad 23. The pad 23 is not closest to the pad 23 and is disposed at a position separated from the drain pad 23. With such a configuration, even if the semiconductor chip 13 is arranged at the center of the cavity bottom surface, the gate wire and the drain wire can be extended without changing the package, and the effects of the present invention can be obtained.

図５のような構成とすることは上述の効果を得ることができるが、ゲートワイヤとドレインワイヤが平行重複（接近）状態となるとＳ１２（逆方向電力利得）に悪影響を及ぼす。そのため、図５では、この点に留意してゲートワイヤ７１はゲートパッド１９の中央部に接続し、ドレインワイヤ７３はドレインパッド２３の中央部に接続している。ただし、図３を参照して説明したようにゲートワイヤおよびドレインワイヤのゲートパッドおよびドレインパッド上の接続点をそれぞれの中央部から離間させることによるワイヤ長の延長は、前述の平行重複（接近）状態による悪影響を回避できれば実施しても良い。 The configuration as shown in FIG. 5 can obtain the above-described effect, but adversely affects S 12 (reverse power gain) when the gate wire and the drain wire are in a parallel overlapping (approaching) state. Therefore, in FIG. 5, with this point in mind, the gate wire 71 is connected to the central portion of the gate pad 19, and the drain wire 73 is connected to the central portion of the drain pad 23. However, as described with reference to FIG. 3, the extension of the wire length by separating the connection points on the gate pad and the drain pad of the gate wire and the drain wire from the respective central portions is the parallel overlap (approach) described above. It may be carried out if the adverse effects due to the state can be avoided.

図６は別の変形の一例を説明する図である。図６は図３に対応する図であり、キャビティ底面を表す平面図である。図６ではソースフレーム８０が図３の場合よりも拡張して配置される。すなわち、半導体チップ１３の配置位置の自由度が高まるから、ゲートワイヤ８２およびドレインワイヤ８４を延長する際のワイヤ長としてとりえる値を拡張することができる。また、図６に示すようにゲートワイヤ８２とドレインワイヤ８４の長さを独立に制御でき、かつ、それぞれのワイヤが最も近接しない（最も離間する）ワイヤ配置とすることができる。また、半導体チップ１３の配置位置の自由度が高まった結果、ゲートワイヤ８２とドレインワイヤ８４の相対角度を９０°以上として伝送損失を抑制することが容易化できる。   FIG. 6 is a diagram for explaining an example of another modification. FIG. 6 corresponds to FIG. 3 and is a plan view showing the bottom surface of the cavity. In FIG. 6, the source frame 80 is arranged in an expanded manner as compared with the case of FIG. That is, since the degree of freedom of the arrangement position of the semiconductor chip 13 increases, the value that can be taken as the wire length when the gate wire 82 and the drain wire 84 are extended can be expanded. Further, as shown in FIG. 6, the lengths of the gate wire 82 and the drain wire 84 can be controlled independently, and the wires can be arranged such that the respective wires are not closest (most separated). Further, as a result of increasing the degree of freedom of the arrangement position of the semiconductor chip 13, it is possible to easily suppress the transmission loss by setting the relative angle between the gate wire 82 and the drain wire 84 to 90 ° or more.

図７は別の変形の一例を説明する図である。図７は半導体チップ１３および半導体チップ１３から伸びる各ワイヤを拡大した斜視図である。図７では、本発明の効果を得るために、ゲートワイヤ９０とドレインワイヤ９２をソースワイヤ９８よりも半導体チップ上面すなわちキャビティ底面に対して垂直方向に高く伸びるようにした構成が示されている。この場合に、ゲートワイヤ９８とドレインワイヤ９２がパッケージの蓋であるキャップと接触しないように形成される。このようにドレインワイヤ９２とソースワイヤ９８をキャビティ底面に対して垂直方向に高く伸びるようにすると、ドレインワイヤ９２とソースワイヤ９８を延長することができるため、本発明の効果を得ることができる。   FIG. 7 is a diagram illustrating an example of another modification. FIG. 7 is an enlarged perspective view of the semiconductor chip 13 and each wire extending from the semiconductor chip 13. FIG. 7 shows a configuration in which the gate wire 90 and the drain wire 92 extend higher in the direction perpendicular to the upper surface of the semiconductor chip, that is, the cavity bottom surface than the source wire 98 in order to obtain the effect of the present invention. In this case, the gate wire 98 and the drain wire 92 are formed so as not to come into contact with a cap that is a lid of the package. Thus, if the drain wire 92 and the source wire 98 are made to extend high in the direction perpendicular to the bottom surface of the cavity, the drain wire 92 and the source wire 98 can be extended, so that the effect of the present invention can be obtained.

本実施形態で、半導体チップはキャビティ底面の中央部から１００μｍのオフセットを設けて配置されることとしたが、本発明はこれに限定されない。この１００μｍの値は例示であって、前述のオフセットを設ける限りにおいてゲートワイヤとドレインワイヤの延長ができるので本発明の効果を得ることができる。   In the present embodiment, the semiconductor chip is arranged with an offset of 100 μm from the central portion of the bottom surface of the cavity, but the present invention is not limited to this. The value of 100 μm is an example, and the gate wire and the drain wire can be extended as long as the above-described offset is provided, so that the effect of the present invention can be obtained.

本実施形態ではワイヤは金線ワイヤとしたが、他の材料であっても良い。その他、本発明の範囲を逸脱しない範囲で様々な変形が可能である。   In this embodiment, the wire is a gold wire, but other materials may be used. In addition, various modifications can be made without departing from the scope of the present invention.

実施の形態の高周波半導体装置を説明する正面図である。It is a front view explaining the high frequency semiconductor device of an embodiment. 図１の側面図である。It is a side view of FIG. キャビティ内の平面図である。It is a top view in a cavity. 逆方向電力利得の周波数特性を説明する図である。It is a figure explaining the frequency characteristic of a reverse direction power gain. 半導体チップが図３の場合と比べて９０°回転して配置された構成を説明するキャビティ内の平面図である。It is a top view in the cavity explaining the structure by which the semiconductor chip was rotated 90 degrees compared with the case of FIG. ソースフレームを拡張した場合のキャビティ内の平面図である。It is a top view in the cavity at the time of extending a source frame. ゲートワイヤおよびドレインワイヤ高さを伸ばした構成を説明する斜視図である。It is a perspective view explaining the structure which extended the gate wire and drain wire height.

１０ 高周波半導体装置、 １２ パッケージ、 １３ 半導体チップ、 １６ キャビティ、 １８ ゲートフレーム、 ２０ ソースフレーム、 ２２ ドレインフレーム、 ３０ ソースワイヤ、 ３２ ゲートワイヤ、 ３４ ドレインワイヤ 10 high frequency semiconductor device, 12 package, 13 semiconductor chip, 16 cavity, 18 gate frame, 20 source frame, 22 drain frame, 30 source wire, 32 gate wire, 34 drain wire

Claims (5)

キャビティを有するパッケージと、
前記キャビティ底面に配置され、上面にゲート電極、ソース電極、ドレイン電極を有する半導体チップと、
前記キャビティ底面に配置されたゲートフレームと、
前記キャビティ底面に配置されたドレインフレームと、
前記キャビティ底面に配置されたソースフレームと、
前記ゲート電極と前記ゲートフレームを接続するゲートワイヤと、
前記ドレイン電極と前記ドレインフレームを接続するドレインワイヤと、
前記ソース電極と前記ソースフレームを接続するソースワイヤとを備え、
前記半導体チップは、前記半導体チップが前記キャビティ底面の中央部に配置された場合と比較して前記ゲートワイヤおよび前記ドレインワイヤの長さが長くなるように前記中央部から所定のオフセットだけ離間して配置されたことを特徴とする高周波半導体装置。 A package having a cavity;
A semiconductor chip disposed on the bottom surface of the cavity and having a gate electrode, a source electrode, and a drain electrode on the top surface;
A gate frame disposed on the bottom of the cavity;
A drain frame disposed on the bottom surface of the cavity;
A source frame disposed on the bottom of the cavity;
A gate wire connecting the gate electrode and the gate frame;
A drain wire connecting the drain electrode and the drain frame;
A source wire connecting the source electrode and the source frame;
The semiconductor chip is separated from the central portion by a predetermined offset so that the length of the gate wire and the drain wire is longer than that when the semiconductor chip is disposed at the central portion of the cavity bottom surface. A high-frequency semiconductor device characterized by being arranged. 前記半導体チップは前記キャビティ底面の中央部から１００μｍ以上離間して配置されていることを特徴とする請求項１に記載の高周波半導体装置。   The high-frequency semiconductor device according to claim 1, wherein the semiconductor chip is disposed at a distance of 100 μm or more from a central portion of the bottom surface of the cavity. 前記ゲートワイヤは、前記ゲートフレームのワイヤ接続可能領域であるゲートパッドの中央部に接続された場合と比較して前記ゲートワイヤの長さが長くなるように前記ゲートパッドの中央部から離間した場所と接続され、
前記ドレインワイヤは、前記ドレインフレームのワイヤ接続可能領域であるドレインパッドの中央部に接続された場合と比較して前記ドレインワイヤの長さが長くなるように前記ドレインパッドの中央部から離間した場所に接続されていることを特徴とする請求項１に記載の高周波半導体装置。 The gate wire is located away from the central portion of the gate pad so that the length of the gate wire is longer than that when the gate wire is connected to the central portion of the gate pad, which is a wire connectable region of the gate frame. Connected with
The drain wire is spaced apart from the central portion of the drain pad so that the length of the drain wire is longer than when connected to the central portion of the drain pad, which is a wire connectable region of the drain frame. The high-frequency semiconductor device according to claim 1, wherein the high-frequency semiconductor device is connected to. キャビティを有するパッケージと、
前記キャビティ底面に配置され、上面にゲート電極、ソース電極、ドレイン電極を有する半導体チップと、
前記キャビティ底面に配置されたゲートフレームと、
前記キャビティ底面に配置されたドレインフレームと、
前記キャビティ底面に配置されたソースフレームと、
前記ゲート電極と前記ゲートフレームを接続するゲートワイヤと、
前記ドレイン電極と前記ドレインフレームを接続するドレインワイヤと、
前記ソース電極と前記ソースフレームを接続するソースワイヤとを備え、
前記ゲート電極は、前記ゲート電極が前記ゲートフレームと最近接して配置された場合と比較して前記ゲートワイヤの長さを長くするように、前記半導体チップ上面のうち前記ゲートフレームと最近接せず前記ゲートフレームと離間した位置に配置され、
前記ドレイン電極は、前記ドレイン電極が前記ドレインフレームと最近接して配置された場合と比較して前記ドレインワイヤの長さを長くするように、前記半導体チップ上面のうち前記ドレインフレームと最近接せず前記ドレインフレームと離間した位置に配置されていることを特徴とする高周波半導体装置。 A package having a cavity;
A semiconductor chip disposed on the bottom surface of the cavity and having a gate electrode, a source electrode, and a drain electrode on the top surface;
A gate frame disposed on the bottom of the cavity;
A drain frame disposed on the bottom surface of the cavity;
A source frame disposed on the bottom of the cavity;
A gate wire connecting the gate electrode and the gate frame;
A drain wire connecting the drain electrode and the drain frame;
A source wire connecting the source electrode and the source frame;
The gate electrode is not closest to the gate frame on the upper surface of the semiconductor chip so as to increase the length of the gate wire as compared with the case where the gate electrode is disposed closest to the gate frame. Arranged at a position separated from the gate frame,
The drain electrode is not closest to the drain frame on the upper surface of the semiconductor chip so as to increase the length of the drain wire as compared with the case where the drain electrode is disposed closest to the drain frame. A high-frequency semiconductor device, wherein the high-frequency semiconductor device is disposed at a position separated from the drain frame. キャビティを有するパッケージと、
前記キャビティ底面に配置され、上面にゲート電極、ソース電極、ドレイン電極を有する半導体チップと、
前記キャビティ底面に配置されたゲートフレームと、
前記キャビティ底面に配置されたドレインフレームと、
前記キャビティ底面に配置されたソースフレームと、
前記ゲート電極と前記ゲートフレームを接続するゲートワイヤと、
前記ドレイン電極と前記ドレインフレームを接続するドレインワイヤと、
前記ソース電極と前記ソースフレームを接続するソースワイヤとを備え、
前記ゲートワイヤと前記ドレインワイヤは前記ソースワイヤよりも前記キャビティ底面に対して垂直方向に高く伸びることを特徴とする高周波半導体装置。 A package having a cavity;
A semiconductor chip disposed on the bottom surface of the cavity and having a gate electrode, a source electrode, and a drain electrode on the top surface;
A gate frame disposed on the bottom of the cavity;
A drain frame disposed on the bottom surface of the cavity;
A source frame disposed on the bottom of the cavity;
A gate wire connecting the gate electrode and the gate frame;
A drain wire connecting the drain electrode and the drain frame;
A source wire connecting the source electrode and the source frame;
The high-frequency semiconductor device according to claim 1, wherein the gate wire and the drain wire extend higher in a direction perpendicular to the bottom surface of the cavity than the source wire.
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CN102339802B (en) 2015-05-13
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CN101783326A (en) 2010-07-21
CN102339802A (en) 2012-02-01
CN101783326B (en) 2012-07-04

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