JP2010165747A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2010165747A
JP2010165747A JP2009005089A JP2009005089A JP2010165747A JP 2010165747 A JP2010165747 A JP 2010165747A JP 2009005089 A JP2009005089 A JP 2009005089A JP 2009005089 A JP2009005089 A JP 2009005089A JP 2010165747 A JP2010165747 A JP 2010165747A
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semiconductor device
wiring board
sealing resin
wiring substrate
semiconductor element
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Hiroshi Aoki
広志 青木
Yoshiaki Narisawa
良明 成沢
Tetsuya Hiraoka
哲也 平岡
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Fujitsu Semiconductor Ltd
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Fujitsu Semiconductor Ltd
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Priority to JP2009005089A priority Critical patent/JP2010165747A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a structure of a semiconductor device which prevents generation of deformation, such as warpage, in a resin-sealed semiconductor device, and does not cause explosion of water contained inside an electrode, even at heat treatment, such as, remelting (reflow) treatment of the electrode, namely, can improve heat-resistance. <P>SOLUTION: The semiconductor device 50 is provided with: a wiring substrate 51, whose planar shape is rectangular; a semiconductor element 52 which is mounted in one principal surface of the wiring substrate 51; and a sealing resin 55, which covers the semiconductor element 52 in one principal surface of the wiring substrate 51, wherein in one principal surface of the wiring substrate 51, a warpage-preventing member 57 is optionally disposed between the corner of the semiconductor device 522 and the corner of the wiring substrate 51. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、半導体装置に関し、特に、配線基板の一方の主面に搭載された半導体素子が樹脂封止されてなる半導体装置に関する。   The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a semiconductor element mounted on one main surface of a wiring board is sealed with a resin.

電子機器の小型化、高密度化、ならびに高機能化に伴い、当該電子機器に搭載される半導体装置の小形化、薄形化が要求されている。   With downsizing, high density, and high functionality of electronic devices, there is a demand for downsizing and thinning of semiconductor devices mounted on the electronic devices.

かかる要求に対して、当該半導体装置の形態として、所謂ボール・グリッド・アレイ（ＢＧＡ：Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）等の表面実装型パッケージが提案されている。   In response to such a demand, a surface mount package such as a so-called ball grid array (BGA) has been proposed as a form of the semiconductor device.

当該ＢＧＡ型パッケージ構造を有する半導体装置に於いて、ボールピッチが０．８ｍｍ以下の構造については、ＦＢＧＡ（Ｆｉｎｅ ｐｉｔｃｈ Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）と称され、そのボールピッチは、更に０．３ｍｍ乃至０．４ｍｍへの狭ピッチ化が進められている。   In the semiconductor device having the BGA type package structure, the structure having a ball pitch of 0.8 mm or less is called FBGA (Fine pitch Ball Grid Array), and the ball pitch is further 0.3 mm to 0.4 mm. Narrow pitches are being promoted.

かかるＢＧＡパッケージ構造を有する半導体装置を、図１に示す。即ち、当該半導体装置１０にあっては、配線基板（支持基板、インターポーザとも称される）１の一方の主面（上面）上に、半導体集積回路素子（以下、半導体素子と称する）２が接着材３を介して載置され、配線基板１の電極端子（図示せず）と半導体素子２の電極端子（図示せず）とは、例えば金（Ａｕ）等からなるボンディングワイヤ４により接続されている。そして、当該半導体素子２ならびにボンディングワイヤ４などは、封止用樹脂５により封止されている。一方、前記配線基板１の他方の主面（下面）には、半田を主体とする球状電極端子からなる外部接続端子６が配設されている。   A semiconductor device having such a BGA package structure is shown in FIG. That is, in the semiconductor device 10, a semiconductor integrated circuit element (hereinafter referred to as a semiconductor element) 2 is bonded onto one main surface (upper surface) of a wiring substrate (also referred to as a support substrate or an interposer) 1. The electrode terminal (not shown) of the wiring board 1 and the electrode terminal (not shown) of the semiconductor element 2 are placed via the material 3 and connected by a bonding wire 4 made of, for example, gold (Au) or the like. Yes. The semiconductor element 2 and the bonding wire 4 are sealed with a sealing resin 5. On the other hand, the other main surface (lower surface) of the wiring board 1 is provided with an external connection terminal 6 made of a spherical electrode terminal mainly composed of solder.

かかる構成に於いて、前記配線基板１は、ガラスエポキシ樹脂などの絶縁性樹脂を基材とし、その一方の主面（上面）に銅（Ｃｕ）等からなる導電層（図示せず）が選択的に配設されている。当該導電層は、前記ボンディングワイヤ４が接続される部位を除いてソルダーレジスト層により選択的に被覆されている。尚、当該配線基板１は、例えば０．３０ｍｍ程の厚さを有する。   In this configuration, the wiring board 1 is made of an insulating resin such as glass epoxy resin as a base material, and a conductive layer (not shown) made of copper (Cu) or the like is selected on one main surface (upper surface) thereof. Are arranged. The conductive layer is selectively covered with a solder resist layer except for a portion to which the bonding wire 4 is connected. The wiring board 1 has a thickness of about 0.30 mm, for example.

また、当該配線基板１の他方の主面（下面）にも、銅（Ｃｕ）等からなる導電層が選択的に配設され、当該導電層は、前記半田を主体とする球状電極からなる外部接続端子６が配設される部位を除いて、ソルダーレジスト層により選択的に被覆されている。尚、当該外部接続端子６は、例えば０．２５ｍｍ乃至０．３５ｍｍ程の厚さ（高さ）を有する。   In addition, a conductive layer made of copper (Cu) or the like is selectively disposed on the other main surface (lower surface) of the wiring board 1, and the conductive layer is an external device made of a spherical electrode mainly composed of the solder. Except for the portion where the connection terminal 6 is disposed, it is selectively covered with a solder resist layer. The external connection terminal 6 has a thickness (height) of, for example, about 0.25 mm to 0.35 mm.

一方、前記半導体素子２は、その厚さが０．２０ｍｍ程とされ、その背面（電子回路非形成面）が所謂ダイボンドフィルムからなる接着材３を介して配線基板１上に固着されている。   On the other hand, the semiconductor element 2 has a thickness of about 0.20 mm, and its back surface (surface on which no electronic circuit is formed) is fixed on the wiring substrate 1 via an adhesive 3 made of a so-called die bond film.

そして、前記封止用樹脂５としては、エポキシ樹脂などの熱硬化性樹脂が適用される。そして、前記配線基板１上に於ける厚さ（高さ）が、０．６０ｍｍ程とされる。   A thermosetting resin such as an epoxy resin is applied as the sealing resin 5. The thickness (height) on the wiring board 1 is set to about 0.60 mm.

かかる構造を有する半導体装置１０の製造工程に於いて、配線基板１上に封止樹脂５を形成する際に発生する残留応力、又は封止樹脂５、当該封止樹脂５により封止される半導体素子２及び配線基板１等の半導体装置１０を構成する各部材の熱膨張係数は相違する。例えば、配線基板１の線膨張係数は約１３ｐｐｍ乃至約１５ｐｐｍであるのに対し、封止樹脂６の線膨張係数は約１０ｐｐｍ乃至約１３ｐｐｍである。   In the manufacturing process of the semiconductor device 10 having such a structure, the residual stress generated when the sealing resin 5 is formed on the wiring substrate 1, or the sealing resin 5 and the semiconductor sealed by the sealing resin 5 The thermal expansion coefficients of the members constituting the semiconductor device 10 such as the element 2 and the wiring board 1 are different. For example, the linear expansion coefficient of the wiring substrate 1 is about 13 ppm to about 15 ppm, while the linear expansion coefficient of the sealing resin 6 is about 10 ppm to about 13 ppm.

この様な構成部材の熱膨張係数の相違に起因して、当該半導体装置１０に於いては、図２（ａ）に示す如く上方に凸状となる反り、或いは図２（ｂ）に示す如く下方に凸状となる反りを生ずる場合がある。なお、図２では、前記半導体素子２、接着剤３、及びボンディングワイヤ４などの図示を省略している。この様な反りの量は、コプラナリティ値、即ち、半導体装置１０を平坦面に載置した際の外部接続端子（バンプ）６の高さの最小値と最大値の差として管理されている。   Due to the difference in the coefficient of thermal expansion of the constituent members, the semiconductor device 10 has a warp that protrudes upward as shown in FIG. 2A, or as shown in FIG. 2B. There is a case where a downwardly convex warp is generated. In FIG. 2, the semiconductor element 2, the adhesive 3, the bonding wire 4, and the like are not shown. The amount of warping is managed as a coplanarity value, that is, a difference between the minimum value and the maximum value of the height of the external connection terminal (bump) 6 when the semiconductor device 10 is placed on a flat surface.

図２に示す半導体装置１０にあっては、平坦面上に載置した際の、配線基板１の中央部に配設された外部接続端子６ａと配線基板１の周縁部近傍に配設された外部接続端子６ｂとの鉛直方向に於ける先端部の位置の差がコプラナリティ値に相当する。   In the semiconductor device 10 shown in FIG. 2, the external connection terminal 6 a disposed in the center portion of the wiring substrate 1 and the vicinity of the peripheral portion of the wiring substrate 1 when placed on a flat surface. The difference in the position of the tip in the vertical direction with respect to the external connection terminal 6b corresponds to the coplanarity value.

ボールピッチの狭ピッチ化に伴い、コプラナリティの管理値は厳しくなってきており、例えば１辺が１８ｍｍの配線基板１を備えた半導体装置にあっては、コプラナリティ値が８０μｍであることが求められる場合がある。   As the ball pitch becomes narrower, the management value of coplanarity has become stricter. For example, in a semiconductor device including a wiring board 1 with one side of 18 mm, the coplanarity value is required to be 80 μm. There is.

一辺の長さが１８ｍｍの正方形状配線基板を用いて、前記図１に示す構造を有するところの半導体装置１０の反り量を図３に示す。   FIG. 3 shows the amount of warping of the semiconductor device 10 having the structure shown in FIG. 1 using a square wiring board having a side length of 18 mm.

同図に於いて、符号ａ、符号ａ’により示す領域は、反りが殆ど発生していない領域であり、符号ｂから、符号ｃ、符号ｄ、符号ｅ、更には符号ｆという順番に従って上方への反り量が大きくなる領域を示し、一方、符号ｂ’から、符号ｃ’、符号ｄ’、符号ｅ’、更には符号ｆ’という順番に従って下方への反り量が大きくなる領域を示している。即ち、当該配線基板の中央部から離間するにつれて、反り量が大きくなってゆく。   In the same figure, areas indicated by reference signs a and a ′ are areas in which almost no warping occurs, and move upward from reference sign b in the order of reference signs c, d, e, and f. 2 shows a region where the amount of warpage increases, and on the other hand, shows a region where the amount of warpage downward increases in the order of code b ′, code c ′, code d ′, code e ′, and further code f ′. . That is, the amount of warpage increases as the distance from the center of the wiring board increases.

図３（ａ）は、半導体装置１０に於いて、その中央部が上方に凸状となる反りが発生した場合の、当該反り量の測定結果を示している。即ち、半導体装置１０は配線基板１の中央部から当該配線基板１の四隅及びその近傍の領域に向かうに従い、下方へ湾曲しており、従って、当該半導体装置１０はその中央部が上方に凸状に反っている。   FIG. 3A shows a measurement result of the amount of warping in the case where a warp in which the central portion of the semiconductor device 10 is convex upward occurs. That is, the semiconductor device 10 is curved downward from the central portion of the wiring substrate 1 toward the four corners of the wiring substrate 1 and the vicinity thereof, and thus the central portion of the semiconductor device 10 is convex upward. It is warped.

この様に、中央部が上方に凸状に反る形態は、配線基板１が４層以上の多層構造とされた場合に発生し易い。即ち、封止樹脂５の硬化収縮よりも配線基板１の熱収縮が大きく、封止樹脂５による樹脂封止工程後、封止樹脂５は配線基板１方向に引張される為、半導体装置１０にはその中央部が上方に凸状となる反りが発生し易い。   In this way, the form in which the central portion warps upward is likely to occur when the wiring board 1 has a multilayer structure of four or more layers. That is, the thermal contraction of the wiring substrate 1 is larger than the curing shrinkage of the sealing resin 5, and the sealing resin 5 is pulled in the direction of the wiring substrate 1 after the resin sealing process with the sealing resin 5. Tends to generate warpage in which the central portion is convex upward.

一方、図３（ｂ）は、半導体装置１０に於いて、その中央部が下方に凸状となる反りが発生した場合の、当該反り量の測定結果を示している。即ち、半導体装置１０は配線基板１の中央部から当該配線基板１の四隅及びその近傍の領域に向かうに従い、上方へ湾曲しており、従って、当該半導体装置１０はその中央部が下方に凸状に反っている。   On the other hand, FIG. 3B shows a measurement result of the amount of warpage in the case where a warp in which the central portion of the semiconductor device 10 is convex downward occurs. That is, the semiconductor device 10 is curved upward from the central portion of the wiring substrate 1 toward the four corners of the wiring substrate 1 and the vicinity thereof, and therefore the central portion of the semiconductor device 10 is convex downward. It is warped.

この様に、中央部が下方に凸状に反る形態は、配線基板１が２層程度の積層構造とされた場合に発生し易い。即ち、封止樹脂５の硬化収縮が配線基板１の熱収縮よりも大きく、封止樹脂５による樹脂封止工程後、配線基板１は封止用樹脂５方向に引張される為、半導体装置１０にはその中央部が下方に凸状となる反りが発生し易い。   In this way, the form in which the central portion warps downward is likely to occur when the wiring board 1 has a laminated structure of about two layers. That is, the curing shrinkage of the sealing resin 5 is larger than the thermal shrinkage of the wiring substrate 1, and after the resin sealing process with the sealing resin 5, the wiring substrate 1 is pulled in the direction of the sealing resin 5. In the case, warpage in which the central portion is convex downward tends to occur.

そして、この様に反りが生ずる場合、半導体装置１０の中心に向って各部材は引張される。従って、中心部から最も遠い位置にある配線基板の隅部に於いてより大きな変形を生ずる。   When warping occurs in this way, each member is pulled toward the center of the semiconductor device 10. Accordingly, a larger deformation occurs at the corner of the wiring board that is farthest from the center.

またこの時、作用する力が不均衡であると、半導体装置１０自体に、うねり或いは捩れが発生してしまう。   At this time, if the acting force is imbalanced, the semiconductor device 10 itself will be swelled or twisted.

尚、樹脂封止型半導体装置に於いて、半導体パッケージ用樹脂フレームなどのパッケージ基板の表面に、その縁部に沿い、且つ半導体素子搭載部を囲んで、幅広の矩形枠状金属パターンを配置することによって反りを防止することが、下記特許文献１或いは特許文献２に開示されている。また、樹脂封止型半導体装置に於いて、封止用樹脂中に、矩形枠状或いはＬ時状の鉄製補強材を配設することによって反りを防止することが、下記特許文献３に開示されている。   In a resin-encapsulated semiconductor device, a wide rectangular frame-shaped metal pattern is disposed on the surface of a package substrate such as a resin frame for a semiconductor package along the edge and surrounding the semiconductor element mounting portion. Patent Document 1 or Patent Document 2 below discloses preventing the warpage from occurring. Further, in the resin-encapsulated semiconductor device, it is disclosed in Patent Document 3 below to prevent warping by disposing a rectangular frame-shaped or L-shaped iron reinforcing material in the sealing resin. ing.

特開平９−１５３５６４号公報JP-A-9-153564 特開平１１−１３５６７７号公報JP-A-11-135679 特開２００３−９２３７６号公報JP 2003-92376 A

上述の如く、配線基板１と封止樹脂５との熱収縮量の相違によって反りが生ずることから、当該配線基板１上へ封止用樹脂５を被覆形成した後の製造工程に於いて問題が生じ、結果として半導体装置１０の製造歩留りの低下を招来してしまう。   As described above, warping occurs due to the difference in thermal shrinkage between the wiring board 1 and the sealing resin 5, and thus there is a problem in the manufacturing process after the sealing resin 5 is formed on the wiring board 1. As a result, the manufacturing yield of the semiconductor device 10 is reduced.

即ち、当該配線基板１の他方の主面に、半田を主体とする球状電極からなる外部接続端子６を配設する際、当該配線基板１に反り或いはうねりがあることにより、球状電極の配置・接続が適切に行なえない状態を生ずる可能性がある。   That is, when the external connection terminal 6 composed of a spherical electrode mainly composed of solder is disposed on the other main surface of the wiring board 1, the wiring board 1 is warped or swelled. There is a possibility that the connection cannot be properly made.

また、当該外部接続端子６が配設され、半導体装置１０が形成されたとしても、当該半導体装置１０を電子機器に適用される大判の配線基板（所謂マザーボード）に搭載する際に、外部接続端子６を形成する半田を主体とする球状電極の再溶融（リフロー）に必要な熱処理がなされることにより、前記配線基板１に於ける反り或いはうねりが助長されて、当該半導体装置１０の外部接続端子６の一部が、マザーボード上の電極端子に接続されない状態を生ずる可能性がある。   Even when the external connection terminal 6 is provided and the semiconductor device 10 is formed, when the semiconductor device 10 is mounted on a large wiring board (so-called motherboard) applied to an electronic device, the external connection terminal 6 is applied to the external connection terminal of the semiconductor device 10 by the heat treatment necessary for re-melting (reflowing) the spherical electrode mainly composed of the solder forming the semiconductor substrate 6. There is a possibility that a part of 6 is not connected to the electrode terminal on the mother board.

更に、かかる半田を主体とする球状電極の再溶融（リフロー）処理の際、加熱温度のピーク値は２４０℃乃至約２６０℃となる。   Further, when the spherical electrode mainly composed of the solder is remelted (reflowed), the peak value of the heating temperature is 240 ° C. to about 260 ° C.

この為、封止用樹脂５により被覆された構造を有する半導体装置１０にあっては、内部に含まれる水分の膨張・気化を生じ、所謂水蒸気爆発を引き起こす可能性がある。   For this reason, in the semiconductor device 10 having a structure covered with the sealing resin 5, the moisture contained therein is expanded and vaporized, which may cause a so-called steam explosion.

そして、かかる水分は、図４に示される矢印Ａ１の如く、配線基板１と封止用樹脂５との界面に沿って移動し、当該配線基板１の表面に配設されたソルダーレジスト層と封止用樹脂５との界面に於いて剥離を生じてしまう。尚、当該水分は、当該半導体装置の製造工程中に於いて、接着材３ならびに封止用樹脂５などの中に取り込まれている。   Then, the moisture moves along the interface between the wiring substrate 1 and the sealing resin 5 as indicated by an arrow A1 shown in FIG. 4, and seals with the solder resist layer disposed on the surface of the wiring substrate 1. Peeling occurs at the interface with the stop resin 5. The moisture is taken into the adhesive 3 and the sealing resin 5 during the manufacturing process of the semiconductor device.

ソルダーレジスト層と封止用樹脂５との界面に於いて剥離が生ずると、前記配線基板１の電極端子からのボンディングワイヤ４の剥離を生じ、また、半導体素子に対しての当該界面を通しての外部からの水分の侵入を容易化してしまう。   When peeling occurs at the interface between the solder resist layer and the sealing resin 5, peeling of the bonding wire 4 from the electrode terminal of the wiring board 1 occurs, and the outside through the interface with respect to the semiconductor element. Intrusion of moisture from the water will be facilitated.

尚、前記特許文献１ならびに特許文献２に示される技術にあっては、パッケージ基板の表面に、その縁部に沿って且つ半導体素子搭載部を囲んで、幅広の矩形枠状金属パターンを配置することにより当該パッケージ基板の反りを防止しようとしている。しかしながら、当該幅広の矩形枠状金属パターンの適用は、パッケージ基板の表面に於ける配線層、電極端子などの配設の自由度を大きく低下させてしまう。そして、当該配線層、電極端子などの配設の自由度を高めようとすると、当該パッケージ基板の大形化（大面積化）を招来してしまう。   In the technique disclosed in Patent Document 1 and Patent Document 2, a wide rectangular frame-shaped metal pattern is disposed on the surface of the package substrate along the edge and surrounding the semiconductor element mounting portion. This is intended to prevent warpage of the package substrate. However, the application of the wide rectangular frame-shaped metal pattern greatly reduces the degree of freedom of arrangement of wiring layers, electrode terminals, and the like on the surface of the package substrate. If an attempt is made to increase the degree of freedom in arranging the wiring layers, electrode terminals, etc., the package substrate will be increased in size (increase in area).

一方、前記特許文献３に示される技術にあっては、封止用樹脂中に、矩形枠状或いはＬ時状の鉄製補強材を配設することによって反りを防止しようとしているが、封止用樹脂中にこの様な矩形枠状或いはＬ時状の鉄製補強材を配設することは、その為の樹脂封止金型の設定、ならびに樹脂封止工程の適用が必要であり、製造される半導体装置の高価格化を招いてしまう。   On the other hand, in the technique disclosed in Patent Document 3, warping is prevented by disposing a rectangular frame-shaped or L-shaped iron reinforcing material in the sealing resin. Providing such a rectangular frame-shaped or L-shaped iron reinforcement in the resin requires the setting of a resin-sealing mold for that purpose and the application of a resin-sealing process, which is manufactured. This will increase the cost of semiconductor devices.

そして、これらの特許文献に開示される技術にあっては、半導体装置内部に於ける水分の膨張・気化、所謂水蒸気爆発の発生に対する対応策について何ら検討されていない。   In the techniques disclosed in these patent documents, no countermeasures have been studied for countermeasures against the expansion and vaporization of moisture inside the semiconductor device, that is, the so-called steam explosion.

本発明は、この様な従来技術の問題点を解決すべくなされたものであって、樹脂封止形半導体装置に於ける、反りなど変形の発生を防止すると共に、電極の再溶融（リフロー）処理など加熱処理の際にも内部に含まれる水分の爆発を招来しない、即ち耐熱性の向上を図ることができる半導体装置の構造を提供することを目的とする。   The present invention has been made to solve such problems of the prior art, and prevents the occurrence of deformation such as warpage in the resin-encapsulated semiconductor device and remelts the electrode (reflow). It is an object of the present invention to provide a structure of a semiconductor device that does not cause an explosion of moisture contained in a heat treatment such as a treatment, that is, can improve heat resistance.

本発明によれば、平面形状が矩形状を有する配線基板と、前記配線基板の一方の主面に搭載された半導体素子と、前記配線基板の一方の主面に於いて、前記半導体素子を被覆する封止用樹脂と、を具備し、前記配線基板の一方の主面に於いて、前記半導体素子の隅部と当該配線基板の隅部との間に、反り防止部材が選択的に配設されてなることを特徴とする半導体装置が提供される。   According to the present invention, a wiring board having a rectangular planar shape, a semiconductor element mounted on one main surface of the wiring board, and covering the semiconductor element on one main surface of the wiring board And a warping prevention member is selectively disposed between a corner of the semiconductor element and a corner of the wiring board on one main surface of the wiring board. Thus, a semiconductor device is provided.

本発明によれば、半導体装置の反りの発生を防止・低減すると共に、耐熱性が高められた半導体装置を提供することができる。   According to the present invention, it is possible to provide a semiconductor device with improved heat resistance while preventing or reducing the occurrence of warping of the semiconductor device.

ＢＧＡパッケージ構造を有する半導体装置の断面図である。It is sectional drawing of the semiconductor device which has a BGA package structure. 図１に示す半導体装置の反りの状態を示す図である。It is a figure which shows the state of the curvature of the semiconductor device shown in FIG. 図１に示す構造を有する半導体装置であって、配線基板として１辺が約１８ｍｍの基板を用いた場合に於ける、当該半導体装置の反りを測定した結果を示す図である。FIG. 3 is a diagram showing a result of measuring warpage of the semiconductor device having the structure shown in FIG. 1 when a substrate having a side of about 18 mm is used as a wiring substrate; 図１に示す半導体装置をマザーボード等に実装する際に発生する恐れがある問題点を示す図である。It is a figure which shows the problem which may generate | occur | produce when mounting the semiconductor device shown in FIG. 1 on a motherboard. 本発明の実施の形態に係る半導体装置を示す図である。It is a figure showing a semiconductor device concerning an embodiment of the invention. 本発明の実施の形態に係る半導体装置の第１の変形例を示す図である。It is a figure which shows the 1st modification of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の第２の変形例を示す図である。It is a figure which shows the 2nd modification of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の第３の変形例を示す図である。It is a figure which shows the 3rd modification of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の第４の変形例を示す図である。It is a figure which shows the 4th modification of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の第５の変形例を示す図である。It is a figure which shows the 5th modification of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の第６の変形例を示す図である。It is a figure which shows the 6th modification of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の第７の変形例を示す図である。It is a figure which shows the 7th modification of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の製造方法を示す図（その１）である。It is FIG. (The 1) which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の製造方法を示す図（その２）である。FIG. 6 is a diagram (part 2) illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention; 本発明の実施の形態に係る半導体装置の製造方法を示す図（その３）である。It is FIG. (3) which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の製造方法を示す図（その４）である。FIG. 6 is a view (No. 4) illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention. 本発明の実施の形態に係る半導体装置の製造方法を示す図（その５）である。It is FIG. (5) which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の製造方法を示す図（その６）である。It is FIG. (6) which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の製造方法を示す図（その７）である。FIG. 7 is a view (No. 7) showing a method for manufacturing a semiconductor device according to an embodiment of the present invention; 切断されると図６に示す反り防止部材６７を構成する集合体の平面図である。It is a top view of the aggregate | assembly which comprises the curvature prevention member 67 shown in FIG. 6 when cut | disconnected. 図１１に示す半導体装置１１０を製造する工程を説明するための図である。FIG. 12 is a diagram for explaining a process for manufacturing the semiconductor device 110 shown in FIG. 11. 図１２に示す半導体装置１２０を製造する工程を説明するための図である。FIG. 13 is a diagram for explaining a process for manufacturing the semiconductor device 120 shown in FIG. 12.

以下、図面を参照して本発明の実施の形態について説明する。   Embodiments of the present invention will be described below with reference to the drawings.

先ず、本発明の実施の形態に於ける半導体装置について説明し、次いで、当該半導体装置の製造方法について説明する。   First, a semiconductor device according to an embodiment of the present invention will be described, and then a method for manufacturing the semiconductor device will be described.

１．半導体装置
本発明の実施の形態にかかる半導体装置を、図５に示す。図５（ａ）は、当該半導体装置の上面を示し、図５（ｂ）は、図５（ａ）の点線Ａ−Ａ’ に於ける断面を示す。また、図５（ｃ）は、図５（ａ）に於いて矢印Ｐ１で示す方向に見たときの側面を示している。尚、図５（ａ）に於いては、封止用樹脂の表示を行なっていない。 1. Semiconductor Device FIG. 5 shows a semiconductor device according to an embodiment of the present invention. FIG. 5A shows a top surface of the semiconductor device, and FIG. 5B shows a cross section taken along a dotted line AA ′ in FIG. FIG. 5C shows a side view when viewed in the direction indicated by the arrow P1 in FIG. In FIG. 5A, the sealing resin is not displayed.

即ち、本発明の実施の形態に於ける半導体装置５０にあっては、配線基板（支持基板、インターポーザとも称される）５１の一方の主面（上面）の中央部に、半導体集積回路素子（以下、半導体素子と称する）５２が接着材５３を介して載置され、当該配線基板５１に配設された電極端子（図示せず）と半導体素子５２に於ける電極端子（図示せず）との間は、例えば金（Ａｕ）等からなるボンディングワイヤ５４により接続されている。そして、当該半導体素子５２ならびにボンディングワイヤ５４などは、封止用樹脂５５により封止されている。一方、前記配線基板５１の他方の主面（下面）には、半田を主体とする球状電極端子からなる外部接続端子５６が配設されている。   That is, in the semiconductor device 50 according to the embodiment of the present invention, a semiconductor integrated circuit element (on the central portion of one main surface (upper surface) of a wiring substrate (also called a support substrate or an interposer) 51 is formed. Hereinafter, an electrode terminal (not shown) disposed on the wiring substrate 51 and an electrode terminal (not shown) in the semiconductor element 52 are placed on the wiring substrate 51. Are connected by a bonding wire 54 made of, for example, gold (Au) or the like. The semiconductor element 52 and the bonding wire 54 are sealed with a sealing resin 55. On the other hand, the other main surface (lower surface) of the wiring substrate 51 is provided with an external connection terminal 56 made of a spherical electrode terminal mainly composed of solder.

前記配線基板５１は、例えば、ガラスエポキシ樹脂などの絶縁性樹脂を基材として形成され、平面形状が矩形形状を有し、その一方の主面（上面）には銅（Ｃｕ）等からなる導電層が選択的に配設されている。当該導電層は、前記ボンディングワイヤ５４が接続される領域を除いて、ソルダーレジスト層（図示せず）により選択的に被覆されている。   The wiring substrate 51 is formed using, for example, an insulating resin such as a glass epoxy resin as a base material, and has a rectangular planar shape, and one main surface (upper surface) of which is made of copper (Cu) or the like. A layer is selectively disposed. The conductive layer is selectively covered with a solder resist layer (not shown) except for the region where the bonding wire 54 is connected.

また、当該配線基板５１の他方の主面（下面）にも、銅（Ｃｕ）等からなる導電層が選択的に配設され、当該導電層は、前記半田を主体とする球状電極からなる外部接続端子５６が配設される部位を除いて、ソルダーレジスト層（図示せず）により選択的に被覆されている。   Also, a conductive layer made of copper (Cu) or the like is selectively disposed on the other main surface (lower surface) of the wiring board 51, and the conductive layer is an external formed of a spherical electrode mainly composed of the solder. Except for the portion where the connection terminal 56 is disposed, it is selectively covered with a solder resist layer (not shown).

一方、前記半導体素子５２は、シリコン（Ｓｉ）或いはガリウム砒素（ＧａＡｓ）半導体基板が用いられ、周知の半導体製造プロセスにより、その一方の主面に形成された能動素子、受動素子層ならびにこれらの機能素子を相互に接続する配線層をもって電子回路が形成されている。そして、その表面に、当該配線層に接続された電極端子（電極パッド）が設けられている。当該半導体素子５２は、その背面（電子回路非形成面）が所謂ダイボンドフィルムからなる接着材５３を介して配線基板５１上に固着されている。そして、前記封止用樹脂５５としては、エポキシ樹脂などの熱硬化性樹脂が適用される。   On the other hand, the semiconductor element 52 is made of a silicon (Si) or gallium arsenide (GaAs) semiconductor substrate, and an active element, a passive element layer, and their functions formed on one main surface by a known semiconductor manufacturing process. An electronic circuit is formed with a wiring layer for connecting elements to each other. And the electrode terminal (electrode pad) connected to the said wiring layer is provided in the surface. The semiconductor element 52 is fixed on the wiring substrate 51 via an adhesive 53 made of a so-called die-bonding film on the back surface (non-electronic circuit-formed surface). A thermosetting resin such as an epoxy resin is applied as the sealing resin 55.

この様な本発明の実施の形態に於ける半導体装置５０にあっては、その特徴的構成として、前記配線基板５１の一方の主面に於いて、前記半導体素子５２の近傍から当該配線基板５１の四つの隅部（コーナー部）に延在して、板状の反り防止部材５７が配設されている。当該反り防止部材５７も、半導体素子５２と同様、ダイボンドフィルムからなる接着材５３を介して、配線基板５１上に固着されている。   Such a semiconductor device 50 according to the embodiment of the present invention has a characteristic configuration in which one main surface of the wiring board 51 is located near the semiconductor element 52 from the vicinity of the semiconductor element 52. A plate-like warpage preventing member 57 is provided extending to the four corners (corner portions). Similar to the semiconductor element 52, the warpage preventing member 57 is also fixed on the wiring substrate 51 via an adhesive 53 made of a die bond film.

通常、半導体素子５２も平面形状が矩形状を有し、その四つの隅部が配線基板５１の四つの隅部に対応して搭載されることから、当該反り防止部材５７は、半導体素子５２の四つの隅部近傍から当該配線基板５１に於ける四つの隅部（コーナー部）に延在してそれぞれ選択的に配設される。   Normally, the semiconductor element 52 also has a rectangular shape in plan view, and its four corners are mounted corresponding to the four corners of the wiring board 51. From the vicinity of the four corners to the four corners (corner parts) in the wiring board 51, the respective parts are selectively arranged.

そして、当該反り防止部材５７は、その端部が、前記封止用樹脂５５から露出して配設されている。   The warp preventing member 57 is disposed with its end exposed from the sealing resin 55.

当該反り防止部材５７は、板状のシリコン（Ｓｉ）からなり、前記半導体素子５２と同様、所謂ダイボンディングフィルム又はペースト状等のダイボンディング材からなる接着剤５５を介して、配線基板５１上に接着固定される。当該反り防止部材５７としては、前記半導体素子５２と同等の線膨張係数（約３ｐｐｍ）及び曲げ強度（約８０ＭＰａ）を有する材料であれば、セラミック材などを適用することもできる。   The warpage preventing member 57 is made of plate-like silicon (Si), and is formed on the wiring substrate 51 via an adhesive 55 made of a die bonding material such as a so-called die bonding film or paste like the semiconductor element 52. Bonded and fixed. As the warpage preventing member 57, a ceramic material or the like can be applied as long as it has a linear expansion coefficient (about 3 ppm) and bending strength (about 80 MPa) equivalent to those of the semiconductor element 52.

この様に、前記配線基板５１の一方の主面に、半導体素子５２の四つの隅部の近傍から当該配線基板５１に於ける四つの隅部（コーナー部）のそれぞれに延在して、板状の反り防止部材５７が固着・配設されていることにより、当該配線基板５１の機械的強度が高められる。従って、当該半導体装置５０は、高い機械的強度を有し、配線基板５１ならびに封止樹脂５５などの熱膨張係数の相違に基づく反り、或いは不均衡な力に起因するうねり又は捩れの発生が防止・抑制される。   Thus, on one main surface of the wiring substrate 51, the four corners of the wiring substrate 51 are extended from the vicinity of the four corners of the semiconductor element 52 to the plate. By fixing and arranging the warp preventing member 57 in the shape, the mechanical strength of the wiring board 51 is increased. Therefore, the semiconductor device 50 has high mechanical strength, and prevents warping or twisting due to a difference in thermal expansion coefficient between the wiring substrate 51 and the sealing resin 55 or an unbalanced force.・ Suppressed.

従って、樹脂封止工程の後、当該配線基板５１の他方の主面に外部接続端子５６を配設する際にも、当該配線基板５１に反り或いはうねりが生じておらず、当該外部接続端子５６の配置・接続が適切に行なわれる。   Therefore, even when the external connection terminal 56 is disposed on the other main surface of the wiring board 51 after the resin sealing step, the wiring board 51 is not warped or undulated, and the external connection terminal 56 Are properly arranged and connected.

また、当該半導体装置５０を電子機器に適用される大判の配線基板（所謂マザーボード）に搭載する際に、前記外部接続端子５６を形成する半田を主体とする球状電極の再溶融（リフロー）処理がなされても、前記配線基板５１に於いては反り或いはうねりが生ずることなく、当該半導体装置５０の外部接続端子５６は、マザーボード上の電極端子に確実に接続される。   Further, when the semiconductor device 50 is mounted on a large-sized wiring board (so-called mother board) applied to an electronic device, remelting (reflow) processing of a spherical electrode mainly composed of solder forming the external connection terminal 56 is performed. Even if it is made, the external connection terminal 56 of the semiconductor device 50 is reliably connected to the electrode terminal on the mother board without causing warpage or undulation in the wiring board 51.

また、当該半導体装置５０に於いては、反り防止部材５７は、半導体素子５２の近傍から当該配線基板５１の四つの隅部（コーナー部）に延在して配設されているに止まり、当該配線基板５１の周縁部に沿って延在するものではない。従って、当該配線基板５１の表面に於ける、配線層、電極端子などの配設の自由度を低下させず、もって当該半導体装置５０の小形化を妨げない。   Further, in the semiconductor device 50, the warp preventing member 57 extends from the vicinity of the semiconductor element 52 to the four corners (corner portions) of the wiring substrate 51, and It does not extend along the peripheral edge of the wiring board 51. Accordingly, the degree of freedom of arrangement of wiring layers, electrode terminals, and the like on the surface of the wiring substrate 51 is not lowered, and thus miniaturization of the semiconductor device 50 is not hindered.

一方、前記反り防止部材５７は、前述の如く、半導体素子５２の四つの隅部近傍から配線基板５１に於ける四つの隅部（コーナー部）に延在され、更にその端部が封止用樹脂５５から露出して配設されている。   On the other hand, as described above, the warp preventing member 57 extends from the vicinity of the four corners of the semiconductor element 52 to the four corners (corner portions) of the wiring substrate 51, and further, the end thereof is for sealing. It is exposed from the resin 55 and disposed.

かかる構成に於いては、反り防止部材５７の構成材料であるシリコン（Ｓｉ）と封止用樹脂５６との密着性が低いため、当該反り防止部材５７と封止用樹脂５５との接触部には隙間が生じ易い。かかる隙間は、当該半導体装置５０の内部に於いて接着材５３或いは封止用樹脂５６に含まれる水分の通路となり得る。そして、反り防止部材５７の端部が、封止用樹脂５５から露出していることにより、当該水分の放散は容易になされる。   In such a configuration, since the adhesion between silicon (Si), which is a constituent material of the warp preventing member 57, and the sealing resin 56 is low, a contact portion between the warp preventing member 57 and the sealing resin 55 is not present. Are likely to have gaps. Such a gap can serve as a passage for moisture contained in the adhesive 53 or the sealing resin 56 inside the semiconductor device 50. And since the edge part of the curvature prevention member 57 is exposed from the sealing resin 55, the said water | moisture content is made easy.

この為、当該半導体装置５０をマザーボードに搭載するにあたり、半田を主体とする球状電極からなる外部接続端子５６の再溶融（リフロー）処理を行なう際には、１５０℃乃至１９０℃程の予備加熱の段階で、当該半導体装置５０の内部に含まれる水分は反り防止部材５７と封止用樹脂５５との界面に於ける隙間を通して、矢印Ｓ１の如く外部に放散される。従って、当該リフロー処理中に於いて、２４０℃乃至約２６０℃程のピーク温度に到達しても、当該半導体装置５０に於いては水蒸気爆発を生じない。   For this reason, when the semiconductor device 50 is mounted on the mother board, when re-melting (reflowing) the external connection terminal 56 made of a spherical electrode mainly composed of solder, preheating of about 150 ° C. to 190 ° C. is performed. At this stage, moisture contained in the semiconductor device 50 is diffused to the outside as indicated by an arrow S1 through a gap at the interface between the warp prevention member 57 and the sealing resin 55. Therefore, even if a peak temperature of about 240 ° C. to about 260 ° C. is reached during the reflow process, no steam explosion occurs in the semiconductor device 50.

これにより、配線基板５１上に配設されたソルダーレジスト層と封止用樹脂との間の剥離、ならびに電極端子に接続されたボンディングワイヤ５４の断線を防止することができ、当該半導体装置５０は高い信頼性を維持することができる。   As a result, peeling between the solder resist layer disposed on the wiring substrate 51 and the sealing resin and disconnection of the bonding wire 54 connected to the electrode terminal can be prevented. High reliability can be maintained.

尚、当該反り防止部材５７の表面に、例えばアルミニウム（Ａｌ）等の金属層を被覆することにより、封止用樹脂５５との密着性をより低下せしめることもできる。   In addition, by covering the surface of the warpage preventing member 57 with a metal layer such as aluminum (Al), the adhesion to the sealing resin 55 can be further reduced.

尚、当該反り防止部材５７の内端は、半導体素子５２に近接するものの、当該半導体素子５２に接しはしない。両者の間には、封止用樹脂５５が存在する。   Although the inner end of the warpage preventing member 57 is close to the semiconductor element 52, it does not contact the semiconductor element 52. A sealing resin 55 exists between the two.

かかる構成により、反り防止部材５７と封止用樹脂５５との界面に於ける隙間を通して外部から水分などが侵入して半導体素子５２に到達することを防止する。   With this configuration, moisture or the like is prevented from entering from the outside through the gap at the interface between the warpage preventing member 57 and the sealing resin 55 and reaching the semiconductor element 52.

次に、本発明の実施の形態に係る半導体装置の変形例を、図６乃至図１２を用いて示す。尚、これらの図に於いて、前記図５に示した部位に対応する部位には同じ符号を付して、その説明を省略する。   Next, modified examples of the semiconductor device according to the embodiment of the present invention will be described with reference to FIGS. In these drawings, parts corresponding to the parts shown in FIG. 5 are denoted by the same reference numerals, and description thereof is omitted.

［第１の変形例］
本発明の実施の形態に係る半導体装置の、第１の変形例を図６に示す。図６（ａ）は、当該半導体装置の上面を示し、図６（ｂ）は、図６（ａ）に於いて矢印Ｐ２で示す方向に見たときの側面を示す。尚、図６（ａ）に於いては、封止用樹脂の表示を行なっていない。 [First Modification]
FIG. 6 shows a first modification of the semiconductor device according to the embodiment of the present invention. 6A shows the top surface of the semiconductor device, and FIG. 6B shows the side surface when viewed in the direction indicated by the arrow P2 in FIG. 6A. In FIG. 6A, the sealing resin is not displayed.

即ち、本第１の変形例に於ける半導体装置６０にあっても、配線基板（支持基板、インターポーザとも称される）５１の一方の主面（上面）の中央部に、半導体素子５２が接着材５３を介して載置され、当該配線基板５１に配設された電極端子（図示せず）と半導体素子５２に於ける電極端子（図示せず）との間は、例えば金（Ａｕ）等からなるボンディングワイヤ５４により接続されている。そして、当該半導体素子５２ならびにボンディングワイヤ５４などは、封止用樹脂５５により封止されている。一方、前記配線基板５１の他方の主面（下面）には、半田を主体とする球状電極端子からなる外部接続端子５６が配設されている。   That is, even in the semiconductor device 60 according to the first modification, the semiconductor element 52 is bonded to the central portion of one main surface (upper surface) of the wiring substrate (also referred to as a support substrate or an interposer) 51. Between an electrode terminal (not shown) placed on the wiring substrate 51 and disposed on the wiring substrate 51 and an electrode terminal (not shown) in the semiconductor element 52, for example, gold (Au) or the like Are connected by a bonding wire 54 made of The semiconductor element 52 and the bonding wire 54 are sealed with a sealing resin 55. On the other hand, the other main surface (lower surface) of the wiring substrate 51 is provided with an external connection terminal 56 made of a spherical electrode terminal mainly composed of solder.

そして、前記配線基板５１の一方の主面に於いて、前記半導体素子５２の近傍から当該配線基板５１の四つの隅部（コーナー部）に延在して、板状のシリコン（Ｓｉ）からなる反り防止部材６７が選択的に配設されている。当該反り防止部材６７も、半導体素子５２と同様、ダイボンドフィルムからなる接着材５３を介して、配線基板５１上に固着されている。当該反り防止部材６７は、その端部が、前記封止用樹脂５５から露出して配設されている。   Then, on one main surface of the wiring board 51, it extends from the vicinity of the semiconductor element 52 to the four corners of the wiring board 51 and is made of plate-like silicon (Si). A warp prevention member 67 is selectively provided. Similar to the semiconductor element 52, the warpage preventing member 67 is also fixed on the wiring substrate 51 via an adhesive 53 made of a die bond film. The warp preventing member 67 is disposed with its end exposed from the sealing resin 55.

本変形例１に於ける特徴的構成として、かかる反り防止部材６７の配置構成に於いて、当該反り防止部材６７は、半導体素子５２の近傍から配線基板５１の隅部（コーナー部）に近づくにつれて、その幅が漸次拡大されている。   As a characteristic configuration in the first modification, in the arrangement configuration of the warp preventing member 67, the warp preventing member 67 approaches the corner portion (corner portion) of the wiring substrate 51 from the vicinity of the semiconductor element 52. , Its width is gradually enlarged.

この様に、前記配線基板５１の一方の主面に、半導体素子５２の四つの隅部の近傍から当該配線基板５１に於ける四つの隅部（コーナー部）に延在して、板状の反り防止部材５７が固着・配設されていることにより、当該配線基板５１の機械的強度が高められる。従って、当該半導体装置６０に於いては、高い機械的強度を有し、配線基板５１ならびに封止樹脂５５などの熱膨張係数の相違に基づく反り、或いは不均衡な力に起因するうねり又は捩れの発生が防止・抑制される。   In this manner, one main surface of the wiring board 51 extends from the vicinity of the four corners of the semiconductor element 52 to the four corners (corner parts) of the wiring board 51 to form a plate-like shape. Since the warp preventing member 57 is fixed and disposed, the mechanical strength of the wiring board 51 is increased. Accordingly, the semiconductor device 60 has high mechanical strength, and is warped or twisted due to a warp due to a difference in thermal expansion coefficient between the wiring substrate 51 and the sealing resin 55 or an unbalanced force. Occurrence is prevented / suppressed.

また、当該半導体装置６０に於ける構造によれば、封止用樹脂５５から露出する反り防止部材６７の端面の面積が拡大し、従って当該反り防止部材６７と封止用樹脂５５との間に於ける接触部の長さが増加して、当該反り防止部材６７と封止用樹脂５５との接触部に於ける隙間の長さが増加されている。   Further, according to the structure of the semiconductor device 60, the area of the end surface of the warp preventing member 67 exposed from the sealing resin 55 is increased, and therefore, the space between the warp preventing member 67 and the sealing resin 55 is increased. The length of the contact portion in the contact portion increases, and the length of the gap in the contact portion between the warpage prevention member 67 and the sealing resin 55 is increased.

かかる隙間の拡大により、当該半導体装置６０の内部に於いて接着材５３或いは封止用樹脂５５に含まれる水分の外部への放散が容易化され、当該半導体装置５０をマザーボードに搭載するにあたり、半田を主体とする球状電極からなる外部接続端子５６の再溶融（リフロー）処理を行なう際には、１５０℃乃至１９０℃程の予備加熱の段階で、当該半導体装置５０の内部に含まれる水分は容易に外部に放散される。前述の如く、反り防止部材６７の端部が、封止用樹脂５５から露出していることから、当該水分の放散は容易になされる。   The expansion of the gap facilitates the diffusion of moisture contained in the adhesive material 53 or the sealing resin 55 to the outside inside the semiconductor device 60, and when mounting the semiconductor device 50 on the motherboard, soldering is performed. When re-melting (reflowing) the external connection terminal 56 made of a spherical electrode mainly composed of the above, the moisture contained in the semiconductor device 50 is easy at the preheating stage of about 150 ° C. to 190 ° C. Dissipated to the outside. As described above, since the end portion of the warp preventing member 67 is exposed from the sealing resin 55, the moisture is easily diffused.

［第２の変形例］
本発明の実施の形態に係る半導体装置の第２の変形例を、図７に示す。図７（ａ）は、当該半導体装置の上面を示し、図７（ｂ）は、図７（ａ）に於いて矢印Ｐ３で示す方向に見たときの側面を示す。尚、図７（ａ）に於いては、封止用樹脂の表示を行なっていない。 [Second Modification]
FIG. 7 shows a second modification of the semiconductor device according to the embodiment of the present invention. FIG. 7A shows the top surface of the semiconductor device, and FIG. 7B shows the side surface when viewed in the direction indicated by the arrow P3 in FIG. 7A. In FIG. 7A, the sealing resin is not displayed.

本第２の変形例に於ける半導体装置７０にあっては、配線基板（支持基板、インターポーザとも称される）５１の一方の主面（上面）の中央部に、半導体素子５２が当該配線基板５１の表面に配設された電極端子に対して、所謂フリップチップ（フェイスダウン）実装法をもって載置されている。尚、ここでは、当該半導体素子５２に於ける電極端子ならびに配線基板５１の表面に配設された電極端子については図示していない。そして、当該半導体素子５２は、封止用樹脂５５により封止されている。一方、前記配線基板５１の他方の主面（下面）には、半田を主体とする球状電極端子からなる外部接続端子５６が配設されている。   In the semiconductor device 70 according to the second modification, the semiconductor element 52 is provided at the center of one main surface (upper surface) of a wiring board (also referred to as a support board or interposer) 51. The electrode terminals disposed on the surface of 51 are mounted by a so-called flip-chip (face-down) mounting method. Here, the electrode terminals in the semiconductor element 52 and the electrode terminals arranged on the surface of the wiring board 51 are not shown. The semiconductor element 52 is sealed with a sealing resin 55. On the other hand, the other main surface (lower surface) of the wiring substrate 51 is provided with an external connection terminal 56 made of a spherical electrode terminal mainly composed of solder.

そして、前記配線基板５１の一方の主面に於いて、前記半導体素子５２の近傍から当該配線基板５１の四つの隅部（コーナー部）に延在して、板状のシリコン（Ｓｉ）からなる反り防止部材７７が配設されている。当該反り防止部材７７も、半導体素子５２と同様、ダイボンドフィルムからなる接着材５３を介して、配線基板５１上に固着されている。当該反り防止部材７７も、その端部が、前記封止用樹脂５５から露出して配設されている。   Then, on one main surface of the wiring board 51, it extends from the vicinity of the semiconductor element 52 to the four corners of the wiring board 51 and is made of plate-like silicon (Si). A warp prevention member 77 is provided. Similar to the semiconductor element 52, the warpage preventing member 77 is also fixed on the wiring substrate 51 via an adhesive 53 made of a die bond film. The warp prevention member 77 is also disposed with its end exposed from the sealing resin 55.

この様な、半導体素子の実装形態として所謂フリップチップ（フェイスダウン）実装法が適用された半導体装置にあっても、配線基板５１の一方の主面に、半導体素子５２の四つの隅部の近傍から当該配線基板５１に於ける四つの隅部（コーナー部）に延在して、板状の反り防止部材７７が固着・配設されていることにより、当該配線基板５１の機械的強度が高められる。   Even in such a semiconductor device to which a so-called flip-chip (face-down) mounting method is applied as a semiconductor element mounting form, the vicinity of the four corners of the semiconductor element 52 is formed on one main surface of the wiring substrate 51. To the four corners (corner portions) of the wiring board 51, and the plate-like warpage preventing member 77 is fixed and disposed, thereby increasing the mechanical strength of the wiring board 51. It is done.

従って、当該半導体装置７０は、高い機械的強度を有し、配線基板５１ならびに封止樹脂５５などの熱膨張係数の相違に基づく反り、或いは不均衡な力に起因するうねり又は捩れの発生が防止・抑制される。   Therefore, the semiconductor device 70 has high mechanical strength, and prevents warping or twisting due to a difference in thermal expansion coefficient between the wiring substrate 51 and the sealing resin 55 or an unbalanced force.・ Suppressed.

一方、前記反り防止部材７７は、半導体素子５２の四つの隅部近傍から配線基板５１に於ける四つの隅部（コーナー部）に延在され、更にその端部が封止用樹脂５５から露出して配設されている。   On the other hand, the warp preventing member 77 extends from the vicinity of the four corners of the semiconductor element 52 to the four corners (corner portions) of the wiring board 51, and its end is exposed from the sealing resin 55. Arranged.

前述の如く、反り防止部材７７の構成材料であるシリコン（Ｓｉ）と封止用樹脂５５との密着性が低いため、当該反り防止部材７７と封止用樹脂５５との接触部には隙間が生じ易い。かかる隙間の存在により、当該半導体装置７０の内部に於いて接着材５３或いは封止用樹脂５５に含まれる水分の外部への放散が容易化され、当該半導体装置７０をマザーボードに搭載するにあたり、半田を主体とする球状電極からなる外部接続端子５６の再溶融（リフロー）処理を行なう際には、１５０℃乃至１９０℃程の予備加熱の段階で、当該半導体装置７０の内部に含まれる水分は容易に外部に放散される。前述の如く、反り防止部材７７の端部が、封止用樹脂５５から露出していることから、当該水分の放散は容易になされる。   As described above, since the adhesion between silicon (Si), which is a constituent material of the warp preventing member 77, and the sealing resin 55 is low, there is a gap at the contact portion between the warp preventing member 77 and the sealing resin 55. It is likely to occur. Due to the existence of such a gap, the diffusion of moisture contained in the adhesive 53 or the sealing resin 55 to the outside is facilitated inside the semiconductor device 70, and when mounting the semiconductor device 70 on the motherboard, soldering is performed. When re-melting (reflowing) the external connection terminal 56 made of a spherical electrode mainly composed of the water, the moisture contained in the semiconductor device 70 is easy at the preheating stage of about 150 ° C. to 190 ° C. Dissipated to the outside. As described above, since the end portion of the warp preventing member 77 is exposed from the sealing resin 55, the moisture is easily diffused.

［第３の変形例］
本発明の実施の形態に係る半導体装置の第３の変形例を、図８に示す。図８（ａ）は、当該半導体装置の上面を示し、図８（ｂ）は、図８（ａ）に於いて矢印Ｐ４で示す方向に見たときの側面を示している。尚、図８（ａ）に於いては、封止用樹脂の表示を行なっていない。 [Third Modification]
FIG. 8 shows a third modification of the semiconductor device according to the embodiment of the present invention. FIG. 8A shows the top surface of the semiconductor device, and FIG. 8B shows the side surface when viewed in the direction indicated by the arrow P4 in FIG. 8A. In FIG. 8A, the sealing resin is not displayed.

本第３の変形例に於ける半導体装置８０は、所謂ＬＧＡ（Ｌａｎｄ Ｇｒｉｄ Ａｒｒａｙ）型と称される半導体装置である。   The semiconductor device 80 in the third modification is a so-called LGA (Land Grid Array) type semiconductor device.

即ち、本第３の変形例に於ける半導体装置８０にあっても、配線基板（支持基板、インターポーザとも称される）５１の一方の主面（上面）の中央部に、半導体素子５２が接着材５３を介して載置され、当該配線基板５１に配設された電極端子（図示せず）と半導体素子５２に於ける電極端子（図示せず）との間は、例えば金（Ａｕ）等からなるボンディングワイヤ５４により接続されている。そして、当該半導体素子５２ならびにボンディングワイヤ５４などは、封止用樹脂５５により封止されている。   That is, even in the semiconductor device 80 according to the third modification, the semiconductor element 52 is bonded to the central portion of one main surface (upper surface) of the wiring substrate (also referred to as a support substrate or an interposer) 51. Between an electrode terminal (not shown) placed on the wiring substrate 51 and disposed on the wiring substrate 51 and an electrode terminal (not shown) in the semiconductor element 52, for example, gold (Au) or the like Are connected by a bonding wire 54 made of The semiconductor element 52 and the bonding wire 54 are sealed with a sealing resin 55.

一方、前記配線基板５１の他方の主面（下面）ＳＡ２には、半田を主体とする球状電極端子ではなく、ニッケル（Ｎｉ）及び金（Ａｕ）メッキが施された銅（Ｃｕ）などからなるランド状外部接続端子が配設されている（図示せず）。   On the other hand, the other main surface (lower surface) SA2 of the wiring substrate 51 is not made of a spherical electrode terminal mainly composed of solder, but is made of copper (Cu) plated with nickel (Ni) and gold (Au). Land-like external connection terminals are provided (not shown).

そして、前記配線基板５１の一方の主面に於いて、前記半導体素子５２の近傍から当該配線基板５１の四つの隅部（コーナー部）に延在して、板状のシリコン（Ｓｉ）からなる反り防止部材８７が選択的に配設されている。当該反り防止部材８７も、半導体素子５１と同様、ダイボンドフィルムからなる接着材５３を介して、配線基板５１上に固着されている。そして、当該反り防止部材８７も、その端部が、前記封止用樹脂５５から露出して配設されている。   Then, on one main surface of the wiring board 51, it extends from the vicinity of the semiconductor element 52 to the four corners of the wiring board 51 and is made of plate-like silicon (Si). A warp prevention member 87 is selectively provided. Similarly to the semiconductor element 51, the warpage preventing member 87 is also fixed on the wiring substrate 51 via an adhesive 53 made of a die bond film. The warp preventing member 87 is also disposed with its end exposed from the sealing resin 55.

この様に、前記配線基板５１の一方の主面に、半導体素子５２の四つの隅部の近傍から当該配線基板５１に於ける四つの隅部（コーナー部）に延在して、板状の反り防止部材８７が固着・配設されていることにより、当該配線基板５１の機械的強度が高められる。従って、当該半導体装置８０は、高い機械的強度を有し、配線基板５１ならびに封止樹脂５５などの熱膨張係数の相違に基づく反り、或いは不均衡な力に起因するうねり又は捩れの発生が防止・抑制される。   In this manner, one main surface of the wiring board 51 extends from the vicinity of the four corners of the semiconductor element 52 to the four corners (corner parts) of the wiring board 51 to form a plate-like shape. Since the warp preventing member 87 is fixed and disposed, the mechanical strength of the wiring board 51 is increased. Therefore, the semiconductor device 80 has high mechanical strength, and prevents warping or twisting due to a difference in thermal expansion coefficient between the wiring substrate 51 and the sealing resin 55 or an unbalanced force.・ Suppressed.

一方、前記反り防止部材８７は、半導体素子５２の四つの隅部近傍から配線基板５１に於ける四つの隅部（コーナー部）に延在され、更にその端部が封止用樹脂５５から露出して配設されている。   On the other hand, the warp preventing member 87 extends from the vicinity of the four corners of the semiconductor element 52 to the four corners (corner portions) of the wiring board 51, and its end is exposed from the sealing resin 55. Arranged.

前述の如く、反り防止部材８７の構成材料であるシリコン（Ｓｉ）と封止用樹脂５５との密着性が低いため、当該反り防止部材８７と封止用樹脂５５との接触部には隙間が生じ易い。かかる隙間の存在により、当該半導体装置８０の内部に於いて接着材５３或いは封止用樹脂５５に含まれる水分の外部への放散が容易化され、当該半導体装置８０をマザーボードに搭載するにあたり、半田を主体とする球状電極からなる外部接続端子５６の再溶融（リフロー）処理を行なう際には、１５０℃乃至１９０℃程の予備加熱の段階で、当該半導体装置８０の内部に含まれる水分は容易に外部に放散される。前述の如く、反り防止部材８７の端部が、封止用樹脂５５から露出していることから、当該水分の放散は容易になされる。   As described above, since the adhesion between silicon (Si), which is a constituent material of the warp preventing member 87, and the sealing resin 55 is low, there is a gap at the contact portion between the warp preventing member 87 and the sealing resin 55. It is likely to occur. Due to the existence of such a gap, the diffusion of moisture contained in the adhesive 53 or the sealing resin 55 to the outside is facilitated inside the semiconductor device 80, and soldering is performed when the semiconductor device 80 is mounted on the motherboard. When re-melting (reflowing) the external connection terminal 56 made of a spherical electrode mainly composed of the water, the moisture contained in the semiconductor device 80 is easy at the preheating stage of about 150 ° C. to 190 ° C. Dissipated to the outside. As described above, since the end portion of the warp preventing member 87 is exposed from the sealing resin 55, the moisture is easily diffused.

［第４の変形例］
本発明の実施の形態に係る半導体装置の第４の変形例を、図９に示す。図９（ａ）は、上面外観を示している。また、図９（ｂ）は、当該半導体装置に於いて、封止用樹脂の図示を省略して示し、図９（ｃ）は、図９（ｂ）の点線Ａ−Ａ’ に於ける断面を示している。 [Fourth Modification]
FIG. 9 shows a fourth modification of the semiconductor device according to the embodiment of the present invention. FIG. 9A shows the top appearance. FIG. 9B shows the semiconductor device with the sealing resin omitted, and FIG. 9C shows a cross section taken along the dotted line AA ′ in FIG. 9B. Is shown.

本第４の変形例に於ける半導体装置９０にあっては、反り防止部材の厚さが、封止用樹脂と同等の高さとされている。   In the semiconductor device 90 according to the fourth modification, the thickness of the warp preventing member is set to the same height as the sealing resin.

即ち、本第１の変形例に於ける半導体装置９０にあっても、配線基板（支持基板、インターポーザとも称される）５１の一方の主面（上面）の中央部に、半導体素子５２が接着材５３を介して載置され、当該配線基板５１に配設された電極端子（図示せず）と半導体素子５２に於ける電極端子（図示せず）との間は、例えば金（Ａｕ）等からなるボンディングワイヤ５４により接続されている。そして、当該半導体素子５２ならびにボンディングワイヤ５４などは、封止用樹脂５５により封止されている。一方、前記配線基板５１の他方の主面（下面）には、半田を主体とする球状電極端子からなる外部接続端子５６が配設されている。   That is, even in the semiconductor device 90 according to the first modification, the semiconductor element 52 is bonded to the central portion of one main surface (upper surface) of the wiring substrate (also referred to as a support substrate or an interposer) 51. Between an electrode terminal (not shown) placed on the wiring substrate 51 and disposed on the wiring substrate 51 and an electrode terminal (not shown) in the semiconductor element 52, for example, gold (Au) or the like Are connected by a bonding wire 54 made of The semiconductor element 52 and the bonding wire 54 are sealed with a sealing resin 55. On the other hand, the other main surface (lower surface) of the wiring substrate 51 is provided with an external connection terminal 56 made of a spherical electrode terminal mainly composed of solder.

そして、前記配線基板５１の一方の主面に於いて、前記半導体素子５２の近傍から当該配線基板５１の四つの隅部（コーナー部）に延在して、板状のシリコン（Ｓｉ）からなる反り防止部材９７が配設されている。当該反り防止部材９７は、半導体素子５２と同様、ダイボンドフィルムからなる接着材５３を介して、配線基板５１上に固着されている。   Then, on one main surface of the wiring board 51, it extends from the vicinity of the semiconductor element 52 to the four corners of the wiring board 51 and is made of plate-like silicon (Si). A warp prevention member 97 is provided. Similar to the semiconductor element 52, the warpage preventing member 97 is fixed on the wiring substrate 51 via an adhesive 53 made of a die bond film.

そして、本変形例に於ける特徴的構成として、当該反り防止部材９７は、その側端部が前記封止用樹脂５５から露出して配設されると共に、その上端が前記配線基板５１上に於いて封止用樹脂５５の表面と同等の高さを有し、その上面は当該封止用樹脂５５から表出している。   As a characteristic configuration in this modification, the warp preventing member 97 is disposed with its side end exposed from the sealing resin 55, and its upper end on the wiring substrate 51. In this case, the sealing resin 55 has the same height as the surface of the sealing resin 55, and its upper surface is exposed from the sealing resin 55.

この様に、前記配線基板５１の一方の主面に、半導体素子５２の四つの隅部の近傍から当該配線基板５１に於ける四つの隅部（コーナー部）に延在して、板状の反り防止部材９７が固着・配設されていることにより、当該配線基板５１の機械的強度がいっそう高められる。   In this manner, one main surface of the wiring board 51 extends from the vicinity of the four corners of the semiconductor element 52 to the four corners (corner parts) of the wiring board 51 to form a plate-like shape. Since the warp preventing member 97 is fixed and disposed, the mechanical strength of the wiring board 51 is further increased.

従って、当該半導体装置９０は、高い機械的強度を有し、配線基板５１ならびに封止樹脂５５などの熱膨張係数の相違に基づく反り、或いは不均衡な力に起因するうねり又は捩れの発生が大きく防止・抑制される。   Therefore, the semiconductor device 90 has high mechanical strength, and warp or twist caused by a difference in thermal expansion coefficients of the wiring board 51 and the sealing resin 55 or an undulation or twist due to an unbalanced force is large. Prevented / suppressed.

一方、前記反り防止部材９７は、半導体素子５２の四つの隅部近傍から配線基板５１に於ける四つの隅部（コーナー部）に延在され、その側端部が封止用樹脂５５から露出すると共に、その上端部も封止用樹脂５５から露出して配設されている。   On the other hand, the warp prevention member 97 extends from the vicinity of the four corners of the semiconductor element 52 to the four corners (corner portions) of the wiring substrate 51, and the side end portions thereof are exposed from the sealing resin 55. In addition, the upper end portion thereof is also exposed from the sealing resin 55.

前述の如く、反り防止部材９７の構成材料であるシリコン（Ｓｉ）と封止用樹脂５５との密着性が低いため、当該反り防止部材９７と封止用樹脂５５との接触部には隙間が生じ易い。かかる隙間の存在により、当該半導体装置９０の内部に於いて接着材５３或いは封止用樹脂５５に含まれる水分の外部への放散が容易化され、当該半導体装置９０をマザーボードに搭載するにあたり、半田を主体とする球状電極からなる外部接続端子５６の再溶融（リフロー）処理を行なう際には、１５０℃乃至１９０℃程の予備加熱の段階で、当該半導体装置８０の内部に含まれる水分は容易に外部に放散される。   As described above, since the adhesion between silicon (Si), which is a constituent material of the warp prevention member 97, and the sealing resin 55 is low, there is a gap at the contact portion between the warp prevention member 97 and the sealing resin 55. It is likely to occur. Due to the existence of such a gap, the diffusion of moisture contained in the adhesive 53 or the sealing resin 55 to the outside is facilitated inside the semiconductor device 90, and when mounting the semiconductor device 90 on the motherboard, soldering is performed. When re-melting (reflowing) the external connection terminal 56 made of a spherical electrode mainly composed of the water, the moisture contained in the semiconductor device 80 is easy at the preheating stage of about 150 ° C. to 190 ° C. Dissipated to the outside.

当該半導体装置９０にあっては、封止用樹脂５５の上面に於いても、反り防止部材９７との間に隙間が存在し、当該反り防止部材９７が封止用樹脂５５から表出いることから、水分の放散はいっそう容易になされる。   In the semiconductor device 90, a gap exists between the upper surface of the sealing resin 55 and the warp preventing member 97, and the warp preventing member 97 is exposed from the sealing resin 55. Therefore, moisture can be more easily released.

更に、当該半導体装置９０にあっては、反り防止部材９７の上面が封止用樹脂５５の上面に於いて露出していることから、当該反り防止部材９７の上面に放熱体を配設することにより、その放熱性を高めることができる。   Further, in the semiconductor device 90, since the upper surface of the warp preventing member 97 is exposed on the upper surface of the sealing resin 55, a heat radiator is provided on the upper surface of the warp preventing member 97. Therefore, the heat dissipation can be enhanced.

［第５の変形例］
本発明の実施の形態に係る半導体装置の、第５の変形例を図１０に示す。図１０（ａ）は、当該半導体装置の上面を示し、図１０（ｂ）は、図１０（ａ）に於いて矢印Ｐ５で示す方向に見たときの側面を示す。尚、図１０（ａ）に於いては、封止用樹脂の表示を行なっていない。 [Fifth Modification]
FIG. 10 shows a fifth modification of the semiconductor device according to the embodiment of the present invention. FIG. 10A shows the top surface of the semiconductor device, and FIG. 10B shows the side surface when viewed in the direction indicated by the arrow P5 in FIG. 10A. In FIG. 10A, the sealing resin is not displayed.

即ち、本第５の変形例に於ける半導体装置１００にあっても、配線基板（支持基板、インターポーザとも称される）５１の一方の主面（上面）の中央部に、半導体素子５２が接着材５３を介して載置され、当該配線基板５１に配設された電極端子（図示せず）と半導体素子５２に於ける電極端子（図示せず）との間は、例えば金（Ａｕ）等からなるボンディングワイヤ５４により接続されている。そして、当該半導体素子５２ならびにボンディングワイヤ５４などは、封止用樹脂５５により封止されている。一方、前記配線基板５１の他方の主面（下面）には、半田を主体とする球状電極端子からなる外部接続端子５６が配設されている。   That is, even in the semiconductor device 100 according to the fifth modification, the semiconductor element 52 is bonded to the central portion of one main surface (upper surface) of the wiring substrate (also referred to as a support substrate or an interposer) 51. Between an electrode terminal (not shown) placed on the wiring substrate 51 and disposed on the wiring substrate 51 and an electrode terminal (not shown) in the semiconductor element 52, for example, gold (Au) or the like Are connected by a bonding wire 54 made of The semiconductor element 52 and the bonding wire 54 are sealed with a sealing resin 55. On the other hand, the other main surface (lower surface) of the wiring substrate 51 is provided with an external connection terminal 56 made of a spherical electrode terminal mainly composed of solder.

但し、前記半導体素子５２が半導体記憶素子であって、その電極端子は対向する２辺に沿って配設されている。そして、前記ボンディングワイヤ５４は、当該対向する２辺から導出されている。従って、前記電極端子が配設された２辺とは異なる２辺の近傍に於ける配線基板表面には、ボンディングワイヤの接続部位を配設する必要がない。   However, the semiconductor element 52 is a semiconductor memory element, and its electrode terminals are arranged along two opposing sides. The bonding wire 54 is led out from the two opposing sides. Therefore, it is not necessary to provide a bonding wire connecting portion on the surface of the wiring board in the vicinity of two sides different from the two sides on which the electrode terminals are provided.

この為、本変形例に於ける特徴的構成として、前記半導体素子５２に於ける電極端子の存在しない辺の近傍から、配線基板５１の近接する周縁部に延在して、板状のシリコン（Ｓｉ）からなる反り防止部材１０７が配設されている。当該反り防止部材１０７は、半導体素子５２と同様、ダイボンドフィルムからなる接着材５３を介して、配線基板５１上に固着されている。   For this reason, as a characteristic configuration in this modification, a plate-like silicon (from the vicinity of the side where the electrode terminal does not exist in the semiconductor element 52 to the adjacent peripheral part of the wiring substrate 51 is formed. A warp preventing member 107 made of Si) is provided. Similar to the semiconductor element 52, the warpage preventing member 107 is fixed on the wiring substrate 51 via an adhesive 53 made of a die bond film.

そして、当該反り防止部材１０７は、その端部が、前記封止用樹脂５５から露出して配設されている。   The warp preventing member 107 is disposed with its end exposed from the sealing resin 55.

この様に、前記配線基板５１の一方の主面に、半導体素子５２の側面近傍から当該配線基板５１に於ける周縁部に延在して、板状の反り防止部材１０７が固着・配設されていることにより、当該配線基板５１の機械的強度が高められる。従って、当該半導体装置１００は、高い機械的強度を有し、配線基板５１ならびに封止樹脂５５などの熱膨張係数の相違に基づく反り、或いは不均衡な力に起因するうねり又は捩れの発生が防止・抑制される。   In this manner, the plate-shaped warpage prevention member 107 is fixed and disposed on one main surface of the wiring board 51 from the vicinity of the side surface of the semiconductor element 52 to the peripheral edge of the wiring board 51. As a result, the mechanical strength of the wiring board 51 is increased. Therefore, the semiconductor device 100 has high mechanical strength, and prevents warping or twisting due to a difference in thermal expansion coefficient between the wiring substrate 51 and the sealing resin 55 or an unbalanced force.・ Suppressed.

一方、前記反り防止部材１０７は、半導体素子５２の側面近傍から配線基板５１に於ける周縁部に延在され、更にその端部が封止用樹脂５５から露出して配設されている。   On the other hand, the warp preventing member 107 extends from the vicinity of the side surface of the semiconductor element 52 to the peripheral edge of the wiring board 51, and its end is exposed from the sealing resin 55.

前述の如く、反り防止部材１０７の構成材料であるシリコン（Ｓｉ）と封止用樹脂５５との密着性が低いため、当該反り防止部材１０７と封止用樹脂５５との接触部には隙間が生じ易い。かかる隙間の存在により、当該半導体装置１００の内部に於いて接着材５３或いは封止用樹脂５５に含まれる水分の外部への放散が容易化され、当該半導体装置１００をマザーボードに搭載するにあたり、半田を主体とする球状電極からなる外部接続端子５６の再溶融（リフロー）処理を行なう際には、１５０℃乃至１９０℃程の予備加熱の段階で、当該半導体装置１００の内部に含まれる水分は容易に外部に放散される。前述の如く、反り防止部材１０７の端部が、封止用樹脂５５から露出していることから、当該水分の放散は容易になされる。   As described above, since the adhesion between silicon (Si), which is a constituent material of the warp prevention member 107, and the sealing resin 55 is low, there is a gap at the contact portion between the warp prevention member 107 and the sealing resin 55. It is likely to occur. Due to the existence of such gaps, the diffusion of moisture contained in the adhesive 53 or the sealing resin 55 to the outside is facilitated inside the semiconductor device 100, and when mounting the semiconductor device 100 on the motherboard, soldering is performed. When re-melting (reflowing) the external connection terminal 56 made of a spherical electrode mainly composed of, the moisture contained in the semiconductor device 100 is easy at the stage of preheating at about 150 ° C. to 190 ° C. Dissipated to the outside. As described above, since the end portion of the warp preventing member 107 is exposed from the sealing resin 55, the moisture is easily diffused.

［第６の変形例］
本発明の実施の形態に係る半導体装置の第６の変形例を、図１１に示す。図１１は、当該半導体装置の上面を示し、封止用樹脂の図示を省略している。 [Sixth Modification]
FIG. 11 shows a sixth modification of the semiconductor device according to the embodiment of the present invention. FIG. 11 shows the top surface of the semiconductor device, and illustration of the sealing resin is omitted.

即ち、本第６の変形例に於ける半導体装置１１０にあっても、配線基板（支持基板、インターポーザとも称される）５１の一方の主面（上面）の中央部に、半導体素子５２が接着材５３を介して載置され、当該配線基板５１に配設された電極端子（図示せず）と半導体素子５２に於ける電極端子（図示せず）との間は、例えば金（Ａｕ）等からなるボンディングワイヤ５４により接続されている。そして、当該半導体素子５２ならびにボンディングワイヤ５４などは、封止用樹脂５５により封止されている。   That is, even in the semiconductor device 110 according to the sixth modification, the semiconductor element 52 is bonded to the central portion of one main surface (upper surface) of the wiring substrate (also referred to as a support substrate or an interposer) 51. Between an electrode terminal (not shown) placed on the wiring substrate 51 and disposed on the wiring substrate 51 and an electrode terminal (not shown) in the semiconductor element 52, for example, gold (Au) or the like Are connected by a bonding wire 54 made of The semiconductor element 52 and the bonding wire 54 are sealed with a sealing resin 55.

そして、本変形例６に於ける特徴的構成として、前記配線基板５１の各隅部（コーナー部）に於いて、矩形状を有するシリコン（Ｓｉ）からなる反り防止部材１１７が選択的に配設されている。当該反り防止部材１１７は、その端部が、前記封止用樹脂５５から露出して配設されている。   As a characteristic configuration in the sixth modification, a warp preventing member 117 made of silicon (Si) having a rectangular shape is selectively provided at each corner (corner) of the wiring board 51. Has been. The warp preventing member 117 is disposed with its end exposed from the sealing resin 55.

かかる構成によれば、前記配線基板５１の各隅部（コーナー部）に、矩形状を有する反り防止部材１１７が固着・配設されていることにより、当該配線基板５１の機械的強度が高められる。従って、当該半導体装置１１０は、高い機械的強度を有し、配線基板５１ならびに封止樹脂５５などの熱膨張係数の相違に基づく反り、或いは不均衡な力に起因するうねり又は捩れの発生が防止・抑制される。   According to such a configuration, the warpage prevention member 117 having a rectangular shape is fixed and disposed at each corner (corner portion) of the wiring board 51, whereby the mechanical strength of the wiring board 51 is increased. . Therefore, the semiconductor device 110 has high mechanical strength, and prevents warping or twisting due to a difference in thermal expansion coefficient between the wiring substrate 51 and the sealing resin 55 or an unbalanced force.・ Suppressed.

また、かかる反り防止部材１１７の配置構成によれば、半導体素子５２の周囲に於ける配線層、電極端子などの配設の自由度を損なうことがない。   Further, according to the arrangement configuration of the warp preventing member 117, the degree of freedom of arrangement of the wiring layers, electrode terminals, and the like around the semiconductor element 52 is not impaired.

［第７の変形例］
本発明の実施の形態に係る半導体装置の第７の変形例を、図１２に示す。図１２は、当該半導体装置の上面を示し、封止用樹脂の図示を省略している。 [Seventh Modification]
FIG. 12 shows a seventh modification of the semiconductor device according to the embodiment of the present invention. FIG. 12 shows the top surface of the semiconductor device, and illustration of the sealing resin is omitted.

即ち、本第７の変形例に於ける半導体装置１２０にあっても、配線基板（支持基板、インターポーザとも称される）５１の一方の主面（上面）の中央部に、半導体素子５２が接着材５３を介して載置され、当該配線基板５１に配設された電極端子（図示せず）と半導体素子５２に於ける電極端子（図示せず）との間は、例えば金（Ａｕ）等からなるボンディングワイヤ５４により接続されている。そして、当該半導体素子５２ならびにボンディングワイヤ５４などは、封止用樹脂５５により封止されている。   That is, even in the semiconductor device 120 according to the seventh modification, the semiconductor element 52 is bonded to the central portion of one main surface (upper surface) of the wiring substrate (also referred to as a support substrate or an interposer) 51. Between an electrode terminal (not shown) placed on the wiring substrate 51 and disposed on the wiring substrate 51 and an electrode terminal (not shown) in the semiconductor element 52, for example, gold (Au) or the like Are connected by a bonding wire 54 made of The semiconductor element 52 and the bonding wire 54 are sealed with a sealing resin 55.

そして、本変形例７に於ける特徴的構成として、前記配線基板５１の各隅部（コーナー部）に於いて、三角形状を有するシリコン（Ｓｉ）からなる反り防止部材１２７が選択的に配設されている。当該反り防止部材１２７は、その端部が、前記封止用樹脂５５から露出して配設されている。   As a characteristic configuration in the seventh modification, a warp prevention member 127 made of silicon (Si) having a triangular shape is selectively provided at each corner (corner) of the wiring board 51. Has been. The warp preventing member 127 is disposed such that an end thereof is exposed from the sealing resin 55.

かかる構成によれば、前記配線基板５１の各隅部（コーナー部）に、矩形状を有する反り防止部材１２７が固着・配設されていることにより、当該配線基板５１の機械的強度が高められる。従って、当該半導体装置１２０は、高い機械的強度を有し、配線基板５１ならびに封止樹脂５５などの熱膨張係数の相違に基づく反り、或いは不均衡な力に起因するうねり又は捩れの発生が防止・抑制される。   According to such a configuration, the warp prevention member 127 having a rectangular shape is fixed and disposed at each corner (corner portion) of the wiring board 51, so that the mechanical strength of the wiring board 51 is increased. . Therefore, the semiconductor device 120 has high mechanical strength, and prevents warping or twisting due to a difference in thermal expansion coefficient between the wiring substrate 51 and the sealing resin 55 or an unbalanced force.・ Suppressed.

また、かかる反り防止部材１２７の配置構成によれば、半導体素子５２の周囲に於ける配線層、電極端子などの配設の自由度を損なうことがない。   Further, according to the arrangement configuration of the warp preventing member 127, the degree of freedom of arrangement of the wiring layer, electrode terminal, and the like around the semiconductor element 52 is not impaired.

２．半導体装置の製造方法
次に、図１３乃至図１９を参照して、本発明の実施の形態に係る半導体装置５０の製造方法について説明する。 2. Method for Manufacturing Semiconductor Device Next, a method for manufacturing the semiconductor device 50 according to the embodiment of the present invention will be described with reference to FIGS.

これらの図１３、図１４、図１５、図１６、及び図１８のそれぞれに於いて、（ａ）は上面を示し、（ｂ）は（ａ）のＹ−Ｙ’ 断面を示している。一方、図１７、図１９は、断面のみを示している。尚、これらの図に於けるＹ−Ｙ’ 断面は、図１３に於いて記入している一点鎖線に沿うものであって、図１４乃至図１８に於いても、これに相当する箇所の断面を描いている。   In each of FIG. 13, FIG. 14, FIG. 15, FIG. 16, and FIG. 18, (a) shows the top surface, and (b) shows the Y-Y 'cross section of (a). On the other hand, FIGS. 17 and 19 show only a cross section. Note that the YY ′ cross section in these figures is taken along the alternate long and short dash line in FIG. 13, and in FIGS. Is drawn.

当該半導体装置５０の製造に際しては、大判の配線基板５００が容易され、その一方の主面（上面）に設けられた複数個の半導体素子搭載部のそれぞれに、接着材５３を介して半導体素子５２を搭載・固着する。（図１３参照）
当該図１３に於いて、実線Ｌ１にて描かれる6個の領域が、分割されて配線基板５１となる部位であり、また破線Ｌ２にて囲繞される領域が樹脂封止対象の部位である。 When manufacturing the semiconductor device 50, the large-sized wiring board 500 is facilitated, and the semiconductor element 52 is connected to each of a plurality of semiconductor element mounting portions provided on one main surface (upper surface) via an adhesive 53. Is mounted and fixed. (See Figure 13)
In FIG. 13, the six regions drawn by the solid line L1 are parts that are divided to become the wiring board 51, and the region surrounded by the broken line L2 is a part to be sealed with resin.

前記半導体素子搭載部は、当該配線基板５００が分割されて形成される配線基板５１のほぼ中央部に位置する。   The semiconductor element mounting portion is located at a substantially central portion of the wiring board 51 formed by dividing the wiring board 500.

当該大判の配線基板５００は、例えばガラスエポキシ樹脂などの無機絶縁性樹脂を基材とし、その主面及び／或いは内層に銅（Ｃｕ）等からなる導電層が選択的に配設されて、所謂多層配線構造を呈している。   The large-sized wiring substrate 500 is based on an inorganic insulating resin such as glass epoxy resin, for example, and a conductive layer made of copper (Cu) or the like is selectively disposed on the main surface and / or the inner layer, so-called It has a multilayer wiring structure.

半導体素子５２は、シリコン（Ｓｉ）或いはガリウム砒素（ＧａＡｓ）半導体基板が用いられ、周知の半導体製造プロセスにより、その一方の主面に形成された能動素子、受動素子層ならびにこれらの機能素子を相互に接続する配線層をもって電子回路が形成されている。そして、その表面に、当該配線層に接続された電極端子（電極パッド）が設けられている。   The semiconductor element 52 uses a silicon (Si) or gallium arsenide (GaAs) semiconductor substrate, and an active element, a passive element layer, and these functional elements formed on one main surface of the semiconductor element 52 are mutually connected by a known semiconductor manufacturing process. An electronic circuit is formed with a wiring layer connected to the. And the electrode terminal (electrode pad) connected to the said wiring layer is provided in the surface.

また、接着材５３としては、所謂ダイボンドフィルム、或いはペースト状接着材を適用することができる。当該ダイボンドフィルムは、半導体基板のダイシング処理に対応して、半導体素子の裏面に配設することができる。   As the adhesive 53, a so-called die bond film or a paste-like adhesive can be applied. The die bond film can be disposed on the back surface of the semiconductor element corresponding to the dicing process of the semiconductor substrate.

次いで、前記配線基板５００の一方の主面上に於いて、各半導体素子５２の隅部近傍に位置して、反り防止部材の集合体５７０を配置する。（図１４参照）
当該反り防止部材の集合体５７０の一つは、平面形状がＸ字状或いはＶ字状を有し、それぞれの板状部が、個々の半導体素子５２の隅部と、配線基板５００にあって当該半導体素子５２が搭載される配線基板５１の隅部となる位置を結ぶ如く配置される。 Next, on one main surface of the wiring board 500, an assembly 570 of warpage preventing members is disposed in the vicinity of the corner of each semiconductor element 52. (See Figure 14)
One of the warpage preventing member aggregates 570 has an X-shape or a V-shape in plan view, and each plate-like portion is provided at a corner of each semiconductor element 52 and the wiring board 500. It arrange | positions so that the position used as the corner part of the wiring board 51 in which the said semiconductor element 52 is mounted may be tied.

即ち、個々の半導体素子５２間にあっては、Ｘ字状の反り防止部材の集合体５７０ａが、その交点部（交差部）を複数の配線基板５１の隣接部、即ち当該配線基板５１の隅部（コーナー部）に位置して配置される。また当該配線基板５００の外縁部側にあっては、Ｖ字状の反り防止部材の集合体５７０ｂ或いはＸ字状の反り防止部材の集合体５７０ａが、その交点部（交差部）を個々の配線基板５１の外縁部相当部に位置して配置される。   That is, between the individual semiconductor elements 52, the X-shaped warp preventing member assembly 570 a has an intersection (intersection) adjacent to the plurality of wiring boards 51, that is, corners of the wiring boards 51 ( It is placed at the corner. On the outer edge side of the wiring board 500, a V-shaped warp preventing member aggregate 570b or an X-shaped warp preventing member aggregate 570a has individual wirings at the intersections (intersections). The substrate 51 is disposed at a position corresponding to the outer edge portion.

尚、当該配線基板５１の外縁部とは、配線基板５００が後のダイシング工程に於いて切断されて、半導体装置５０の配線基板５１として分離された際に、その外縁部でかつ隅部（コーナー部）となる部位に相当する。   The outer edge portion of the wiring substrate 51 is the outer edge portion and the corner portion (corner) when the wiring substrate 500 is cut in a later dicing process and separated as the wiring substrate 51 of the semiconductor device 50. Part).

当該反り防止部材の集合体５７０は、シリコン（Ｓｉ）或いはセラミックなど、半導体素子５２と同等の線膨張係数（約３ｐｐｍ）及び曲げ強度（約８０ＭＰａ）を有する材料から形成されることが望ましい。また、その厚さは１００μｍ以上とされ、配線基板５１の構成・厚さ、半導体素子５２の厚さ、ならびに樹脂用封止５５の厚さなどに応じて適宜選択される。   The warp preventing member aggregate 570 is preferably formed of a material having a linear expansion coefficient (about 3 ppm) and bending strength (about 80 MPa) equivalent to those of the semiconductor element 52, such as silicon (Si) or ceramic. The thickness is 100 μm or more, and is appropriately selected according to the configuration / thickness of the wiring substrate 51, the thickness of the semiconductor element 52, the thickness of the resin sealing 55, and the like.

そして、当該反り防止部材の集合体５７０は、前記半導体素子５２と同様に、接着材５３を介して配線基板５００の一方の主面上に固着される。この時、当該反り防止部材の集合体５７０は、４個または２個の反り防止部材が一対に形成されたものであることから、Ｘ字状の反り防止部材の集合体５７０ａにあっては４個の反り防止部材を、またＶ字状の反り防止部材の集合体５７０ｂにあっては２個の反り防止部材を一括して固着することに相当し、その作業性は高い。   Then, the assembly 570 of the warp preventing members is fixed on one main surface of the wiring board 500 through the adhesive 53, like the semiconductor element 52. At this time, since the assembly 570 of the warp preventing members is formed of a pair of four or two warp preventing members, the assembly 570a of the X-shaped warp preventing members has 4 This corresponds to fixing the two warp preventing members together, and, in the V-shaped warp preventing member aggregate 570b, the two warp preventing members are fixed together, and the workability thereof is high.

尚、当該反り防止部材の集合体５７０の表面に、例えばアルミニウム（Ａｌ）等の金属層を被覆しても良い。これにより、封止用樹脂５５との密着性をより低下せしめることができる。   Note that a metal layer such as aluminum (Al) may be coated on the surface of the assembly 570 of the warp preventing members. Thereby, adhesiveness with resin 55 for sealing can be reduced more.

次いで、前記半導体素子に於ける電極端子と配線基板に於ける電極端子との間を、ボンディングワイヤ５４により接続する（図１５参照）。当該ボンディングワイヤ５４としては、金（Ａｕ）を主体とするワイヤが適用される。   Next, the electrode terminals in the semiconductor element and the electrode terminals in the wiring board are connected by bonding wires 54 (see FIG. 15). As the bonding wire 54, a wire mainly composed of gold (Au) is applied.

次いで、前記大判の配線基板５００の一方の主面に対して樹脂封止処理を行ない、当該一方の主面に搭載された複数個の半導体素子５２、反り防止部材の集合体５７０などを、封止用樹脂によって一括して樹脂封する。（図１６参照）
尚、当該図１６（ａ）に於いて、破線Ｌ２で囲繞された領域が被樹脂封止領域５５０である。 Next, a resin sealing process is performed on one main surface of the large-sized wiring board 500 to seal the plurality of semiconductor elements 52 mounted on the one main surface, the aggregate 570 of warpage prevention members, and the like. The resin is sealed together with a stopping resin. (See Figure 16)
In FIG. 16A, a region surrounded by a broken line L2 is a resin-sealed region 550.

この時、前記配線基板５００の外縁部側に配設されたＶ字状或いはＸ字状の反り防止部材の集合体５７０は、その一部が被樹脂封止領域５５０の外に露出される。   At this time, a part of the V-shaped or X-shaped warpage preventing member assembly 570 disposed on the outer edge side of the wiring substrate 500 is exposed outside the resin-sealed region 550.

次いで、前記大判の配線基板５００の他方の主面（裏面）に於いて、前記複数個の半導体素子５１のそれぞれに対応して配設されている電極端子（図示せず）に対して、半田を主体とする球状電極端子からなる外部接続用端子５６を配設する。（図１７参照）。配線基板５００の他方の主面（裏面）に配設された電極端子の配置によっては、当該外部接続用端子５６は格子状に配列されることとなる。   Next, on the other main surface (back surface) of the large-sized wiring substrate 500, solder is applied to electrode terminals (not shown) arranged corresponding to the plurality of semiconductor elements 51, respectively. An external connection terminal 56 composed of a spherical electrode terminal mainly composed of is disposed. (See FIG. 17). Depending on the arrangement of the electrode terminals disposed on the other main surface (back surface) of the wiring board 500, the external connection terminals 56 are arranged in a grid pattern.

しかる後、前記樹脂封止領域５５０と大判の配線基板５００とを、ダイシング処理によりその厚さ方向に切断して、図１８に於いて、実線Ｌ１にて示される部位を切断し、個々の半導体装置５０を形成する。   Thereafter, the resin-encapsulated region 550 and the large-sized wiring board 500 are cut in the thickness direction by a dicing process, and a portion indicated by a solid line L1 in FIG. A device 50 is formed.

この時、前記大判の配線基板５００上に配設されているところの、Ｘ字状或いはＶ字状を有する反り防止部材の集合体５７０も切断・分離されて、個々の半導体装置５０に於いては、半導体素子５２の隅部近傍から配線基板５１の隅部に延在し、封止用樹脂５５の側面に於いて表出する板状の反り防止部材５７が配設される。   At this time, the assembly 570 of warp preventing members having an X-shape or V-shape disposed on the large-sized wiring board 500 is also cut and separated, and the individual semiconductor devices 50 are separated. Is provided with a plate-like warpage preventing member 57 extending from the vicinity of the corner of the semiconductor element 52 to the corner of the wiring substrate 51 and exposed on the side surface of the sealing resin 55.

かかる工程を経て形成された、半導体装置５０の断面構造を、図１９に示す。   FIG. 19 shows a cross-sectional structure of the semiconductor device 50 formed through this process.

即ち、この様な製造方法によれば、複数個の半導体素子５２を配線基板５００に搭載・固着した後、当該配線基板５１上に反り防止部材２００を搭載・固着し、ボンディングワイヤの配設、樹脂封止処理、外部接続端子の配設との工程を経た後、前記反り防止部材の集合体５７０を、樹脂封止領域５５０と大判の配線基板５００と共に一括してダイシング処理することにより、特別な工程を経ることなく、容易に、半導体装置５０を形成することができる。   That is, according to such a manufacturing method, after mounting and fixing a plurality of semiconductor elements 52 on the wiring substrate 500, the warp prevention member 200 is mounted and fixed on the wiring substrate 51, and bonding wires are disposed. After passing through the steps of resin sealing treatment and external connection terminal arrangement, the warp preventing member aggregate 570 is specially treated by dicing together with the resin sealing region 550 and the large-sized wiring substrate 500. The semiconductor device 50 can be formed easily without going through a complicated process.

この様な半導体装置５０の製造方法は、その変形例に応じて、適宜変更することができる。   The manufacturing method of such a semiconductor device 50 can be appropriately changed according to the modification.

一つに、前記図１４に示される反り防止部材の集合材５７０は、その形状が一様な幅を有する板状部がＸ字状或いはＶ字状とされたものが適用されているが、これは、図２０に示される様に、連結部に向うにつれてその幅が漸次拡大された形状とすることができる。   For example, the aggregate member 570 of the warpage preventing member shown in FIG. 14 is applied with a plate-like portion having a uniform width that is X-shaped or V-shaped. As shown in FIG. 20, this can be a shape in which the width is gradually enlarged toward the connecting portion.

当該図２０に示される線Ｌ３にて切断されることにより、前記第１の変形例である半導体装置６０に於ける、反り防止部材５７が形成される。   By cutting along the line L3 shown in FIG. 20, a warp preventing member 57 in the semiconductor device 60 according to the first modification is formed.

また、前記第２の変形例に示される半導体装置７０を形成する場合には、前記図１３に示される半導体素子搭載工程に於いて、フリップチップ（フェイスダウン）実装法を適用して、半導体素子５２を大判の配線基板５００上に実装する。   When the semiconductor device 70 shown in the second modification is formed, the flip-chip (face-down) mounting method is applied in the semiconductor element mounting step shown in FIG. 52 is mounted on a large-sized wiring board 500.

また、前記第３の変形例に示される半導体装置８０を形成する場合には、大判の配線基板５００の他方の主面（下面）に、半田を主体とする球状電極端子は設けられず、ニッケル（Ｎｉ）及び金（Ａｕ）メッキが施された銅（Ｃｕ）などからなるランド状外部接続端子を配設する。   Further, when the semiconductor device 80 shown in the third modification is formed, a spherical electrode terminal mainly composed of solder is not provided on the other main surface (lower surface) of the large-sized wiring substrate 500. Land-like external connection terminals made of copper (Cu) plated with (Ni) and gold (Au) are disposed.

そして、前記第４の変形例に示される半導体装置９０を形成する場合には、反り防止部材の集合材５７０の厚さが、樹脂封止部の厚さ（封止厚）と同等の厚さ（高さ）となる様、当該反り防止部材の集合材５７０の厚さ及び／或いは封止用樹脂の厚さを予め選択・決定する。   When the semiconductor device 90 shown in the fourth modification is formed, the thickness of the warpage preventing member aggregate 570 is equal to the thickness of the resin sealing portion (sealing thickness). The thickness of the warpage preventing member aggregate 570 and / or the thickness of the sealing resin is selected and determined in advance so as to be (height).

一方、前記第５の変形例に示される半導体装置１００を形成する場合には、半導体素子５１に於いてボンディングワイヤ５４が導出されない辺に沿う側面の近傍に、板状の反り防止部材の一端を配置し、その他端を、配線基板５１の外縁部（実線Ｌ１に沿う縁部）を越えて、他の配線基板部に搭載されているところの半導体素子５１のボンディングワイヤ５４が導出されない辺に沿う側面の近傍などに配置する。   On the other hand, when the semiconductor device 100 shown in the fifth modification is formed, one end of the plate-like warpage preventing member is provided near the side surface along the side where the bonding wire 54 is not led out in the semiconductor element 51. The other end extends beyond the outer edge (the edge along the solid line L1) of the wiring board 51 and extends along the side where the bonding wire 54 of the semiconductor element 51 mounted on the other wiring board is not led out. Place near the side.

更に、前記第６の変形例に示される半導体装置１１０、或いは第７の変形例に示される半導体装置１２０を形成する場合には、大判の配線基板５００に於けるそれぞれの配線基板５１の四隅部（コーナー部）に対して、正方形を有する反り防止部材５７０ｃを選択的に配設する。   Further, when forming the semiconductor device 110 shown in the sixth modified example or the semiconductor device 120 shown in the seventh modified example, the four corners of each wiring board 51 in the large-sized wiring board 500 are formed. A warp preventing member 570c having a square shape is selectively disposed with respect to the (corner portion).

即ち、第６の変形例に示される半導体装置１１０を形成する際には、大判の配線基板５００に於ける配線基板５１の四隅部（コーナー部）に対して、正方形を有する反り防止部材５７０ｃを、その一辺が当該配線基板５１の外縁部と平行、即ち実線Ｌ１と平行となる様に配設する。かかる状態を、図２１に示す。   That is, when the semiconductor device 110 shown in the sixth modification is formed, the warp prevention member 570c having a square shape is formed on the four corners (corner portions) of the wiring substrate 51 in the large-sized wiring substrate 500. The one side is arranged so as to be parallel to the outer edge of the wiring board 51, that is, parallel to the solid line L1. Such a state is shown in FIG.

また、第７の変形例に示される半導体装置１２０を形成する際には、大判の配線基板５００に於ける配線基板５１の四隅部（コーナー部）に対して、正方形を有する反り防止部材５７０ｃを、その四隅（コーナー部）が当該配線基板５１の外縁部と一致する様に配設する。即ち、前記第６の変形例に示される半導体装置１１０を形成する場合に対し、正方形を有する反り防止部材５７０ｃを９０度回転させて配置する。かかる状態を、図２２に示す。   Further, when the semiconductor device 120 shown in the seventh modification is formed, the warp preventing member 570c having a square shape is formed on the four corners (corner portions) of the wiring substrate 51 in the large-sized wiring substrate 500. The four corners (corner portions) are arranged so as to coincide with the outer edge portion of the wiring board 51. That is, the warp preventing member 570c having a square shape is rotated 90 degrees and disposed in the case where the semiconductor device 110 shown in the sixth modification is formed. Such a state is shown in FIG.

この様に、隣接する配線基板５１の四隅部に対して、正方形状を有する反り防止部材５７０ｃを配設することは、４個の反り防止部材を一括して固着することに相当する。   Thus, disposing the warp preventing members 570c having a square shape at the four corners of the adjacent wiring board 51 corresponds to fixing the four warp preventing members together.

当該正方形状を有する反り防止部体５７０ｃを適用し、これを配線基板５１の四隅部に配置すれば、前記樹脂封止領域５５０と大判の配線基板５００とをダイシング処理によりその厚さ方向に切断して個々の半導体装置を形成する際に、当該正方形状の反り防止部材５７０ｃも切断・分離される。   If the warp preventing part 570c having the square shape is applied and disposed at the four corners of the wiring board 51, the resin sealing region 550 and the large wiring board 500 are cut in the thickness direction by dicing. When the individual semiconductor devices are formed, the square warpage preventing member 570c is also cut and separated.

そして、個々の半導体装置に於ける配線基板５１の四隅部に於いて、当該配線基板５１上にあっては正方形或いは三角形を呈し、且つ半導体装置の側面に於いてその端面を表出する反り防止部材５７が配設される。   Then, at the four corners of the wiring board 51 in each semiconductor device, a warp prevention that presents a square or a triangle on the wiring board 51 and exposes its end face on the side surface of the semiconductor device. A member 57 is disposed.

本発明の実施の形態について詳述したが、本発明は特定の実施形態に限定されるものではなく、特許請求の範囲に記載された本発明の要旨の範囲内に於いて、種々の変形及び変更が可能である。例えば、前記実施の態様ならびにその変形例にあっては、反り防止部材５７の形状を板状として説明したが、これは帯状とも言え、またその厚さが大となれば、棒状或いは柱状と称される形態も生ずることは勿論である。   Although the embodiments of the present invention have been described in detail, the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed. For example, in the above-described embodiment and modifications thereof, the shape of the warp preventing member 57 has been described as a plate shape, but this can also be referred to as a belt shape, and if the thickness increases, it is referred to as a rod shape or a column shape. Of course, some forms may occur.

５０、６０、７０、８０、９０、１００、１１０、１２０ 半導体装置
５１ 配線基板
５２ 半導体素子
５４ ボンディングワイヤ
５５ 封止樹脂
５７、６７、７７、８７、１０７、１１７、１２７ 反り防止部材 50, 60, 70, 80, 90, 100, 110, 120 Semiconductor device 51 Wiring substrate 52 Semiconductor element 54 Bonding wire 55 Sealing resin 57, 67, 77, 87, 107, 117, 127 Warpage prevention member

Claims (5)

平面形状が矩形状を有する配線基板と、
前記配線基板の一方の主面に搭載された半導体素子と、
前記配線基板の一方の主面に於いて、前記半導体素子を被覆する封止用樹脂と
を具備し、
前記配線基板の一方の主面に於いて、前記半導体素子の隅部と当該配線基板の隅部との間に、反り防止部材が選択的に配設されてなることを特徴とする半導体装置。 A wiring board having a rectangular planar shape;
A semiconductor element mounted on one main surface of the wiring board;
On one main surface of the wiring board, comprising a sealing resin that covers the semiconductor element,
A semiconductor device, wherein a warp preventing member is selectively disposed between a corner portion of the semiconductor element and a corner portion of the wiring substrate on one main surface of the wiring substrate. 請求項１記載の半導体装置であって、
前記反り防止部材は、前記配線基板の隅部に選択的に配設されてなることを特徴とする半導体装置。 The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the warp preventing member is selectively disposed at a corner of the wiring board. 請求項１又は２記載の半導体装置であって、
前記反り防止部材は、前記半導体素子の角部から前記配線基板の角部に向かって幅が漸次拡大された形状を有することを特徴とする半導体装置。 A semiconductor device according to claim 1 or 2,
The warpage preventing member has a shape in which a width is gradually enlarged from a corner portion of the semiconductor element toward a corner portion of the wiring board. 請求項１乃至３いずれか一項記載の半導体装置であって、
前記配線基板の隅部に於いて、前記反り防止部材の端面が、前記封止用樹脂から露出していることを特徴とする半導体装置。 A semiconductor device according to any one of claims 1 to 3,
The semiconductor device according to claim 1, wherein an end surface of the warpage preventing member is exposed from the sealing resin at a corner of the wiring board. 請求項１乃至４いずれか一項記載の半導体装置であって、
前記反り防止部材は、前記配線基板上に設けられた前記封止用樹脂の厚さと略等しい厚さを有し、
前記反り防止部材の上面が前記封止用樹脂から表出していることを特徴とする半導体装置。 A semiconductor device according to any one of claims 1 to 4, wherein
The warpage prevention member has a thickness substantially equal to the thickness of the sealing resin provided on the wiring board,
The semiconductor device according to claim 1, wherein an upper surface of the warpage preventing member is exposed from the sealing resin.
JP2009005089A 2009-01-13 2009-01-13 Semiconductor device Pending JP2010165747A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024005172A1 (en) * 2022-06-29 2024-01-04 ソニーセミコンダクタソリューションズ株式会社 Semiconductor device and electronic apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024005172A1 (en) * 2022-06-29 2024-01-04 ソニーセミコンダクタソリューションズ株式会社 Semiconductor device and electronic apparatus

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