JP2010164552A - Differential hybrid circuit and testing device using same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To cancel influence of transmitting signals transmitted from a driver when evaluating receiving signals from a device by canceling unbalance of a differential line. <P>SOLUTION: A main driver amplifier 62 generates a first differential signal Vdp/Vdn on the basis of pattern data PAT. A replica driver amplifier 64 generates a second differential signal Vcp/Vcn on the basis of the pattern data PAT. Subtracters SUB1, SUB2 generate potential differential signals HP(=RP-Vep), HN(=RN-Ven) respectively. Sample hold circuits SH1, SH2 sample and hold the potential differential signals HP, HN respectively. A comparison part 12 compares a differential amplitude signal DA(=HHP-HHN) with a threshold VOH. A latch circuit 18 latches output of the comparison part 12. The timing of sampling of the sample hold circuits SH1, SH2 and that of latch of the latch circuit 18 are independently regulatable. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a test technique for a semiconductor device, and relates to a technique for evaluating a differential signal output from a device under test.

  In recent years, a differential transmission system has been adopted in order to transmit video signals and audio signals at high speed between digital home appliances such as a television receiver and a DVD (Digital Versatile Disc) player. The differential transmission system will be applied to data transmission between devices such as a memory and a CPU (Central Processing Unit) in the near future.

  For example, an XDR-DRAM (eXtreme Data Rate Dynamic Random Access Memory) transmits a differential signal pair (hereinafter simply referred to as a differential signal) bidirectionally at high speed using a single differential signal line. When testing a device having such a bi-directional differential interface, a test is performed to measure the amplitude of a differential signal output from the device under test (DUT) and determine whether it is good or bad.

  FIGS. 1A and 1B are block diagrams illustrating a part of the configuration of a test apparatus that tests a device having a differential interface. As shown in FIG. 1A, the test system 300 includes a pin electronics PE and a test fixture TF. The DUT 200 is mounted on a socket board (SB). A differential comparator 110 is provided in the pin electronics PE. The differential comparator 110, also called a timing comparator, receives the differential signal UP / UN output from the DUT 200, and determines the level of the differential signal UP / UN at a timing synchronized with the strobe signal. In this specification, “P / N” indicates a differential pair. On the test fixture TF, a differential signal line pair 50P / 50N (hereinafter also collectively referred to as a differential signal line 50) for connecting the socket board SB and the pin electronics PE is provided.

FIG. 1B is a circuit diagram showing a configuration of the differential comparator 110. The differential comparator 110 includes a subtractor 112, a first comparator 114, a second comparator 116, a first latch 118, and a second latch 120. The subtractor 112 generates a difference between the differential signals RP and RN, that is, a differential amplitude signal DA. The first comparator 114 compares the differential amplitude signal DA with the upper threshold voltage VOH. The first latch 118 latches the comparison result SH at the timing of the first strobe signal Hstb. The second comparator 116 compares the differential amplitude signal DA with the lower threshold voltage VOL. The second latch 120 latches the comparison result SL at the timing of the second strobe signal Lstb. The logical values of the data SH and SL indicating the comparison results are determined based on the following formulas (1a) and (1b).
SH = sign (VOH− (RP−RN)) (1a)
SL = sign ((RP-RN) -VOL) (1b)
here,
sign (x) is a function that takes 1 when x> 0 and 0 when x <0.

  Ideally, the length of the pair of differential signal lines 50 formed in the test fixture TF is uniform, but the length may be different in a practical test apparatus. 2A and 2B are operation waveform diagrams of the differential comparator 110 when the lengths of the differential lines are uniform and non-uniform, respectively. As shown in FIG. 2A, when the differential signal line 50 has a uniform length, the differential signal UP / UN output from the DUT 200 reaches the differential comparator 110 after receiving an equal delay tpd (see FIG. 2A). RP / RN).

  Attention is paid to the transition from the low level (0) to the high level (1) of the differential amplitude signal (RP-RN). The outputs SH and SL of the two comparators 114 and 116 are latched at the timing of the strobe signals Hstb and Lstb having a time difference Tcr.

  Based on the combination of the values of the latched signals (fail signals) FH and FL, the transition time T from the low level (<VOL) to the high level (> VOH) of the differential amplitude signal (RP-RN) is a predetermined value. It is determined whether or not it is shorter than Tcr. In FIG. 2A, since both the signals FH and FL are at a low level, it is determined that T <Trc.

  FIG. 2B shows a case where the lengths of the differential signal lines 50P / 50N are different and the delay amount received by the differential signal UN is longer than the delay amount received by the differential signal UP by a predetermined time te. In this case, the waveform of the differential amplitude signal (RP-RN) that should have been correctly output from the DUT 200 is determined inside the test apparatus, and the fail signal FH is determined to be high level and the fail signal FL is determined to be low level. The transition time T is erroneously determined to be longer than the predetermined value Tcr.

  For example, if a variable-length coaxial tube (trombone) is provided on a path in series with the test fixture TF, the unbalance of the differential line can be canceled by changing the length of the coaxial tube. However, the variable-length coaxial tube is expensive and large, and it is impractical to provide each differential line in a test apparatus having hundreds to thousands of channels. Moreover, since the variable-length coaxial tube is a device in which the line length changes mechanically, it is difficult to adjust quickly.

  Although it is possible to form the entire differential signal line 50 using a line having excellent symmetry such as a twisted pair, in this case, the differential signal UP / UN from the DUT 200 has a phase difference or asymmetry. In some cases, they are averaged during propagation, making it difficult to evaluate the true waveform from the DUT 200 on the test equipment side. The original merit of the differential line that the waveform asymmetry is averaged in the middle of the transmission line is a demerit from the viewpoint of the test apparatus.

  In addition, Patent Documents 1 to 3 disclose techniques for dealing with unbalanced differential line lengths.

  A test apparatus for testing a DUT having a bidirectional differential interface is provided with a transmitter and a receiver connected to a common differential signal line pair (hereinafter also simply referred to as a differential signal line). The transmitter transmits a test pattern to the DUT, and the receiver determines the logical value of the differential signal output from the DUT or checks the amplitude of the differential voltage of the differential signal pair.

  The receiver of the test apparatus is connected to the DUT through the differential signal line pair and is also connected to the transmitter on the test apparatus side. Therefore, it is necessary to design a test apparatus for a DUT having a bidirectional differential interface so that its receiver is not affected by the output of an adjacent transmitter. Some of the above-mentioned patent documents (particularly, Patent Documents 5 to 7) disclose circuits (hybrid circuits) that cancel their own transmission signals and receive only signals from the other party in bidirectional communication. .

US Pat. No. 7,397,289 US Pat. No. 6,909,980B2 International Publication No. 05/081004 Pamphlet US Pat. No. 7,121,132 JP 2006-23233 A JP 47-011702 A Japanese Patent Laid-Open No. 8-023354 US Pat. No. 2,725,532 US Pat. No. 6,133,725 US Pat. No. 6,563,298 US Pat. No. 7,373,574

  The present invention has been made in such a situation, and one of its exemplary purposes is to eliminate the unbalance in the differential line and to evaluate the received differential signal from the device under test from the driver. It is to provide a differential bidirectional interface capable of canceling the influence of a transmission differential signal supplied to a test device.

  In one aspect of the present invention, a reception differential signal output from a device under test is received via a differential line, and the differential amplitude of the reception differential signal is compared with a predetermined threshold voltage. The present invention relates to a differential hybrid circuit that supplies a transmission differential signal to a device under test via a line. The differential hybrid circuit includes a first input / output terminal through which one of the reception differential signals and one of the transmission differential signals are input / output, and the other of the reception differential signals and the other of the transmission differential signals. 2 input / output terminals, a main driver amplifier that generates a first differential signal based on pattern data to be transmitted to the device under test, one output terminal of the main driver amplifier, and a first input / output terminal A replica driver amplifier that generates a second differential signal based on pattern data, a second resistor provided between the first resistor, the other output terminal of the main driver amplifier, and a second input / output terminal A third resistor having a first terminal connected to one output terminal of the replica driver amplifier, a fourth resistor having a first terminal connected to the other output terminal of the replica driver amplifier, and a first input / output terminal A first subtracter for generating a first potential difference signal corresponding to the potential difference between the potential and the potential of the second terminal of the third resistor; and a potential difference between the potential of the second input / output terminal and the potential of the second terminal of the fourth resistor. A second subtracter for generating the second potential difference signal, a first sample hold circuit that samples the first potential difference signal at a specified timing, and then holds the sample, and a second potential difference signal is sampled at the specified timing. Then, the second sample and hold circuit that holds the signal, the comparison unit that compares a signal corresponding to the difference between the output signals of the first and second sample and hold circuits with a predetermined threshold value, and the output of the comparison unit are latched And the latch timing of the first and second sample and hold circuits and the latch timing of the latch circuit can be adjusted independently.

The device under test and the differential hybrid circuit are connected by a pair of differential lines composed of a positive line and a negative line, but the line lengths of the two differential lines may deviate. In this case, the variation in the line length of the differential line can be canceled by adjusting the sampling timing of the first sample hold circuit and the second sample hold circuit according to the deviation of the wiring length. This means that the raw differential signal output from the device under test can be properly evaluated.
Further, by providing the replica driver amplifier, it is possible to determine the amplitude of the differential signal received from the DUT in a state where the influence of the output of the main driver amplifier on the input voltage of the comparison unit is canceled.

  The first sample and hold circuit includes a first switch, a first capacitor, a second switch, and a predetermined voltage, which are sequentially provided in series between the first input / output terminal and the second terminal of the third resistor. A first voltage source for generating a first reference voltage shifted by a potential difference corresponding to the threshold voltage, a connection point between the second switch and the first capacitor, and a third switch provided between the first voltage source, , May be included. The first sample hold circuit includes steps of turning on the first and second switches and turning off the third switch, and turning off the first and second switches and turning on the third switch. You may perform with the timing according to a strobe signal. The second sample and hold circuit includes a fourth switch, a second capacitor, a fifth switch, and a predetermined voltage, which are sequentially provided in series between the second input / output terminal and the second terminal of the fourth resistor. A second voltage source for generating a second reference voltage shifted by a potential difference corresponding to the threshold voltage, a connection point between the fifth switch and the second capacitor, and a sixth switch provided between the second voltage sources; , May be included. The second sample hold circuit includes steps of turning on the fourth and fifth switches and turning off the sixth switch, and turning off the fourth and fifth switches and turning on the sixth switch. You may perform with the timing according to a strobe signal. The comparison unit compares the potential at the connection point between the first switch and the first capacitor with the potential at the connection point between the fourth switch and the second capacitor, and the latch circuit determines the output of the comparison unit according to the strobe signal. May be latched.

  In this aspect, the functions of the first and second subtractors are equivalently realized by the calculation using the capacitor, so that a high-speed analog subtracter is not necessary. Thereby, there is an advantage that the difficulty of circuit design can be reduced, or that it can be implemented by an inexpensive CMOS process.

The differential hybrid circuit according to an aspect may further include a replica load circuit. The replica load circuit includes a single amplifier, a fifth resistor provided between the output terminal of the single amplifier and the third resistor, and a sixth resistor provided between the output terminal of the single amplifier and the fourth resistor. May be included.
By providing the replica load circuit, the load condition of the replica driver amplifier can be made substantially the same as that of the main driver.

  Another aspect of the present invention is a test apparatus. The test apparatus includes a first differential hybrid circuit and a second differential hybrid circuit. The first differential hybrid circuit receives the reception differential signal output from the device under test, and compares the differential amplitude of the reception differential signal with a predetermined upper threshold voltage. The second differential hybrid circuit receives the reception differential signal output from the device under test, and compares the differential amplitude of the reception differential signal with a predetermined lower threshold voltage. The first and second differential hybrid circuits are configured in any of the above-described manners, and share the fourth resistor from the first and second input / output terminals, the main driver amplifier, the replica driver amplifier, and the first resistor. To do.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other between methods and apparatuses are also effective as an aspect of the present invention.

  The differential hybrid circuit according to an aspect of the present invention cancels the unbalance of the differential signal lines and is supplied from the driver to the device under test when evaluating the received differential signal from the device under test. The influence of the transmission differential signal can be canceled.

FIGS. 1A and 1B are block diagrams illustrating a part of the configuration of a test apparatus that tests a device having a differential interface. 2A and 2B are operation waveform diagrams of the differential comparator when the lengths of the differential lines are uniform and non-uniform, respectively. It is a circuit diagram which shows a part of structure of the test apparatus which concerns on embodiment. 4A to 4C are diagrams for explaining the configuration and operation of the main driver amplifier and the replica driver amplifier. 4 is a time chart illustrating the operation of the test apparatus in FIG. 3. It is a circuit diagram which shows another structural example of the test apparatus which concerns on embodiment. 7 is a time chart illustrating the operation of the test apparatus in FIG. 6.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

  In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are physically directly connected, or the member A and the member B are electrically connected. The case where it is indirectly connected through another member that does not affect the state is also included. Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical condition. It includes the case of being indirectly connected through another member that does not affect the connection state.

  FIG. 3 is a circuit diagram showing a part of the configuration of the test apparatus 100 according to the embodiment. The test apparatus 100 includes a pin electronics PE and a test fixture TF. The DUT 200 outputs a differential output signal (hereinafter referred to as a reception differential signal) UP / UN. The reception differential signal UP / UN is input to the first input / output terminal P1 and the second input / output terminal P2 of the pin electronics PE through the differential signal line 50P / 50N formed in the test fixture TF.

  The pin electronics PE includes at least one differential hybrid circuit 8. Although one differential hybrid circuit is shown in FIG. 3, the actual test apparatus 100 is usually provided with a plurality of differential hybrid circuits.

The differential hybrid circuit 8 includes an upper (High-side) differential comparator 10H, a lower (Low-side) differential comparator 10L, and a driver unit 60. The differential hybrid circuit 8
(1) Function as a timing comparator for evaluating the level of the received differential signal RP / RN based on the timing of the input strobe signals φ0H and φ0L. (2) For the DUT 200 via the differential signal line 50P / 50N It also has two functions as a driver that supplies a transmission differential signal.

  First, the transmission side driver unit 60 will be described. The driver unit 60 includes a main driver amplifier 62, a replica driver amplifier 64, a first resistor R1 to a fourth resistor R4, and a replica load circuit 66.

  The main driver amplifier 62 generates the first differential signal Vdp / Vdn based on the pattern data PAT to be transmitted to the DUT 200. The replica driver amplifier 64 generates the second differential signal Vcp / Vcn based on the pattern data PAT.

  The first resistor R1 is provided between one output terminal (non-inverting output terminal) of the main driver amplifier 62 and the first input / output terminal P1. The second resistor R2 is provided between the other output terminal (inverted output terminal) of the main driver amplifier 62 and the second input / output terminal P2. Further, one end (first terminal) of the third resistor R3 is connected to one output terminal (non-inverted output terminal) of the replica driver amplifier 64. One end (first terminal) of the fourth resistor R4 is connected to the other output terminal (inverted output terminal) of the replica driver amplifier 64.

  The resistance values of the first resistor R1 and the second resistor R2 are preferably equal to Ra, and are preferably matched with the characteristic impedance of the differential signal line 50. The resistance values of the third resistor R3 and the fourth resistor R4 are equal to β · Ra. Here, β is a parameter.

  As will be described later, the replica driver amplifier 64, the third resistor R3, and the fourth resistor R4 are provided to cancel the first differential signal Vdp / Vdn output from the main driver amplifier 62.

  The replica load circuit 66 includes a single amplifier 68, a fifth resistor R5, and a sixth resistor R6. The single amplifier 68 outputs a predetermined voltage VRL. Since this predetermined voltage VRL is finally canceled, its value is not particularly meaningful, but it may be made to coincide with the common voltage of the differential signal UUP / UUN generated in the DUT 200, for example. The fifth resistor R5 is provided between the output terminal of the single amplifier 68 and the second terminal of the third resistor R3. The sixth resistor R6 is provided between the output terminal of the single amplifier 68 and the second terminal of the fourth resistor R4. The resistance values of the fifth resistor R5 and the sixth resistor R6 are equally β · Ra. The replica load circuit 66 makes the load condition of the replica driver amplifier 64 substantially the same as that of the main driver amplifier 62.

  It is desirable that the drive ratio (also referred to as current supply capability) of the main driver amplifier 62 and the replica driver amplifier 64, in other words, the ratio of the sizes of the transistors (particularly the output stage) constituting them is approximately β: 1. When designed in this way, the balance between the driving capability and the load resistance can be matched between the main driver amplifier 62 and the replica driver amplifier 64.

  When β = 1, the main driver amplifier 62 and the replica driver amplifier 64 are approximately the same size. From the viewpoint of power consumption and circuit area, it is desirable that the size of the replica driver amplifier 64 is small. Therefore, β is preferably larger than 1, but from a practical point of view, β is preferably about 10.

4A to 4C are diagrams illustrating the configuration and operation of the main driver amplifier 62 and the replica driver amplifier 64. FIG. 4A shows a circuit symbol of the amplifier, and FIG. 4B shows an operation waveform. Amp represents the half-value amplitude of the differential output signals OutP and OutN, and Offset represents the bias voltage (common voltage) of the differential output signals OutP and OutN. When the input signal PAT is 1, the non-inverted output OutP and the inverted output OutN are respectively
OutP = Offset + Amp
OutN = Offset-Amp
When the input signal PAT is 0,
OutP = Offset-Amp
OutN = Offset + Amp
It becomes.

  Note that the amplifier indicated by the circuit symbol in FIG. 4 (a) merely indicates that the amplitude and common voltage of the amplifier have values represented by Amp and Offset. It is not necessary to have a terminal for setting.

  The main driver amplifier 62 and the replica driver amplifier 64 may be constituted by purely differential amplifiers having the above-described functions, or may be configured as shown in FIG. The differential amplifier of FIG. 4C includes a first buffer 80, a second buffer 82, an inverter 84, a first delay circuit 86, a second delay circuit 88, an analog adder 90, and an analog subtractor 92.

  The analog adder 90 adds the half-value amplitude Amp and the common voltage Offset and supplies the sum to the power supply terminal (Vdd) on the upper side of the buffers 80 and 82. The analog subtractor 92 supplies a voltage obtained by subtracting the half-value amplitude Amp from the common voltage Offset to the lower power supply terminal (Vss) of the buffers 80 and 82.

The first delay circuit 86 gives a delay to the pattern data PAT. The buffer 80 outputs the delayed pattern data PAT as a non-inverted output OutP.
The inverter 84 inverts the pattern data PAT, and the second delay circuit 88 gives a delay to the inverted pattern data. The buffer 82 outputs the inverted and delayed pattern data PAT as an inverted output OutN.

  According to the amplifier of FIG. 4C, the differential amplitude and the common voltage can be adjusted, and the skew between the non-inverted output OutP and the inverted output OutN can be adjusted by the delay circuits 86 and 88.

  The above is the configuration of the driver unit 60. Next, returning to FIG. 3, the configuration of the differential comparators 10H and 10L will be described.

  The differential comparator 10H compares the differential amplitude component DA (= RP−RN) of the received differential signal RP / RN with a predetermined upper threshold voltage VOH. The differential comparator 10L compares the differential amplitude component (RP-RN) with a predetermined lower threshold voltage VOL.

  Since the differential comparators 10H and 10L have the same configuration, only the upper differential comparator 10H will be described below. The lower differential comparator 10L may read the suffix “H” of the reference numerals attached to each signal or member as “L”. Further, as shown in the lower right symbol in FIG. 3, the switch SW shown in this specification is turned off (cut off) and 1 (high level) when 0 (low level) is inputted as a control signal. It shall be turned on (conducted) when As such a switch, an analog switch such as a transfer gate can be preferably used.

    The differential comparator 10H includes a first sample hold circuit SH1, a second sample hold circuit SH2, a comparison unit 12, a latch circuit 18, a timing control unit 20, a first subtractor SUB1, and a second subtractor SUB2.

  A non-inverted component (hereinafter referred to as a positive signal) RP, which is one of the received differential signals RP / RN, is input to the first input / output terminal P1. An inverted component (hereinafter referred to as a negative signal) RN, which is the other of the reception differential signals RP / RN, is input to the second input / output terminal P2.

  The first subtracter SUB1 generates a first potential difference signal HP corresponding to the potential difference (RP−Vep) between the potential RP of the first input / output terminal P1 and the potential Vep of the second terminal of the third resistor R3. Similarly, the second subtracter SUB2 generates a second potential difference signal HN corresponding to the potential difference (RN−Ven) between the potential RN of the second input / output terminal P2 and the potential Ven of the second terminal of the fourth resistor R4.

The first sample hold circuit SH1 samples the first potential difference signal HP generated by the first subtractor SUB1 at a timing (for example, negative edge timing) designated by the first control signal (hold signal) φ1HP, and then The sampled value HP _HOLD is held (hold mode). During a period before the sampling timing, the output signal HHP of the first sample hold circuit SH1 coincides with the input signal HP (tracking mode).

Similarly, the second sample hold circuit SH2 samples the second potential difference signal HN generated by the second subtracter SUB2 at a timing (for example, negative edge timing) designated by the second control signal (hold signal) φ1HN. Thereafter, the value HN _HOLD is held (hold mode). During a period before the sampling timing, the output signal HHN of the second sample hold circuit SH2 coincides with the input signal HN (tracking mode).

  That is, the first sample hold circuit SH1 and the second sample hold circuit SH2 have a function of outputting (tracking) the input signal as it is, sampling and holding it at a designated timing.

  In FIG. 3, the first sample hold circuit SH1 and the second sample hold circuit SH2 are in the tracking mode when the switch SW is turned on, and when the switch SW is turned off, the values are sampled and held. Each of the first sample hold circuit SH1 and the second sample hold circuit SH2 includes a switch SW and a capacitor C. However, their configurations are not limited to those shown in FIG. Other configurations not described may be used.

  The comparison unit 12 determines the difference between the output signal (hold positive signal) HHP of the first sample hold circuit SH1 and the output signal (hold negative signal) HHN of the second sample hold circuit SH2, that is, the differential amplitude (HHP−HHN). The corresponding differential amplitude signal DA is compared with the upper threshold voltage VOH. As a result of the comparison, a comparison signal SH that is low when (HHP−HHN)> VOH and high when (HHP−HHN) <VOH is output.

  In FIG. 3, the comparison unit 12 includes a subtracter 14 and a comparator 16. The subtractor 14 subtracts the hold negative signal HHN from the hold positive signal HHP in an analog manner. For example, the subtractor 14 may be a subtractor including a combination of a resistor and an operational amplifier, or may be another type of subtracter. The comparator 16 compares the differential amplitude signal DA output from the subtractor 14 with the threshold voltage VOH. Note that the configuration of the comparison unit 12 is not limited to that shown in FIG.

  The latch circuit 18 latches the comparison signal SH at a timing (for example, positive edge) according to the third control signal φ3H. The latched fail signal FH is input to a determination circuit (not shown).

The timing control unit 20 generates control signals φ1HP, φ1HN, and φ3H based on a reference strobe signal φ0H input from the outside, and the first sample hold circuit SH1, the second sample hold circuit SH2, and the latch circuit 18 are generated. Control.
The transition timing of each control signal φ1HP, φ1HN, φ3H can be arbitrarily adjusted. That is, the sampling timing of the first sample hold circuit SH1 and the second sample hold circuit SH2 and the latch timing of the latch circuit 18 can be adjusted independently.

The timing control unit 20 includes a first delay circuit 22, a second delay circuit 24, a first AND gate 26, a first inverter 28, a second inverter 30, and a third delay circuit 32.
The first delay circuit 22 and the second delay circuit 24 branch the strobe signal φ0H, and give first and second variable delays VDHP and VDHN to the strobe signal φ0H, respectively. The first inverter 28 inverts the output signal of the corresponding first delay circuit 22 and outputs the inverted signal to the first sample hold circuit SH1 as the first control signal φ1HP. The second inverter 30 inverts the output signal of the corresponding second delay circuit 24 and outputs the inverted signal to the second sample and hold circuit SH2 as the second control signal φ1HN.

  The first AND gate 26 generates a logical product of the output signals of the first delay circuit 22 and the second delay circuit 24. The output signal of the first AND gate 26 changes following one of the first control signal φ1HP and the second control signal φ1HN that changes late. The third delay circuit 32 gives the third delay FD1 to the output signal of the first AND gate 26 and outputs it as the third control signal φ3H. Therefore, the latch circuit 18 latches the comparison signal SH from the comparison unit 12 after the third delay FD1 from the timing when both the first control signal φ1HP and the second control signal φ1HN are in the hold mode.

  The above is the configuration of the differential comparator 10H.

  Next, the operation of the test apparatus 100 of FIG. 3 will be described. FIG. 5 is a time chart illustrating the operation of the test apparatus 100 of FIG. The period T1 is a period during which the test apparatus 100 receives a signal from the DUT 200, and the period T2 is a period during which the test apparatus 100 transmits a signal to the DUT 200.

  The main driver amplifier 62 and the replica driver amplifier 64 generate substantially the same differential signals. That is, Vdp = Vcp and Vdn = Vcn are established. Here, for simplification of description, it is assumed that the main driver amplifier 62, the replica driver amplifier 64, and the DUT 200 are ideal amplifiers having zero output impedance.

Now, in the circuit diagram of FIG. 3, the voltages of the differential signals RP, RN, Vep, and Ven are given as follows.
RP = (Vdp + UUP) / 2 (2a)
RN = (Vdn + UUN) / 2 (2b)
Vep = (Vcp + VRL) / 2 (2c)
Ven = (Vcn + VRL) / 2 (2d)

Potential difference signals HP and HN are generated by the first subtracter SUB1 and the second subtracter SUB2 of the differential comparator 10H.
HP = RP-Vep
HN = RN-Ven

  Focus on the differential comparator 10H side. Prior to the test of the DUT 200, it is assumed that the line length difference of the differential signal lines 50P / 50N, in other words, the propagation time difference te is measured in advance. The propagation time error te can be measured by the method disclosed in US Pat. No. 7,121,132, for example. As a result of the measurement, it is assumed that one propagation time of the differential signal line 50 is given by tpd and the other propagation time is given by tpd + te.

On both the differential comparators 10H side and 10L side, the first variable delay VDHP (VDLP) and the second variable delay VDHN (VDLN) are set based on the measured error te. Specifically, the delay amounts of the first delay circuit 22 and the second delay circuit 24 are:
VDHN = VDHP + te
VDLN = VDLP + te
It is adjusted to satisfy. By this adjustment, the timing at which the second control signal φ1HN instructs the second sample hold circuit SH2 to sample is delayed by a time difference te from the timing at which the first control signal φ1HP instructs the first sample hold circuit SH1 to sample.

  In order to simplify the description, in the time chart of FIG. 5, it is assumed that te = 0 and the propagation delays of the differential signal lines 50P and 50N are equal.

  Prior to time t0, the strobe signal φ0H is at a low level, and the first control signal φ1HP and the second control signal φ1HN are both at a high level. During this time, both the first sample hold circuit SH1 and the second sample hold circuit SH2 are set to the tracking mode.

  At time t0, the strobe signal φ0H changes to high level. When the first control signal φ1HP transitions to the low level at the time t1 after the first variable delay VDHP has elapsed from the time t0, the first sample hold circuit SH1 is set to the hold mode, and the value of the first potential difference signal HP is sampled. Then hold.

  When the second control signal φ1HN transitions from the high level to the low level at the time t2 after the first variable delay VDHN has elapsed from the time t0, the second sample hold circuit SH2 is set to the hold mode, and the second potential difference signal HN Is sampled and then retained. As described above, when te = 0, the time t1 matches the time t2.

  Here, attention is focused on the differential amplitude signal DA (= HHP−HHN) output from the subtractor 14. The value of the differential amplitude signal (HHP−HHN) changes as follows according to the states of the first sample hold circuit SH1 and the second sample hold circuit SH2.

(1) Before time t1 In this state, both the first sample hold circuit SH1 and the second sample hold circuit SH2 are in the tracking mode.
HHP = HP
HHN = HN
Focusing on the differential amplitude signal DA during this period,
DA = HP-HN
= (RP-Vep)-(RN-Ven) (3)
Holds. If the equations (2a) to (2d) are substituted into the equation (3) and the main driver amplifier 62 and the replica driver amplifier 64 generate substantially the same differential signal,
DA = (UUP-UUN) / 2
Get. This expression does not include the signals Vdp and Vpn generated by the main driver amplifier 62, and only the signals UUP / UUN generated by the DUT 200 remain. From this, it can be seen that according to the test apparatus 100 of FIG. 3, the influence of the transmission differential signal on the reception differential signal can be suitably removed.

(2) Time t1 to t2 (t1 ≦ t2)
During this time, the first sample hold circuit SH1 is in the hold mode and the second sample hold circuit SH2 is in the tracking mode. In the time chart of FIG. 5, this period does not exist.
HHP = HP _HOLD
HHN = HN
DA = HP _HOLD -HN

(3) After time t2 In this state, the first sample hold circuit SH1 and the second sample hold circuit SH2 are both in the hold mode.
HHP = HP _HOLD
HHN = HN _HOLD
DA = HP _HOLD -HN _HOLD

  When the differential amplitude signal DA crosses the threshold voltage VOH at time t3 between times t0 and t1, the comparison signal SH changes from high level to low level.

  The third control signal φ3H transitions to the high level at time t4 after the lapse of the delay time FD1 from the times t1 and t2 when both the first sample hold circuit SH1 and the second sample hold circuit SH2 are in the hold mode, and the latch circuit 18 latches the output of the comparator 12. At this time, since the comparison signal SH is at the low level, the value of the fail signal FH is fixed at the low level.

  As shown in the lower part of FIG. 5, the differential comparator 10L operates in the same manner as the differential comparator 10H with reference to the strobe signal φ0L. A low level fail signal FL is generated by the differential comparator 10L.

  The above is the operation of the test apparatus 100. According to the test apparatus 100, when evaluating the reception differential signal UP / UN from the DUT 200, it is possible to cancel the influence of the transmission differential signal Vdp / Vdn supplied from the driver unit 60 to the DUT 200. Furthermore, by optimizing the values of the delay amounts VDHP, VDHN, VDLP, VDLN, and FD, the unbalance of the line lengths of the differential signal lines 50P / 50N can be canceled.

  FIG. 6 is a circuit diagram showing another configuration example of the test apparatus 100 according to the embodiment. The first sample hold circuit SH1 and the second sample hold circuit SH2 in FIG. 6 have a subtractor 14 and a first subtracter SUB1, in addition to the functions of the first sample hold circuit SH1 and the second sample hold circuit SH2 in FIG. It also has the function of the second subtracter SUB2.

The first sample hold circuit SH1 includes a first capacitor C1, a first switch SW1 to a third switch SW3, and a first voltage source VS1.
The first switch SW1, the first capacitor C1, and the second switch SW2 are sequentially provided in series between the first input / output terminal P1 and the second terminal of the third resistor R3.
The first voltage source VS1 generates a first reference voltage (Vc−VOH / 2) obtained by shifting the predetermined voltage Vc to a lower potential side by a potential difference (VOH / 2) corresponding to the threshold voltage VOH. The voltage Vc may be ½ of the power supply voltage, may be a common voltage of the differential signal RP / RN, or may be another constant voltage.
The third switch SW3 is provided between the connection point of the second switch SW2 and the first capacitor C1 and the first voltage source VS1.

  The second sample and hold circuit SH2 includes a second capacitor C2, a fourth switch SW4 to a sixth switch SW6, and a second voltage source VS2, and is configured in the same manner as the first sample and hold circuit SH1. The second voltage source VS2 generates a second reference voltage (Vc + VOH / 2) obtained by shifting the predetermined voltage Vc to the high potential side by a potential difference (VOH / 2) corresponding to the threshold voltage VOH.

  The timing control unit 20 receives the strobe signal φ0H and generates control signals φ1HP, φ1HN, φ2H, and φ3H. The timing control unit 20 of FIG. 6 further includes a fourth delay circuit 34 in addition to that of FIG. The fourth delay circuit 34 gives a delay FD2 to the output signal of the first AND gate 26 to generate a control signal φ2H.

  The first switch SW1 and the second switch SW2 are controlled by a common control signal φ1HP. The fourth switch SW4 and the fifth switch SW5 are controlled by a common control signal φ1HN. The third switch SW3 and the sixth switch SW6 are controlled by a control signal φ2H.

  The first sample hold circuit SH1 performs the following processing.

1. Tracking mode φ1HP = 1, φ1HN = 1, φ2H = 0
At this time, the first switch SW1 and the second switch SW2 are turned on, the third switch SW3 is turned off,
VcapHP = RP-Vep
VcapHN = RN-Ven
Holds.

2. When the hold mode φ1HP = 0 and φ1HN = 0 is switched, the first switch SW1 and the second switch SW2 are turned off. As a result, the potential difference so far is held in the first capacitor C1.
VcapHPP = RP _HOLD -Vep _HOLD
VcapHN = RN _HOLD -Ven _HOLD

3. When the calculation mode is switched to φ2H = 1, the third switch SW3 is turned on. As a result, the potentials of the first capacitor C1 and the second capacitor C2 shift,
SHP = Vc−VOH / 2 + VcappHP
SHN = Vc + VOH / 2 + VcapHN
The operation is performed.

The comparator 16 (comparator 12) compares the potential SHP at the connection point between the first switch SW1 and the first capacitor C1 with the potential SHN at the connection point between the fourth switch SW4 and the second capacitor C2. as a result,
SH = sign (SHN-SHP)
= Sign (VOH- (VcapP-VcapHN))
The comparison signal SH given by is generated. Furthermore, using equation (3),
SH = sign (VOH- (UUP-UUN) / 2)
Therefore, it can be seen that only the signal component generated by the DUT 200 can be evaluated and determined by the comparator 16.

  A similar process is executed on the second sample hold circuit SH2 side.

  The above is the configuration of the test apparatus 100 of FIG. Next, the operation will be described. FIG. 7 is a time chart illustrating the operation of the test apparatus 100 of FIG.

  Prior to time t0, the strobe signal φ0H is at a low level, and the control signal φ1HP and the control signal φ1HN are both at a high level. During this time, each of the first capacitor C1 and the second capacitor C2 is charged (tracking mode).

  At time t0, the strobe signal φ0H changes to high level. When the control signal φ1HP transitions from the high level to the low level at the time t1 after the first variable delay VDHP has elapsed from the time t0, the first switch SW1 and the second switch SW2 are turned off, and the voltage VcappH of the first capacitor C1 is held. (Hold mode)

  When the control signal φ1HN transitions from the high level to the low level at time t2 after the second variable delay VDHN has elapsed from time t0, the fourth switch SW4 and the fifth switch SW5 are turned off, and the voltage VcapH of the second capacitor C2 is held. Is done. When te = 0, the time t1 and the time t2 coincide with each other, and FIG. 7 shows this situation.

  When the two input signals SHP and SHN of the comparator 16 cross at time t6 between times t0 and t1, the comparison signal SH transitions to a low level.

At time t3 after the delay time FD2 has elapsed from time t2, the control signal φ2H becomes high level, and the third switch SW3 and the sixth switch SW6 are turned on (calculation mode).
When the third switch SW3 is turned on, the potential SHP at the connection point of the first capacitor C1 and the first switch SW1 is
SHP = Vc−VOH / 2 + VcappHP
Shift to. Similarly, when the sixth switch SW6 is turned on, the potential SHN at the connection point between the second capacitor C2 and the fourth switch SW4 is
SHN = Vc + VOH / 2 + VcapHN
Shift to.

  The third control signal φ3H transitions to the high level at time t4 after the delay time FD1 has elapsed from time t1, t2 when both the first sample hold circuit SH1 and the second sample hold circuit SH2 are in the hold mode, and the latch circuit 18 latches the output of the comparator 12. At this time, since the comparison signal SH is at the low level, the value of the fail signal FH is fixed at the low level.

  At time t5, when the control signals φ1HP and φ1HN change to the high level and the control signal φ2H changes to the low level, the control mode returns to the tracking mode.

The above is the operation of the test apparatus 100 of FIG.
According to the test apparatus 100 of FIG. 6, similarly to the test apparatus 100 of FIG. 3, the influence of the transmission differential signal on the reception differential signal can be suitably removed. Further, by adjusting the delay times VDHP and VDHN, the unbalance of the wiring lengths of the differential signal lines 50P / 50N can be canceled, and the raw differential signal UP / UN output from the DUT 200 is appropriately evaluated. it can.

  Furthermore, since the test apparatus 100 of FIG. 6 uses the calculation based on the charge transfer of the first capacitor C1 and the second capacitor C2, the analog subtracters (SUB1, SUB2, and 14) used in FIG. 3 become unnecessary. . The circuit of FIG. 3 requires a high-speed amplifier that can follow the high-bit-rate received differential signal output from the DUT 200, but such an amplifier is difficult to design. On the other hand, in the test apparatus 100 of FIG. 6, since such a high-speed amplifier is unnecessary, the difficulty of design can be reduced.

  Although the present invention has been described based on the embodiments, the embodiments merely show the principle and application of the present invention, and the embodiments depart from the idea of the present invention defined in the claims. Many modifications and arrangements can be made without departing from the scope.

DESCRIPTION OF SYMBOLS 8 ... Differential hybrid circuit, 10 ... Differential comparator, P1 ... 1st input / output terminal, P2 ... 2nd input / output terminal, SH1 ... 1st sample hold circuit, SH2 ... 2nd sample hold circuit, 12 ... Comparison part, DESCRIPTION OF SYMBOLS 14 ... Subtractor, 16 ... Comparator, 18 ... Latch circuit, 20 ... Timing control part, 22 ... 1st delay circuit, 24 ... 2nd delay circuit, 26 ... 1st AND gate, 28 ... 1st inverter, 30 ... 2nd Inverter, 32 ... third delay circuit, 34 ... fourth delay circuit, SUB1 ... first subtractor, SUB2 ... second subtractor, 50 ... differential signal line, 60 ... driver unit, 62 ... main driver amplifier, 64 ... Replica driver amplifier, 66 ... replica load circuit, 68 ... single amplifier, R1 ... first resistor, R2 ... second resistor, R3 ... third resistor, R4 ... fourth resistor, R5 ... fifth Anti-R6: Sixth resistor, 100: Test device, 200: DUT, C1: First capacitor, C2: Second capacitor, SW1: First switch, SW2: Second switch, SW3: Third switch, SW4: First 4 switch, SW5 ... 5th switch, SW6 ... 6th switch, VS1 ... 1st voltage source, VS2 ... 2nd voltage source.

Claims (4)

A reception differential signal output from the device under test is received via a differential line, the differential amplitude of the reception differential signal is compared with a predetermined threshold voltage, and the differential line is transmitted via the differential line. A differential hybrid circuit for supplying a transmission differential signal to a device under test,
A first input / output terminal to which one of the reception differential signals and one of the transmission differential signals are input / output;
A second input / output terminal through which the other of the reception differential signal and the other of the transmission differential signal are input / output;
A main driver amplifier that generates a first differential signal based on pattern data to be transmitted to the device under test;
A first resistor provided between one output terminal of the main driver amplifier and the first input / output terminal;
A second resistor provided between the other output terminal of the main driver amplifier and the second input / output terminal;
A replica driver amplifier that generates a second differential signal based on the pattern data;
A third resistor having a first terminal connected to one output terminal of the replica driver amplifier;
A fourth resistor having a first terminal connected to the other output terminal of the replica driver amplifier;
A first subtracter for generating a first potential difference signal corresponding to a potential difference between the potential of the first input / output terminal and the potential of the second terminal of the third resistor;
A second subtracter for generating a second potential difference signal corresponding to a potential difference between the potential of the second input / output terminal and the potential of the second terminal of the fourth resistor;
A first sample and hold circuit that samples the first potential difference signal at a designated timing and then holds the first potential difference signal;
A second sample and hold circuit that samples the second potential difference signal at a designated timing and then holds the second potential difference signal;
A comparator for comparing a signal corresponding to a difference between output signals of the first and second sample and hold circuits with a predetermined threshold;
A latch circuit for latching the output of the comparator;
The differential hybrid circuit is characterized in that the sampling timing of the first and second sample hold circuits and the latch timing of the latch circuit can be adjusted independently. The first sample and hold circuit includes:
A first switch, a first capacitor, a second switch provided in series between the first input / output terminal and the second terminal of the third resistor;
A first voltage source for generating a first reference voltage by shifting a predetermined voltage by a potential difference corresponding to the threshold voltage;
A connection point between the second switch and the first capacitor, and a third switch provided between the first voltage source;
Including
Turning the first and second switches on and the third switch off;
Turning off the first and second switches;
Turning off the first and second switches and turning on the third switch;
At a timing according to the strobe signal,
The second sample and hold circuit includes:
A fourth switch, a second capacitor, and a fifth switch provided in series between the second input / output terminal and the second terminal of the fourth resistor;
A second voltage source that generates a second reference voltage by shifting a predetermined voltage by a potential difference corresponding to the threshold voltage;
A connection point between the fifth switch and the second capacitor and a sixth switch provided between the second voltage source;
Including
Turning the fourth and fifth switches on and the sixth switch off;
Turning off the fourth and fifth switches;
Turning off the fourth and fifth switches and turning on the sixth switch;
At a timing according to the strobe signal,
The comparison unit compares the potential at the connection point between the first switch and the first capacitor with the potential at the connection point between the fourth switch and the second capacitor;
The differential hybrid circuit according to claim 1, wherein the latch circuit latches the output of the comparison unit at a timing corresponding to the strobe signal. A single amplifier,
A fifth resistor provided between the output terminal of the single amplifier and the third resistor;
A sixth resistor provided between the output terminal of the single amplifier and the fourth resistor;
The differential hybrid circuit according to claim 1, further comprising a replica load circuit including The first differential hybrid according to claim 1 or 2, wherein a reception differential signal output from a device under test is received, and a differential amplitude of the reception differential signal is compared with a predetermined upper threshold voltage. Circuit,
The second difference according to claim 1 or 2, wherein a reception differential signal output from the device under test is received, and a differential amplitude of the reception differential signal is compared with a predetermined lower threshold voltage. Dynamic hybrid circuit,
With
The first and second differential hybrid circuits share the first and second input / output terminals, the main driver amplifier, the replica driver amplifier, and a first resistor to a fourth resistor.

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