JP4685813B2 - Receiver - Google Patents

Description

  The present invention relates to a signal transmission technique for performing high-speed signal transmission between a plurality of LSI chips or between a plurality of elements and circuit blocks in one chip, or between a plurality of boards or a plurality of enclosures. In particular, the present invention relates to a receiver that performs these signal transmissions.

  In recent years, the performance of components constituting computers and other information processing devices has been greatly improved. For example, the performance improvement of semiconductor storage devices such as DRAM (Dynamic Random Access Memory) and processors is remarkable. As the performance of the semiconductor memory device, processor, etc. is improved, the performance of the system cannot be improved unless the signal transmission speed between components or elements is improved. Specifically, for example, a signal transmission speed between a main storage device such as a DRAM and a processor (between LSIs) is becoming an obstacle to improving the performance of the entire computer. Furthermore, not only signal transmission between the chassis and the board (printed wiring board) such as between the server and the main storage device or the server via the network, but also high integration and enlargement of the semiconductor chip and low power supply voltage. Due to (lowering of signal amplitude level) and the like, it is necessary to improve the signal transmission speed in signal transmission between chips and signal transmission between elements and circuit blocks in the chip. Therefore, a transceiver circuit capable of evaluating and diagnosing a signal transmission system, optimizing transmission / reception parameters and increasing the sensitivity of the receiver, and a receiver capable of removing a large common mode voltage in a circuit performing signal transmission. Offer is desired.

  In recent years, it is necessary to increase the signal transmission speed per pin in order to cope with an increase in the amount of data transmission between LSIs and boards or between enclosures. This is to avoid an increase in the cost of the package or the like due to an increase in the number of pins. As a result, recently, the signal transmission speed between LSIs exceeds 1 Gbps, and in the future (about 3 to 8 years ahead), it is expected to become extremely high values (high-speed signal transmission) such as 4 Gbps or 10 Gbps. Yes.

  FIG. 1 is a block diagram schematically showing an example of a conventional signal transmission system. In FIG. 1, reference numeral 101 denotes a differential driver, 102 denotes a signal transmission path (cable), and 103 denotes a differential receiver (receiver).

  As shown in FIG. 1, for example, differential signal transmission is generally performed in high-speed signal transmission between boards or between bodies (for example, between a server and a main storage device). Here, for example, the differential driver 101 is provided in a server (main storage device) that is a signal transmission side, and the receiver 103 is provided in a main storage device (server) that is a signal reception side. Note that signal transmission using differential signals (complementary signals) is used not only between boards and housings, but also between, for example, elements and circuit blocks in a chip.

  FIG. 2 is a waveform diagram showing an example of signal data transmitted by the signal transmission system of FIG.

  When transmitting data signals between LSIs, boards, or enclosures, if the transmission distance by the transmission line (cable 102), etc. is relatively long or the conductor width of the transmission line is narrow, etc. Interference occurs between codes due to high-frequency loss, and it is difficult to accurately determine “0” and “1” of signal data, making high-speed signal transmission difficult. That is, for example, in the signal transmission system as illustrated in FIG. 1, when data “101001011...” Is transmitted from the transmission-side differential driver 101 to the reception-side differential receiver 103 via the cable 102. The waveform of the signal data sent to the side (differential receiver 103) is distorted as shown in FIG. 2, for example, the intersection at the point (EP) where the voltage value of the differential signal should originally cross. In order not to occur, in the differential receiver (103) using a normal differential amplifier, the transmitted data is erroneously determined as “100001111...”.

  Further, for example, the same applies when a high-speed signal of several Gbps is passed through a wiring on a printed circuit board or a copper cable, and the received waveform is shown in FIG. 2 rather than a digital signal such as “0” and “1”. Rather, it is a waveform that takes an intermediate value between analog “0” and “1”. Therefore, in order for the high-speed signal transmission / reception circuit (transceiver circuit) to operate correctly, it is necessary to acquire data relating to the waveform actually reaching the receiver and adjust the transceiver circuit based on this value.

  However, in the prior art, for example, since there is no means for observing an actual waveform in a state where an LSI is mounted on a printed circuit board, a determination only about whether or not a signal can be received by a receiver (go / no-go type) It was only possible to make a decision.

  By the way, in signal transmission between LSIs, boards, or housings, differential signal transmission is usually used when the transmission distance is relatively long. This is because the noise induced in the transmission path (signal line) in the signal transmission process generally becomes common mode noise with respect to the signal, and common mode noise can be removed in differential transmission. .

  FIG. 3 is a circuit diagram showing an example of a conventional receiver, and shows a differential receiver. In FIG. 3, reference numerals 131 and 132 denote P-channel MOS transistors (PMOS transistors), and 133 to 135 denote N-channel MOS transistors (NMOS transistors).

  As shown in FIG. 3, the conventional receiver is constituted by a differential amplification stage using a differential pair of transistors, for example, in order to receive a differential signal (V +, V-). However, the differential pair is normally operated only when the differential amplifier stage operates as an active element. Further, for example, when a large common mode voltage is applied, the characteristics of the differential amplifier stage are different from those in the case where the common mode noise is small, and the designed characteristics cannot be obtained.

  That is, the common mode voltage removing means using an active element such as a differential amplifier stage has a problem to be solved that the common mode voltage range that can be handled cannot be increased so much. Conventionally, a wide range of common-mode voltages has been removed using a transformer. For example, an external passive component (transformer) that does not pass a DC signal is added to the outside of the LSI. This will be a major factor in the cost increase.

  An object of the present invention is to provide a receiver capable of removing a large common mode voltage in a circuit that performs signal transmission.

According to the present invention, a plurality of signal lines, a plurality of signal voltage storage nodes connected to the respective signal lines via first switches, and a second switch connected to the signal voltage storage nodes. A plurality of signal voltage storage nodes having a capacitance connected between each signal voltage storage node and a reference point, or between adjacent signal voltage storage nodes. Thus, the operation of the receiver includes at least a sample period and a determination period, and the sample period and the determination period are alternately repeated. In the sample period, the first switch is turned on. with said second turning off the switch, it accumulates a voltage of the signal line connecting the signal voltage storage node and said signal line to the signal voltage storage node, the signal voltage accumulated Bruno Applying a common mode voltage with said signal lines to one end of the connected the capacity de, the in the determination period, and turns on the second switch by turning off the first switch, the signal voltage storage node Connected to the determination circuit, the voltage of the signal line stored in the signal voltage storage node is transmitted to the determination circuit, the receiver further prior to the determination operation of the determination circuit, Provided is a receiver comprising a common mode voltage removing means for removing the common mode voltage of the signal line by connecting one end of the capacitor connected to the signal voltage storage node to a specific voltage value. Is done.

[Remarks]
1. An offset applying unit that gives a known offset to the input signal; and a determination circuit that compares the input signal to which the offset is given with a reference voltage, and the input signal is obtained from a result of the determination circuit and the known offset. The receiver characterized by confirming the level of.

    2. 2. The receiver according to item 1, wherein the offset applying means includes offset level control means for controlling the level of the offset by a digital signal.

    3. 3. The receiver according to item 2, wherein the receiver further increases or decreases the offset level by the offset level control means, and searches for an offset level at which a result of the determination circuit changes to search for an input signal level. An input signal level detecting means for detecting the signal.

    4). Item 4. The receiver according to Item 3, further comprising timing control means for controlling the determination timing of the determination circuit to change relative to the internal clock of the receiver, and the receiver is previously input from the outside. A receiver characterized in that a predetermined test pattern is determined at an output timing of the timing control means to adjust the level of the offset, and the input signal level detection means acquires information relating to the input signal.

    5. Item 2. The receiver according to Item 1, wherein the offset application unit is configured to cause a constant current to flow through a termination resistor provided in parallel with the input terminal of the receiver.

    6). The receiver according to item 1, wherein the offset applying means includes a plurality of capacitors and switches, and the offset level is changed by changing a precharge voltage of each capacitor. Receiver.

    7). 2. The receiver according to item 1, wherein the offset applying means changes the level of the offset by flowing a constant current into an internal node of the receiver.

    8). 2. The receiver according to item 1, wherein the offset applying means changes the level of the offset by flowing a constant current into an internal node of the receiver.

    9. In the receiver according to any one of items 1 to 8, using the waveform of the input signal obtained from the result of the determination circuit and the known offset, diagnosis of the signal quality of the received input signal, Alternatively, a receiver characterized by adjusting the characteristics of the receiver or driver.

    10. A transceiver circuit having a receiver for receiving a signal to be input and a driver for outputting a signal, wherein the receiver includes an offset applying means for giving a known offset to the input signal, and an input signal to which the offset is given A transceiver for comparing the input signal level with a reference voltage, and confirming a level of the input signal from a result of the determination circuit and the known offset.

    11. 11. The transceiver circuit according to item 10, wherein the offset applying means includes offset level control means for controlling the level of the offset by a digital signal.

    12 12. The transceiver circuit according to item 11, wherein the receiver further increases or decreases the level of the offset by the offset level control means, and searches for an offset level at which a result of the determination circuit changes to search for the input signal. A transceiver circuit comprising input signal level detection means for detecting a level.

    13. Item 13. The transceiver circuit according to Item 12, wherein the receiver further includes timing control means for controlling the determination timing by the determination circuit to change relative to the internal clock of the receiver, and is input from the outside. A transceiver characterized in that a predetermined test pattern is determined at an output timing of the timing control means, the level of the offset is adjusted, and information on the input signal is acquired by the input signal level detection means. circuit.

    14 Item 11. The transceiver circuit according to Item 10, wherein the offset applying means is configured to pass a constant current through a termination resistor provided in parallel with the input terminal of the receiver.

    15. Item 11. The transceiver circuit according to Item 10, wherein the offset applying means includes a plurality of capacitors and switches, and the offset level is changed by changing a precharge voltage of each capacitor. Transceiver circuit.

    16. Item 11. The transceiver circuit according to Item 10, wherein the offset applying means changes the level of the offset by flowing a constant current into an internal node of the receiver.

    17. Item 11. The transceiver circuit according to Item 10, wherein the offset applying means changes the level of the offset by flowing a constant current into an internal node of the receiver.

    18. Item 17. The transceiver circuit according to any one of Items 10 to 16, wherein a signal quality diagnosis of the received input signal is performed using the result of the determination circuit and the waveform of the input signal obtained from the known offset. Alternatively, a transceiver circuit characterized by adjusting the characteristics of the receiver or driver.

    19. Item 11. The transceiver circuit according to Item 10, wherein the transceiver circuit transmits a test pattern predetermined by the driver to a receiver of another transceiver circuit, and a test transmitted from the driver of the other transceiver circuit. A test pattern determination unit that receives a pattern at the receiver and determines the pattern at a predetermined timing by the determination circuit; and a test pattern level detection unit that detects the level of the test pattern by adjusting the level of the offset, A transceiver circuit, wherein an equalization parameter of the receiver is adjusted by an output of a test pattern level detection means.

    20. Item 11. The transceiver circuit according to Item 10, wherein the transceiver circuit sends a boundary signal to be determined to be at the boundary between "0" and "1" of data by the driver to a receiver of another transceiver circuit. Boundary offset for receiving a boundary signal transmitted from a transmission means and a driver of another transceiver circuit by the receiver and searching for a boundary offset where the determination result of the determination circuit is a boundary between data “0” and “1” A transceiver circuit, wherein the receiver is zero-adjusted by applying the boundary offset to the receiver when receiving a normal input signal.

    21. Item 11. The transceiver circuit according to Item 10, wherein the transceiver circuit transmits a test pattern predetermined by the driver to a receiver of another transceiver circuit, and a test transmitted from the driver of the other transceiver circuit. A reception timing change test pattern level detection means for detecting a level of the test pattern by receiving a pattern while sequentially changing the reception timing at the receiver; and a parameter of the transceiver circuit by an output of the reception timing change test pattern level detection means A transceiver circuit comprising: an arithmetic circuit for adjusting

22. A signal transmission system comprising a first transceiver circuit, a second transceiver circuit, and a signal transmission path connecting the first and second transceiver circuits,
Each transceiver circuit includes a receiver that receives an input signal and a driver that outputs a signal, and the receiver is provided with offset applying means for providing a known offset to the input signal, and the offset is provided. A signal transmission system comprising: a determination circuit that compares an input signal with a reference voltage; and a level of the input signal is confirmed from a result of the determination circuit and the known offset.

    23. 23. The signal transmission system according to item 22, wherein the offset applying means includes offset level control means for controlling the level of the offset by a digital signal.

    24. 24. The signal transmission system according to item 23, wherein the receiver further increases or decreases the offset level by the offset level control means, and searches for the input signal by searching for an offset level at which a result of the determination circuit changes. A signal transmission system comprising input signal level detecting means for detecting the level of the signal.

    25. 25. The signal transmission system according to item 24, wherein the receiver further includes timing control means for controlling the determination timing by the determination circuit to change relative to the internal clock of the receiver, and is input from the outside. The predetermined test pattern is determined at the output timing of the timing control means, the offset level is adjusted, and the input signal level detection means acquires information on the input signal. Signal transmission system.

    26. Item 23. The signal transmission system according to Item 22, wherein the offset applying unit is configured to pass a constant current through a termination resistor provided in parallel with the input terminal of the receiver.

    27. Item 23. The signal transmission system according to Item 22, wherein the offset applying means includes a plurality of capacitors and switches, and the offset level is changed by changing a precharge voltage of each capacitor. Signal transmission system.

    28. Item 23. The signal transmission system according to Item 22, wherein the offset applying unit changes the level of the offset by flowing a constant current into an internal node of the receiver.

    29. Item 23. The signal transmission system according to Item 22, wherein the offset applying unit changes the level of the offset by flowing a constant current into an internal node of the receiver.

    30. 30. The signal transmission system according to any one of Items 22 to 29, wherein the waveform of the input signal obtained from the result of the determination circuit and the known offset is used to determine the signal quality of the received input signal. A signal transmission system characterized in that diagnosis or characteristic adjustment of the receiver or driver is performed.

    31. Item 22. The signal transmission system according to Item 22, wherein a predetermined test pattern is transmitted from a driver of the first transceiver circuit, and the test pattern is determined at a predetermined timing by a receiver of the second transceiver circuit. A signal transmission system comprising: adjusting an offset level in the second transceiver circuit to detect the level of the test pattern; and adjusting receiver equalization parameters in the second transceiver circuit.

    32. 23. The signal transmission system according to item 22, wherein a boundary signal to be determined to be at a boundary between “0” and “1” of data by the driver of the first transceiver circuit is sent to the receiver of the second transceiver circuit. The boundary signal is received by the receiver of the second transceiver circuit, and the boundary offset where the determination result of the determination circuit in the receiver becomes the boundary between data “0” and “1” is searched, and the boundary offset Is provided to the receiver of the second transceiver circuit when receiving a normal input signal, thereby performing zero adjustment of the receiver.

    33. 23. The signal transmission system according to item 22, wherein a test pattern predetermined by a driver of the first transceiver circuit is sent to a receiver of the first transceiver circuit, and the test pattern is received by a receiver of the second transceiver circuit. The transceiver circuit is characterized by detecting the level of the test pattern by sequentially changing the reception timing in step (b) and adjusting the parameter of the second transceiver circuit.

34. A receiver comprising a plurality of signal lines and a capacity network having a capacity connected to the signal lines and a switch for controlling connection of the capacity,
Common mode voltage removing means for connecting at least one of the capacitance nodes including the common mode voltage component of the plurality of signal lines to a node maintained at a specific voltage value to remove the common mode voltage of the signal lines. A receiver comprising:

35. A receiver comprising a plurality of signal lines and a capacity network having a capacity connected to the signal lines and a switch for controlling connection of the capacity,
Common mode voltage removal for removing the common mode voltage of the signal line by connecting at least one of the capacitance nodes including the common mode voltage component of the plurality of signal lines to a node precharged to a specific voltage value. A receiver comprising means.

    36. 36. In the receiver according to item 34 or 35, the common mode voltage removing means includes a corresponding voltage generating circuit for generating a voltage value corresponding to the common mode voltage, and one end of the capacitor by an output voltage of the corresponding voltage generating circuit. And a capacity charging means for charging.

    37. 36. In the receiver according to item 34 or 35, the common mode voltage removing means includes a differential voltage capacity charging means for charging an input capacity with a differential voltage of the plurality of signal lines, and a terminal of the input capacity following the charging period. And a connection control means for connecting to the input terminal of the determination circuit.

    38. Item 37. The receiver according to Item 37, wherein the differential voltage capacity charging unit simultaneously performs removal of the common mode voltage and differential single-ended conversion by connecting one node of the capacitor to a constant voltage. Receiver characterized by that.

    39. 38. The receiver according to item 37, wherein the differential voltage capacity charging means inputs two nodes of the capacity to a single-ended amplifier, respectively.

    40. 36. The receiver according to item 34 or 35, wherein the capacity network realizes PRD.

    41. 36. The receiver of item 34 or 35, wherein the receiver provides feedback to remove the common mode voltage to the outputs of two single-ended amplifiers that receive signals from the capacitive network. Featured receiver.

    42. 36. The receiver according to item 34 or 35, wherein the capacitance network has two or more coupling capacitances, and the coupling capacitances are connected in parallel in the precharge period and connected in series in the determination period. And receiver.

  FIG. 4 is a block circuit diagram showing the basic configuration of the receiver according to the first embodiment of the present invention, and FIG. 5 is a diagram for explaining the operation of the receiver of FIG.

  As shown in FIG. 4, the first embodiment of the present invention is provided with means for giving a known offset voltage (Voff +, Voff−) to the receiver 3. The waveform to which the offset is applied is compared with a reference voltage by the determination circuit of the receiver 3, and is converted into a digital signal ("0" or "1") according to the result. Specifically, if the input is larger than the reference voltage, the determination circuit outputs “1”, and if smaller, outputs “0”.

  That is, as shown in FIG. 5, when the voltage level of the differential (complementary) input signal is V +, V−, the execution input Va is Va = {(V +) − (V −)} + { (Voff +) − (Voff−)} and the inversion of the output “0” or “1” by the determination circuit is when the sign of the execution input Va is inverted. Therefore, the boundary at which “0” and “1” of the determination output of the receiver are inverted is the case of {(V +) − (V −)} = − {(Voff +) − (Voff−)}. When {(V +) − (V −)}> − {(Voff +) − (Voff−)}, the determination output of the receiver is “1”, conversely, {(V +) − In the case of (V −)} <− {(Voff +) − (Voff−)}, the determination output of the receiver is “0”.

  In the receiver according to the first embodiment of the present invention, for example, while the value of the offset voltage (Voff +, Voff−) is digitally controlled by the D / A converter, the determination is repeated with respect to the periodic test pattern. The analog value of the input signal (V +, V-) can be known from the resolution of the D / A converter by searching for a boundary where the output of the decision circuit inverts between “0” and “1”. it can. Furthermore, the analog value of the signal input to the receiver can be accurately known by performing the determination while gradually shifting the determination timing relative to the test pattern.

  In other words, the signal at the fixed determination timing is obtained by searching for a boundary where the output of the determination circuit is inverted between “0” and “1” by sequentially changing the offset voltage with the determination timing fixed. Further, the level of the signal at each determination timing (that is, an analog signal waveform) can be confirmed by sequentially changing the determination timing and repeating the same processing.

  Thus, according to the first aspect of the present invention, first, analog values of signals input to the receiver can be collected, and signal transmission at high speed (for example, about several Gbps) is performed. Even in this case, it is possible to evaluate the transmission waveform of the signal and the quality of the waveform in a state where the chip is mounted. Further, according to the first embodiment of the present invention, it is possible to adjust transceiver parameters (e.g., parameters used for equalization) based on analog data, and further, receivers due to variations in transistor threshold voltage (Vth). The input offset voltage can be adjusted.

  Therefore, according to the first aspect of the present invention, it is possible to accurately know the analog value of the signal waveform input to the input terminal of the receiver using the receiver that performs digital operation, and to evaluate and diagnose the transceiver circuit, and It is possible to adjust parameters and the like. As a result, the cost required for the test can be reduced, and further, a high-speed signal transmission transceiver excellent in performance can be realized.

  ADVANTAGE OF THE INVENTION According to this invention, the receiver which can remove a big common mode voltage in the circuit which performs signal transmission can be provided.

  Hereinafter, embodiments of a receiver according to the present invention will be described in detail with reference to the drawings.

  FIG. 6 is a block circuit diagram schematically showing an example of a signal transmission system to which the present invention is applied. In FIG. 6, reference numeral 1 is a driver (differential driver), 21 and 22 are signal transmission paths (cables), 3 is a receiver, and 41 and 42 are termination resistors.

  For example, the driver 1 sends the NRZ signal to the signal transmission paths (cables) 21 and 22 at a data transfer rate of 1.25 Gbps. The signal output from the driver 1 is terminated by the termination resistors 41 and 42 through the cables 21 and 22 and then input to the input terminals (V +, V−) of the receiver 3.

  FIG. 7 is a circuit diagram showing a receiver as a first embodiment of the present invention, and shows the receiver 3 in FIG. In FIG. 7, reference numerals 31 and 32 are P-channel MOS transistors (PMOS transistors), 33 to 38 are N-channel MOS transistors (NMOS transistors), and 39 is a determination circuit (latch circuit). Reference symbol Vcn indicates a bias voltage applied to the gates of the transistors 35 and 38.

  As shown in FIG. 7, the receiver 3 applies differential pair transistors 33 and 34 for applying input signals (input voltages V +, V−) and offset signals (offset voltages Voff +, Voff−). And a determination circuit (regenerative latch circuit) 39 for determining the output of the preamplifier. That is, a positive logic input signal V + is supplied to the gate of one transistor 33 of the first differential pair, and a negative logic input signal V- is supplied to the gate of the other transistor 34. Further, a positive logic offset signal Voff + is supplied to the gate of one transistor 36 of the second differential pair, and a negative logic offset signal Voff− is supplied to the gate of the other transistor 37. Then, the output of the preamplifier having the first and second differential pairs is taken in by the regenerative latch circuit (determination circuit) 39 by the latch signal LAT, and the output “0” or “1” is determined. Here, the voltage level of the offset signal (offset differential voltage Voff +, Voff−) given to the second differential pair (offset voltage application differential pair) is known.

  According to the first embodiment, whether or not the received voltage (input voltage V +, V−) at the timing when the determination circuit 39 operates exceeds the reference voltage (offset voltage Voff +, Voff−), more precisely, It can be determined whether {(V +)-(V-)} exceeds-{(Voff +)-(Voff-)}, and the quality of the signal transmission system from the driver to the receiver can be evaluated. it can. In addition, since the determination result (determination output) is output as digital data of “0” or “1”, it can be used for evaluation, characteristic adjustment, etc. by transferring it to the logic circuit or processor side that controls the transceiver. Is possible. For example, when there is a malfunction in the device, it is possible to know whether the received waveform is above the reference value with respect to the test pattern in the state where the chip and cable are mounted according to the first embodiment. It becomes possible to provide.

  FIG. 8 is a block circuit diagram showing a receiver as a second embodiment of the present invention. In FIG. 8, reference numeral 4 denotes a D / A converter that outputs an offset code after digital / analog conversion.

  As shown in FIG. 8, the second embodiment is provided with means for increasing or decreasing the offset level (offset value: offset voltage) compared to the first embodiment shown in FIG. Specifically, for example, while applying the test pattern periodically, the offset value is changed step by step from the minimum value to the maximum value by using the D / A converter 5, and the determination values “0” and “1” are changed. Observe where and will switch. As a result, the signal value (V +, V−) applied to the receiver (determination circuit) 3 can be known with the resolution of the D / A converter 5, and the analog received signal value (input signal level) can be obtained. For example, it can be known in a state where an LSI is mounted on a printed circuit board. Here, the offset code given to the D / A converter 5 can be 6 bits or 7 bits, for example.

FIG. 9 is a circuit diagram showing an example of the D / A converter 5 in the receiver of FIG.
As shown in FIG. 9, the D / A converter 5 includes a plurality of PMOS transistors 511 to 513, 521 to 523,..., 5n1 to 5n3 and load resistors 501 and 502, for example. A bias voltage Vcp is applied to the gates of the transistors 511, 521,..., 5n1, and offset codes b1, b2,. , Bn and / b1, / b2, ..., / bn are supplied. Then, the currents flowing through the transistors 512, 522,..., 5n2 and 513, 523,..., 5n3 are collected and flow to the load end resistors 502 and 501, and the offset voltages Voff− and Voff + are output. That is, the D / A converter 5 generates offset voltages Voff + and Voff− at levels according to the offset codes (b1, / b1; b2, / b2;...; Bn, / bn).

  FIG. 10 is a block circuit diagram showing a receiver as a third embodiment of the present invention. In FIG. 10, reference numeral 6 indicates a phase interpolator, and 7 indicates a controller.

  As is apparent from the comparison between FIG. 8 and FIG. 10, in the third embodiment, in addition to the second embodiment described above, the reception timing (determination timing) is set relatively to the reception signal (input signal). A means for shifting (phase interpolator 6) is provided. Here, as the phase interpolator 6, various known configurations can be applied.

  That is, the receiver 3 (determination circuit 39) operates at the rising edge of the timing pulse LAT from the phase interpolator 6, for example. The phase code given to the phase interpolator 6 is controlled by, for example, a 6-bit digital signal from a clock recovery circuit (not shown) when receiving a normal signal, but is given from a separate control circuit (controller 7) during waveform diagnosis. It is controlled by the signal. The controller 7 not only generates the offset code given to the D / A converter 5 upon receiving the output of the receiver 3, but also generates the phase code (eg 6-bit digital signal) given to the phase interpolator 6. It is supposed to be.

  According to the third embodiment, not only the level of the received signal (input signal) but also the waveform of the received signal can be obtained by adding a few circuits (providing only a few additional circuits to the timing generation circuit). It can be acquired with high temporal resolution. Specifically, for example, when the clock frequency of the phase interpolator 6 is 625 MHz (one cycle is 1.6 ns) and the phase code is a 6-bit signal, the waveform of the received signal can be obtained with a time resolution of 25 ps. Note that the level of the received signal is defined by the resolution of the D / A converter 5 (for example, a 6-bit or 7-bit offset code), as in the second embodiment described above.

  FIG. 11 is a block circuit diagram showing a receiver as a fourth embodiment of the present invention. In FIG. 11, reference numeral 300 indicates a receiver (differential receiver), and 500 indicates a current D / A converter.

  As shown in FIG. 11, in the fourth embodiment, the receiver 300 is a general differential receiver, and an offset is given in the previous stage (input stage) of the receiver 300. That is, a D / A converter 500 whose current value is controlled by an offset code is provided for the terminating resistors 41 and 42 provided in the signal transmission lines 21 and 22, and the D / A converter 500 is fixed at the input terminal of the receiver 300. By injecting a current from a current source, an offset voltage (Voff +, Voff−) is applied to the received signal (V +, V−) at the input stage of the receiver 300. Here, the D / A converter 500 is controlled by an offset code of about 6 bits, for example.

  Thus, according to the fourth embodiment, if the receiver is terminated on the receiving side, an offset (Voff +, Voff-) can be given without depending on the circuit system of the receiver. Furthermore, it is not necessary to add an extra circuit to the internal node of the receiver 300, and an additional circuit is provided on the input side of low impedance (because the terminating resistor is in parallel), so that the high speed of the circuit is not impaired. There are also advantages. In the fourth embodiment, a regenerative latch circuit is used as the receiver 300.

  FIG. 12 is a block circuit diagram showing a receiver as a fifth embodiment of the present invention. In FIG. 12, reference numerals 311 and 312 denote termination resistors, 313 to 316 denote capacitors, and 321 to 326 denote switches.

  In the fifth embodiment, first, in the precharge period, the switches 321 and 324 are turned off, the switches 322, 323, 325, and 326 are turned on, and the capacitors 314 and 315 are supplied with the precharge voltage Vpr and the reference voltage Vo (Vo Charge is stored by applying a voltage difference from-, Vo +). Next, when the received signal is determined by the regenerative latch circuit 300, as shown in FIG. 12, the switches 321 and 324 are turned on, the switches 322, 323, 325, and 326 are turned off, and the capacitor 314 , 315 and capacitors 313, 316 are connected in parallel.

  That is, the receiver (regenerative latch circuit 300) is coupled to the input by a capacitor, and the input node of the latch circuit 300 is precharged to the precharge voltage Vpr during the precharge period. On the other hand, the node on the signal line side across the capacitors 314 and 315 is supplied with the reference voltage Vo (Vo−, Vo +) by the switches 322 and 323 in the on state. Here, the offset voltage (Voff +, Voff−) can be adjusted by controlling the value of the precharge voltage Vpr by, for example, a 6-bit D / A converter. This is because the voltage across the capacitors 314 and 315 is (Vpr−Vo), and this voltage is applied to the input during the determination period.

  The fifth embodiment can be applied to any circuit type receiver as long as the input terminal is connected to the gate electrode. Further, since the mechanism for applying the offset voltage is essentially linear, there is an advantage that distortion due to non-linearity does not occur.

FIG. 13 is a block circuit diagram showing a receiver as a sixth embodiment of the present invention.
As shown in FIG. 13, in the sixth embodiment, the input stage of the determination circuit (regenerative latch circuit 39) is a differential pair having a constant tail current. That is, in addition to the original input differential pair (transistors 323 and 324), constant current circuits (transistors 327 and 328) for supplying a constant differential current (Io +, Io-) are provided. These currents flow into the PMOS transistors (load devices) 321 and 322, and this output is determined by a regenerative latch circuit (determination circuit). The currents Io + and Io− flowing through the transistors 326 and 329 connected to the transistors 327 and 328 in a current mirror are changed in value (offset level) by the D / A converter (5) as shown in FIG. Can be made.

  The sixth embodiment can be applied to higher-speed signal transmission because the offset is given not by voltage but by current as compared with the fifth embodiment described above. Furthermore, since the bias can be changed with a smaller control current, current consumption can be reduced.

  FIG. 14 is a block circuit diagram showing a receiver as a seventh embodiment of the present invention. In FIG. 14, reference numerals 331 and 332 denote termination resistors, 333, 334, 341 to 343, and 351 to 353 denote capacitors, and 335 to 340, 344 to 346, and 354 to 356 denote switches. Here, the capacitors 341 to 343 and 351 to 353 and the switches 344 to 346 and 354 to 356 are for controlling the equalization parameters. In FIG. is not.

  In the seventh embodiment, first, in the precharge period, as shown in FIG. 14, the switches 335 to 338 are turned on, the switches 339 and 340 are turned off, and the capacitors 333 and 334 have the reference voltage Vo (Vo Charge is stored by applying a voltage difference between-and Vo +) and the reference voltage Vref. Next, when the reception signal is determined by the receiver (regenerative latch circuit 300), the switches 335 to 338 are turned off and the switches 339 and 340 are turned on.

  In other words, in the seventh embodiment, in addition to the fifth embodiment described above, the input coupling capacitance of the receiver 300 performs PRD (Partial Response Detection). This PRD equalizes the waveform of the input signal, and the equalization parameter is controlled by switching the capacitance value. That is, the switches 344 to 346 and 354 to 356 are determined to be on / off so that, for example, the input signal can be received with high sensitivity at the time of initialization such as when the power is turned on. The switch state is maintained regardless of the etc. That is, the seventh embodiment receives a continuous signal of 2 bits, and selects equalization parameters so that the dependency of the reception level of the subsequent signal on the previous bit is minimized (switches 344 to 346). , 354 to 356 are controlled) to enable optimum equalization.

  FIG. 15 is a block circuit diagram showing a signal transmission system as an eighth embodiment of the present invention. Here, the termination voltage Vtt applied to the termination resistors 41 and 42 is an optimum voltage for the receiver 3.

  In the eighth embodiment, the driver 1 has a function of outputting a signal in which the voltage difference between two signal pairs (complementary signals V +, V-) becomes zero by setting the output stage to a high impedance state. That is, as shown in FIG. 15, the gates of the PMOS transistor 11 and the NMOS transistor 12 provided between the inverters 13 and 14 in the output stage of the driver 1 and the high potential and low potential power supply lines (Vdd, Vss). Are applied with signals Hiz (high level “H”) and / Hiz (low level “L”) to prevent current from flowing through the inverters 13 and 14, respectively. ) Is operated to obtain an offset voltage (Voff +, Voff−) at which the determination result (determination output) switches to “0” or “1”.

  Then, by using the offset voltage at the time of normal signal reception, the determination circuit can determine the reception signal in a state where the input offset is compensated. In the eighth embodiment, even if an offset voltage is generated at the input of the determination circuit due to variations in transistor characteristics, it can be compensated for, so that highly sensitive reception is possible.

  FIG. 16 is a block circuit diagram showing a receiver as a ninth embodiment of the present invention. In FIG. 16, reference numeral 8 indicates the PRD capacity net described with reference to FIG.

  In the ninth embodiment, a test pattern (for example, a data pattern such as “1000”) is periodically generated from a driver of another transceiver circuit during a period for adjusting the characteristics of the transceiver (for example, an initialization period at power-on). The offset voltage (Voff +, Voff-) is changed via the D / A converter 5 and the judgment timing is sequentially changed via the phase interpolator 6, and the test pattern is received by the receiver 3 (determination circuit). And receive the analog value of the received waveform. These values are sent to the controller (processor for control) 70, and the controller 70 determines the optimum value of the offset voltage (optimum offset code), the optimum value of the reception timing (optimum phase code) from the received data, and Then, an equalization parameter (optimum capacity code) that minimizes intersymbol interference is calculated, and values of these receiver control codes are set in the receiver. Here, the capacity code supplied to the PRD capacity net 8 is for controlling the on / off states of the switches 344 to 346 and 354 to 356 in FIG. The controller 70 that has acquired the analog value of the received waveform can also perform feedback control so as to adjust, for example, the amplitude level of the signal with respect to the driver of another transceiver circuit that has transmitted the test pattern.

  As described above, according to the ninth embodiment, the input signal can be received using the offset voltage and the reception timing that maximize the received signal and the equalization parameter that minimizes the intersymbol interference. Sensitivity signal reception becomes possible.

  As described above, according to the first to ninth embodiments (first embodiment) of the present invention, the quality of the signal waveform can be evaluated in the mounted state, and the equalization parameters can be optimized in the mounted state. Therefore, it is possible to provide a highly sensitive receiver, transceiver circuit, and signal transmission system that are excellent in maintainability.

  By the way, as described above, in signal transmission between LSIs, boards, or enclosures, when the transmission distance is relatively long, differential signal transmission is usually used. In the conventional differential receiver as shown in FIG. 3, the compatible common mode voltage range cannot be increased so much.

  The receiver circuit described below can remove a large common mode voltage.

  FIG. 17 is a diagram (part 1) for explaining the principle of the receiver according to the second embodiment of the present invention. FIG. 17 (a) shows the signal lines SL0 to SLn, and FIG. The capacity network for the period is shown, and FIG. 17C shows the capacity network for the determination period. Here, for example, the signal line SL0 is common, and a signal is transmitted between the common signal line SL0 and each of the signal lines SL1 to SLn. Reference numerals V0 to Vn indicate signal levels (voltages) of the signal lines SL0 to SLn, and C0, C1, C2,.

  First, as shown in FIG. 17B, each node (n + 1 nodes) of the capacity network is charged to voltages V0, V1,..., Vn, respectively, in the sample period.

  Next, as shown in FIG. 17C, when the node to which the voltage V0 is applied is connected to the zero potential in the determination period, the voltages of the other nodes are V1-V0, V2-V0,. -V0. That is, the voltage V0 is subtracted from all node voltages.

  Here, if the voltage V0 is a common mode voltage, the common mode voltage is subtracted from the voltages of other nodes. Therefore, if this voltage is connected to the input of the receiver, a voltage (signal) from which the common mode voltage is subtracted is input to the receiver, and the common mode voltage can be removed.

  FIG. 18 is a diagram (part 2) for explaining the principle of the receiver according to the second embodiment of the present invention. FIG. 18 (a) shows the connection relationship between the capacitor and the receiver in the sample period, and FIG. (B) has shown the connection relation of the capacity | capacitance and a receiver in a determination period.

  As shown in FIG. 18A, in the sample period, the capacitors C1, C2, C3,... Are connected between the signal line SL0 and SL1, SL2, SL3,. A difference voltage (V1-V0, V2-V0, V3-V0,...) From the voltage V0 is applied. At this time, the inputs of the determination circuits DT1 to DTn are precharged to the precharge voltage Vpr.

  As shown in FIG. 18B, in the determination period, the capacitors C1, C2, C3,... Are disconnected from the signal lines SL0 to SLn and connected to the inputs of the determination circuits DT1 to DTn, respectively.

  That is, in FIG. 18, instead of grounding the node (V0) of the reference signal line SL0 to zero potential in FIG. 17, the difference voltage between the reference signal line SL0 and each of the signal lines SL1 to SLn is changed between both ends of the capacitors C1 to Cn. The common mode voltage is removed by connecting these capacitors to the input nodes of the receivers (DT1 to DTn) precharged at a constant potential.

  The receivers described with reference to FIGS. 17 and 18 both use a capacitance network having a plurality of switches and capacitors for connecting an input signal and an input terminal of the receiver, and a common node is connected to one node of the capacitance network. Configure so that the mode voltage is generated, and connect only the differential voltage from which the common mode voltage is removed by connecting the node to a constant potential or by connecting it to a node precharged to a constant potential. It is supposed to be.

  Thus, according to the second embodiment of the present invention, the common mode voltage removing means is realized by switching the passive element (capacitance). Therefore, even if the transistor characteristics vary, the common mode voltage removing characteristics can be obtained. There is no impact. Furthermore, even if the common mode noise changes greatly, its removal performance is not affected, and the common mode voltage hardly propagates to the subsequent receiver, so that a receiver with high common mode noise tolerance can be realized.

  FIG. 19 is a circuit diagram (sample period) showing a receiver as a tenth embodiment of the present invention, and FIG. 20 is a circuit diagram (determination period) showing a receiver as a tenth embodiment of the present invention. 19 and 20, reference numeral 40 denotes a receiver (regenerative latch circuit), R11 and R12 denote termination resistors, C11 and C12 denote coupling capacitors, and SW11 to SW16 denote switches. Reference numerals SL0 and SL1 indicate differential (complementary) signal lines.

  As shown in FIG. 19, the regenerative latch circuit 40 includes PMOS transistors 411 to 416 and NMOS transistors 421 to 425, and the latch signal LAT is supplied to the gates of the transistors 411, 416, and 423. That is, when the latch signal LAT is at the low level “L” (precharge period), the NMOS transistor 423 is turned off and the PMOS transistors 411 and 416 are turned on, and the input of the latch circuit 40 (the gates of the transistors 422 and 425). Input) is precharged to the precharge voltage Vpr. When the latch signal LAT becomes a high level “H”, the precharge voltage Vpr is cut off, the NMOS transistor 423 is turned on, and the input signal is captured.

  First, as shown in FIG. 19, in the sample period (precharge period), the switches SW11 to SW13 are turned on and the switches SW14 to SW16 are turned off, and the coupling capacitors C11 and C12 are connected to the signal lines SL0 and SL1. To do. The other nodes of the coupling capacitors C11 and C12 are connected to a node NC that becomes a common mode potential. This node NC is connected to the middle point where the terminating resistors R11 and R12 are connected by the switch SW12 in the on state. As described above, in the precharge period (sample period), the input node of the latch circuit 40 is precharged to the precharge voltage Vpr.

  Next, as shown in FIG. 20, in the determination period, the switches SW11 to SW13 are turned off and the switches SW14 to SW16 are turned on, so that the coupling capacitors C11 and C12 are connected to the signal lines SL0 and SL1 and the termination resistors R11 and R12. And is connected to the input node of the latch circuit 40 and the reference voltage Vref. As a result, the common mode voltage in the signal lines SL0 and SL1 is completely removed, so that the common mode voltage does not appear at the input of the latch circuit 40.

  That is, in the precharge period, the two capacitors C11 and C12 are charged between the common mode voltage node NC and the signal lines SL0 and SL1, respectively, and the node NC to which the common mode voltage is applied in the determination period is The node connected to the reference voltage Vref and to which the signal line voltages (V0, V1) are applied is connected to the input of the latch circuit (differential receiver) 40. In this way, the common mode voltage at the input of the latch circuit 40 can be removed.

  In this embodiment (the same applies to each of the following embodiments), the common mode voltage removing means is realized by switching the passive element (capacitance). Therefore, even if the transistor characteristics vary, the removal characteristics are not affected. Further, even if the common mode noise changes greatly, the removal performance is not affected, and the common mode voltage hardly propagates to the subsequent circuit. As a result, a receiver having high common mode noise tolerance can be realized.

FIG. 21 is a circuit diagram showing an example of the switch in FIGS. 19 and 20.
As shown in FIG. 21, each of the switches SW (SW11 to SW16) is constituted by, for example, a transfer gate composed of a PMOS transistor 401 and an NMOS transistor 402, and the control signal SS is inverted directly and by an inverter 403 so that the transistors 402 and 403 is supplied to the gate. That is, the transfer gate is turned on when the control signal SS is at a high level “H”, and conversely, is turned off when the control signal SS is at a low level “L”.

  FIG. 22 is a circuit diagram (sample period) showing a receiver as an eleventh embodiment of the present invention, and FIG. 23 is a circuit diagram (determination period) showing a receiver as the eleventh embodiment of the present invention.

  First, as shown in FIG. 22, in the sample period (precharge period), the switches SW21, SW24 are turned off and the switches SW22, SW23, SW25, SW26 are turned on. That is, a common mode voltage is applied to each of the coupling capacitors C21 and C22 via the switches (SW22, SW23) and the termination resistors (R11, R12), and each other node is connected to the latch circuit 40. The input node is precharged to the precharge voltage Vpr. At this time, as the common mode voltage, the midpoint voltage of the termination resistors R11 and R12 is used.

  Next, as shown in FIG. 23, in the determination period, the switches SW21, SW24 are turned on and the switches SW22, SW23, SW25, SW26 are turned off. That is, in the coupling capacitors C21 and C22, one node to which the common mode voltage is applied is connected to the signal lines SL0 and SL1 via the switches (SW21 and SW22), and the precharge switches (SW25 and SW26). Is turned off.

  Thus, in the eleventh embodiment, when the precharge period ends and the input node of the latch circuit 40 is disconnected from the precharge voltage Vpr, the voltage at the input node is always constant (precharge voltage Vpr). The channel charge injected into the input node does not depend on the signal charge, and the signal determination can be performed with higher accuracy.

  FIG. 24 is a circuit diagram (sample period) showing a receiver as a twelfth embodiment of the present invention, and FIG. 25 is a circuit diagram (determination period) showing a receiver as a twelfth embodiment of the present invention. In the twelfth embodiment, the two coupling capacitors C11 and C12 in the tenth embodiment described with reference to FIGS. 19 and 20 are configured as one capacitor C30, and with reference to FIGS. 22 and 23. As in the eleventh embodiment described, the input node of the latch circuit 40 is precharged to the precharge voltage Vpr during the sample period (precharge period).

  That is, as shown in FIG. 24, in the sample period, the switches SW31, SW32, SW35, and SW36 are turned on and the switches SW33 and SW34 are turned off to connect both ends of the coupling capacitor C30 to the signal lines SL0 and SL1. . At this time, the input node of the latch circuit 40 is precharged to the precharge voltage Vpr.

  Next, as shown in FIG. 25, in the determination period, the switches SW31, SW32, SW35, and SW36 are turned off and the switches SW33 and SW34 are turned on to disconnect both ends of the coupling capacitor C30 from the signal lines SL0 and SL1. To the input node of the latch circuit 40.

  In the twelfth embodiment, the common mode voltage is removed using one coupling capacitor C30 (so-called flying capacitor), and the number of necessary capacitors and switches (switch transistors) is reduced. There is an advantage that you can.

  FIG. 26 is a circuit diagram (sample period) showing a receiver as a thirteenth embodiment of the present invention, and FIG. 27 is a circuit diagram (determination period) showing a receiver as the thirteenth embodiment of the present invention. In the thirteenth embodiment, in addition to the eleventh embodiment described with reference to FIGS. 22 and 23, two coupling capacitors are provided to constitute a PRD (Partial Response Detection). .

  First, as shown in FIG. 26, in the sample period, the switches SW42, SW43, SW45, and SW46 are turned on, the switches SW41 and SW44 are turned off, and the switch (SW42, SW43) is connected to one node of the coupling capacitors C42 and C43. A common mode voltage is applied through SW43) and termination resistors (R11, R12). The other node of the coupling capacitors C42 and C43 is precharged to the precharge voltage Vpr of the input node of the latch circuit 40. One end of the coupling capacitors C41 and C44 is always connected to the signal lines SL0 and SL1, and the other end is connected to the input node of the latch circuit 40.

  Next, as shown in FIG. 27, in the determination period, the switches SW42, SW43, SW45, and SW46 are turned off and the switches SW41 and SW44 are turned on so that the coupling capacitors C42 and C43 and the coupling capacitors C41 and C44 are connected. Connect each in parallel. At this time, the precharge switches (SW45, SW46) are turned off. Here, for example, in the conventional PRD, the node on the signal line side of the coupling capacitor is repeatedly charged to a constant voltage and connected to the signal line, but in the thirteenth embodiment, instead of the constant voltage, A common mode voltage is applied to the power source.

  According to the thirteenth embodiment, it is possible to remove the common mode voltage in the capacity network portion that realizes the PRD. Therefore, it is possible to simultaneously remove the intersymbol interference in addition to the removal of the common mode voltage, Even higher transmission rates can be realized.

  FIG. 28 is a circuit diagram (sample period) showing a receiver as a fourteenth embodiment of the present invention, and FIG. 29 is a circuit diagram (determination period) showing a receiver as a fourteenth embodiment of the present invention. In the fourteenth embodiment, the common mode voltage is removed and the conversion from the differential signal to the single-ended signal is simultaneously performed by the capacitance network.

  First, as shown in FIG. 28, in the sample period, the switches SW51, SW52, and SW55 are turned on and the switches SW53 and SW54 are turned off, and both ends of the coupling capacitor (flying capacitor) C50 are connected to the signal lines SL0 and SL1. Connecting. At this time, the input node of the CMOS inverter IN50 is precharged by connecting its input and output.

  Next, as shown in FIG. 29, in the determination period, the switches SW51, SW52, and SW55 are turned off and the switches SW53 and SW54 are turned on to disconnect both ends of the capacitor C50 from the signal lines SL0 and SL1. The reference voltage Vref is applied to the other input of the inverter IN50.

  As described above, the fourteenth embodiment performs not only the removal of the common mode voltage but also the differential / single-end conversion in the capacitor network. Therefore, if there is one high-speed and sensitive inverter (IN50), The first stage can be configured.

  30 is a circuit diagram (sample period) showing a receiver as a fifteenth embodiment of the present invention, and FIG. 31 is a circuit diagram (determination period) showing a receiver as a fifteenth embodiment of the present invention. The fifteenth embodiment differs from the fourteenth embodiment described above in that two inverters as the first stage of the receiver are used for each signal line.

  First, as shown in FIG. 30, in the sample period, the switches SW61, SW62, SW65, and SW66 are turned on and the switches SW63 and SW64 are turned off, and both ends of the coupling capacitor (flying capacitor) C60 are connected to the signal line SL0, Connect to SL1. At this time, the input nodes of the CMOS inverters IN61 and IN62 are precharged by connecting the input and the output, respectively.

  Next, as shown in FIG. 31, in the determination period, the switches SW61, SW62, SW65, and SW66 are turned off and the switches SW63 and SW64 are turned on, so that both ends of the capacitor C60 are disconnected from the signal lines SL0 and SL1. Each is connected to an input node of inverters IN61 and IN62.

  By the way, normally, even if the inverter is used as in the fifteenth embodiment, it does not operate as a differential amplifier. However, since the common mode voltage has already been removed by the capacitance network, the inverter operates as a differential amplifier as a whole. Become. The fifteenth embodiment is advantageous in that it is resistant to power supply fluctuations and operates stably because the circuit has high symmetry.

  FIG. 32 is a circuit diagram (sample period) showing a receiver as a sixteenth embodiment of the present invention, and FIG. 33 is a circuit diagram (determination period) showing a receiver as the sixteenth embodiment of the present invention. In the sixteenth embodiment, compared to the fifteenth embodiment shown in FIGS. 30 and 31, the common mode feedback circuit 600 is provided at the output of each of the inverters IN61 and IN62 so as to increase the common mode voltage rejection ratio. It has become. Note that the switching operation in the sample period and determination period of the receiver is the same as in the fifteenth embodiment.

  FIG. 34 is a circuit diagram showing an example of the common mode feedback circuit 600 in the sixteenth embodiment shown in FIGS.

  As shown in FIG. 34, the common mode feedback circuit 600 includes PMOS transistors 601 and 602, NMOS transistors 603 to 608, and inverters IN601 and IN602. The common mode feedback circuit 600 detects the common mode voltage of the outputs of the inverter pairs IN61 and IN62, and feeds back a constant current so that the difference between the common mode voltage and the reference voltage Vref (for example, Vdd / 2) becomes zero. It is like that.

  As described above, according to the sixteenth embodiment, not only a higher common-mode voltage removal performance can be obtained, but also the operation of the first-stage inverter (IN61, IN62) has a good symmetry, so that a stable operation is performed. Can do.

  FIG. 35 is a circuit diagram (sample period) showing a receiver as a seventeenth embodiment of the present invention, and FIG. 36 is a circuit diagram (determination period) showing a receiver as the seventeenth embodiment of the present invention. In the seventeenth embodiment, two flying capacitors (C71, C72) are provided, and in the precharge period, the two capacitors C71, C72 are connected in parallel between the signal lines SL0, SL1, and in the determination period, 2 Two capacitors C71 and C72 are connected in series and connected to the input node of the latch circuit 40.

  That is, as shown in FIG. 35, in the sample period (precharge period), the switches SW71 to SW74 are turned on and the switches SW75 to SW78 are turned off, so that the two capacitors C71 and C72 are connected between the signal lines SL0 and SL1. Connect in parallel.

  Next, as shown in FIG. 36, in the determination period, the switches SW71 to SW74 are turned off and the switches SW75 to SW78 are turned on, so that the two capacitors C71 and C72 are connected in series to the input node of the latch circuit 40. Connecting. Thereby, in the seventeenth embodiment, in addition to the removal of the common mode voltage, the signal voltage generated at the input of the latch circuit 40 can be doubled, and a receiver with higher sensitivity can be configured. .

  As described above, according to the tenth to seventeenth embodiments (second embodiment) of the present invention, for example, removal of common mode voltage or differential / single-end conversion using only passive elements, as well as a transformer, and The signal voltage can be increased, and many elements can be integrated in the CMOS circuit unlike the transformer. Therefore, it is possible to configure a receiver having high common mode noise resistance without external components.

It is a block diagram which shows an example of the conventional signal transmission system roughly. It is a wave form diagram which shows an example of the signal data transmitted by the signal transmission system of FIG. It is a circuit diagram which shows an example of the conventional receiver. It is a block circuit diagram which shows the principle structure of the receiver of the 1st form which concerns on this invention. FIG. 5 is a diagram for explaining the operation of the receiver of FIG. 4. 1 is a block circuit diagram schematically showing an example of a signal transmission system to which the present invention is applied. It is a circuit diagram which shows the receiver as 1st Example of this invention. It is a block circuit diagram which shows the receiver as 2nd Example of this invention. It is a circuit diagram which shows an example of the D / A converter in the receiver of FIG. It is a block circuit diagram which shows the receiver as 3rd Example of this invention. It is a block circuit diagram which shows the receiver as 4th Example of this invention. It is a block circuit diagram which shows the receiver as 5th Example of this invention. It is a block circuit diagram which shows the receiver as 6th Example of this invention. It is a block circuit diagram which shows the receiver as 7th Example of this invention. It is a block circuit diagram which shows the signal transmission system as 8th Example of this invention. It is a block circuit diagram which shows the receiver as 9th Example of this invention. It is FIG. (1) for demonstrating the principle of the receiver of the 2nd form which concerns on this invention. It is FIG. (2) for demonstrating the principle of the receiver of the 2nd form which concerns on this invention. It is a circuit diagram (sample period) which shows the receiver as 10th Example of this invention. It is a circuit diagram (determination period) which shows the receiver as 10th Example of this invention. It is a circuit diagram which shows an example of the switch in FIG. 19 and FIG. It is a circuit diagram (sample period) which shows the receiver as 11th Example of this invention. It is a circuit diagram (determination period) which shows the receiver as 11th Example of this invention. It is a circuit diagram (sample period) which shows the receiver as 12th Example of this invention. It is a circuit diagram (determination period) which shows the receiver as 12th Example of this invention. It is a circuit diagram (sample period) which shows the receiver as 13th Example of this invention. It is a circuit diagram (determination period) which shows the receiver as 13th Example of this invention. It is a circuit diagram (sample period) which shows the receiver as 14th Example of this invention. It is a circuit diagram (determination period) which shows the receiver as 14th Example of this invention. It is a circuit diagram (sample period) which shows the receiver as 15th Example of this invention. It is a circuit diagram (determination period) which shows the receiver as 15th Example of this invention. It is a circuit diagram (sample period) which shows the receiver as 16th Example of this invention. It is a circuit diagram (determination period) which shows the receiver as 16th Example of this invention. It is a circuit diagram which shows an example of the common mode feedback circuit in 16th Example shown in FIG. 32 and FIG. It is a circuit diagram (sample period) which shows the receiver as 17th Example of this invention. It is a circuit diagram (determination period) which shows the receiver as 17th Example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Driver 3,300 Receiver 5,500 D / A converter 6 Phase interpolator 7 Controller 21, 22 Signal transmission path 39 Judgment circuit 40 Latch circuit 41, 42 Termination resistance C (C11, C12, ...) Capacity LAT Latch signal R11 , R12 Termination resistors SL0, SL1,..., SLn Signal line SW (SW11, SW12,...) Switch (transfer gate)
V0, V1, ..., Vn Signal voltage V +, V- Input voltage Voff +, Voff- Offset voltage Vpr Precharge voltage Vref Reference voltage

Claims (8)

A plurality of signal lines; a plurality of signal voltage storage nodes respectively connected to the signal lines via a first switch; and a determination circuit connected to the signal voltage storage node via a second switch. Receiver,
The plurality of signal voltage storage nodes form a capacitance network by connecting a capacitor between each signal voltage storage node and a reference point, or between adjacent signal voltage storage nodes,
The operation of the receiver includes at least a sample period and a determination period, and the sample period and the determination period are alternately repeated,
Together in the sample period, and turns on the first switch to turn off the second switch and accumulates voltage by connecting the signal voltage storage node and said signal lines signal lines to the signal voltage storage node Applying a common mode voltage of the signal line to one end of the capacitor connected to the signal voltage storage node ;
In the determination period, the first switch is turned off and the second switch is turned on, the signal voltage storage node is connected to the determination circuit, and the voltage of the signal line stored in the signal voltage storage node To the determination circuit,
The receiver further includes:
Prior to the determination operation of the determination circuit, the common mode voltage elimination means for removing the common mode voltage with said signal line by connecting one end of the connected the capacitor to the signal voltage storage node to a specific voltage value A receiver characterized by comprising.   2. The receiver according to claim 1, wherein the common mode voltage removing means charges a one end of the capacitor with a corresponding voltage generating circuit that generates a voltage value corresponding to the common mode voltage, and an output voltage of the corresponding voltage generating circuit. And a capacity charging means.   2. The receiver according to claim 1, wherein the common mode voltage removing means determines a differential voltage capacity charging means for charging an input capacity with a differential voltage of the plurality of signal lines and a terminal of the input capacity following a charging period. And a connection control means for connecting to an input terminal of the circuit.   4. The receiver according to claim 3, wherein the differential voltage capacity charging unit performs removal of the common mode voltage and differential single-ended conversion simultaneously by connecting one end of the input capacity to a constant voltage value. A receiver characterized by that.   4. The receiver according to claim 3, wherein the differential voltage capacity charging means inputs each of two nodes of the capacity to a single-ended amplifier.   2. The receiver according to claim 1, wherein the capacity network is adapted to realize PRD.   2. The receiver of claim 1, wherein the receiver provides feedback to remove the common mode voltage to the outputs of two single-ended amplifiers that receive signals from the capacitive network. And receiver.   2. The receiver according to claim 1, wherein the capacitive network includes two or more coupling capacitors, and the coupling capacitors are connected in parallel in the sample period and connected in series in the determination period. And receiver.

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