JP4806719B2 - Differential comparator and test apparatus using the same - Google Patents

Description

  The present invention relates to a test technique for a semiconductor device, and relates to a technique for evaluating a differential signal output from a device under test.

  In recent years, a differential transmission system has been adopted in order to transmit video signals and audio signals at high speed between digital home appliances such as a television receiver and a DVD (Digital Versatile Disc) player. The differential transmission system will be applied to data transmission between devices such as a memory and a CPU (Central Processing Unit) in the near future.

  FIGS. 1A and 1B are block diagrams illustrating a part of the configuration of a test apparatus that tests a device having a differential interface. As shown in FIG. 1A, the test system 300 includes a pin electronics PE and a test fixture TF. The DUT 200 is mounted on a socket board (SB). A differential comparator 110 is provided in the pin electronics PE. The differential comparator 110, also called a timing comparator, receives the differential signal UP / UN output from the DUT 200, and determines the level of the differential signal UP / UN at a timing synchronized with the strobe signal. In this specification, “P / N” indicates a differential pair. On the test fixture TF, a differential signal line pair 50P / 50N (hereinafter also collectively referred to as a differential signal line 50) for connecting the socket board SB and the pin electronics PE is provided.

FIG. 1B is a circuit diagram showing a configuration of the differential comparator 110. The differential comparator 110 includes a subtractor 112, a first comparator 114, a second comparator 116, a first latch 118, and a second latch 120. The subtractor 112 generates a difference between the differential signals RP and RN, that is, a differential amplitude signal DA. The first comparator 114 compares the differential amplitude signal DA with the upper threshold voltage VOH. The first latch 118 latches the comparison result SH at the timing of the first strobe signal Hstb. The second comparator 116 compares the differential amplitude signal DA with the lower threshold voltage VOL. The second latch 120 latches the comparison result SL at the timing of the second strobe signal Lstb. The logical values of the data SH and SL indicating the comparison results are determined based on the following formulas (1a) and (1b).
SH = sign (VOH− (RP−RN)) (1a)
SL = sign ((RP-RN) -VOL) (1b)
here,
sign (x) is a function that takes 1 when x> 0 and 0 when x <0.

  Ideally, the length of the pair of differential signal lines 50 formed in the test fixture TF is uniform, but the length may be different in a practical test apparatus. 2A and 2B are operation waveform diagrams of the differential comparator 110 when the lengths of the differential lines are uniform and non-uniform, respectively. As shown in FIG. 2A, when the differential signal line 50 has a uniform length, the differential signal UP / UN output from the DUT 200 reaches the differential comparator 110 after receiving an equal delay tpd (see FIG. 2A). RP / RN).

  The vertical axis and the horizontal axis of the time chart shown in this specification are appropriately expanded or reduced for easy understanding, and each waveform shown is also simplified for easy understanding. . In the time chart, “X” indicates that the value is indefinite (INVALID).

  Pay attention to the transition from the low level to the high level of the differential amplitude signal (RP-RN). The outputs SH and SL of the two comparators 114 and 116 are latched at the timing of the strobe signals Hstb and Lstb having a time difference Tcr.

  Based on the combination of the values of the latched signals (fail signals) FH and FL, the transition time T from the low level (<VOL) to the high level (> VOH) of the differential amplitude signal (RP-RN) is a predetermined value. It is determined whether or not it is shorter than Tcr. In FIG. 2A, since both the signals FH and FL are at a low level, it is determined that T <Trc.

  FIG. 2B shows a case where the lengths of the differential signal lines 50P / 50N are different and the delay amount received by the differential signal UN is longer than the delay amount received by the differential signal UP by a predetermined time te. In this case, the waveform of the differential amplitude signal (RP-RN) that should have been correctly output from the DUT 200 is determined inside the test apparatus, and the fail signal FH is determined to be high level and the fail signal FL is determined to be low level. The transition time T is erroneously determined to be longer than the predetermined value Tcr.

  For example, if a variable-length coaxial tube (trombone) is provided on a path in series with the test fixture TF, the unbalance of the differential line can be canceled by changing the length of the coaxial tube. However, the variable-length coaxial tube is expensive and large, and it is impractical to provide each differential line in a test apparatus having hundreds to thousands of channels. Moreover, since the variable-length coaxial tube is a device in which the line length changes mechanically, it is difficult to adjust quickly.

  Although it is possible to form the entire differential signal line 50 using a line having excellent symmetry such as a twisted pair, in this case, the differential signal UP / UN from the DUT 200 has a phase difference or asymmetry. In some cases, they are averaged during propagation, making it difficult to evaluate the true waveform from the DUT 200 on the test equipment side. The original merit of the differential line that the waveform asymmetry is averaged in the middle of the transmission line is a demerit from the viewpoint of the test apparatus.

  In addition, Patent Documents 1 to 3 disclose techniques for dealing with unbalanced differential line lengths.

US Pat. No. 7,397,289 US Pat. No. 6,909,980B2 International Publication No. 05/081004 Pamphlet US Pat. No. 7,121,132

  The present invention has been made in such a situation, and one of the exemplary purposes thereof is to provide a differential comparator capable of eliminating the unbalance of the differential line by an approach different from the conventional one.

One embodiment of the present invention relates to a differential comparator that receives a differential signal output from a device under test and compares the differential amplitude of the differential signal with a predetermined threshold voltage. The differential comparator has a first input terminal to which one of differential signals is input, a second input terminal to which the other differential signal is input, and a signal input to the first input terminal at a designated timing. A first sample and hold circuit that samples and then holds the signal, and a second sample and hold circuit that samples and holds the signal input to the second input terminal at a specified timing, and the first and second sample and hold circuits. A comparison unit that compares a signal corresponding to a difference between output signals of the circuits with a predetermined threshold value, and a latch circuit that latches the output of the comparison unit are provided. The sampling timing of the first and second sample hold circuits and the latch timing of the latch circuit can be adjusted independently.
The device under test and the differential comparator are connected by a pair of differential lines composed of a positive line and a negative line, but the line lengths of the two differential lines may deviate. In this case, the variation in the line length of the differential line can be canceled by adjusting the sampling timing of the first sample hold circuit and the second sample hold circuit according to the deviation of the wiring length. This means that the raw differential signal output from the device under test can be properly evaluated.

In one aspect, the first sample-and-hold circuit is provided between a first capacitor having a fixed potential at one end, a second capacitor having a fixed potential at one end, and the other end of the first capacitor and the first input terminal. The first switch, a second switch provided between the other end of the first capacitor and the other end of the second capacitor, and a first reference in which a predetermined voltage is shifted by a potential difference corresponding to the threshold voltage A first voltage source for generating a voltage; and a third switch provided between the first voltage source and the other end of the second capacitor. The first sample and hold circuit executes the following steps 1 to 3 in synchronization with the input strobe signal.
Step 1. The second switch is turned off, and the first and third switches are turned on.
Step 2. The first switch and the third switch are turned off.
Step 3. The first and third switches are turned off and the second switch is turned on.
The second sample and hold circuit is provided between the third capacitor having a fixed potential at one end, the fourth capacitor having a fixed potential at one end, and the other end of the third capacitor and the second input terminal. A fourth switch, a fifth switch provided between the other end of the third capacitor and the other end of the fourth capacitor, and a second reference voltage obtained by shifting a predetermined voltage by a potential difference corresponding to the threshold voltage. A second voltage source to be generated; and a sixth switch provided between the second voltage source and the other end of the fourth capacitor.
The second sample hold circuit executes the following processing in synchronization with the strobe signal.
Step 1. The fifth switch is turned off, and the fourth and sixth switches are turned on.
Step 2. Turn off the fourth and sixth switches.
Step 3. The fourth and sixth switches are turned off and the fifth switch is turned on.
The comparison unit may compare the voltage generated in the second capacitor with the voltage generated in the fourth capacitor. The latch circuit may latch the output of the comparison unit at a timing according to the strobe signal.

  The differential comparator according to an aspect may further include a dummy comparator to which a potential generated in the first capacitor and a potential generated in the third capacitor are input.

The first sample and hold circuit includes a seventh switch having one end connected to the first input terminal, a fifth capacitor having one end connected to the other end of the seventh switch, and a predetermined voltage according to a threshold voltage. A third voltage source for generating a third reference voltage shifted by the potential difference, an eighth switch provided between one end of the fifth capacitor and the third voltage source, and a fourth voltage source for generating a fourth reference voltage And a ninth switch provided between the other end of the fifth capacitor and the fourth voltage source. The first sample and hold circuit executes the following steps 1 to 3 in synchronization with the strobe signal.
Step 1. The eighth switch is turned off and the seventh and ninth switches are turned on.
Step 2. The seventh and ninth switches are turned off.
Step 3. The seventh and ninth switches are turned off and the eighth switch is turned on.
The second sample and hold circuit includes a tenth switch having one end connected to the second input terminal, a sixth capacitor having one end connected to the other end of the tenth switch, and a predetermined voltage according to a threshold voltage. A fifth voltage source for generating a fifth reference voltage shifted by the potential difference, an eleventh switch provided between one end (first terminal) of the sixth capacitor and the fifth voltage source, and the other end of the sixth capacitor And a twelfth switch provided between the fourth voltage source and the fourth voltage source.
The second sample and hold circuit executes the following steps 1 to 3 in synchronization with the strobe signal.
Step 1. The eleventh switch is turned off and the tenth and twelfth switches are turned on.
Step 2. The tenth and twelfth switches are turned off.
Step 3. The tenth and twelfth switches are turned off and the eleventh switch is turned on.
The comparison unit may compare the voltage generated at the other end of the fifth capacitor with the voltage generated at the other end of the sixth capacitor. The latch circuit may latch the output of the comparison unit at a timing according to the strobe signal.

  In one embodiment, the first and second sample and hold circuits receive the potential of the other end of the fifth capacitor and the potential of the other end of the sixth capacitor instead of the ninth and twelfth switches and the fourth voltage source. A differential amplifier, a thirteenth switch provided between the non-inverting input terminal and the inverting output terminal of the differential amplifier, and a fourteenth switch provided between the inverting input terminal and the non-inverting output terminal of the differential amplifier; , May be included. The comparison unit may compare the potential of the inverting output terminal of the differential amplifier with the potential of the non-inverting output terminal.

In one aspect, the comparison unit replaces the signal according to the difference between the output signals of the first and second sample and hold circuits with a predetermined threshold value, and replaces the first and second sample and hold circuits with each other. The output signals may be compared.
In this case, variation in the wiring length of the differential line can be canceled, and the magnitude relationship of the differential signal can be appropriately evaluated.

  Another aspect of the present invention relates to a test apparatus. The test apparatus receives the differential signal output from the device under test, compares the differential amplitude of the differential signal with a predetermined upper threshold voltage, and the differential comparator according to any one of the above. One of the above-mentioned differential comparators that compares the differential amplitude of the dynamic signal with a predetermined lower threshold voltage.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other between methods and apparatuses are also effective as an aspect of the present invention.

  The differential comparator according to an aspect of the present invention can cancel the unbalance of the differential signal lines.

FIGS. 1A and 1B are block diagrams illustrating a part of the configuration of a test apparatus that tests a device having a differential interface. 2A and 2B are operation waveform diagrams of the differential comparator when the lengths of the differential lines are uniform and non-uniform. It is a circuit diagram which shows a part of structure of the test apparatus which concerns on embodiment. 4A and 4B are time charts illustrating the operation of the differential comparator of FIG. It is a circuit diagram which shows the 1st modification of the differential comparator which concerns on embodiment. 6A and 6B are time charts illustrating the operation of the differential comparator of FIG. It is a circuit diagram which shows the 2nd modification of the differential comparator which concerns on embodiment. 8A and 8B are time charts illustrating the operation of the differential comparator in FIG. It is a circuit diagram which shows the 3rd modification of the differential comparator which concerns on embodiment. It is a circuit diagram which shows the 4th modification of the differential comparator which concerns on embodiment. 11 is a time chart illustrating the operation of the differential comparator of FIG. 10.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

  In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are physically directly connected, or the member A and the member B are electrically connected. The case where it is indirectly connected through another member that does not affect the state is also included. Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical condition. It includes the case of being indirectly connected through another member that does not affect the connection state.

  FIG. 3 is a circuit diagram showing a part of the configuration of the test apparatus 100 according to the embodiment. The test apparatus 100 includes a pin electronics PE and a test fixture TF. The DUT 200 outputs a differential output signal (hereinafter simply referred to as a differential signal) UP / UN. The differential signal UP / UN is input to the first input terminal P1 and the second input terminal P2 of the pin electronics PE through the differential signal line 50P / 50N formed in the test fixture TF.

  The pin electronics PE includes an upper (High-side) differential comparator 10H and a lower (Low-side) differential comparator 10L. The pin electronics PE functions as a timing comparator that evaluates the level of the differential signal based on the timing of the input strobe signals φ0H and φ0L.

  The differential comparator 10H compares the differential amplitude component DA (= RP−RN) of the received differential signal RP / RN with a predetermined upper threshold voltage VOH. The differential comparator 10L compares the differential amplitude component (RP-RN) with a predetermined lower threshold voltage VOL.

  Since the differential comparators 10H and 10L have the same configuration, only the upper differential comparator 10H will be described below. The lower differential comparator 10L may read the suffix “H” of the reference numerals attached to each signal or member as “L”. Further, as shown in the lower right symbol in FIG. 3, the switch SW shown in this specification is turned off (cut off) and 1 (high level) when 0 (low level) is inputted as a control signal. It shall be turned on (conducted) when As such a switch, an analog switch such as a transfer gate can be preferably used.

    The differential comparator 10H includes a first input terminal P1, a second input terminal P2, a first sample hold circuit SH1, a second sample hold circuit SH2, a comparison unit 12, a latch circuit 18, a timing control unit 20, and a first termination amplifier TA1. And a second termination amplifier TA2.

  A non-inverted component (hereinafter referred to as a positive signal) RP, which is one of the received differential signals RP / RN, is input to the first input terminal P1. An inverted component (hereinafter referred to as a negative signal) RN, which is the other of the reception differential signals RP / RN, is input to the second input terminal P2.

  The first termination amplifier TA1 and the second termination amplifier TA2 are respectively connected to the first input terminal P1 and the second input terminal P2, and terminate the differential signal lines 50P / 50N viewed from the DUT 200. When bidirectional transmission is performed between the test apparatus 100 and the DUT 200, a driver that outputs data to the DUT 200 may be provided instead of the termination amplifier.

  The first sample hold circuit SH1 samples the positive signal RP input to the first input terminal P1 at a timing (for example, a positive edge timing) specified by the first control signal (hold signal) φ1HP, and then samples. The measured value RPH is held (hold mode). During a period before the sampling timing, the output signal HP of the first sample hold circuit SH1 coincides with the input positive signal RP (tracking mode).

  Similarly, the second sample hold circuit SH2 samples the negative signal RN input to the second input terminal P2 at a timing (for example, positive edge timing) designated by the second control signal (hold signal) φ1HN, Thereafter, the value RNH is held (hold mode). During a period before the sampling timing, the output signal HN of the second sample-and-hold circuit SH2 matches the input negative signal RN (tracking mode).

  That is, the first sample hold circuit SH1 and the second sample hold circuit SH2 have a function of outputting (tracking) the input signal as it is, sampling and holding it at a designated timing.

  In FIG. 3, the first sample hold circuit SH1 and the second sample hold circuit SH2 are in the tracking mode when the switch SW is turned on, and when the switch SW is turned off, the values are sampled and held. Each of the first sample hold circuit SH1 and the second sample hold circuit SH2 includes a switch SW and a capacitor C. However, their configurations are not limited to those shown in FIG. Other configurations not described may be used.

  The comparison unit 12 sets the difference between the output signal (hold positive signal) HP of the first sample hold circuit SH1 and the output signal (hold negative signal) HN of the second sample hold circuit SH2, that is, the differential amplitude (HP−HN). The corresponding differential amplitude signal DA is compared with the upper threshold voltage VOH. As a result of the comparison, a comparison signal SH that is low when (HP−HN)> VOH and becomes high when (HP−HN) <VOH is output.

  In FIG. 3, the comparison unit 12 includes a subtracter 14 and a comparator 16. The subtracter 14 subtracts the hold negative signal HN from the hold positive signal HP in an analog manner. For example, the subtractor 14 may be a subtractor including a combination of a resistor and an operational amplifier, or may be another type of subtracter. The comparator 16 compares the differential amplitude signal DA output from the subtractor 14 with the threshold voltage VOH. Note that the configuration of the comparison unit 12 is not limited to that shown in FIG.

  The latch circuit 18 latches the comparison signal SH at a timing (for example, positive edge) according to the third control signal φ3H. The latched fail signal FH is input to a determination circuit (not shown).

The timing control unit 20 generates control signals φ1HP, φ1HN, and φ3H based on a reference strobe signal φ0H input from the outside, and the first sample hold circuit SH1, the second sample hold circuit SH2, and the latch circuit 18 are generated. Control.
The transition timing of each control signal φ1HP, φ1HN, φ3H can be arbitrarily adjusted. That is, the sampling timing of the first sample hold circuit SH1 and the second sample hold circuit SH2 and the latch timing of the latch circuit 18 can be adjusted independently.

The timing control unit 20 includes a first delay circuit 22, a second delay circuit 24, a first AND gate 26, a first inverter 28, a second inverter 30, and a third delay circuit 32.
The first delay circuit 22 and the second delay circuit 24 branch the strobe signal φ0H, and give first and second variable delays VDHP and VDHN to the strobe signal φ0H, respectively. The first inverter 28 inverts the output signal of the corresponding first delay circuit 22 and outputs the inverted signal to the first sample hold circuit SH1 as the first control signal φ1HP. The second inverter 30 inverts the output signal of the corresponding second delay circuit 24 and outputs the inverted signal to the second sample and hold circuit SH2 as the second control signal φ1HN.

  The first AND gate 26 generates a logical product of the output signals of the first delay circuit 22 and the second delay circuit 24. The output signal of the first AND gate 26 changes following one of the first control signal φ1HP and the second control signal φ1HN that changes late. The third delay circuit 32 gives the third delay FD1 to the output signal of the first AND gate 26 and outputs it as the third control signal φ3H. Therefore, the latch circuit 18 latches the comparison signal SH from the comparison unit 12 after the third delay FD1 from the timing when both the first control signal φ1HP and the second control signal φ1HN are in the hold mode.

  The above is the configuration of the differential comparator 10H. Next, the operation will be described. 4A and 4B are time charts illustrating the operation of the differential comparator of FIG. 4A illustrates the operation of the upper differential comparator 10H, and FIG. 4B illustrates the operation of the lower differential comparator 10L.

  Prior to the test of the DUT 200, it is assumed that the line length difference of the differential signal lines 50P / 50N, in other words, the propagation time difference te is measured in advance. The propagation time error te can be measured by the method disclosed in US Pat. No. 7,121,132, for example. As a result of the measurement, it is assumed that one propagation time of the differential signal line 50 is given by tpd and the other propagation time is given by tpd + te.

On both the differential comparators 10H side and 10L side, the first variable delay VDHP (VDLP) and the second variable delay VDHN (VDLN) are set based on the measured error te. Specifically, the delay amounts of the first delay circuit 22 and the second delay circuit 24 are:
VDHN = VDHP + te
VDLN = VDLP + te
It is adjusted to satisfy. By this adjustment, the timing at which the second control signal φ1HN instructs the second sample hold circuit SH2 to sample is delayed by a time difference te from the timing at which the first control signal φ1HP instructs the first sample hold circuit SH1 to sample.

  Reference is made to FIG. Prior to time t0, the strobe signal φ0H is at a low level, and the first control signal φ1HP and the second control signal φ1HN are both at a high level. During this time, both the first sample hold circuit SH1 and the second sample hold circuit SH2 are set to the tracking mode.

  At time t0, the strobe signal φ0H changes to high level. When the first control signal φ1HP transitions to the low level at the time t1 after the first variable delay VDHP has elapsed from the time t0, the first sample hold circuit SH1 is set to the hold mode, and the value RPH of the differential signal RP is sampled. Then hold.

  When the second control signal φ1HN transitions from the high level to the low level at the time t2 after the elapse of the first variable delay VDHN from the time t0, the second sample hold circuit SH2 is set to the hold mode, and the value RNH of the differential signal RN Is sampled and then held.

Here, attention is focused on the differential amplitude signal (HP-HN) output from the subtractor 14. The value of the differential amplitude signal (HP-HN) changes as follows according to the states of the first sample hold circuit SH1 and the second sample hold circuit SH2.
(1) Before time t1 In this state, because HP = RP and HN = RN,
(HP-HN) = RP-RN
(2) Time t1 to t2
In this state, since the first sample hold circuit SH1 is in the hold mode and the second sample hold circuit SH2 is in the tracking mode, RP = RPH and HN = RN.
(HP-HN) = RPH-RN
(3) After time t2 In this state, since both the first sample hold circuit SH1 and the second sample hold circuit SH2 are in the hold mode, RP = RPH and HN = RNH.
(HP-HN) = RPH-RNH

  When the differential amplitude (HP-HN) crosses the threshold voltage VOH at time t3 between times t1 and t2, the comparison signal SH changes from high level to low level.

  At time t4 after the lapse of the delay time FD3 from time t2 when both the first sample hold circuit SH1 and the second sample hold circuit SH2 are in the hold mode, the third control signal φ3H transitions to the high level, and the latch circuit 18 The output of the comparison unit 12 is latched. At this time, since the comparison signal SH is at the low level, the value of the fail signal FH is fixed at the low level.

  As shown in FIG. 4B, the differential comparator 10L operates in the same manner as the differential comparator 10H with reference to the strobe signal φ0L. A low level fail signal FL is generated by the differential comparator 10L.

  The effects of the differential comparators 10H and 10L according to the embodiment are clarified by comparison with the conventional differential comparator.

  When there is an error in the wiring length of the differential lines 50P / 50N, when a normal differential signal UP / UN is evaluated using the conventional circuit shown in FIG. 1, a fail signal is obtained as shown in FIG. There has been a problem that FH is at a high level and the transition time is erroneously determined as not satisfying the standard.

  On the other hand, according to the differential comparators 10H and 10L in FIG. 3, since the fail signals FH and FL are both determined to be at a low level, the transition time of the differential signal UP / UN output from the DUT 200 satisfies the standard. It can be correctly determined that it satisfies. That is, while having the same function as the conventional differential comparator, even when an unbalance occurs in the wiring length of the differential line, the influence of the unbalance can be eliminated and the differential signal can be evaluated.

  Further, since the differential comparators 10H and 10L in FIG. 3 can be easily configured by a CMOS process, the circuit area does not increase so much as compared with the differential comparator 110 in FIG.

  FIG. 5 is a circuit diagram showing a first modification of the differential comparator according to the embodiment. The first sample hold circuit SH1 and the second sample hold circuit SH2 in FIG. 5 have the function of the subtracter 14 in addition to the functions of the first sample hold circuit SH1 and the second sample hold circuit SH2 in FIG. .

The first sample hold circuit SH1 includes a first capacitor C1, a second capacitor C2, a first switch SW1, a second switch SW2, a third switch SW3, and a first voltage source VS1.
One end (first terminal) of the first capacitor C1 is grounded, and its potential is fixed. Similarly, one end (first terminal) of the second capacitor C2 is grounded and its potential is fixed. The first switch SW1 is provided between the other end (second terminal) of the first capacitor C1 and the first input terminal P1. The second switch SW2 is provided between the other end (second terminal) of the first capacitor C1 and the other end (second terminal) of the second capacitor C2. The capacitance values of the capacitors C1 to C4 are all set equal.

  The first voltage source VS1 generates a first reference voltage (Vc−VOH / 2) obtained by shifting the predetermined voltage Vc to a lower potential side by a potential difference (VOH / 2) corresponding to the threshold voltage VOH. The voltage Vc may be ½ of the power supply voltage, may be a common voltage of the differential signal RP / RN, or may be other constant voltage. The third switch SW3 is provided between the first voltage source VS1 and the other end (second terminal) of the second capacitor C2.

  The second sample hold circuit SH2 includes a third capacitor C3, a fourth capacitor C4, a fourth switch SW4, a fifth switch SW5, a sixth switch SW6, and a second voltage source VS2. The configuration is the same as that of the first sample hold circuit SH1. The second voltage source VS2 generates a second reference voltage (Vc + VOH / 2) obtained by shifting the predetermined voltage Vc to the high potential side by a potential difference (VOH / 2) corresponding to the threshold voltage VOH.

  The timing control unit 20 generates control signals φ1HP, φ1HN, φ2H, φ1H, and φ3H based on the strobe signal φ0H. The timing control unit 20 includes a first delay circuit 22, a second delay circuit 24, a first inverter 28, a second inverter 30, a NAND gate 34, a third inverter 36, a fourth delay circuit 38, and a fifth delay circuit 40. .

  The strobe signal φ0H is supplied to the first switch SW1 as the control signal φ1HP through the first delay circuit 22 and the first inverter 28. Further, the control signal φ1HN is supplied to the fourth switch SW4 through the second delay circuit 24 and the second inverter 30.

  The NAND gate 34 generates a negative logical product of the output signals of the first delay circuit 22 and the second delay circuit 24. The output signal of the NAND gate 34 is supplied to the third switch SW3 and the sixth switch SW6 as the control signal φ1H.

  The output signal of the NAND gate 34 is supplied to the second switch SW2 and the fifth switch SW5 as the control signal φ2H through the third inverter 36 and the fourth delay circuit 38. The control signal φ2H is given a delay FD2 by the fifth delay circuit 40, and a control signal φ3H is generated.

  The configuration of the timing control unit 20 is not limited to this, and any circuit having the same function may be used.

  A dummy comparator 17 is further provided in the differential comparator 10H. The dummy comparator 17 receives the potential HHP generated in the first capacitor C1 and the potential HHN generated in the third capacitor C3. The dummy comparator 17 is not intended to perform voltage comparison but is provided to balance the load. By providing the dummy comparator 17, the first sample hold circuit SH1 and the second sample hold circuit SH2 are symmetric with respect to the second switch SW2 and the fifth switch SW5, so that the accuracy of signal processing is dramatically increased.

  The above is the configuration of the differential comparators 10H and 10L in FIG. Next, the operation will be described.

  On each of the differential comparators 10H side and 10L side, the first variable delay VDHP (VDLP) and the second variable delay VDHN (VDLN) are set based on the error te.

  The differential comparator 10H executes the following processing in synchronization with the strobe signal φ0H.

Step 1. (Initialization mode)
On the first sample hold circuit SH1 side, the second switch SW2 is turned off, and the first switch SW1 and the third switch are turned on. As a result, the first capacitor C1 is charged with the potential (RP) of the first input terminal P1, and the second capacitor C2 is charged with the first reference voltage (Vc−VOH / 2).
On the second sample hold circuit SH2 side, the fifth switch SW5 is turned off, and the fourth switch SW4 and the sixth switch SW6 are turned on. As a result, the third capacitor C3 is charged with the potential (RN) of the second input terminal P2, and the fourth capacitor C4 is charged with the second reference voltage (Vc + VOH / 2).

Step 2. (Hold mode)
On the first sample hold circuit SH1 side, the first switch SW1 is turned off at a timing according to the control signal φ1HP. At this time, the differential signal RP is sampled and held in the first capacitor C1. Further, the third switch SW3 is turned off at a timing according to the control signal φ1H.
On the second sample and hold circuit SH2 side, the fourth switch SW4 is turned off at a timing according to the control signal φ1HN. At this time, the differential signal RN is sampled and held in the third capacitor C3. Further, the sixth switch SW6 is turned off at a timing according to the control signal φ1H.

Step 3. (Calculation mode)
On the first sample hold circuit SH1 side, the second switch SW2 is turned on at a timing according to the control signal φ2H with the first switch SW1 and the third switch SW3 turned off. As a result, charge redistribution occurs between the first capacitor C1 and the second capacitor C2, and the potential HHP and the potential SHP are averaged.

  On the second sample and hold circuit SH2 side, with the fourth switch SW4 and the sixth switch SW6 turned off, the fifth switch SW5 is turned on at a timing according to the control signal φ2H. As a result, charge redistribution occurs between the third capacitor C3 and the fourth capacitor C4, and the potential HHN and the potential SHN are averaged.

Step 4.
The comparator 16 (comparator 12) compares the voltage SHP generated in the second capacitor C2 with the voltage SHN generated in the fourth capacitor C4, and generates a comparison signal SH corresponding to the comparison result. The latch circuit 18 latches the output SH of the comparison unit 12 at a timing (φ3H) according to the strobe signal φ0H.

  The understanding will be further deepened by referring to the time chart. FIGS. 6A and 6B are time charts illustrating the operation of the differential comparator of FIG. 6A illustrates the operation of the upper differential comparator 10H, and FIG. 6B illustrates the operation of the lower differential comparator 10L.

  Reference is made to FIG. Prior to time t0, the strobe signal φ0H is at a low level, and the control signal φ1HP and the control signal φ1HN are both at a high level. During this time, the first capacitor C1 to the fourth capacitor C4 are charged (step 1).

  At time t0, the strobe signal φ0H changes to high level. When the control signal φ1HP transitions from the high level to the low level at the time t1 after the first variable delay VDHP has elapsed from the time t0, the first sample hold circuit SH1 samples the value RPH of the differential signal RP, and holds it thereafter ( Step 2).

  When the control signal φ1HN transitions from the high level to the low level at the time t2 after the first variable delay VDHN elapses from the time t0, the second sample hold circuit SH2 samples the value RNH of the differential signal RN and then holds it ( Step 2).

  At time t2 when both the first sample hold circuit SH1 and the second sample hold circuit SH2 are in the hold mode, the control signal φ1H transitions to the low level, and the third switch SW3 and the sixth switch SW6 are turned off. At time t3 after the delay time FD1 has elapsed from time t2, the control signal φ2H becomes high level, and the second switch SW2 and the fifth switch SW5 are turned on (step 3).

  When the second switch SW2 is turned on, the charge is redistributed between the first capacitor C1 and the second capacitor C2, the held signal RPH and the reference voltage (Vc−VOH / 2) are averaged, and asymptotically approach each other. Finally, it is settled to (RPH + Vc−VOH / 2) / 2 (step 3).

  When the fifth switch SW5 is turned on, charges are redistributed between the third capacitor C3 and the fourth capacitor C4, the held signal RNH and the reference voltage (Vc + VOH / 2) are averaged, and asymptotically approach each other, Finally, it is settled to (RNH + Vc + VOH / 2) / 2. Since the switches including the second switch SW2 and the fifth switch SW5 have non-zero ON resistance, each voltage changes according to the CR time constant (step 3).

  The potential SHP of the second capacitor C2 and the potential SHN of the fourth capacitor C4 become equal (intersect) at time t4 during the charge redistribution process. At time t4 when the two potentials SHP and SHN intersect, the level of the output signal SH of the comparator 16 changes from the high level to the low level.

  At time t5 when the control signal φ3H is asserted, the comparison signal SH is latched by the latch circuit 18, and the value of the fail signal FH is fixed to the low level (step 4).

  As shown in FIG. 6B, the differential comparator 10L operates in the same manner as the differential comparator 10H with reference to the strobe signal φ0L. A low level fail signal FL is generated by the differential comparator 10L.

  Thus, according to the differential comparators 10H and 10L in FIG. 5, the unbalance of the wiring lengths of the differential lines 50P / 50N can be canceled, and the raw differential signals UP / UN output from the DUT 200 can be reduced. Can be evaluated appropriately.

  Further, the comparator 16 formed of a CMOS circuit may have an input offset voltage of several tens to several hundreds mV. Therefore, the input offset voltage of the comparator 16 is suitably canceled by intentionally shifting and optimizing each reference voltage generated by the first voltage source VS1 and the second voltage source VS2 in accordance with the input offset voltage. There is also an advantage of being able to.

FIG. 7 is a circuit diagram showing a second modification of the differential comparator according to the embodiment.
The differential comparator 10H includes a fifth capacitor C5, a sixth capacitor C6, a seventh switch SW7 to a twelfth switch SW12, a third voltage source VS3, a fourth voltage source VS4, and a timing control unit 20.

  The seventh switch SW7, the fifth capacitor C5, the third voltage source VS3, and the fourth voltage source VS4 correspond to the first sample hold circuit SH1.

One end of the seventh switch SW7 is connected to the first input terminal P1. One end (first terminal) of the fifth capacitor C5 is connected to the other end of the seventh switch SW7.
The third voltage source VS3 generates a third reference voltage (Vc + VOH / 2) obtained by shifting the predetermined voltage Vc to the high potential side by a potential difference (VOH / 2) corresponding to the threshold voltage VOH. The eighth switch SW8 is provided between one end of the fifth capacitor C5 and the third voltage source VS3. The fourth voltage source VS4 generates a fourth reference voltage Vc. The ninth switch SW9 is provided between the other end (second terminal) of the fifth capacitor C5 and the fourth voltage source VS4.

  Similarly, the eighth switch SW8, the sixth capacitor C6, the fifth voltage source VS5, and the fourth voltage source VS4 correspond to the second sample hold circuit SH2. The topology of the second sample and hold circuit SH2 is the same as that of the first sample and hold circuit SH1.

  The timing control unit 20 is configured in the same manner as in FIG. 5, and generates control signals φ1HP, φ1HN, φ2H, φ1H, and φ3H based on the strobe signal φ0H.

  The above is the configuration of the differential comparators 10H and 10L in FIG. Next, the operation will be described. The differential comparator 10H executes the following processing in synchronization with the strobe signal φ0H.

Step 1. (Tracking mode)
On the first sample hold circuit SH1 side, the eighth switch SW8 is turned off, and the seventh switch SW7 and the ninth switch SW9 are turned on. As a result, the potential (RP) of the first input terminal P1 and the fourth reference voltage Vc are applied to both ends of the fifth capacitor C5, and the fifth capacitor C5 is charged.

  On the second sample hold circuit SH2 side, the eleventh switch SW11 is turned off and the tenth switch SW10 and the twelfth switch SW12 are turned on. As a result, the sixth capacitor C6 is charged.

Step 2. (Hold mode)
On the first sample hold circuit SH1 side, the seventh switch SW7 is turned off at a timing according to the control signal φ1HP. At this time, the potential HHP at one end of the fifth capacitor C5 is held at the potential RPH. Further, the ninth switch SW9 is turned off at a timing according to the control signal φ1H. As a result, the voltage VcapHP of the fifth capacitor C5 is held at (Vc−RPH).

  On the second sample and hold circuit SH2 side, the tenth switch SW10 is turned off at a timing corresponding to the control signal φ1HN. At this time, the potential HHN at one end of the sixth capacitor C6 is held at the potential RNH. Further, the twelfth switch SW12 is turned off at a timing according to the control signal φ1H. As a result, the voltage VcapHN of the sixth capacitor C6 is held at (Vc−RNH).

Step 3. (Calculation mode)
On the first sample hold circuit SH1 side, the eighth switch SW8 is turned on at a timing according to the control signal φ2H with the seventh switch SW7 and the ninth switch SW9 turned off. As a result, the potential SHP at the other end of the fifth capacitor C5 is (VcapHP + Vc + VOH / 2).
On the second sample hold circuit SH2 side, the eleventh switch SW11 is turned on at a timing according to the control signal φ2H with the tenth switch SW10 and the twelfth switch SW12 turned off. As a result, the potential SHN at the other end of the sixth capacitor C6 is (VcapHN + Vc−VOH / 2).

Step 4.
The comparator 16 (comparator 12) compares the voltage SHP generated at the other end of the fifth capacitor C5 with the voltage SHN generated at the sixth capacitor C6, and generates a comparison signal SH according to the comparison result.
The output SH of the comparator 16 is
sign (SHP-SHN) = sign (VOH- (RPH-RNH))
And is equivalent to equation (1a). The latch circuit 18 latches the output SH of the comparison unit 12 at a timing (φ3H) according to the strobe signal φ0H.

On the differential comparator 10L side, the output SL of the comparator 16 is
sign (SLN-SLP) = sign ((RPL-RNL) -VOL)
Which is equivalent to equation (1b).

  The above processing will be further understood by referring to the time chart. 8A and 8B are time charts illustrating the operation of the differential comparator in FIG. FIG. 8A illustrates the operation of the upper differential comparator 10H, and FIG. 8B illustrates the operation of the lower differential comparator 10L.

  Reference is made to FIG. Prior to time t0, the strobe signal φ0H is at a low level, and the control signals φ1HP, φ1HN, and φ1H are all at a high level. During this time, the fifth capacitor C5 and the sixth capacitor C6 are charged (step 1).

  At time t0, the strobe signal φ0H changes to high level. When the control signal φ1HP transitions from the high level to the low level at time t1 after the first variable delay VDHP has elapsed from time t0, the seventh switch SW7 is turned off. At this time, the potential HHP at one end of the fifth capacitor C5 is held at the potential RPH (step 2).

  When the control signal φ1HN transitions from the high level to the low level at the time t2 after the first variable delay VDHN has elapsed from the time t0, the tenth switch SW10 is turned off, and the potential HHN at one end of the sixth capacitor C6 becomes the potential RNH. Hold (step 2).

  At time t2, the control signal φ1H changes to the low level, and the ninth switch SW9 and the twelfth switch SW12 are turned off. As a result, the voltage VcapHPP of the fifth capacitor C5 and the voltage VcapHN of the sixth capacitor C6 are held (step 2).

When φ2H transits to a high level at time t3, the eighth switch SW8 and the eleventh switch SW11 are turned on. Then, the input voltages SHP and SHN of the comparator 16 are respectively
SHP = 2 × Vc−RPH + VOH / 2
SHN = 2 * Vc-RNH-VOH / 2
Level shifted to At this time, the output SH of the comparator 16 transitions from an indefinite state to a low level (step 3).

  At time t5 when the control signal φ3H is asserted, the comparison signal SH is latched by the latch circuit 18, and the value of the fail signal FH is fixed to the low level.

  As shown in FIG. 8B, the differential comparator 10L operates in the same manner as the differential comparator 10H with reference to the strobe signal φ0L. A low level fail signal FL is generated by the differential comparator 10L.

  As described above, according to the differential comparators 10H and 10L in FIG. 7, the unbalance of the wiring length of the differential line can be canceled, and the differential signal UP / UN from the DUT 200 can be appropriately evaluated.

FIG. 9 is a circuit diagram showing a third modification of the differential comparator according to the embodiment.
The differential comparator 10H in FIG. 9 is a circuit using a chopper type operational amplifier, and instead of the ninth switch SW9, the twelfth switch SW12, and the fourth voltage source VS4 in FIG. 7, a differential amplifier 42 and a thirteenth switch SW13. The 14th switch SW14 is provided.

  The differential amplifier 42 receives the potential SHP of the other end of the fifth capacitor C5 at its non-inverting input terminal, and receives the potential SHN of the other end of the sixth capacitor C6 at its inverting input terminal. To do.

  The thirteenth switch SW13 is provided between the non-inverting input terminal and the inverting output terminal of the differential amplifier 42, and the fourteenth switch SW14 is provided between the inverting input terminal and the non-inverting output terminal of the differential amplifier 42.

On / off of the thirteenth switch SW13 and the fourteenth switch SW14 is controlled by a control signal φ1H. When the non-inverting output of the differential amplifier 42 is written as THP and the inverting output is written as THN, when the thirteenth switch SW13 and the fourteenth switch SW14 are off,
THP = Vc + (SHP−SHN) × A / 2
THN = Vc− (SHP−SHN) × A / 2
Is established. When the thirteenth switch SW13 and the fourteenth switch SW14 are on,
THP = SHN = Vc
THN = SHP = Vc
Is established.

  The comparator 16 (comparator 12) compares the potential THP of the non-inverting output terminal of the differential amplifier 42 with the potential THN of the inverting output terminal.

  The differential comparator 10H in FIG. 9 operates in the same manner as the differential comparator 10H in FIG. Therefore, the unbalance of the wiring length of the differential line can be canceled, and the differential signal UP / UN from the DUT 200 can be appropriately evaluated.

  FIG. 10 is a circuit diagram showing a fourth modification of the differential comparator according to the embodiment. In the above-described embodiments, the differential comparators that compare the differential amplitude (RP-RN) with the upper threshold voltage VOH and the lower threshold voltage VOL have been described. On the other hand, the differential comparator of FIG. 10 shows a configuration in which both threshold voltages VOH and VOL are zero. The differential comparator 10 determines whether the sign of the differential amplitude signal (RP-RN) is positive or negative, in other words, the magnitude relationship of the differential signal RP / RN.

  The differential comparator 10 of FIG. 10 has a configuration in which the subtracter 14 is removed from the differential comparators 10H and 10L of FIG. That is, the comparator 16 compares the output HP of the first sample hold circuit SH1 with the output HN of the second sample hold circuit SH2. The latch circuit 18 latches the output SC of the comparator 16 at a timing according to the control signal φ3, and generates a fail signal FC.

  FIG. 11 is a time chart illustrating the operation of the differential comparator 10 of FIG.

  Prior to time t0, the strobe signal φ0H is at the low level, and therefore the first control signal φ1HP and the second control signal φ1HN are both at the high level, and the first sample hold circuit SH1 and the second sample hold circuit SH2 are both Is also set to tracking mode.

  At time t0, the strobe signal φ0 changes to high level (assert). When the first control signal φ1P transitions from the high level to the low level at the time t1 after the first variable delay VDP has elapsed from the time t0, the first sample hold circuit SH1 is set to the hold mode, and the value RPH of the differential signal RP Is sampled and then held.

  When the second control signal φ1N transitions from the high level to the low level at the time t2 after the first variable delay VDN has elapsed from the time t0, the second sample hold circuit SH2 is set to the hold mode, and the value RNH of the differential signal RN Is sampled and then held.

  Prior to time t2, the output HP of the first sample-and-hold circuit SH1 and the output HN of the second sample-and-hold circuit SH2 cross each other, and the comparison signal SC transitions to a high level. Thereafter, when the control signal φ3H becomes high level at time t4, the value of the fail signal FC is determined.

  According to the differential comparator 10 of FIG. 10, even when there is an error in the line length of the differential signal lines 50P / 50N, the influence is canceled, and the cross point of the differential signal UP / UN output from the DUT 200 is appropriately set. Can be evaluated.

  Although the present invention has been described based on the embodiments, the embodiments merely show the principle and application of the present invention, and the embodiments depart from the idea of the present invention defined in the claims. Many modifications and arrangements can be made without departing from the scope.

DESCRIPTION OF SYMBOLS 10 ... Differential comparator, P1 ... 1st input terminal, P2 ... 2nd input terminal, SH1 ... 1st sample hold circuit, SH2 ... 2nd sample hold circuit, 12 ... Comparison part, 14 ... Subtractor, 16 ... Comparator, DESCRIPTION OF SYMBOLS 17 ... Dummy comparator, 18 ... Latch circuit, 20 ... Timing control part, 22 ... 1st delay circuit, 24 ... 2nd delay circuit, 26 ... 1st AND gate, 28 ... 1st inverter, 30 ... 2nd inverter, 32 ... 3rd delay circuit, 34 ... NAND gate, 36 ... 3rd inverter, 38 ... 4th delay circuit, 40 ... 5th delay circuit, 42 ... differential amplifier, TA1 ... 1st termination amplifier, TA2 ... 2nd termination amplifier, 50 ... differential signal line, 100 ... test apparatus, 200 ... DUT, C1 ... first capacitor, C2 ... second capacitor, C3 ... third capacitor, C4 ... fourth capacitor, 5 ... 5th capacitor, C6 ... 6th capacitor, SW1 ... 1st switch, SW2 ... 2nd switch, SW3 ... 3rd switch, SW4 ... 4th switch, SW5 ... 5th switch, SW6 ... 6th switch, SW7 ... 7th switch, SW8 ... 8th switch, SW9 ... 9th switch, SW10 ... 10th switch, SW11 ... 11th switch, SW12 ... 12th switch, SW13 ... 13th switch, SW14 ... 14th switch, VS1 ... 1st Voltage source, VS2 ... second voltage source, VS3 ... third voltage source, VS4 ... fourth voltage source, VS5 ... fifth voltage source.

Claims (7)

A differential comparator that receives a differential signal output from a device under test and compares the differential amplitude of the differential signal with a predetermined threshold voltage;
A first input terminal to which one of the differential signals is input;
A second input terminal to which the other of the differential signals is input;
A first sample-and-hold circuit that samples a signal input to the first input terminal at a designated timing and then holds the sample;
A second sample and hold circuit that samples the signal input to the second input terminal at a designated timing and then holds the sample;
A comparator for comparing a signal corresponding to a difference between output signals of the first and second sample and hold circuits with a predetermined threshold;
A latch circuit for latching the output of the comparator;
And a differential comparator capable of independently adjusting a sampling timing of the first and second sample hold circuits and a latch timing of the latch circuit. The first sample and hold circuit includes:
A first capacitor having a fixed potential at one end;
A second capacitor having a fixed potential at one end;
A first switch provided between the other end of the first capacitor and the first input terminal;
A second switch provided between the other end of the first capacitor and the other end of the second capacitor;
A first voltage source for generating a first reference voltage by shifting a predetermined voltage by a potential difference corresponding to the threshold voltage;
A third switch provided between the first voltage source and the other end of the second capacitor;
And turning off the second switch and turning on the first and third switches;
Turning off the first and third switches;
Turning off the first and third switches and turning on the second switch;
At a timing according to the strobe signal,
The second sample and hold circuit includes:
A third capacitor having a fixed potential at one end;
A fourth capacitor having a fixed potential at one end;
A fourth switch provided between the other end of the third capacitor and the second input terminal;
A fifth switch provided between the other end of the third capacitor and the other end of the fourth capacitor;
A second voltage source that generates a second reference voltage by shifting a predetermined voltage by a potential difference corresponding to the threshold voltage;
A sixth switch provided between the second voltage source and the other end of the fourth capacitor;
And turning off the fifth switch and turning on the fourth and sixth switches;
Turning off the fourth and sixth switches;
Turning off the fourth and sixth switches and turning on the fifth switch;
At a timing according to the strobe signal,
The comparison unit compares the voltage generated in the second capacitor with the voltage generated in the fourth capacitor;
The differential comparator according to claim 1, wherein the latch circuit latches the output of the comparison unit at a timing corresponding to the strobe signal.   The differential comparator according to claim 2, further comprising a dummy comparator to which a potential generated in the first capacitor and a potential generated in the third capacitor are input. The first sample and hold circuit includes:
A seventh switch having one end connected to the first input terminal;
A fifth capacitor having one end connected to the other end of the seventh switch;
A third voltage source for generating a third reference voltage by shifting a predetermined voltage by a potential difference corresponding to the threshold voltage;
An eighth switch provided between the one end of the fifth capacitor and the third voltage source;
A fourth voltage source for generating a fourth reference voltage;
A ninth switch provided between the other end of the fifth capacitor and the fourth voltage source;
And turning off the eighth switch and turning on the seventh and ninth switches;
Turning off the seventh and ninth switches;
Turning the seventh and ninth switches off and the eighth switch on;
At a timing according to the strobe signal,
The second sample and hold circuit includes:
A tenth switch having one end connected to the second input terminal;
A sixth capacitor having one end connected to the other end of the tenth switch;
A fifth voltage source for generating a fifth reference voltage obtained by shifting a predetermined voltage by a potential difference corresponding to the threshold voltage;
An eleventh switch provided between the one end of the sixth capacitor and the fifth voltage source;
A twelfth switch provided between the other end of the sixth capacitor and the fourth voltage source;
And the eleventh switch is turned off and the tenth and twelfth switches are turned on.
Turning off the tenth and twelfth switches;
Turning the tenth and twelfth switches off and the eleventh switch on;
At a timing according to the strobe signal,
The comparison unit compares the voltage generated at the other end of the fifth capacitor with the voltage generated at the other end of the sixth capacitor;
The differential comparator according to claim 1, wherein the latch circuit latches the output of the comparison unit at a timing corresponding to the strobe signal. The first and second sample and hold circuits are replaced with the ninth and twelfth switches and the fourth voltage source.
A differential amplifier that receives a potential of the other end of the fifth capacitor and a potential of the other end of the sixth capacitor;
A thirteenth switch provided between a non-inverting input terminal and an inverting output terminal of the differential amplifier;
A fourteenth switch provided between the inverting input terminal and the non-inverting output terminal of the differential amplifier;
Including
The differential comparator according to claim 4, wherein the comparison unit compares the potential of the inverting output terminal of the differential amplifier with the potential of the non-inverting output terminal.   The comparison unit outputs the outputs of the first and second sample and hold circuits instead of the process of comparing the signal corresponding to the difference between the output signals of the first and second sample and hold circuits with a predetermined threshold value. The differential comparator according to claim 1, wherein the signals are compared. The differential comparator according to claim 1, which receives a differential signal output from a device under test and compares the differential amplitude of the differential signal with a predetermined upper threshold voltage;
A test apparatus comprising: the differential comparator according to claim 1, wherein the differential amplitude of the differential signal is compared with a predetermined lower threshold voltage.

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