JP2010164449A - Resolver digital converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a resolver digital converter for removing noise while suppressing detection errors. <P>SOLUTION: The resolver digital converter includes: a switched capacitor filter to which a sin-phase signal and a cos-phase signal from a resolver are input; an arithmetic processing means arithmetically processing an output of the switched capacitor filter and outputting an angle signal; and a PLL (Phase-Locked Loop) circuit to which an excitation signal for magnetically exciting the resolver is input. The switched capacitor filter is driven by a VCO (Voltage-Controlled Oscillator) included in the PLL circuit. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a resolver / digital converter that outputs an angle signal based on a sin phase signal and a cos phase signal input from a resolver.

  Conventionally, a variable reluctance type (VR type) resolver that detects a rotation angle of a rotor by detecting a distance between a rotor having a non-circular portion and a stator by a magnetic method has been widely used. In a variable reluctance type (VR type) resolver, an exciting coil and a detecting coil are arranged on the stator so as to be aligned along the circumferential direction of the rotor, and a change in magnetic resistance caused by a change in the distance from the rotor is detected. By doing so, the rotation angle of the rotor is detected. The detection coil is a sin-phase detection coil wound so as to obtain an output (sin phase signal) proportional to the rotor rotation angle sin, and an output (cos phase) proportional to the rotor rotation angle cos. A cos phase detection coil wound so as to obtain a The application target of the present invention is not limited to a variable reluctance type (VR type) resolver, but can be applied to any resolver that outputs a sin phase signal and a cos phase signal.

  The sin-phase signal and the cos-phase signal output in this way are converted into angle signals by a resolver digital converter. An invention relating to a digital conversion method of an analog signal related to this is disclosed (for example, see Patent Document 1). In this method, a rotation angle detection signal (sin phase signal and cos phase signal) is introduced into a multiplying D / A converter and subjected to mutual detection with a cosine and a sine of a digital angle output, followed by synchronous detection and control deviation. Seeking. Then, the digital angle output is determined so that the control deviation approaches the value zero (tracking method).

JP 2000-353957 A

  By the way, in a resolver digital converter, it is desirable to remove noise by filtering an input signal. However, the phase shift of the signal due to the filter processing may increase, and this may cause an error in the detection angle. Therefore, a resolver is used to make the signal amplitude sufficient instead of inserting a steep filter. Therefore, it is necessary to increase the excitation signal amplitude or increase the power supply voltage of the excitation signal generation circuit and the power supply voltage of the detection circuit to widen the dynamic range of the circuit.

  The present invention has been made to solve such problems, and a main object of the present invention is to provide a resolver / digital converter capable of removing noise while suppressing detection errors.

In order to achieve the above object, one embodiment of the present invention provides:
A switched capacitor filter to which a sin phase signal and a cos phase signal from the resolver are input;
Arithmetic processing means for arithmetically processing the output of the switched capacitor filter and outputting an angle signal;
A PLL (Phase-Locked Loop) circuit to which an excitation signal for exciting the resolver is input,
The switched capacitor is driven by a VCO (Voltage-Controlled Oscillator) included in the PLL circuit.
It is a resolver digital converter.

  According to this aspect of the present invention, since the switched capacitor filter is driven by a signal synchronized with the excitation signal for exciting the resolver, the cut-off frequency in the switched capacitor filter follows the fluctuation of the excitation signal. As a result, it is possible to remove noise while suppressing detection errors.

  ADVANTAGE OF THE INVENTION According to this invention, the resolver digital converter which can perform noise removal, suppressing a detection error can be provided.

1 is a system configuration example of a resolver / digital converter 1 according to an embodiment of the present invention. 3 is a circuit configuration example of a PLL circuit 5; It is a figure which shows the circuit structural example of the switched capacitor filters 6 and 7, and a circuit structure equivalent to this. It is a figure which shows the circuit structure of a simple switched capacitor, and a circuit structure equivalent to this. It is a figure which shows together the time change of the signal input into the delta-sigma modulators 10 and 20, and the time change of the bit stream signal which the delta-sigma modulators 10 and 20 output. It is explanatory drawing for demonstrating the process at the time of the detection signal production | generation part 40 producing | generating reference data {F (t + (alpha))}.

  Hereinafter, the best mode for carrying out the present invention will be described with reference to the accompanying drawings.

  Hereinafter, a resolver / digital converter 1 according to an embodiment of the present invention will be described. FIG. 1 is a system configuration example of a resolver / digital converter 1 according to an embodiment of the present invention. A resolver 100 is connected to the resolver / digital converter 1. The resolver / digital converter 1 is a device that outputs an angle signal φ based on a sin phase signal and a cos phase signal input from the resolver 100.

  First, the configuration and function of the resolver 100 will be outlined. The resolver 100 is a variable reluctance resolver, for example, and is attached to a rotating body such as an electric motor. The resolver 100 includes a rotor that rotates integrally with an attached rotating body, and a stator that is used while being fixed to a case or the like. The rotor is coupled to the stator by a bearing or the like so as to be relatively rotatable. The outer contour of the rotor is defined not by a constant diameter but by a periodically changing diameter. The stator is formed by laminating silicon steel plates, for example, has an annular shape facing the outer peripheral surface of the rotor, and is connected to the rotor so that the rotation center of the rotor coincides with the center of the stator.

A stator core (teeth) arranged along the circumferential direction of the rotor is formed on the stator so as to protrude on the side (inner side) facing the rotor. Each of the stator cores is wound with an excitation coil connected to the power supply device and a detection coil for converting the magnetic flux resistance to the generated magnetism into a voltage and outputting it to the resolver / digital converter 1. Thereby, a coil row in which a plurality of excitation coils and a plurality of detection coils are arranged along the circumferential direction of the rotor is arranged. An excitation coil and a detection coil are concentrically wound around each coil. The detection coil has a sin-phase detection coil wound so as to obtain an output proportional to sin θ (sin-phase signal) and an output proportional to cos θ (cos-phase A cos phase detection coil wound to obtain a signal. At both ends of the excitation coil, for example, several [kHz], the number [Vp _- p] of about AC is input. Each of the sin phase detection coil and the cos phase detection coil is connected to an input terminal of the resolver / digital converter 1.

When the excitation coil is excited and magnetism is generated, the detection coil generates electricity. When the rotor rotates due to an external force or the like, the interval between the detection coil and the rotor changes periodically, and accordingly, the magnetic flux resistance changes and the voltage induced in the detection coil changes. Assuming that the input voltage applied to both ends of the exciting coil is f (t), the output voltage E _SIN-GND of the sin phase detection coil is expressed by the following equation (1), and the output voltage of the cos phase detection coil: E _COS-GND is represented by the following formula (2), respectively. K is a constant, and α and β are phase differences. These parameters are determined by the number of exciting windings, the number of output windings, the shape and material of the rotor and stator, and the like. The input voltage f (t) is expressed as, for example, Esinωt. E is a constant.

E _SIN-GND = Ksinθ · f (t + α) (1)
E _COS-GND = K cos θ · f (t + β) (2)

  Hereinafter, the resolver / digital converter 1 will be described on the assumption of this. As shown in FIG. 1, the resolver / digital converter 1 includes, as main components, a PLL circuit 5, switched capacitor filters 6 and 7, delta-sigma modulators 10 and 20, cosROM 11, sinROM 21, and multiplier 12. And 22, digital filters 13 and 23, synchronous detectors 14 and 24, a subtractor 30, a counter circuit 32, and a detection signal generator 40.

  FIG. 2 is a circuit configuration example of the PLL circuit 5. The PLL circuit 5 includes a phase comparator 5A, a low-pass filter 5B, a VCO (Voltage-Controlled Oscillator) 5C, and a frequency divider 5D. The phase comparator 5A receives the excitation signal sinωt of the resolver 100 (hereinafter, constants E and K are omitted) and a signal fed back from the VCO 5C via the frequency divider 5D, and the phase difference between these signals. Is output to the low-pass filter 5B. The VCO 5C outputs a pulse signal whose frequency is determined by the voltage signal input from the low-pass filter 5B. The frequency divider 5D has, for example, a programmable counter, and divides the input frequency into N (N is an integer or a fraction) and outputs it. With this configuration, the PLL circuit 5 outputs a signal having a frequency Nω that is N times the frequency ω of the excitation signal sin ωt of the resolver 100. When N = 1, the frequency divider 5D is not necessary. The output signal of the VCO 5C is output to the switched capacitor filters 6 and 7 to drive them.

  The switched capacitor filter 6 receives a sin phase signal sin θ · f (t + α), and the switched capacitor filter 7 receives a cos phase signal cos θ · f (t + β), respectively, and performs filtering.

  FIG. 3A is a circuit configuration example of the switched capacitor filters 6 and 7, and FIG. 3B is a diagram showing a circuit configuration equivalent to this.

  Here, the function of the switched capacitor filter will be described. FIG. 4A shows a simple switched capacitor circuit configuration, and FIG. 4B shows an equivalent circuit configuration. As shown in the figure, a switched capacitor is equivalent to a variable resistor having a resistance value 1 / (f · C), where f is the switching frequency and C is the capacitance of the capacitor. When this is applied to the switched capacitor filters 5 and 6 in FIG. 3A, the cutoff frequency Fc of the switched capacitor filters 5 and 6 is obtained by the following equation (3).

  Fc = 1 / (2π · C2 · R) = (f · C1) / (2π · C2) (3)

  As shown in the above equation (3), the cutoff frequency Fc is determined by the switching frequency f and the capacitance ratio of the capacitor. Accordingly, by synchronizing (making proportional to) the switching frequency f with the excitation signal sin ωt of the resolver 100, even if the excitation signal sin ωt varies, the cutoff frequency Fc follows the variation. As a result, it is possible to prevent fluctuations in the signal gain and phase shift caused by the filter processing. That is, noise can be removed while suppressing detection errors.

  The capacitors used in the switched capacitor filters 5 and 6 are usually configured as a semiconductor integrated circuit (IC) and have a characteristic that the relative value accuracy is high although the variation in absolute value is large, so that two capacitors are used. As a result, variations in filter characteristics can be suppressed.

  The delta sigma modulator 10 has a sin phase signal sin θ · f (t + α) via a switched capacitor filter 6, and the delta sigma modulator 20 has a cos phase signal cos θ · f (via a switched capacitor filter 7). t + β) are respectively input. Hereinafter, digital data is represented by {...}, and bit stream data is represented by [...].

  The delta-sigma modulators 10 and 20 perform pulse density modulation on the input signals and convert them into 1-bit bit stream signals [sin θ · f (t + α)] and [cos θ · f (t + β)], respectively. FIG. 5 is a diagram illustrating a time change of signals input to the delta sigma modulators 10 and 20 and a time change of the bit stream signal output from the delta sigma modulators 10 and 20 together. As illustrated, when pulse density modulation is performed, the higher the input signal value, the higher the Hi signal density, and the lower the input signal value, the higher the Lo signal density.

  The output signal [sin θ · f (t + α)] of the delta sigma modulator 10 is multiplied by the output of the cos ROM 11 by the multiplier 12. The cos ROM 11 is fed back with the angle signal φ output from the counter circuit 32, and outputs a signal indicating cos φ with reference to the cos table stored in the ROM. Accordingly, the multiplier 12 outputs a multi-bit bit stream signal [cos φ · sin θ · f (t + α)].

  The output signal [cos θ · f (t + β)] of the delta sigma modulator 20 is multiplied by the output of the sin ROM 21 by the multiplier 22. The sin ROM 21 is fed back with the angle signal φ output from the counter circuit 32, and outputs a signal indicating sin φ with reference to a sin table stored in the ROM. Accordingly, the multiplier 22 outputs a multi-bit bit stream signal [sinφ · cos θ · f (t + β)].

  The digital filter 13 applies a technique such as obtaining a moving average with respect to the output of the multiplier 12, and the output [cosφ · sinθ · f (t + α)] of the multiplier 12 is converted into digital data {cosφ · sinθ · f (t + α)}. Demodulate. Similarly, the digital filter 23 applies a technique such as obtaining a moving average with respect to the output of the multiplier 22, and the output [sinφ · cos θ · f (t + β)] of the multiplier 22 is converted into digital data {sinφ · cos θ · f ( t + β)}.

  The synchronous detection unit 14 approximately divides the digital data {cosφ · sin θ · f (t + α)} by the reference data {F (t + α)} input from the detection signal generation unit 40 to approximate the excitation component of the resolver 100. Remove and output to the subtractor 30. Similarly, the synchronous detection unit 24 divides the digital data {sinφ · cos θ · f (t + β)} by the reference data {F (t + α)} input from the detection signal generation unit 40 to obtain the excitation component of the resolver 100. Approximate removal and output to the subtractor 30. The reference data {F (t + α)} is, for example, a binary signal having a value X and a value −X. Originally, the digital data is divided by a sine wave to remove the excitation component of the resolver 100. The positive part of the sine wave is the value X (Hi signal) and the negative part is the value -X (Lo signal). Even if it replaces with, it can remove an excitation component approximately. As the value X, for example, a value obtained by dividing an integral value of a sine wave from zero to π by a period π can be used.

  FIG. 6 is an explanatory diagram for explaining processing when the detection signal generation unit 40 generates the reference data {F (t + α)}. The processing for generating the reference data {F (t + β)} is performed in the same manner.

  The detection signal generator 40 generates an excitation signal clock based on the input excitation signal {f (t)}. Then, a leveled signal obtained by leveling the digital data {cosφ · sinθ · f (t + α)} is generated, and rises or falls at the point where the digital data {cosφ · sinθ · f (t + α)} and the leveled signal cross. Thus, reference data {F (t + α)} is generated.

  The rise and fall of the reference data {F (t + α)} is determined based on the excitation signal clock. For example, the section including the falling edge of the excitation signal clock (A in the figure) and the section including the rising edge (B in the figure) are set separately, and the digital data {cosφ · sinθ · When the leveling signal crosses f (t + α)}, the reference data {F (t + α)} falls at the crossing point. Conversely, if the digital data {cosφ · sinθ · f (t + α)} and the leveling signal cross in the section including the rising edge of the excitation signal clock, the reference data {F (t + α)} rises at the crossing point. . As described above, the detection signal generation unit 40 uses the excitation signal only for the selection of the rising edge and the falling edge, so that the generation of an error can be suppressed.

  The subtractor 30 calculates the difference between the outputs of the synchronous detectors 14 and 24 and outputs a control deviation ε = sin (θ−φ).

  In the counter circuit 32, the angle signal φ is increased or decreased so that the control deviation ε approaches zero. In the control of the angle signal φ, a proportional component, an integral component, a temporary delay component, and the like may be considered.

  In this way, since the input sin-phase signal and cos-phase signal are first converted into a bit stream signal and then multiplied by the cosine and sine of the angle signal, the calculation load related to multiplication is reduced and the calculation is performed. It is possible to suppress the occurrence of errors.

  According to the resolver / digital converter 1 of this embodiment described above, noise can be removed while suppressing detection errors.

  The best mode for carrying out the present invention has been described above with reference to the embodiments. However, the present invention is not limited to these embodiments, and various modifications can be made without departing from the scope of the present invention. And substitutions can be added.

  For example, the configurations of the delta-sigma modulators 10 and 20 and subsequent components that output the angle signal by calculating the outputs of the switched capacitor filters 6 and 7 are not limited to those of the embodiment, and various configurations can be adopted. Is possible.

  The present invention can be used in the automobile manufacturing industry, the automobile parts manufacturing industry, and the like.

1 Resolver / Digital Converter 5 PLL Circuit 5A Phase Comparator 5B Low Pass Filter 5C VCO
5D frequency divider 6, 7 Switched capacitor filter 10, 20 Delta sigma modulator 11 cosROM
12, 22 Multipliers 13, 23 Digital filters 14, 24 Synchronous detection unit 21 sinROM
30 Subtractor 32 Counter Circuit 40 Detection Signal Generation Unit 100 Resolver

Claims (1)

A switched capacitor filter to which a sin phase signal and a cos phase signal from the resolver are input;
Arithmetic processing means for arithmetically processing the output of the switched capacitor filter and outputting an angle signal;
A PLL (Phase-Locked Loop) circuit to which an excitation signal for exciting the resolver is input,
The switched capacitor is driven by a VCO (Voltage-Controlled Oscillator) included in the PLL circuit.
Resolver digital converter.