JP2010157587A - Semiconductor device, and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem wherein, in a semiconductor device where two or more transistors of the same conductivity type each having a high-k film and a metal gate electrode are formed in the same substrate, it is difficult to set the difference between threshold voltages larger than the difference between threshold voltages derived from the difference between impurity concentrations in channel regions. <P>SOLUTION: This semiconductor device includes a first transistor, and a second transistor of the same conductivity type as that of the first transistor. The first transistor includes a first gate insulation film 8a containing a high dielectric material and a first metal, and a first gate electrode 11a. The second transistor includes a second gate insulation film 8b containing a high dielectric material, a first metal and impurities for adjusting a threshold voltage, and a second gate electrode 11b. The first gate insulation film 8a is low in concentration of impurities for adjusting a threshold voltage relative to that of the second gate insulation film 8b, or does not contain the impurities for adjusting a threshold voltage. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method of manufacturing the same, and in particular, has the same high-k film (a gate insulating film containing a high dielectric material) and a metal gate electrode (a gate electrode made of a conductive film and a polysilicon film). The present invention relates to a semiconductor device in which two or more transistors of a conductive type are formed in the same substrate and a manufacturing method thereof.

  In recent years, a transistor using a high-k film and a metal gate electrode has been developed in order to improve the performance of the transistor. In a transistor using a high-k film and a metal gate electrode, a high threshold phenomenon called Fermi level pinning is a problem. However, in a semiconductor device having an N-type MISFET (Metal-Insulator-Semiconductor Field Effect Transistor) and a P-type MISFET, the N-type MISFET uses a high-k film containing lanthanum (La), and the P-type MISFET It is known that a threshold voltage can be reduced by using a high-k film containing aluminum (Al) (Patent Document 1).

  A semiconductor device in which two or more transistors having the same conductivity type but different threshold voltages are provided on the same substrate is also known. The structure of such a semiconductor device will be described with reference to FIG.

  FIG. 9 is a cross-sectional view of a conventional semiconductor device. In FIG. 9, “LNTr” shown on the left side indicates a first N-type MISFET formation region LNTr in which a first N-type MISFET having a relatively low threshold voltage is formed, and “HNTr” shown on the right side. Indicates a second N-type MISFET formation region HNTr in which a second N-type MISFET having a relatively high threshold voltage is formed.

  In the semiconductor device shown in FIG. 9, a buried element isolation (shallow trench isolation) 2 is formed on an upper portion of a semiconductor substrate 1 made of p-type silicon, whereby the semiconductor substrate 1 includes a first active region 1a and a first active region 1a. A second active region 1 b is formed via a buried element isolation region 2. A first p-type well region 3a is formed in the semiconductor substrate 1 including the first active region 1a, and a second p-type well region 3b is formed in the semiconductor substrate 1 including the second active region 1b. Has been. A first N-type MISFET is provided on the first active region 1a, and a second N-type MISFET is provided on the second active region 1b.

  The first N-type MISFET includes a first gate insulating film 98a formed on the first active region 1a, a first conductive film 9a and a first conductive film 9a sequentially formed on the first gate insulating film 98a. A first gate electrode 11a composed of a single silicon film 10a, a first sidewall 14a formed on a side surface of the first gate electrode 11a via a first offset spacer 12a, A first n-type extension region 13a having a relatively shallow junction depth formed in a region below the side of the first gate electrode 11a in the active region 1a, and a first sidewall 14a in the first active region 1a. First n-type source / drain region 15a having a relatively deep junction depth formed in a region on the outer side of the first n-type source region, and a first silicon layer on first n-type source / drain region 15a and first gate electrode 11a. A first silicide layer 16a formed on the silicon film 10a and a first p-type channel region Ra formed in a region immediately below the first gate electrode 11a in the first active region 1a. Yes.

  The second N-type MISFET includes a second gate insulating film 98b formed on the second active region 1b, a second conductive film 9b and a second conductive film 9b sequentially formed on the second gate insulating film 98b. A second gate electrode 11b composed of two silicon films 10b, a second sidewall 14b formed on the side surface of the second gate electrode 11b via a second offset spacer 12b, and a second A second n-type extension region 13b having a relatively shallow junction depth formed in a region below the second gate electrode 11b in the active region 1b, and a second sidewall 14b in the second active region 1b. A second n-type source / drain region 15b having a relatively deep junction depth formed in a region on the outer side of the second n-type electrode, and a second silicon layer on the second n-type source / drain region 15b and the second gate electrode 11b. A second silicide layer 16b formed on the silicon film 10b, and a second p-type channel region Rb formed in a region immediately below the second gate electrode 11b in the second active region 1b. Yes.

  In the configuration of the second N-type MISFET, the concentration of the p-type impurity in the second channel region Rb is higher than the concentration of the p-type impurity in the first channel region Ra as compared with the configuration of the first N-type MISFET. In other respects, the other configurations are substantially the same.

As described above, in the conventional semiconductor device, the concentration of the p-type impurity in the second channel region Rb is set higher than the concentration of the p-type impurity in the first channel region Ra, so that the threshold value of the first N-type MISFET is increased. A second N-type MISFET having a threshold voltage higher than the voltage is formed.
US 2007/0138563 A1

  However, in the semiconductor device shown in FIG. 9, the threshold voltage of the first transistor can only be made about 100 mV lower than the threshold voltage of the second transistor. Nowadays, the threshold voltage of the first transistor is made about 0.2 V lower than the threshold voltage of the second transistor (for example, the threshold voltage of the first transistor is set to 0.3 V, and the threshold voltage of the second transistor is set to 0). In the semiconductor device shown in FIG. 9, it is difficult to meet such a requirement.

  The present invention has been made to solve the above-described problems, and has as its object to form two or more transistors of the same conductivity type having a high-k film and a metal gate electrode on the same substrate. In the semiconductor device and the manufacturing method thereof, the threshold voltage difference of the transistor is made larger than the threshold voltage difference derived from the impurity concentration difference in the channel region.

  In order to achieve the above object, the present invention provides a semiconductor device in which two or more transistors of the same conductivity type having a high-k film and a metal gate electrode are formed in the same substrate, and a method for manufacturing the same. By changing the concentration of the substance whose voltage is changed in the high-k film or the kind of the substance for each transistor, the difference in threshold voltage of the transistor is larger than the difference in threshold voltage derived from the difference in impurity concentration in the channel region. It is an invention that can be done.

  A method for manufacturing a semiconductor device according to the present invention includes a first transistor provided on a first active region in a semiconductor region, and the same conductivity type as that provided on a second active region in the semiconductor region and the first transistor. And a second transistor manufacturing method. Specifically, the method for manufacturing a semiconductor device of the present invention includes a step (a) of forming a high dielectric film made of a high dielectric material on a semiconductor region, and a second active region of the high dielectric film. A step (b) of introducing a threshold voltage adjusting impurity into a portion provided on the first active region of the high dielectric film while introducing a threshold voltage adjusting impurity into the portion provided above; A step (c) of forming a first threshold voltage control film containing a first metal on the high dielectric film; and after the step (c), the first metal in the first threshold voltage control film is increased A step (d) of diffusing into the dielectric film, a step (e) of sequentially forming a conductive film and a silicon film on the high dielectric film, and patterning the silicon film, the conductive film and the high dielectric film, A first gate insulating film containing a high dielectric material and a first metal on the first active region; A first gate electrode having one silicon film and a first conductive film is formed, and a high dielectric material, a first metal, and a threshold voltage adjusting impurity are contained on the second active region. A step (f) of forming a second gate insulating film and a second gate electrode having a second silicon film and a second conductive film. The first gate insulating film has a lower concentration of threshold voltage adjusting impurities than the second gate insulating film or does not contain threshold voltage adjusting impurities.

  In a preferred embodiment described later, in step (b), nitrogen is introduced as the threshold voltage adjusting impurity. Nitrogen suppresses the introduction of the first metal into the high dielectric film. Therefore, in the step (d), the first metal diffuses to the portion of the high dielectric film provided on the first active region, but on the second active region of the high dielectric film. Difficult to diffuse into the provided part. Here, the first metal acts to lower the threshold voltage of the transistor. Thereby, the threshold voltage of the first transistor can be made lower than the threshold voltage of the second transistor.

  As described above, in a preferred embodiment described later, the concentration of nitrogen in the portion of the high dielectric film provided on the first active region is set to the concentration of nitrogen in the portion of the high dielectric film provided on the second active region. If the concentration is lower than the concentration of nitrogen, the concentration of the first metal in the portion of the high dielectric film provided on the first active region is provided on the second active region of the high dielectric film. The concentration of the first metal in the portion can be higher, and thus the threshold voltage of the first transistor can be lower than the second transistor threshold voltage. Accordingly, the difference between the threshold voltage of the first transistor and the threshold voltage of the second transistor can be made larger than the difference in threshold voltage derived from the difference in impurity concentration in the channel region.

  In another preferred embodiment described later, the high dielectric material is a metal oxide, metal oxynitride, or metal silicate containing a second metal, and in step (b), the second dielectric is used as a threshold voltage adjusting impurity. Introducing the metal. The second metal suppresses the introduction of the first metal into the high dielectric film. Therefore, in the step (d), the first metal diffuses to the portion of the high dielectric film provided on the first active region, but on the second active region of the high dielectric film. Difficult to diffuse into the provided part. Thereby, the threshold voltage of the first transistor can be made lower than the threshold voltage of the second transistor.

  In another preferred embodiment described later, in the step (b), a third metal is introduced as an impurity for adjusting the threshold voltage. The third metal acts to raise the threshold voltage in the opposite direction to the first metal having the action of lowering the threshold voltage. Therefore, the threshold voltage of the first transistor can be made lower than the second transistor threshold voltage.

  The semiconductor device thus manufactured has the following structural features.

  A semiconductor device according to the present invention includes a first transistor provided on a first active region in a semiconductor region, and a first transistor provided on a second active region in the semiconductor region and having the same conductivity type as the first transistor. 2 transistors. The first transistor is formed on the first active region, and includes a first gate insulating film containing a high dielectric material and a first metal, and a first gate insulating film formed on the first gate insulating film. A first gate electrode having a first conductive film and a first silicon film formed on the first conductive film. The second transistor is formed on the second active region, and includes a second gate insulating film containing a high dielectric material, a first metal, and a threshold voltage adjusting impurity, and a second gate insulating film. And a second gate electrode having a second conductive film made of the same material as the first conductive film and a second silicon film formed on the second conductive film. ing. The first gate insulating film has a lower concentration of the threshold voltage adjusting impurity than the second gate insulating film or does not contain the threshold voltage adjusting impurity.

  In the semiconductor device of the present invention, the threshold voltage of the first transistor is lower than the threshold voltage of the second transistor.

  In the semiconductor device of the present invention, the concentration of the first metal in the first gate insulating film is preferably higher than the concentration of the first metal in the second gate insulating film. Thereby, the threshold voltage of the first transistor can be made lower than the threshold voltage of the second transistor.

  In a preferred embodiment described later, the threshold voltage adjusting impurity is nitrogen.

  In another preferred embodiment described below, the high dielectric material is a metal oxide, metal oxynitride or metal silicate containing a second metal, and the threshold voltage adjusting impurity is the second metal, The concentration of the second metal in the first gate insulating film is lower than the concentration of the second metal in the second gate insulating film. Here, the second metal is hafnium.

  In another preferred embodiment described later, the threshold voltage adjusting impurity is a third metal, and the second gate insulating film contains the third metal, while the first gate insulating film is the third metal. Contains no metal. At this time, when each of the first transistor and the second transistor is an N-type MIS transistor, the third metal is preferably aluminum. In addition, when each of the first transistor and the second transistor is a P-type MIS transistor, it is preferable that the third metal is at least one of a lanthanoid element, scandium, strontium, and magnesium.

  In the semiconductor device of the present invention, when each of the first transistor and the second transistor is an N-type MIS transistor, the first metal is preferably at least one of a lanthanoid element, scandium, strontium, and magnesium. . When the first transistor and the second transistor are P-type MIS transistors, the first metal is preferably aluminum.

  According to the semiconductor device and the manufacturing method thereof according to the present invention, the difference in threshold voltage of the transistor is changed by changing the concentration of the substance that changes the threshold voltage of the transistor in the high-k film or the type of the substance for each transistor. The threshold voltage difference can be made larger than the difference in impurity concentration in the channel region. Therefore, two or more transistors having the same conductivity type but different threshold voltages can be formed in the same substrate.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, this invention is not limited to embodiment shown below. For example, the film thickness and the like are not limited to the numerical values shown below, and the film forming method and the etching method are not limited to the methods shown below. Moreover, below, the same code | symbol may be attached | subjected with respect to the same member, and description may be abbreviate | omitted.

<< First Embodiment >>
A first embodiment of the present invention will be described with reference to the drawings. FIG. 1A to FIG. 1E and FIG. 2A to FIG. 2C are cross-sectional views showing a method of manufacturing a semiconductor device according to this embodiment in the order of steps. In FIG. 1A and FIG. 2A, “LNTr” shown on the left side is a first N-type MISFET (first transistor) having a relatively low threshold voltage. The “HNTr” shown on the right side indicates the second N-type MISFET formation region HNTr in which the second N-type MISFET (second transistor) having a relatively high threshold voltage is formed. ing.

  First, in the process shown in FIG. 1A, an element isolation region 2 in which an insulating film is embedded in a trench above a semiconductor substrate 1 made of p-type silicon by an embedded element isolation (Shallow Trench Isolation: STI) method. Are selectively formed. As a result, the first active region 1a made of the semiconductor substrate 1 surrounded by the element isolation region 2 is formed in the first N-type MISFET formation region LNTr, and the second N-type MISFET formation region HNTr has A second active region 1b made of the semiconductor substrate 1 surrounded by the element isolation region 2 is formed. Thereafter, a p-type impurity is implanted into the semiconductor substrate 1 to form a first p-type well region 3a in the first N-type MISFET formation region LNTr and a second p-type in the second N-type MISFET formation region HNTr. Well region 3b is formed. At this time, although not shown, the p-type impurity concentration in the region serving as the first channel region and the p-type impurity concentration in the region serving as the second channel region are the same. In the present embodiment, the first p-type well region 3a and the second p-type well region 3b are separately described. However, the first p-type well region 3a and the second p-type well region 3b are formed of well regions having substantially the same impurity concentration.

  Thereafter, a base film (not shown) made of silicon oxynitride (SiON) and having a thickness of 1.6 nm is formed on the entire top surface of the semiconductor substrate 1. Thereafter, a high dielectric film 4 made of hafnium silicate (HfSiON) and having a thickness of 2 nm is formed on the base film by, for example, metal organic chemical vapor deposition (MOCVD) (step (a) )). As the high dielectric film 4, an insulating film having a relative dielectric constant larger than that of a silicon oxide film or silicon oxynitride film is used, and a metal oxide, metal oxynitride, silicate, or nitrogen-containing silicate having a relative dielectric constant of 8 or more is used. An insulating film made of a high dielectric material is used. Examples of the high dielectric material include oxides of metals such as hafnium (Hf), zirconium (Zr), and yttrium (Y), oxynitrides, silicates, and nitrogen-containing silicates. The above-described HfSiON is one example. is there. Thereafter, the protective film 5 made of, for example, titanium nitride (TiN) and having a thickness of 30 nm is formed on the high dielectric film 4 by, for example, physical vapor deposition (PVD).

  Next, in the step shown in FIG. 1B, the portion of the protective film 5 formed on the first active region 1a is covered by photolithography, while the second active region 1b of the protective film 5 is covered. A resist 6 is formed so as to expose the portion formed above. Thereafter, using the resist 6 as a mask, the protective film 5 is etched using an APM (ammonia hydrogen peroxide mixture) solution or an SPM (sulfuric acid hydrogen peroxide mixture) solution. As a result, a protective mask 5A which is a part of the protective film 5 is formed on the portion of the high dielectric film 4 formed on the first active region 1a, while the second of the high dielectric film 4 is the second. The portion formed on the active region 1b is exposed from the protective mask 5A. Thereafter, the resist 6 is removed.

  Subsequently, in the step shown in FIG. 1C, surface treatment is performed on the high dielectric film 4. Specifically, the surface of the high dielectric film 4 is nitrided by, for example, plasma nitriding. At this time, a protective mask 5A is formed on the portion of the high dielectric film 4 formed on the first active region 1a. Therefore, nitrogen is not introduced into the portion of the high dielectric film 4 formed on the first active region 1a, but the portion of the high dielectric film 4 formed on the second active region 1b Nitrogen is introduced (step (b)). As a result, a high dielectric film (a part of the high dielectric film 4) 4A having a low concentration of the threshold voltage adjusting impurity is formed on the first active region 1a, while on the second active region 1b. A high dielectric film 4B having a high concentration of the threshold voltage adjusting impurity is formed.

  At this time, when a high-dielectric film containing nitrogen (for example, an HfSiON film) is used as the high-dielectric film 4 as described above, the high-dielectric film 4A having a low threshold voltage adjustment impurity concentration is a The high dielectric film 4B containing nitrogen derived from No. 4 and having a high concentration of threshold voltage adjusting impurities was introduced not only by nitrogen derived from the high dielectric film 4 but also by the nitriding treatment in FIG. It also contains nitrogen. That is, in this case, the high dielectric film 4A having a low threshold voltage adjustment impurity concentration contains nitrogen, and the nitrogen concentration is higher in the high dielectric film 4A having a lower threshold voltage adjustment impurity concentration. The concentration of the voltage adjusting impurity is lower than that of the high dielectric film 4B.

When a high dielectric film that does not contain nitrogen (for example, an HfO ₂ film) is used as the high dielectric film 4, the high dielectric film 4A having a low threshold voltage adjusting impurity concentration does not contain nitrogen. The high dielectric film 4B having a high concentration of the threshold voltage adjusting impurity contains nitrogen introduced by the nitriding process in FIG. That is, in this case, the high dielectric film 4B having a high concentration of the threshold voltage adjusting impurity contains nitrogen, but the high dielectric film 4A having a low concentration of the threshold voltage adjusting impurity contains nitrogen. Absent.

  Thereafter, the protective mask 5A is removed using an APM solution or an SPM solution. As described above, in the protective mask 5A, a portion of the high dielectric film 4 located immediately below the protective mask 5A (a portion formed on the first active region 1a of the high dielectric film 4) is nitrided. In other words, it is a mask for preventing nitrogen from being introduced into a portion of the high dielectric film 4 located immediately below the protective mask 5A. Further, since the protective mask 5A is removed after the nitriding step is completed, in order to remove only the protective mask 5A without removing the high dielectric film 4, a high selectivity with respect to the high dielectric film 4 is obtained. It is preferable to consist of the material which has. As described above, the protective mask 5A is not limited to the titanium nitride film, and may be a tantalum nitride (TaN) film.

1D, on the high dielectric film 4A having a low threshold voltage adjustment impurity concentration and on the high dielectric film 4B having a high threshold voltage adjustment impurity concentration, For example, the first threshold voltage control film 7 made of La ₂ O ₃ and having a thickness of several tens (for example, 0.5 nm) is formed by a chemical vapor deposition (CVD) method (step (c)). . The first threshold voltage control film 7 is not limited to the La ₂ O ₃ film, and may be a film containing the first metal. The first metal in the present embodiment is a metal that lowers the threshold voltage of the N-type MISFET when introduced into the high dielectric film. The first metal in the present embodiment includes a lanthanoid such as lanthanum (La). Examples of the metal include scandium (Sc), strontium (Sr), and magnesium (Mg). Therefore, the first threshold voltage control film 7 only needs to contain at least one of a lanthanoid metal, scandium, strontium, and magnesium, and may be a La film, for example.

  Subsequently, in the step shown in FIG. 1E, the semiconductor substrate 1 is subjected to a heat treatment, for example, at 800 ° C. for 10 minutes (step (d)). As a result, the first high dielectric film 8A is formed on the first active region 1a, and the second high dielectric film 8B is formed on the second active region 1b.

  At this time, by the nitriding process shown in FIG. 1C, the first metal (lanthanum in this embodiment) is changed from the first threshold voltage control film 7 to the high dielectric film having a low concentration of the threshold voltage adjusting impurity. Although it is diffused to 4A, it is difficult to diffuse to the high dielectric film 4B having a high concentration of the threshold voltage adjusting impurity. In other words, the first metal is transferred from the first threshold voltage control film 7 to the portion of the high dielectric film 4 formed on the second active region 1b in the step shown in FIG. In order to suppress the diffusion, the surface of the portion of the high dielectric film 4 formed on the second active region 1b is nitrided in the step shown in FIG. Thus, the concentration of the first metal in the first high dielectric film 8A is higher than the concentration of the first metal in the second high dielectric film 8B.

The first high dielectric film 8A is obtained by introducing the first metal into the high dielectric film 4A having a low concentration of the threshold voltage adjusting impurity, and the second high dielectric film 8B has the threshold voltage adjustment. The first metal is introduced into the high dielectric film 4B having a high impurity concentration. Therefore, when a high dielectric film (for example, HfSiON film) containing nitrogen is used as the high dielectric film 4, the first high dielectric film 8A contains nitrogen, and the nitrogen concentration is the first concentration. The high dielectric film 8A is lower than the second high dielectric film 8B. On the other hand, when a high-dielectric film that does not contain nitrogen (for example, an HfO ₂ film) is used as the high-dielectric film 4, the first high-dielectric film 8A does not contain nitrogen, and the second high-dielectric film The dielectric film 8B contains nitrogen.

  Depending on the heat treatment conditions in this heat treatment step, the first metal may be present in the first high dielectric film 8A in a uniform mixture with the high dielectric material constituting the high dielectric film 4. For example, it may exist in a layered manner, may exist in the upper part thereof, or may settle in the lower part thereof. The same can be said for the diffusion of the first metal in the second high dielectric film 8B.

  Also, depending on the heat treatment conditions in this heat treatment step, when the heat treatment step is completed, the first threshold voltage control film 7 may disappear as shown in FIG. The threshold voltage control film 7 may remain and be integrated with the high dielectric film 4A having a low concentration of the threshold voltage adjusting impurity and the high dielectric film 4B having a high concentration of the threshold voltage adjusting impurity.

  Subsequently, in the process shown in FIG. 2A, the first high dielectric film 8A and the second high dielectric film 8B are formed on the first high dielectric film 8B and made of TaN, for example, with a film thickness of 20 nm. A conductive film 9 is formed. Thereafter, a silicon film 10 having a thickness of 90 nm is formed on the conductive film 9 (step (e)). Thereafter, the silicon film 10, the conductive film 9, the first high dielectric film 8A, and the second high dielectric film 8B are patterned by dry etching using a resist having a gate pattern shape (not shown). . Thereby, on the first active region 1a, the first gate insulating film 8a composed of the first base film and the first high dielectric film 8A, the first conductive film 9a, and the first conductive film are sequentially formed. The first gate electrode 11a made of the silicon film 10a is formed. On the other hand, on the second active region 1b, a second gate insulating film 8b composed of a second base film and a second high dielectric film 8B, a second conductive film 9b, and a second conductive film are sequentially formed. A second gate electrode 11b made of the silicon film 10b is formed (step (f)).

  2B, a silicon oxide film is formed on the entire upper surface of the semiconductor substrate 1, and then anisotropic etching is performed on the silicon oxide film. As a result, first and second offset spacers 12a and 12b are formed on the side surfaces of the first and second gate electrodes 11a and 11b, respectively. Thereafter, an n-type impurity is implanted into a region of the first active region 1a laterally below the first gate electrode 11a to form the first n-type extension region 13a, while the second active region 1b A second n-type extension region 13b is formed by implanting an n-type impurity into a region below the side of the second gate electrode 11b.

  2C, a silicon nitride film is formed on the entire top surface of the semiconductor substrate 1, and then anisotropic etching is performed on the silicon nitride film. As a result, the first sidewall 14a is formed on the side surface of the first gate electrode 11a via the first offset spacer 12a, while the second offset spacer 12b is formed on the side surface of the second gate electrode 11b. A second sidewall 14b is formed through the gap. Thereafter, an n-type impurity is implanted into a region of the first active region 1a outside the first sidewall 14a to form a first n-type source / drain region 15a, while in the second active region 1b An n-type impurity is implanted into a region below the second sidewall 14b to form a second n-type source / drain region 15b. Thereafter, a first silicide layer 16a made of nickel silicide or the like is formed on the upper portion of the first silicon film 10a of the first gate electrode 11a and the upper portion of the first n-type source / drain region 15a to form the second gate. A second silicide layer 16b made of nickel silicide or the like is formed on the second silicon film 10b of the electrode 11b and on the second n-type source / drain region 15b. In this manner, a semiconductor device in which the first N-type MISFET is formed on the first active region 1a and the second N-type MISFET is formed on the second active region 1b is obtained.

  As described above, in the method of manufacturing the semiconductor device according to this embodiment, in the step shown in FIG. 1C, the high dielectric film having a low threshold voltage adjusting impurity concentration is formed on the first active region 1a. 4A is formed, and a high dielectric film 4B having a high concentration of the threshold voltage adjusting impurity is formed on the second active region 1b. The threshold voltage adjusting impurity in this embodiment suppresses the introduction of the first metal into the high dielectric film. Therefore, in the step shown in FIG. 1E, the first metal diffuses from the first threshold voltage control film 7 to the high dielectric film 4A where the concentration of the threshold voltage adjusting impurity is low, while the first threshold voltage is increased. Difficult to diffuse from the voltage control film 7 to the high dielectric film 4B having a high concentration of the threshold voltage adjusting impurity. Therefore, the concentration of the first metal in the first high dielectric film 8A is higher than the concentration of the first metal in the second high dielectric film 8B. Thereafter, in the step shown in FIG. 2A, the first high dielectric film 8A becomes a part of the first gate insulating film 8a, and the second high dielectric film 8B becomes a part of the second gate insulating film 8b. Therefore, the concentration of the first metal in the first gate insulating film 8a is higher than the concentration of the first metal in the second gate insulating film 8b. When the first metal in the present embodiment is diffused into the high dielectric film, the threshold voltage of the N-type MISFET is lowered. As described above, in the method for manufacturing a semiconductor device according to the present embodiment, the threshold voltage of the first N-type MISFET formed on the first active region 1a is set to the second value formed on the second active region 1b. It can be lower than the threshold voltage of the N-type MISFET.

  In the method for manufacturing a semiconductor device according to the present embodiment, the concentration of the first metal in the first gate insulating film 8a of the first N-type MISFET is set to the second gate insulating film 8b of the second N-type MISFET. The concentration of the first metal in can be higher. Therefore, a method of making the concentration of the p-type impurity in the first channel region of the first N-type MISFET lower than the concentration of the p-type impurity in the second channel region of the second N-type MISFET (conventional method) As compared with the above, the difference between the threshold voltage of the first N-type MISFET formed on the first active region 1a and the threshold voltage of the second N-type MISFET formed on the second active region 1b is increased. can do. For example, in the conventional method, the difference can only be about 100 mV, but in the present embodiment, the difference can be expanded to about 0.2V.

  Furthermore, in the method for manufacturing a semiconductor device according to the present embodiment, the first threshold voltage control film 7 is formed as a method for lowering the threshold voltage of the first N-type MISFET than the threshold voltage of the second N-type MISFET. Prior to this, a method is described in which the surface of the portion of the high dielectric film 4 formed on the second active region 1b is nitrided. Therefore, if this nitriding step and the resist forming step accompanying this nitriding step are performed, the threshold voltage of the first N-type MISFET formed on the first active region 1a and the second active region 1b The difference from the threshold voltage of the formed second N-type MISFET can be made larger than the conventional one. Therefore, two identical conductivity type transistors having a larger threshold voltage difference than the conventional one can be formed in the same substrate without complicating the manufacturing process of the semiconductor device.

  FIG. 3 is a cross-sectional view of the semiconductor device according to the present embodiment. When a semiconductor device is manufactured according to the above manufacturing method, the obtained semiconductor device has the following configuration.

  As shown in FIG. 3, an element in which an insulating film is embedded in a trench so as to partition a first active region 1a and a second active region 1b above a semiconductor substrate 1 made of p-type silicon. An isolation region 2 is formed. The semiconductor substrate 1 including the first active region 1a has a first p-type well region 3a formed deeper than the element isolation region 2, and the semiconductor substrate 1 including the second active region 1b includes The second p-type well region 3 b is formed to a position deeper than the element isolation region 2. The semiconductor device according to the present embodiment includes a first N-type MISFET provided on the first active region 1a of the first N-type MISFET formation region LNTr and a second of the second N-type MISFET formation region HNTr. And a second N-type MISFET provided on the active region 1b.

  The first N-type MISFET includes a first gate insulating film 8a formed on the first active region 1a, and a first conductive film 9a (tantalum nitride) formed on the first gate insulating film 8a. A first gate electrode 11a composed of a first silicon film 10a (polysilicon film, film thickness 90 nm) formed on the first conductive film 9a; The first side wall 14a formed on the side surface of the first gate electrode 11a via the first offset spacer 12a, and the first active region 1a is formed in a region below the side of the first gate electrode 11a. The first n-type extension region 13a having a relatively shallow junction depth and the first junction region having a relatively deep junction depth formed in a region outside the first sidewall 14a in the first active region 1a. 1 n-type source drain Includes a down region 15a, and a first silicide layer 16a formed on the upper of the on the first n-type source drain region 15a first silicon film 10a of the first gate electrode 11a.

  The first gate insulating film 8a contains a first base film (not shown) made of silicon oxynitride, which is sequentially formed from the lower side (first active region 1a side), and a first metal. And a first high dielectric film made of hafnium nitride silicate.

  The second N-type MISFET includes a second gate insulating film 8b formed on the second active region 1b, and a second conductive film 9b (tantalum nitride) formed on the second gate insulating film 8b. A second gate electrode 11b composed of a second silicon film 10b (polysilicon film, film thickness: 90 nm) formed on the second conductive film 9b; The second side wall 14b formed on the side surface of the second gate electrode 11b via the second offset spacer 12b, and the second active region 1b is formed in a region below the side of the second gate electrode 11b. The second n-type extension region 13b having a relatively shallow junction depth and the second junction region having a relatively deep junction depth formed in a region outside the second sidewall 14b in the second active region 1b. 2 n-type source drain Includes a down region 15b, and a second silicide layer 16b formed on the upper of the on the second n-type source drain region 15b second silicon film 10b of the second gate electrode 11b.

  The second gate insulating film 8b includes a second base film (not shown) made of silicon oxynitride, which is sequentially formed from the lower side (second active region 1b side), a first metal, and nitrogen ( And a second high dielectric film made of hafnium nitride silicate containing a threshold voltage adjusting impurity).

  The first N-type MISFET and the second N-type MISFET have the same p-type impurity concentration in the channel region, but the nitrogen concentration and the first metal concentration in the gate insulating film are different from each other. Specifically, when a material containing nitrogen is used as the high dielectric material, the first gate insulating film 8a contains nitrogen, and the nitrogen concentration of the first gate insulating film 8a is higher than that of the first gate insulating film 8a. 2 and lower than the gate insulating film 8b. When a material not containing nitrogen is used as the high dielectric material, the first gate insulating film 8a does not contain nitrogen, and the second gate insulating film 8b contains nitrogen. The concentration of the first metal in the first gate insulating film 8a is higher than the concentration of the first metal in the second gate insulating film 8b. Examples of the first metal in the present embodiment include lanthanoid metals such as lanthanum (La), scandium (Sc), strontium (Sr), and magnesium (Mg).

  As described above, in the semiconductor device according to the present embodiment, the concentration of the first metal in the first gate insulating film 8a is higher than the concentration of the first metal in the second gate insulating film 8b. Here, the first metal acts so as to lower the threshold voltage of the N-type MISFET when introduced into the high dielectric film. Therefore, in the semiconductor device according to the present embodiment, the threshold voltage of the first N-type MISFET formed on the first active region 1a is set to the threshold voltage of the second N-type MISFET formed on the second active region 1b. It can be lower than the threshold voltage.

  In the semiconductor device according to the present embodiment, the threshold voltage of the first N-type MISFET formed on the first active region 1a and the second N-type MISFET formed on the second active region 1b are used. The difference from the threshold voltage can be made larger than that in the conventional semiconductor device in which the p-type impurity concentration in the first channel region is lower than the p-type impurity concentration in the second channel region.

  In addition, this embodiment may have the structure shown below.

  The number of MISFETs is not limited to two as long as it is two or more. This can be said also in first to fifth modifications described later.

  In the semiconductor device manufacturing method according to the present embodiment, the first threshold voltage control film may be formed before the high dielectric film is formed. This can be said also in the first modification described later.

  In the present embodiment, nitrogen has been described as an example of the threshold voltage adjustment impurity, but the threshold voltage adjustment impurity is not limited to nitrogen. Another example of the threshold voltage adjusting impurity is shown in the following first modification, a second modification described later, and a third modification described later.

(First modification)
FIGS. 4A to 4E are cross-sectional views for explaining the manufacturing method of the semiconductor device according to the first modification in the order of steps, and “LNTr” and “PNTr” in FIG. As described in the first embodiment. The threshold voltage adjusting impurity in the present modification is a metal (second metal) constituting the high dielectric material, for example, hafnium. In the following, points different from the first embodiment will be described mainly.

  First, in the step shown in FIG. 4A, the portion of the high dielectric film 4 formed on the second active region 1b is replaced with the step shown in FIGS. 1A and 1B. It is exposed from the protective mask 5A.

  Next, in the step shown in FIG. 4B, after the resist 6 is removed, hafnium serving as a threshold voltage adjusting impurity is introduced into the high dielectric film 4 by, for example, sputtering (step (b)). At this time, the protective mask 5A is formed on the portion of the high dielectric film 4 formed on the first active region 1a. Therefore, hafnium is not introduced into the portion of the high dielectric film 4 formed on the first active region 1a, but the portion of the high dielectric film 4 formed on the second active region 1b Hafnium is introduced. As a result, a high dielectric film (a part of the high dielectric film 4) 24A having a low concentration of the threshold voltage adjusting impurity (hafnium) is formed on the first active region 1a, while the second active region 1b. A high dielectric film 24B having a high concentration of the threshold voltage adjusting impurity is formed thereon.

  At this time, when a high dielectric film containing hafnium is used as the high dielectric film 4 and hafnium is used as the threshold voltage adjustment impurity, the high dielectric film 24A having a low concentration of the threshold voltage adjustment impurity is a high dielectric film. The high dielectric film 24B containing hafnium derived from the film 4 and having a high threshold voltage adjusting impurity concentration was introduced not only by hafnium derived from the high dielectric film 4 but also by sputtering in FIG. 4B. It also contains hafnium. That is, in this case, the high dielectric film 24A having a low threshold voltage adjusting impurity concentration contains hafnium, and the hafnium concentration is lower in the high dielectric film 24A having a lower threshold voltage adjusting impurity concentration. The concentration of the voltage adjusting impurity is lower than that of the high dielectric film 24B.

  Further, when a high dielectric film containing, for example, zirconium or yttrium instead of hafnium is used as the high dielectric film 4 and hafnium is used as the threshold voltage adjusting impurity, the high dielectric film having a low concentration of the threshold voltage adjusting impurity is low. 24A does not contain hafnium, and the high dielectric film 24B having a high concentration of the threshold voltage adjusting impurity contains hafnium introduced by sputtering in FIG. 4B. That is, in this case, the high dielectric film 24B having a high threshold voltage adjustment impurity concentration contains hafnium, but the high dielectric film 24A having a low threshold voltage adjustment impurity concentration contains hafnium. Absent.

Subsequently, in the step shown in FIG. 4C, after removing the protective mask 5A, the high dielectric film 24A on which the concentration of the threshold voltage adjusting impurity is low and the high dielectric material having a high threshold voltage adjusting impurity concentration are formed. A first threshold voltage control film 7 made of La ₂ O ₃ and having a thickness of 0.5 nm is formed on the film 24B by, eg, chemical vapor deposition (step (c)).

  Subsequently, in the step shown in FIG. 4D, the semiconductor substrate 1 is subjected to a heat treatment, for example, at 800 ° C. for 10 minutes (step (d)). As a result, a first high dielectric film 28A is formed on the first active region 1a, and a second high dielectric film 28B is formed on the second active region 1b.

  At this time, by introducing hafnium in the step shown in FIG. 4B, the first metal (lanthanum in this modification) has a threshold voltage adjusting impurity concentration from the first threshold voltage control film 7. Although it diffuses to the low high dielectric film 24A, it is difficult to diffuse to the high dielectric film 24B where the concentration of the threshold voltage adjusting impurity is high. In other words, the first metal is transferred from the first threshold voltage control film 7 to the portion of the high dielectric film 4 formed on the second active region 1b in the step shown in FIG. In order to suppress the diffusion, hafnium is introduced into the portion of the high dielectric film 4 formed on the second active region 1b in the step shown in FIG. 4B. Thereby, the concentration of the first metal in the first high dielectric film 28A is higher than the concentration of the first metal in the second high dielectric film 28B.

  Further, the first high dielectric film 28A is obtained by introducing the first metal into the high dielectric film 24A having a low concentration of the threshold voltage adjusting impurity, and the second high dielectric film 28B has the threshold voltage adjustment. The first metal is introduced into the high dielectric film 24B having a high impurity concentration. Therefore, when a high dielectric film containing hafnium is used as the high dielectric film 4 and hafnium is used as the threshold voltage adjusting impurity, the first high dielectric film 28A contains hafnium. The concentration of the first high dielectric film 28A is lower than that of the second high dielectric film 28B. On the other hand, when a high dielectric film containing zirconium or yttrium instead of hafnium is used as the high dielectric film 4 and hafnium is used as the threshold voltage adjusting impurity, the first high dielectric film 28A contains hafnium. However, the second high dielectric film 28B contains hafnium.

  If the heat treatment conditions in the heat treatment process are different, the degree of diffusion of the first metal in the first high dielectric film 28A and the second high dielectric film 28B is changed, and the heat treatment conditions in the heat treatment process are different. For example, the presence / absence of the first threshold voltage control film 7 changes as described in the first embodiment.

  Thereafter, the step shown in FIG. 2A in the first embodiment is performed. Thus, the first high dielectric film 28A becomes the first gate insulating film 28a, and the second high dielectric film 28B becomes the second gate insulating film 28b. Then, by sequentially performing the steps shown in FIGS. 2B and 2C in the first embodiment, the semiconductor device shown in FIG. 4E can be manufactured.

  In the semiconductor device shown in FIG. 4E, the p-type impurity concentration in the channel region is the same in the first N-type MISFET and the second N-type MISFET, but the hafnium concentration in the gate insulating film and the first n-type MISFET The concentrations of the metals are different from each other. When the high dielectric material contains hafnium, the first gate insulating film 28a contains hafnium, and the hafnium concentration is lower in the first gate insulating film 28a than in the second gate insulating film 28b. On the other hand, when the high dielectric material contains zirconium or yttrium instead of hafnium, the first gate insulating film 28a does not contain hafnium, and the second gate insulating film 28b contains hafnium. . Further, the concentration of the first metal in the first gate insulating film 28a is higher than the concentration of the first metal in the second gate insulating film 28b.

  As described above, in the method for manufacturing a semiconductor device according to this modification, in the step shown in FIG. 4B, the high dielectric film having a low concentration of the threshold voltage adjusting impurity is formed on the first active region 1a. 24A is formed, and a high dielectric film 24B having a high concentration of the threshold voltage adjusting impurity is formed on the second active region 1b. The threshold voltage adjusting impurity (specifically hafnium) in the present modification suppresses the introduction of the first metal into the high dielectric film, as in the first embodiment. Therefore, in the process shown in FIG. 4D, the first metal diffuses from the first threshold voltage control film 7 to the high dielectric film 24A where the concentration of the threshold voltage adjusting impurity is low. Diffusing from the threshold voltage control film 7 to the high dielectric film 24B having a high concentration of the threshold voltage adjusting impurity is difficult. Therefore, in the semiconductor device according to this modification, the concentration of the first metal in the first gate insulating film 28a is set to the first concentration in the second gate insulating film 28b, as in the semiconductor device according to the first embodiment. It can be higher than the metal concentration. Thereby, in this modification, the same effect as that described in the first embodiment can be obtained.

(Second modification)
FIG. 5A to FIG. 5E are cross-sectional views for explaining the manufacturing method of the semiconductor device according to the second modification in the order of steps, and “LNTr” and “HNTr” in FIG. As described in the first embodiment. The threshold voltage adjusting impurity in the present modification is a metal (third metal) having an action of raising the threshold voltage in the opposite direction to the first metal having an action of lowering the threshold voltage in the N-type MISFET. For example, aluminum. In the following, points different from the first embodiment will be described mainly.

  First, in the step shown in FIG. 5A, the portion of the high dielectric film 4 formed on the second active region 1b is replaced with the step shown in FIGS. 1A and 1B. It is exposed from the protective mask 5A.

  Next, in the step shown in FIG. 5B, after the resist 6 is removed, aluminum serving as a threshold voltage adjusting impurity is introduced into the semiconductor substrate 1 by, for example, a sputtering method (step (b)). At this time, the protective mask 5A is formed on the portion of the high dielectric film 4 formed on the first active region 1a. Therefore, aluminum is not introduced into the portion of the high dielectric film 4 formed on the first active region 1a, but the portion of the high dielectric film 4 formed on the second active region 1b Aluminum is introduced. As a result, in the present modification, a high dielectric film (a part of the high dielectric film 4) 34A having a low concentration of the threshold voltage adjusting impurity is formed on the first active region 1a, while the second active region 1a is formed. A high dielectric film 34B having a high concentration of the threshold voltage adjusting impurity is formed on the region 1b.

At this time, when a high dielectric film (for example, HfAlO ₂ film) containing aluminum is used as the high dielectric film 4, the high dielectric film 34 A having a low threshold voltage adjustment impurity concentration is derived from the high dielectric film 4. The high dielectric film 34B having a high threshold voltage adjusting impurity concentration contains not only aluminum derived from the high dielectric film 4 but also aluminum introduced by sputtering in FIG. 5B. ing. That is, in this case, the high dielectric film 34A having a low threshold voltage adjusting impurity concentration contains aluminum, and the aluminum concentration is higher in the high dielectric film 34A having a lower threshold voltage adjusting impurity concentration. The concentration of the threshold voltage adjusting impurity is lower than that of the high dielectric film 34B.

  When a high dielectric film (for example, HfSiON film) that does not contain aluminum is used as the high dielectric film 4, the high dielectric film 34A having a low concentration of the threshold voltage adjusting impurity does not contain aluminum. The high dielectric film 34B having a high concentration of the voltage adjusting impurity contains aluminum introduced by sputtering in FIG. That is, in this case, the high dielectric film 34B having a high concentration of the threshold voltage adjusting impurity contains aluminum, but the high dielectric film 34A having a low concentration of the threshold voltage adjusting impurity contains aluminum. Absent.

5C, after the protective mask 5A is removed, the high dielectric film 34A having a low threshold voltage adjustment impurity concentration and a high dielectric constant having a high threshold voltage adjustment impurity concentration. A first threshold voltage control film 7 made of La ₂ O ₃ and having a thickness of 0.5 nm is formed on the body film 34B by, eg, chemical vapor deposition (step (c)).

  Subsequently, in the step shown in FIG. 5D, the semiconductor substrate 1 is subjected to a heat treatment at 800 ° C. for 10 minutes, for example (step (d)). As a result, a first high dielectric film 38A is formed on the first active region 1a, and a second high dielectric film 38B is formed on the second active region 1b.

  At this time, in the present modification, the portion of the high dielectric film 4 formed on the second active region 1b is not subjected to the nitriding treatment in the first embodiment, and the first The introduction of hafnium in the first modification is not performed. Therefore, the first metal (lanthanum in the present embodiment) is not only diffused from the first threshold voltage control film 7 to the high dielectric film 34A having a low concentration of threshold voltage adjustment impurities, but also for threshold voltage adjustment. It is also diffused into the high dielectric film 34B having a high impurity concentration. Therefore, the concentration of the first metal in the first high dielectric film 38A is substantially the same as the concentration of the first metal in the second high dielectric film 38B.

The first high dielectric film 38A is formed by diffusing the first metal into the high dielectric film 34A having a low threshold voltage adjusting impurity concentration, and the second high dielectric film 38B is formed as follows. The first metal is diffused into the high dielectric film 34B having a high concentration of the threshold voltage adjusting impurity. Therefore, when a high dielectric film (for example, HfAlO ₂ film) containing aluminum is used as the high dielectric film 4, the first high dielectric film 38A contains aluminum, and the aluminum concentration is the first concentration. The first high dielectric film 38A is lower than the second high dielectric film 38B. On the other hand, when a high dielectric film not containing aluminum (for example, HfSiON film) is used as the high dielectric film 4, the first high dielectric film 38A does not contain aluminum, but the second high dielectric film The body film 38B contains aluminum.

  If the heat treatment conditions in this heat treatment process are different, the degree of diffusion of the first metal in the first high dielectric film 38A and the second high dielectric film 38B changes, and the heat treatment conditions in the heat treatment process are different. For example, the presence / absence of the first threshold voltage control film 7 changes as described in the first embodiment.

  Further, depending on the heat treatment conditions in this heat treatment step, aluminum may be present in the second high dielectric film 38B evenly mixed with the high dielectric material constituting the high dielectric film 4 in some cases. In some cases, it may be present in a layered manner, in many cases in the upper part thereof, and in some cases it may settle in the lower part thereof.

  Thereafter, the step shown in FIG. 2A in the first embodiment is performed. Thereby, the first high dielectric film 38A becomes the first gate insulating film 38a, and the second high dielectric film 38B becomes the second gate insulating film 38b. Thereafter, by sequentially performing the steps shown in FIGS. 2B and 2C in the first embodiment, the semiconductor device shown in FIG. 5E can be manufactured.

  In the semiconductor device shown in FIG. 5E, the first N-type MISFET and the second N-type MISFET have the same p-type impurity concentration in the channel region and the first metal concentration in the gate insulating film. The concentrations of aluminum in the gate insulating film are different from each other. Specifically, when the high dielectric material contains aluminum, the first gate insulating film 38a contains aluminum, and the first gate insulating film 38a has a higher aluminum concentration than the second gate insulating film. Lower than 38b. On the other hand, when the high dielectric material does not contain aluminum, the first gate insulating film 38a does not contain aluminum, and the second gate insulating film 38b contains aluminum.

  As described above, in the method for manufacturing a semiconductor device according to this modification, the threshold voltage is applied to the first active region 1a by introducing aluminum (threshold voltage adjusting impurity) in the step shown in FIG. A high dielectric film 34A having a low concentration of adjusting impurities is formed, and a high dielectric film 34B having a high concentration of threshold voltage adjusting impurities is formed on the second active region 1b. The threshold voltage adjusting impurity in this modification acts to increase the threshold voltage of the N-type MISFET when introduced into the high dielectric film, and suppresses the introduction of the first metal into the high dielectric film. Not to do. Therefore, in the step shown in FIG. 5C, the first metal is not only the high dielectric film 34A having a low concentration of the threshold voltage adjusting impurity, but also the high dielectric film 34B having a high concentration of the threshold voltage adjusting impurity. It also spreads. Therefore, in the semiconductor device according to this modification, the concentration of the first metal in the first gate insulating film 38a is the same as the concentration of the first metal in the second gate insulating film 38b. However, the first gate insulating film 38a does not contain aluminum, or the aluminum concentration of the first gate insulating film 38a is lower than that of the second gate insulating film 38b. Since aluminum acts to increase the threshold voltage of the N-type MISFET when introduced into the high dielectric film, the reduction of the threshold voltage due to the introduction of the first metal is suppressed. The effects described in the first embodiment can be obtained. That is, since the introduction of aluminum cancels out the effect of lowering the threshold voltage due to the first metal, the lowering of the threshold voltage is suppressed.

  The semiconductor device according to this modification may be manufactured according to the manufacturing method shown in the following third modification.

(Third Modification)
FIG. 6A to FIG. 6D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a third modification in the order of steps. Note that “LNTr” and “HNTr” in FIG. 6A are as described in the first embodiment.

First, in the process shown in FIG. 6A, an element isolation region 2 in which an insulating film is embedded in a trench is formed on the upper part of a semiconductor substrate 1 made of p-type silicon, following the process shown in FIG. The first p-type well region 3a is formed on the semiconductor substrate 1 including the first active region 1a, and the second p-type well region 3b is formed on the semiconductor substrate 1 including the second active region 1b. Form. Thereafter, a film containing a third metal (not shown, film thickness is 0.5 nm) is formed on the entire top surface of the semiconductor substrate 1. The film containing the third metal may be an Al ₂ O ₃ film or an Al film.

Thereafter, a portion of the film containing the third metal formed on the second active region 1b is covered by a photolithography method, while the film containing the third metal on the first active region 1a is covered. A resist (not shown) is formed so as to expose the portion formed in step (b). Then, by using this resist as a mask, the portion exposed from the resist in the film containing the third metal is removed by wet etching using a chemical solution mainly composed of ammonium hydroxide (NH ₄ OH). As a result, only the portion formed on the second active region 1b of the film containing the third metal remains, and the second threshold voltage control film 17B which is a part of the film containing the third metal. Is formed on the second active region 1b.

Next, in the step shown in FIG. 6B, after forming a base film (not shown) made of silicon oxynitride and having a film thickness of 1.6 nm on the entire upper surface of the semiconductor substrate 1, for example, a metal organic vapor phase is formed. A high dielectric film 4 made of HfSiON and having a thickness of 2 nm is formed on the base film by a deposition method (step (a)). Thereafter, the film thickness is made of La ₂ O ₃ by a chemical vapor deposition method, for example. A first threshold voltage control film 7 having a thickness of 0.5 nm is formed (step (c)). Accordingly, the base film, the high dielectric film 4 and the first threshold voltage control film 7 are sequentially stacked on the first active region 1a, while the second active region 1b has the second layer. The threshold voltage control film 17B, the base film, the high dielectric film 4, and the first threshold voltage control film 7 are sequentially stacked.

  Subsequently, in the step shown in FIG. 6C, the semiconductor substrate 1 is subjected to a heat treatment of, for example, 800 ° C. for 10 minutes (step (b) and step (d)). As a result, a first high dielectric film 38A is formed on the first active region 1a, and a second high dielectric film 38B is formed on the second active region 1b.

  At this time, the first metal (lanthanum in this modification) is only diffused from the first threshold voltage control film 7 to the portion of the high dielectric film 4 formed on the first active region 1a. Instead, the high dielectric film 4 is also diffused into the portion formed on the second active region 1b. Therefore, the concentration of the first metal in the first high dielectric film 38A is substantially the same as the concentration of the first metal in the second high dielectric film 38B.

  On the other hand, since the second threshold voltage control film 17B is formed only on the second active region 1b, aluminum is used in the second active region 1b of the high dielectric film 4 from the second threshold voltage control film 17B. It diffuses only to the part formed above.

When a high dielectric film containing aluminum (for example, an HfAlO ₂ film) is used as the high dielectric film 4, the first high dielectric film 38A contains aluminum derived from the high dielectric film 4, and The second high dielectric film 38B contains not only aluminum derived from the high dielectric film 4 but also aluminum introduced from the second threshold voltage control film 17B. That is, in this case, the first high dielectric film 38A contains aluminum, and the aluminum concentration of the first high dielectric film 38A is lower than that of the second high dielectric film 38B.

  When a high dielectric film (for example, HfSiON film) that does not contain aluminum is used as the high dielectric film 4, the first high dielectric film 38A does not contain aluminum, and the second high dielectric film 38B It contains aluminum introduced from the second threshold voltage control film 17B. That is, in this case, the first high dielectric film 38A does not contain aluminum, but the second high dielectric film 38B contains aluminum.

  Here, if the conditions of the heat treatment in this heat treatment step are different, the diffusion degree of the first metal in the first high dielectric film 38A and the second high dielectric film 38B is changed, respectively, As described in the first embodiment, the presence or absence of the first threshold voltage control film changes when the heat treatment conditions are different.

  Further, as described in the second modification, the degree of diffusion of aluminum in the second high dielectric film 38B changes when the heat treatment conditions in this heat treatment step are different.

  Further, depending on the heat treatment conditions in the heat treatment process, when the heat treatment process is completed, the second threshold voltage control film 17B may disappear as shown in FIG. 6C. In some cases, the threshold voltage control film remains and is integrated with the first high dielectric film.

  Thereafter, the step shown in FIG. 2A in the first embodiment is performed. Thereby, the first high dielectric film 38A becomes the first gate insulating film 38a, and the second high dielectric film 38B becomes the second gate insulating film 38b. Then, when the steps shown in FIGS. 2B and 2C in the first embodiment are sequentially performed, the semiconductor device shown in FIG. 6D can be manufactured. The semiconductor device thus formed has substantially the same configuration as that of the semiconductor device according to the second modification. Therefore, in this modification, the same effect as that obtained in the second modification is obtained. An effect can be obtained.

(Fourth modification)
In the first embodiment and the first modification, a semiconductor device including two N-type MISFETs and a manufacturing method thereof are described. However, the conductivity type of the transistor may be P-type. In the fourth modification, a manufacturing method in the case where the conductivity type of the semiconductor device according to the first embodiment is P type will be described.

  In general, in a P-type MISFET, the semiconductor substrate is made of n-type silicon, the conductivity type of the well region is n-type, the conductivity types of the extension region and the source / drain region are each p-type, and the conductivity constituting the metal gate electrode. A typical example of the film is a TiN film. As the first metal, that is, a metal that acts to lower the threshold voltage of the P-type MISFET when introduced into the high dielectric film, aluminum can be cited as an example. Therefore, in the method of manufacturing the semiconductor device according to the first embodiment, the conductivity type of the semiconductor substrate, the well region, the extension region, and the source / drain region is inverted, the material of the conductive film is changed, and the first threshold voltage control is performed. What is necessary is just to change the material of a film | membrane. In the following, points different from the method of manufacturing the semiconductor device according to the first embodiment will be mainly described.

  FIG. 7A to FIG. 7D are cross-sectional views showing a method of manufacturing a semiconductor device according to this modification in the order of steps. In FIG. 7A to FIG. 7D, “LPTr” shown on the left side means the first P-type MISFET formation region LPTr in which the first P-type MISFET having a relatively low threshold voltage is formed. “HPTr” shown on the right side indicates a second P-type MISFET formation region HPTr in which a second P-type MISFET having a relatively high threshold voltage is formed.

  First, in the step shown in FIG. 7A, the semiconductor substrate 51 made of n-type silicon is prepared instead of the semiconductor substrate 1 made of p-type silicon, and the first p-type well region 3a and the second p-type are prepared. The steps shown in FIGS. 1A to 1C are sequentially performed except that the first n-type well region 53a and the second n-type well region 53b are formed instead of the well region 3b. . Therefore, a high dielectric film 4A having a low threshold voltage adjustment impurity concentration is formed on the first active region 51a, and a high threshold voltage adjustment impurity concentration is high on the second active region 51b. A dielectric film 4B is formed (step (b)).

  At this time, when a high dielectric film containing nitrogen (for example, an HfSiON film) is used as the high dielectric film 4, the high dielectric film 4 A having a low concentration of the threshold voltage adjusting impurity is derived from the high dielectric film 4. The high dielectric film 4B containing nitrogen and having a high threshold voltage adjusting impurity concentration contains not only nitrogen derived from the high dielectric film 4 but also nitrogen introduced by nitriding. That is, in this case, the high dielectric film 4A having a low threshold voltage adjustment impurity concentration contains nitrogen, and the nitrogen concentration is the nitrogen concentration in the high dielectric film 4B having a high threshold voltage adjustment impurity concentration. Lower than.

When a high dielectric film that does not contain nitrogen (for example, an HfO ₂ film) is used as the high dielectric film 4, the high dielectric film 4A having a low threshold voltage adjusting impurity concentration does not contain nitrogen. The high dielectric film 4B having a high concentration of the threshold voltage adjusting impurity contains nitrogen introduced by nitriding. That is, in this case, the high dielectric film 4B having a high concentration of the threshold voltage adjusting impurity contains nitrogen, but the high dielectric film 4A having a low concentration of the threshold voltage adjusting impurity contains nitrogen. Absent.

Subsequently, in the process shown in FIG. 7B, except that the first threshold voltage control film 57 made of Al ₂ O ₃ is formed instead of the first threshold voltage control film 7 made of La ₂ O _3. Performs the step shown in FIG. 1D (step (c)). Here, since the first threshold voltage control film 57 may be a film containing the first metal (aluminum in the present modification), it is not limited to the Al ₂ O ₃ film and may be an Al film. .

  Subsequently, in the step shown in FIG. 7C, in accordance with the step shown in FIG. 1E, the semiconductor substrate 51 is subjected to a heat treatment of, eg, 800 ° C. for 10 minutes (step (d)). As a result, a first high dielectric film 58A is formed on the first active region 51a, and a second high dielectric film 58B is formed on the second active region 51b.

  At this time, the high dielectric film 4A having a low threshold voltage adjustment impurity concentration does not contain nitrogen, but the high dielectric film 4B having a high threshold voltage adjustment impurity concentration contains nitrogen. Alternatively, the nitrogen concentration in the high dielectric film 4A having a low threshold voltage adjusting impurity concentration is lower than the nitrogen concentration in the high dielectric film 4B having a high threshold voltage adjusting impurity concentration. Therefore, the first metal (aluminum in this modification) is diffused from the first threshold voltage control film 57 to the high dielectric film 4A, but is diffused to the surface-treated high dielectric film 4B. Hateful. Therefore, the concentration of the first metal in the first high dielectric film 58A is higher than the concentration of the first metal in the second high dielectric film 58B.

  Thereafter, the first high dielectric film 58A and the second high dielectric film 58B are used as the first gate insulating film 58a and the second gate insulating film 58b, respectively, and the first conductive film 59a made of TiN. And the second conductive film 59b are formed to form the first gate electrode 61a and the second gate electrode 61b, respectively, and the p-type impurity is implanted to form the first p-type extension region 63a and the second gate electrode 61b. Except for forming the p-type extension region 63b and injecting the p-type impurity to form the first p-type source / drain region 65a and the second p-type source / drain region 65b, the first p-type extension region 63b is formed. The steps shown in FIGS. 2A to 2C in the embodiment are sequentially performed. Thereby, the semiconductor device according to this modification can be manufactured.

  In this modification, nitrogen is used as the threshold voltage adjusting impurity. However, as shown in the first modification, a metal (for example, hafnium) constituting the high dielectric material may be used.

(Fifth modification)
In the second and third modifications, a semiconductor device including two N-type MISFETs and a method for manufacturing the same are described. However, the conductivity type of the transistor may be P-type. In the fifth modification, a manufacturing method in the case where the conductivity type of the semiconductor device according to the third modification is P-type will be described.

  As described in the fourth modification, in the P-type MISFET, the semiconductor substrate is made of n-type silicon, the conductivity type of the well region is n-type, and the conductivity type of the extension region and the source / drain region is p-type, respectively. A typical example of the conductive film constituting the metal gate electrode is a TiN film, and aluminum can be used as an example of the first metal. Furthermore, as a third metal, that is, a metal that prevents the threshold voltage of the P-type MISFET from being lowered when introduced into the high dielectric film, a lanthanoid element, scandium, strontium, or magnesium can be cited as an example. it can. Therefore, in the method of manufacturing a semiconductor device according to the third modification, the conductivity types of the semiconductor substrate, the extension region, and the source / drain region are inverted, the material of the conductive film is changed, and the first and second threshold voltage controls are performed. What is necessary is just to change the material of a film | membrane. Hereinafter, points different from the method of manufacturing the semiconductor device according to the third modification will be mainly described.

  FIG. 8A to FIG. 8D are cross-sectional views showing a method for manufacturing a semiconductor device according to this modification in the order of steps. Note that “LPTr” and “HPTr” in FIG. 8A are as described in the fourth modification.

First, in the process shown in FIG. 8A, the semiconductor substrate 51 made of n-type silicon is used instead of the semiconductor substrate 1 made of p-type silicon, and the first p-type well region 3a and the second p-type well are used. Forming the first n-type well region 53a and the second n-type well region 53b instead of the region 3b, and a film containing, for example, lanthanum instead of a film containing aluminum as a film containing the third metal ( The process shown in FIG. 6A is performed except that a La film or a La ₂ O ₃ film is used. As a result, a second threshold voltage control film 67B containing, for example, lanthanum is formed on the second active region 51b.

Next, in the step shown in FIG. 8B, except that the first threshold voltage control film 57 made of Al ₂ O ₃ is formed instead of the first threshold voltage control film 7 made of La ₂ O _3. Performs the step shown in FIG.

  Subsequently, in the process illustrated in FIG. 8C, the semiconductor substrate 51 is subjected to a heat treatment at 800 ° C. for 10 minutes, for example. Then, the first metal (aluminum in this modification) diffuses from the first threshold voltage control film 57 to the high dielectric film 4. In addition, lanthanum (third metal) diffuses from the second threshold voltage control film 67B to a portion of the high dielectric film 4 formed on the second active region 51b. As a result, a first high dielectric film 68A is formed on the first active region 51a, and a second high dielectric film 68B is formed on the second active region 51b.

  At this time, the first metal (aluminum in this modification) is not only the portion formed on the first active region 51a in the high dielectric film 4 but also the high dielectric from the first threshold voltage control film 57. The body film 4 also diffuses into the portion formed on the second active region 51b. Therefore, the concentration of the first metal in the first high dielectric film 68A is substantially the same as the concentration of the first metal in the second high dielectric film 68B. Further, since the second threshold voltage control film 67B is formed only on the second active region 1b, lanthanum is formed from the second threshold voltage control film 67B to the second active region 51b in the high dielectric film 4. It diffuses only to the part formed above.

  In many cases, a high-dielectric film that does not contain lanthanum (for example, an HfSiON film) is used as the high-dielectric film 4, but in this case, the first high-dielectric film 68A does not contain lanthanum, The dielectric film 68B contains lanthanum. That is, in this case, the first high dielectric film 68A does not contain lanthanum, but the second high dielectric film 68B contains aluminum.

  Thereafter, the first high dielectric film 68A and the second high dielectric film 68B are changed to the first gate insulating film 68a and the second gate insulating film 68b, respectively, and the first conductive film 59a made of TiN. And the second conductive film 59b are formed to form the first gate electrode 61a and the second gate electrode 61b, respectively, and the p-type impurity is implanted to form the first p-type extension region 63a and the second gate electrode 61b. Except for forming the p-type extension region 63b and injecting the p-type impurity to form the first p-type source / drain region 65a and the second p-type source / drain region 65b, the first p-type extension region 63b is formed. The steps shown in FIGS. 2A to 2C in the embodiment are sequentially performed. Thereby, the semiconductor device shown in FIG. 8D can be manufactured.

  In the method of manufacturing a semiconductor device according to this modification, instead of forming the second threshold voltage control film, the second active region of the high dielectric film is used as shown in the second modification. A third metal (lanthanoid element, scandium, strontium, or magnesium) may be introduced into the portion formed above.

  As described above, according to the present invention, in a semiconductor device in which two or more transistors of the same conductivity type having a high-k film and a metal gate electrode are formed in the same substrate, the threshold voltages of the transistors are made different. Useful in some cases.

(A)-(e) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment in order of a process. (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment in order of a process. 1 is a cross-sectional view of a semiconductor device according to a first embodiment. (A)-(e) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on a 1st modification in process order. (A)-(e) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on a 2nd modification in process order. (A)-(d) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on a 3rd modification in process order. (A)-(d) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on a 4th modification in process order. (A)-(d) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on a 5th modification in process order. It is sectional drawing of the conventional semiconductor device.

Explanation of symbols

1,51 Semiconductor substrate
1a, 51a First active region
1b, 51b Second active region
4 High dielectric film
7, 57 First threshold voltage control film
8A, 28A, 38A, 58A, 68A First high dielectric film
8B, 28B, 38B, 58B, 68B Second high dielectric film
8a, 28a, 38a, 58a, 68a First gate insulating film
8b, 28b, 38b, 58b, 68b Second gate insulating film
9 Conductive film
9a, 59a First conductive film
9b, 59b Second conductive film
10 Silicon film
10a First silicon film
10b Second silicon film
11a, 61a First gate electrode
11b, 61b Second gate electrode
17B, 67B Second threshold voltage control film

Claims (16)

A first transistor provided on a first active region in the semiconductor region; and a second transistor provided on a second active region in the semiconductor region and having the same conductivity type as the first transistor. A semiconductor device,
The first transistor includes:
A first gate insulating film formed on the first active region and containing a high dielectric material and a first metal;
A first gate electrode having a first conductive film formed on the first gate insulating film and a first silicon film formed on the first conductive film;
The second transistor is
A second gate insulating film formed on the second active region and containing the high dielectric material, the first metal, and a threshold voltage adjusting impurity;
A second conductive film formed on the second gate insulating film and made of the same material as the first conductive film; and a second silicon film formed on the second conductive film; A second gate electrode having
The semiconductor device according to claim 1, wherein the first gate insulating film has a lower concentration of the threshold voltage adjusting impurity than the second gate insulating film or does not contain the threshold voltage adjusting impurity. The semiconductor device according to claim 1,
The semiconductor device, wherein a threshold voltage of the first transistor is lower than a threshold voltage of the second transistor. The semiconductor device according to claim 1 or 2,
The semiconductor device according to claim 1, wherein the threshold voltage adjusting impurity is nitrogen. The semiconductor device according to any one of claims 1 to 3,
The semiconductor device, wherein a concentration of the first metal in the first gate insulating film is higher than a concentration of the first metal in the second gate insulating film. The semiconductor device according to claim 1 or 2,
The high dielectric material is a metal oxide, metal oxynitride or metal silicate containing a second metal,
The threshold voltage adjusting impurity is the second metal,
The semiconductor device, wherein a concentration of the second metal in the first gate insulating film is lower than a concentration of the second metal in the second gate insulating film. The semiconductor device according to claim 5,
The semiconductor device, wherein the second metal is hafnium. The semiconductor device according to claim 1 or 2,
The threshold voltage adjusting impurity is a third metal,
2. The semiconductor device according to claim 1, wherein the second gate insulating film contains the third metal, while the first gate insulating film does not contain the third metal. The semiconductor device according to claim 7,
Each of the first transistor and the second transistor is an N-type MIS transistor,
The semiconductor device, wherein the third metal is aluminum. The semiconductor device according to claim 7,
Each of the first transistor and the second transistor is a P-type MIS transistor,
The semiconductor device, wherein the third metal is at least one of a lanthanoid element, scandium, strontium, and magnesium. The semiconductor device according to any one of claims 1 to 8,
Each of the first transistor and the second transistor is an N-type MIS transistor,
The semiconductor device according to claim 1, wherein the first metal is at least one of a lanthanoid element, scandium, strontium, and magnesium. The semiconductor device according to any one of claims 1 to 7 and 9,
Each of the first transistor and the second transistor is a P-type MIS transistor,
The semiconductor device, wherein the first metal is aluminum. A first transistor provided on a first active region in the semiconductor region; and a second transistor provided on a second active region in the semiconductor region and having the same conductivity type as the first transistor. A method for manufacturing a semiconductor device comprising:
Forming a high dielectric film made of a high dielectric material on the semiconductor region (a);
A threshold voltage adjusting impurity is introduced into a portion of the high dielectric film provided on the second active region, while a portion of the high dielectric film provided on the first active region is provided. (B) not introducing the threshold voltage adjusting impurity,
Forming a first threshold voltage control film containing a first metal on the high dielectric film (c);
A step (d) of diffusing the first metal in the first threshold voltage control film into the high dielectric film after the step (c);
A step (e) of sequentially forming a conductive film and a silicon film on the high dielectric film;
Patterning the silicon film, the conductive film and the high dielectric film, and a first gate insulating film containing the high dielectric material and the first metal on the first active region; A first gate electrode having a first silicon film and a first conductive film is formed, and the high dielectric material, the first metal, and the threshold voltage adjustment are formed on the second active region. A step (f) of forming a second gate insulating film containing impurities and a second gate electrode having a second silicon film and a second conductive film,
The first gate insulating film has a lower concentration of the threshold voltage adjusting impurity than the second gate insulating film or does not contain the threshold voltage adjusting impurity. Production method. In the manufacturing method of the semiconductor device according to claim 12,
A method for manufacturing a semiconductor device, wherein a threshold voltage of the first transistor is lower than a threshold voltage of the second transistor. In the manufacturing method of the semiconductor device according to claim 12 or 13,
In the step (b), nitrogen is introduced as the threshold voltage adjusting impurity,
The method for manufacturing a semiconductor device, wherein the first gate insulating film has a lower concentration of nitrogen than the second gate insulating film or does not contain the nitrogen. In the manufacturing method of the semiconductor device according to claim 12 or 13,
The high dielectric material is a metal oxide, metal oxynitride or metal silicate containing a second metal,
In the step (b), the second metal is introduced as the threshold voltage adjusting impurity,
A method of manufacturing a semiconductor device, wherein a concentration of the second metal in the first gate insulating film is lower than a concentration of the second metal in the second gate insulating film. In the manufacturing method of the semiconductor device according to claim 12 or 13,
In the step (b), a third metal is introduced as the threshold voltage adjusting impurity,
The method of manufacturing a semiconductor device, wherein the second gate insulating film contains the third metal, while the first gate insulating film does not contain the third metal.

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