JP2010157558A - Semiconductor apparatus and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor apparatus capable of efficiently suppressing diffusion of metal contained in the wiring. <P>SOLUTION: A semiconductor apparatus has: an insulating layer formed on a semiconductor substrate; the wiring that contains a metal formed in the insulating layer; a first region that contacts with an upper surface of the wiring and has the same width as that of the upper surface of the wiring; a first barrier metal including a second region having a width wider than that of the first region and which is located on the first region; and a second barrier metal that contacts with a lower surface and a side surface of the wiring, a side surface of the first region, and a lower surface of the second region. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  As a conventional wiring structure, a copper wiring, a barrier metal layer and a barrier layer capable of suppressing copper diffusion covering the lower surface of the copper wiring, and a capping layer capable of suppressing copper diffusion covering the upper surface and side surfaces of the copper wiring Are known (see, for example, Patent Document 1).

According to the wiring structure described in Patent Document 1 and the like, since the upper surface, the lower surface, and the side surface of the copper wiring are covered with the layer capable of suppressing the diffusion of copper, the diffusion of copper can be suppressed.
JP 2005-166757 A

  An object of the present invention is to provide a semiconductor device capable of effectively suppressing diffusion of a metal contained in a wiring and a method for manufacturing the same.

  According to one embodiment of the present invention, an insulating layer formed over a semiconductor substrate, a wiring including a metal formed in the insulating layer, and a width that is in contact with the top surface of the wiring and substantially equal to the width of the top surface of the wiring A first barrier metal including a first region having a first region having a width wider than a width of the first region located on the first region, a lower surface and a side surface of the wiring, A semiconductor device having a side surface of a first region and a second barrier metal in contact with a lower surface of the second region.

  In another aspect of the present invention, an insulating layer formed on a semiconductor substrate, a wiring formed in the insulating layer, a via formed integrally with the wiring under the wiring, and the wiring A first region in contact with the upper surface and having a width substantially equal to a width of the upper surface of the wiring; and a second region having a width wider than the width of the first region located on the first region. A semiconductor device comprising: a first barrier metal; a lower surface and a side surface of the wiring; a lower surface and a side surface of the via; a side surface of the first region; and a second barrier metal in contact with the lower surface of the second region. It is.

  In another aspect of the present invention, a step of forming a groove in an insulating layer on a semiconductor substrate, a step of forming a barrier metal on an inner surface of the groove and an upper surface of the outer side of the groove of the insulating layer, Forming a resist having a predetermined pattern on the barrier metal outside the groove to form another groove having a width wider than the groove on the groove with the resist serving as a side wall; and Forming a wiring containing metal in the other groove, reducing the height of the upper surface of the wiring below the height of the interface between the barrier metal and the resist, and lowering the height of the upper surface of the wiring A step of forming another barrier metal in the groove and the other groove on the wiring; and a step of etching the barrier metal using the other barrier metal and a mask after removing the resist; The No, a method of manufacturing a semiconductor device.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which can suppress effectively the spreading | diffusion of the metal contained in wiring, and its manufacturing method can be provided.

[First Embodiment]
(Configuration of semiconductor device)
FIG. 1A is a cross-sectional view of the semiconductor device 1 according to the first embodiment of the present invention. FIG. 1B is an enlarged cross-sectional view of the first barrier metal 3. FIG. 1C is a conceptual diagram showing a metal diffusion path in the wiring 2.

  The semiconductor device 1 includes a first insulating layer 5 formed on a semiconductor substrate (not shown), a wiring 2 formed in the first insulating layer 5, and a first barrier that covers the upper surface 2a of the wiring 2. Metal 3, second barrier metal 4 covering lower surface 2 b and side surface 2 c of wiring 2, and second insulating layer 6 formed on first barrier metal 3 and first insulating layer 5. .

  The wiring 2 is made of a metal material such as Cu.

  The first barrier metal 3 is made of a metal such as Ti, Ni, Ta, or W, or a compound containing these metals, and has a property of suppressing diffusion of a metal such as Cu contained in the wiring 2. The second barrier metal 4 is made of a metal such as Ti, Ni, Ta, or a compound containing these metals, and has a property of suppressing diffusion of a metal such as Cu contained in the wiring 2.

  The first barrier metal 3 includes a first region 3a and a second region 3b. The lower surface 3c of the first region 3a is in contact with the upper surface 2a of the wiring 2 and has a width L1 substantially equal to the width of the upper surface 2a of the wiring 2. The second region 3b is located on the first region 3a and has a width L2 wider than the width L1 of the first region 3a.

  The second barrier metal 4 is in contact with the lower surface 2b and the side surface 2c of the wiring 2, the side surface 3d of the first region 3a, and the lower surface 3e of the second region 3b.

  The first insulating layer 5 and the second insulating layer 6 are made of an insulating material such as polyimide or a silicon oxide film.

  In general, at the interface between different members that are in contact with each other, the impurities are more easily diffused than inside the members, and become a main diffusion path of the impurities. In the semiconductor device 1, a metal diffusion path 7 that is an interface between the first barrier metal 3 and the second barrier metal 4 serves as a diffusion path for a metal such as Cu contained in the wiring 2. In the present embodiment, by sufficiently increasing the distance of the metal diffusion path 7, the diffusion of the metal contained in the wiring 2 to the insulating layer such as the first insulating layer 5 and the second insulating layer 6 is prevented. Can be suppressed.

  The shortest distance from the wiring 2 of the metal diffusion path 7 to the second insulating layer 6 is the sum of the height L3 of the side surface 3d of the first region 3a and the width L4 of the lower surface 3e of the second region 3b. Is almost equal to When the sum of the height L3 and the width L4 is large, the diffusion of the metal contained in the wiring 2 into the insulating layers such as the first insulating layer 5 and the second insulating layer 6 can be effectively suppressed. it can. For example, the sum of the height L3 and the width L4 is the difference between the height of the upper surface of the wiring 2 and the height of the upper surface of the first insulating layer 5 and the thickness of the second barrier metal 4 as will be described later. Of these, 100% or more of the larger one is preferable.

(Manufacture of semiconductor devices)
2A (a) to 2 (d) and FIGS. 2B (e) to (h) are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

  First, as shown in FIG. 2A (a), the wiring groove 8a is formed in the first insulating layer 5 on the semiconductor substrate (not shown), and the first insulation outside the wiring groove 8a and the inner surface of the wiring groove 8a. A second barrier metal 4 is formed so as to cover the upper surface of the layer 5. Here, the width of the wiring groove 8 a after forming the second barrier metal 4 is substantially equal to the width L 1 of the first region 3 a of the first barrier metal 3.

  The wiring trench 8a is formed by, for example, forming a resist (not shown) having a predetermined pattern on the first insulating layer 5 by photolithography and then etching the first insulating layer 5 using the resist as a mask. It is formed. The second barrier metal 4 is formed by a PVD (Physical Vapor Deposition) method or the like.

  Next, as shown in FIG. 2A (b), a resist 9 is formed on the second barrier metal 4 outside the wiring trench 8a by photolithography or the like. The resist 9 is formed to form a wiring groove 8b having the resist 9 as a side wall. Here, the width of the wiring groove 8 b is substantially equal to the width L 2 of the second region 3 b of the first barrier metal 3.

  Next, as shown in FIG. 2A (c), the wiring 2 is formed in the wiring grooves 8a and 8b. The wiring 2 is formed by an electrolytic plating method or the like.

  Next, as shown in FIG. 2A (d), etching such as wet etching is performed on the upper surface of the wiring 2, and the height of the upper surface of the wiring 2 is set to the upper surface of the second barrier metal 4 outside the wiring groove 8a. The height is made lower than the height (the height of the interface between the second barrier metal 4 and the resist 9).

  Next, as shown in FIG. 2B (e), the first barrier metal 3 is formed in the wiring grooves 8a and 8b on the wiring 2. The first barrier metal 3 is formed by PVD or the like so that the height of the upper surface is higher than the height of the upper surface of the second barrier metal 4 outside the wiring groove 8a.

  Next, as shown in FIG. 2B (f), the resist 9 is removed by oxygen ashing or the like.

  Next, as shown in FIG. 2B (g), the second barrier metal 4 is etched using the first barrier metal 3 as a mask.

  Next, as shown in FIG. 2B (h), a second insulating film 6 is formed on the first insulating film 5 and the first barrier metal 3.

  FIG. 3A is a cross-sectional view of the semiconductor device 10 according to the comparative example. FIG. 3B is a conceptual diagram showing a metal diffusion path in the wiring 12.

  The semiconductor device 10 includes a first insulating layer 15 formed on a semiconductor substrate (not shown), a second barrier metal 14 formed on the first insulating layer 15 and covering the lower surface 12b of the wiring 12, The wiring 12 formed on the second barrier metal 14, the first barrier metal 13 covering the upper surface 12 a and the side surface 12 c of the wiring 12, and the first barrier metal 13 and the first insulating layer 15 are formed. And a second insulating layer 16. It is assumed that the materials and properties of each part are the same as those of the semiconductor device 1 of the first embodiment.

  The second barrier metal 14 and the wiring 12 are formed by the following method, for example. First, the second barrier metal 14 is formed on the entire surface of the first insulating layer 15, and a resist (not shown) having a predetermined pattern is formed thereon by a photolithography method or the like. Next, the wiring 12 is formed in a groove having the top surface of the second barrier metal 14 as the bottom surface and the resist as a side wall, and the resist is removed. Next, the second barrier metal 14 is etched using the wiring 12 as a mask to remove only the portion in contact with the lower surface 12 b of the wiring 12. Next, the first barrier metal 13 is formed on the upper surface 12 a and the side surface 12 c of the wiring 12.

  In the semiconductor device 10, a metal diffusion path 17 that is an interface between the first barrier metal 13 and the second barrier metal 14 serves as a diffusion path for a metal such as Cu contained in the wiring 12. The shortest distance from the wiring 12 of the metal diffusion path 17 to the first insulating layer 15 is substantially equal to the thickness of the second barrier metal 14, and is shorter than the shortest distance of the metal diffusion path 7 according to the first embodiment. The metal contained in the wiring 12 is likely to diffuse into the insulating layer such as the first insulating layer 15.

  The sum of the height L3 and the width L4, which is the shortest distance of the metal diffusion path 7 according to the first embodiment, is the height of the upper surface of the wiring 2 corresponding to the thickness of the second barrier metal 14 due to its structure. And 100% or more of the difference in height between the top surfaces of the first insulating layers 5 can be set.

  FIG. 4A is a cross-sectional view of a semiconductor device 20 according to another comparative example. FIG. 4B is a conceptual diagram showing a metal diffusion path in the wiring 22.

  The semiconductor device 20 includes a first insulating layer 25 formed on a semiconductor substrate (not shown), a wiring 22 formed in the first insulating layer 25, and a second surface covering the lower surface 22b and the side surface 22c of the wiring 22. It has a barrier metal 24, a first barrier metal 23 formed on the wiring 22 and the first insulating layer 25, and a second insulating layer 26 formed on the first barrier metal 23. It is assumed that the materials and properties of each part are the same as those of the semiconductor device 1 of the first embodiment.

  The second barrier metal 24 and the wiring 22 are embedded in the first insulating layer 25 by a normal damascene method. The first barrier metal 23 is formed so as to cover the upper surface 22 a of the wiring 22.

  In the semiconductor device 20, a metal diffusion path 27, which is an interface between the first barrier metal 23 and the second barrier metal 24, serves as a diffusion path for a metal such as Cu contained in the wiring 22. The shortest distance from the wiring 22 of the metal diffusion path 27 to the first insulating layer 25 is substantially equal to the thickness of the second barrier metal 24 and is shorter than the shortest distance of the metal diffusion path 7 according to the first embodiment. The metal contained in the wiring 22 is likely to diffuse into the insulating layer such as the first insulating layer 25.

  The sum of the height L3 and the width L4, which is the shortest distance of the metal diffusion path 7 according to the first embodiment, is the second barrier metal 4 corresponding to the thickness of the second barrier metal 24 due to its structure. Can be set to 100% or more of the thickness.

  That is, the sum of the height L3 and the width L4 is the larger of the difference between the height of the upper surface of the wiring 2 and the height of the upper surface of the first insulating layer 5 and the thickness of the second barrier metal 4. % Or more is preferable.

(Effects of the first embodiment)
According to the first embodiment of the present invention, the diffusion of the metal contained in the wiring 2 to the surrounding insulating layer can be suppressed by sufficiently increasing the distance of the metal diffusion path 7.

[Second Embodiment]
The second embodiment of the present invention is different from the first embodiment in that a wiring and a via are simultaneously formed by a dual damascene method.

(Configuration of semiconductor device)
FIG. 5A is a cross-sectional view of the semiconductor device 30 according to the second embodiment of the present invention. FIG. 5B is an enlarged cross-sectional view of the first barrier metal 33. FIG. 5C is a conceptual diagram showing a metal diffusion path in the wiring 32 and the via 38.

  The semiconductor device 30 is formed in a conductive part 40 such as wiring formed on a semiconductor substrate (not shown), a first insulating layer 35 formed on the conductive part 40, and the first insulating layer 35. Wiring 32, via 41 formed integrally with wiring 32 under wiring 32, first barrier metal 33 covering upper surface 32 a of wiring 32, lower surface 32 b and side surface 32 c of wiring 32, and lower surface of via 41 The first barrier metal 34 covering the 41a and the side surface 41b, and the second insulating layer 36 formed on the first barrier metal 33 and the first insulating layer 35 are included.

  Since the via 41 is formed integrally with the wiring 32, the via 41 is formed of the same material as the wiring 32. The materials and properties of the other members are the same as those of the semiconductor device 1 of the first embodiment.

  The first barrier metal 33 includes a first region 33a and a second region 33b. The lower surface 33c of the first region 33a is in contact with the upper surface 32a of the wiring 32 and has a width L5 that is substantially equal to the width of the upper surface 32a of the wiring 32. The second region 33b is located on the first region 33a and has a width L6 that is wider than the width L5 of the first region 33a.

  The second barrier metal 34 contacts the lower surface 32b and the side surface 32c of the wiring 32, the lower surface 41a and the side surface 41b of the via 41, the side surface 33d of the first region 3a, and the lower surface 33e of the second region 33b.

  In the semiconductor device 30, a metal diffusion path 37 that is an interface between the first barrier metal 33 and the second barrier metal 34 serves as a diffusion path for a metal such as Cu contained in the wiring 32. In the present embodiment, by sufficiently increasing the distance of the metal diffusion path 37, the diffusion of the metal contained in the wiring 32 to the insulating layers such as the first insulating layer 35 and the second insulating layer 36 is reduced. Can be suppressed.

  The shortest distance from the wiring 32 of the metal diffusion path 37 to the second insulating layer 36 is the sum of the height L7 of the side surface 33d of the first region 33a and the width L8 of the lower surface 33e of the second region 33b. Is almost equal to When the sum of the height L7 and the width L8 is large, the diffusion of the metal contained in the wiring 32 to the insulating layers such as the first insulating layer 35 and the second insulating layer 36 can be effectively suppressed. it can. For example, the sum of the height L7 and the width L8 is the same as the sum of the height L3 and the width L4 in the first embodiment, and the height of the upper surface of the wiring 32 and the upper surface of the first insulating layer 35. Of the difference in thickness and the thickness of the second barrier metal 34, the larger one is preferably 100% or more.

(Manufacture of semiconductor devices)
6A to 6C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment of the present invention.

  First, as shown in FIG. 6A, wiring grooves 38a and via holes 38c are formed in the first insulating layer 35 on a semiconductor substrate (not shown), and the inner surfaces of the wiring grooves 38a and via holes 38c and the wiring grooves 38a are formed. A second barrier metal 34 is formed so as to cover the upper surface of the outer first insulating layer 35. Here, the width of the wiring groove 38 a after the formation of the second barrier metal 34 is substantially equal to the width L 5 of the first region 33 a of the first barrier metal 33.

  For example, after forming a resist (not shown) having a predetermined pattern on the first insulating layer 35 by photolithography, the wiring trench 38a and the via hole 38c are formed on the first insulating layer 35 using the resist as a mask. It is formed by etching. The second barrier metal 34 is formed by a PVD (Physical Vapor Deposition) method or the like.

  Next, as shown in FIG. 6B, a resist 39 is formed on the second barrier metal 34 outside the wiring trench 38a by photolithography or the like. The resist 39 is formed to form a wiring groove 38b having the resist 39 as a side wall. Here, the width of the wiring groove 38 b is substantially equal to the width L 6 of the second region 3 b of the first barrier metal 33.

  Next, as shown in FIG. 6C, the via 41 is formed in the via hole 38c, and the wiring 32 is formed in the wiring grooves 38a and 38b. The via 41 and the wiring 32 are formed continuously and integrally by an electrolytic plating method or the like.

  Thereafter, the steps after the step of reducing the height of the upper surface of the wiring 32 (wiring 2 in the first embodiment) are performed in the same manner as in the first embodiment, and the semiconductor device 30 shown in FIG. 5 is obtained.

(Effect of the second embodiment)
According to the second embodiment of the present invention, by sufficiently increasing the distance of the metal diffusion path 37, diffusion of the metal contained in the wiring 32 to the surrounding insulating layer can be suppressed.

[Other Embodiments]
Each of the above embodiments is merely an embodiment, and the present invention is not limited to these embodiments, and various modifications can be made without departing from the spirit of the invention.

  In addition, the constituent elements of the above embodiments can be arbitrarily combined without departing from the spirit of the invention.

(A) is sectional drawing of the semiconductor device which concerns on the 1st Embodiment of this invention, (b) is an expanded sectional view of a 1st barrier metal, (c) is a conceptual diagram showing the diffusion path | route of the metal in wiring It is. (A)-(d) is sectional drawing showing the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. (E)-(h) is sectional drawing showing the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. (A) is sectional drawing of the semiconductor device which concerns on a comparative example, (b) is a conceptual diagram showing the diffusion path | route of the metal in wiring. (A) is sectional drawing of the semiconductor device which concerns on a comparative example, (b) is a conceptual diagram showing the diffusion path | route of the metal in wiring. (A) is sectional drawing of the semiconductor device based on the 2nd Embodiment of this invention, (b) is an expanded sectional view of a 1st barrier metal, (c) is a conceptual diagram showing the diffusion path | route of the metal in wiring It is. (A)-(c) is sectional drawing showing the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1, 30 Semiconductor device, 2, 32 wiring, 2a, 32a upper surface, 2b, 32b lower surface, 2c, 32c side surface, 3, 33 1st barrier metal, 3a, 33a 1st area | region, 3b, 33b 2nd area | region 3c, 33c lower surface, 3d, 33d side surface, 3e, 33e lower surface, 4, 34 second barrier metal, 5, 35 first insulating layer, 6, 36 second insulating layer, 8a, 8b, 38a, 38b Wiring groove, 9, 39 resist, 38c via hole, 41 via, 41a lower surface, 41b side surface.

Claims (5)

An insulating layer formed on a semiconductor substrate;
A wiring containing a metal formed in the insulating layer;
A first region in contact with the upper surface of the wiring and having a width substantially equal to the width of the upper surface of the wiring, and a second region having a width wider than the width of the first region located on the first region A first barrier metal including a region;
A second barrier metal in contact with a lower surface and a side surface of the wiring, a side surface of the first region, and a lower surface of the second region;
A semiconductor device. An insulating layer formed on a semiconductor substrate;
Wiring formed in the insulating layer;
A via formed integrally with the wiring under the wiring;
A first region in contact with the upper surface of the wiring and having a width substantially equal to the width of the upper surface of the wiring, and a second region having a width wider than the width of the first region located on the first region A first barrier metal including a region;
A second barrier metal in contact with a lower surface and a side surface of the wiring, a lower surface and a side surface of the via, a side surface of the first region, and a lower surface of the second region;
A semiconductor device. The sum of the height of the side surface of the first region and the width of the lower surface of the second region is the difference between the height of the upper surface of the wiring and the height of the upper surface of the insulating layer, 100% or more of the thickness of the barrier metal,
The semiconductor device according to claim 1. Forming a groove in an insulating layer on a semiconductor substrate;
Forming a barrier metal on the inner surface of the groove and the upper surface of the insulating layer outside the groove;
Forming a resist having a predetermined pattern on the barrier metal outside the groove, thereby forming another groove having a width wider than the groove on the groove.
Forming a metal-containing wiring in the groove and the other groove;
Lowering the height of the upper surface of the wiring below the height of the interface between the barrier metal and the resist;
After lowering the height of the upper surface of the wiring, forming another barrier metal in the groove and the other groove on the wiring;
Etching the barrier metal as a mask with the other barrier metal after removing the resist;
A method for manufacturing a semiconductor device, comprising: The groove comprises a wiring groove and a via hole under the wiring groove,
Forming the wiring continuously and integrally in the via, the wiring groove and the other groove in the via hole;
A method for manufacturing a semiconductor device according to claim 4.

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