JP2010152473A - Voltage detection circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a voltage detection circuit having short stabilization time. <P>SOLUTION: The voltage detection circuit is started by an enable signal, and is detected by outputting a detection signal whether a measured voltage is higher than or lower than a reference voltage as a threshold. The circuit is provided with: a D-type flip flop using a power supply voltage as a D input, and using an inverted signal of the output of a comparator circuit as a clock, and using an enable inverted signal as a reset input; a detection output circuit for calculating the logical product of the Q output of the D-type flip flop and the output of the comparator circuit, and for outputting a detection signal; and an acceleration charging circuit for calculating the negative logical product of the inverted signal of the D-type flip flop Q output and the output of the comparator circuit, and for outputting a control signal to control connection from a power supply voltage to a divided voltage. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an invention for detecting whether a measured voltage is larger or smaller than a certain voltage in various circuits in addition to voltage control of a charge pump. In particular, the reference voltage is a voltage different from the measured voltage. For this purpose, a voltage dividing circuit that divides the voltage to be measured must be provided and compared, and the divided voltage is obtained by dividing the voltage to be measured by the ratio of the resistance to the ground potential. When the detection result is output using the circuit and the comparison circuit that compares the output of the voltage dividing circuit with the reference voltage, the detection signal is activated by the enable signal and the detected voltage is larger or smaller than the threshold voltage. It is related with the voltage detection circuit performed by doing.

  Conventionally, various circuit configurations of voltage detection circuits have been proposed. FIG. 3 shows an example of a voltage detection circuit that has been frequently used in the past. A waveform diagram of the circuit is shown in FIG.

  A voltage dividing circuit 111 provided to provide an output 153 of a voltage dividing circuit obtained by dividing the voltage to be measured 151 by a ratio of the resistance to the ground potential 152, and an output 153 of the voltage dividing circuit and a reference voltage 154 are compared with each other. Compare with. On the other hand, the enable signal 156 becomes the delay enable signal 157 in the delay circuit 113, and the detection result 158 is obtained by taking the AND of the delay enable signal 157 and the AND circuit 114 from the comparison circuit output 155 of the comparison circuit 112. To do.

  In this case, a voltage dividing input circuit 115 having a switching function by an enable signal is provided so that the voltage to be measured 151 is not directly connected to the voltage dividing circuit 111 so that the detection can be stopped. Specifically, as a result of the circuit in which the enable inversion signal 159 is the gate input of the PMOSFET, the measured voltage 151 is directly divided into the divided input voltage 160 of the voltage dividing circuit 111 only when the enable inversion signal 159 is “Low”. It becomes.

  Further, the comparison circuit 112 works only when the enable signal 161 is “High”.

  The operation waveform of this circuit is as shown in FIG.

  That is, since the enable signal is “Low” before the operation is started 181 and the enable inversion signal 159 is “High” in the initial state, the voltage dividing input circuit 115 is OFF, so the voltage dividing circuit 111 directly. As a result, the ground potential 152 works, and the output 153 of the voltage dividing circuit is at a low voltage. Further, since the same enable signal 161 is “Low”, the comparison circuit 112 does not operate, the comparison circuit output 155 becomes “Low”, and since the enable signal 156 is “Low”, the delay enable of the delay circuit 113 is performed. The signal 157 is finally “Low”, and the detection result 158 output from the AND circuit 114 is also “Low”.

  In this state, when the enable signal is raised, the stabilization time 182 is entered, the enable inversion signal 159 becomes “Low”, and the voltage dividing input circuit 115 is turned on, but it takes time to charge the voltage dividing circuit 111 directly. The output 153 of the voltage dividing circuit is initially at a low voltage. Further, since the same enable signal 161 becomes “High”, the comparison circuit 112 is activated, and the comparison circuit output 155 becomes “High”. However, even when the enable signal 156 becomes “High”, the delay enable of the delay circuit 113 is performed. The signal 157 is initially “Low”, and the detection result 158 from the AND circuit 114 eventually remains “Low”.

  The delay time of the delay circuit 113 is the length of the stable time 182 sufficient to charge the voltage dividing circuit 111 directly. In this way, after the delay time of the delay circuit 113 has elapsed, that is, after the stabilization time, the detection time is reached, and the output 153 of the voltage dividing circuit is divided by the ratio of the measured voltage side resistors 171, 172, 173 and the ground side resistor 174. Comparison times 183, 184 and 185 are entered.

  If the reference voltage 154 serving as the threshold is higher than the divided voltage 153 after the stabilization time has elapsed, that is, the comparison (+) time 183 and 185, the comparison circuit output 155 of the comparison circuit 112 becomes “High”, and the delay enable signal Since 157 is also “High”, the detection result 158 from the AND circuit 114 eventually becomes “High”.

  On the other hand, if the reference voltage 154 serving as the threshold is the comparison (−) time 184 lower than the output 153 of the voltage dividing circuit after the stable time has elapsed, the comparison circuit output 155 of the comparison circuit 112 is also “Low”, and the delay enable Even if the signal 157 is also “High”, the detection result 158 from the AND circuit 114 eventually becomes “Low”.

  Finally, when the enable signal becomes “Low”, the enable inversion signal 159 becomes “High” and the voltage dividing input circuit 115 is turned OFF, so that the voltage dividing circuit 111 directly outputs the output of the voltage dividing circuit to the ground potential 152. 153 voltage drops. On the other hand, since the same enable signal 161 also becomes “Low”, the comparison circuit output 155 of the comparison circuit 112 becomes “Low”. As a result, even if the delay enable signal 157 remains “High”, the detection result 158 finally output from the AND circuit 114 also becomes “Low”, and the comparison time is ended.

  In addition, a technique for shortening the Vout boosting time by changing the number of stages of the charge pump between the case of generating Vout from the low voltage Vcc2 and the case of generating Vout from the high voltage Vcc1 as shown in Patent Document 1 is shown. Has been.

The patent literature is as follows.
JP 2007-188612 A JP 2005-141811 A

  The start-up time can be shortened by using only the self-circuit without using an external circuit to reduce the stabilization time, and the current consumption consumed by the resistance of the voltage divider circuit can be minimized. At the same time, an object is to minimize the generation of heat by minimizing the current consumed by the resistor.

  In order to solve the above-mentioned problems in the present invention, first, in claim 1, a voltage dividing circuit for providing a divided voltage obtained by dividing the voltage to be measured by the ratio of the resistance to the ground potential, an output of the voltage dividing circuit, and a reference When outputting a detection result using a comparison circuit that compares the voltage, a voltage detection circuit that is activated by an enable signal and outputs a detection signal that is larger or smaller than a reference voltage with the measured voltage as a threshold value , A D-type flip-flop having a power source voltage as a D input, an inverted signal of the comparison circuit output as a clock and an enable inverted signal as a reset input, and a Q signal of the D-type flip-flop as a detection signal And a control signal for controlling the connection from the power supply voltage to the divided voltage by the negative logical product of the inverted output signal of the D-type flip-flop Q and the output of the comparison circuit. There is provided a voltage detection circuit, characterized in that it comprises a fast charging circuit.

  Further, in the second aspect, the operation of the comparison circuit is performed by the enable signal, and the discharge circuit that switches off the switch that connects the divided voltage to the ground potential by the enable inversion signal, and the measurement target by the enable signal A voltage detection circuit according to claim 1, further comprising: a voltage dividing input circuit having a switch connected to the voltage dividing circuit as an ON signal.

  According to a third aspect of the present invention, there is provided the voltage detection circuit according to the second aspect, wherein the acceleration charging circuit, the discharging circuit, and the voltage dividing input circuit comprise MOSFETs.

  According to a fourth aspect of the present invention, the acceleration charging circuit generates an inverted signal of the D-type flip-flop Q output and a NAND signal of the comparison circuit output, and the NAND signal is connected to the gate input of the PMOSFET connected from the power supply voltage to the divided voltage. The discharge circuit is composed of a circuit in which the enable inversion signal is the gate input of the NMOSFET, and the voltage dividing input circuit is composed of a circuit in which the enable inversion signal is the gate input of the PMOSFET. The voltage detection circuit according to claim 3 is provided.

  According to the present invention, the start-up time is shortened only by the self-circuit without using an external circuit according to the present invention, the stabilization time is shortened, and the current consumption consumed by the resistance of the voltage dividing circuit is minimized. Thus, there is an effect that it becomes possible to provide a voltage detection circuit which becomes an economical circuit and suppresses heat generation to a minimum by minimizing the current consumed by the resistor.

  According to the second aspect of the present invention, the output of the voltage dividing circuit is not lowered at the start of operation, and it is possible to prevent a malfunction that occurs when the residual charge remains and is higher than the reference voltage. The time required for the shutdown after the completion can be shortened.

  Further, according to the third aspect of the present invention, it is possible to design in a semiconductor integrated circuit and to provide a semiconductor integrated circuit having a fast operation.

  Claim 4 provides a circuit configuration that is specifically realized.

  In carrying out the present invention, the best mode will be described. Naturally, it is not excluded to modify the circuit to have the same effect with an equivalent circuit or the like within the scope of the claims.

  FIG. 1 shows an example of a voltage detection circuit according to an embodiment of the present invention, which will be described using this circuit. A waveform diagram of the circuit is shown in FIG.

  A voltage dividing circuit 11 is provided to provide an output 53 of a voltage dividing circuit obtained by dividing the voltage to be measured 51 by a resistance ratio with respect to the ground potential 52, and the output 53 of the voltage dividing circuit is compared with the reference voltage 54. The circuit 12 compares.

  In this case, a voltage dividing input circuit 15 having a switching function by an enable signal 59 is provided so that the voltage to be measured 51 is not directly connected to the voltage dividing circuit 11 so that detection can be stopped. Specifically, as a result of the circuit in which the enable inversion signal is the gate input of the PMOSFET, the measured voltage 51 is directly divided only when the enable signal is “High”, that is, when the enable inversion signal 59 is “Low”. The divided input voltage 60 of the voltage circuit 11 is obtained.

The divided voltage 53 is divided by the ratio of the measured voltage side resistors 71, 72, 73 and the ground side resistor 74.

  The comparison circuit output 55 of the comparison circuit 12 is logically inverted by the NOT circuit 17 to be a NOT circuit output 57 and then input to the clock of the D-type flip-flop 13. The input D is a power supply voltage 68 that is “High”, and the reset input is an enable inversion signal 56.

  A result obtained by ANDing the AND circuit 14 from the Q output 62 of the D-type flip-flop 13 and the comparison circuit output 55 of the comparison circuit 12 is defined as a detection result 58.

  Separately, the Q output 62 of the D-type flip-flop 13 is further set to a NOT circuit output 63 logically inverted by the NOT circuit 18, and the logical product is inverted by the NAND circuit 19 with the comparison circuit output 55 of the comparison circuit 12. The result of taking the NAND circuit is the acceleration charge suppression signal 64.

  In this case, an acceleration charging circuit 21 having a switching function based on the acceleration charge suppression signal 64 is provided. Specifically, as a result of the circuit in which the acceleration charge suppression signal 64 is the gate input of the PMOSFET, the power supply voltage 65 which is “High” only at the output 53 of the voltage divider circuit when the acceleration charge suppression signal 64 does not work. Directly connected, the output 53 of the voltage dividing circuit becomes “High”.

  On the other hand, a discharge circuit 22 having a switching function by an enable inversion signal 66 is provided. Specifically, as a result of the circuit in which the enable inversion signal is the gate input of the NMOSFET, the output 53 of the voltage dividing circuit is output only when the enable signal is “Low”, that is, when the enable inversion signal 66 is “High”. Directly connected to the ground potential 67, the residual charge of the output 53 of the voltage dividing circuit flows to the ground potential 67, and the output 53 of the voltage dividing circuit becomes “Low” which is the ground potential.

  The operation waveform of this circuit is as shown in FIG.

  That is, since the enable signal is “Low” 81 before the operation is started, that is, when the enable inversion signal 59 is “High”, the voltage dividing input circuit 15 is OFF. Causes the ground potential 52 to work, the divided voltage 53 is low, the output 53 of the voltage dividing circuit is directly connected to the ground potential 67, and the residual charge of the output 53 of the voltage dividing circuit flows to the ground potential 67. The output 53 of the voltage dividing circuit is a low voltage that is the ground potential.

  Further, since the same enable signal 61 is “Low”, the comparison circuit 12 does not operate, the comparison circuit output 55 becomes “Low”, and the Q output 62 of the D-type flip-flop 13 has the enable inversion signal 56 “High”. For this reason, since the reset input is input, it becomes “Low”, and the detection result 58 that is the result of AND of the AND circuit 14 and the comparison circuit output 55 of the comparison circuit 12 becomes “Low”. Similarly, the NOT circuit output 63 logically inverted by the NOT circuit 18 of the Q output 62 of the D-type flip-flop 13 is “High”, and the logical product is inverted by the NAND circuit 14 from the comparison circuit output 55 of the comparison circuit 12. The acceleration charge suppression signal 64 that is a result of the NAND is “High”. As a result, the NMOSFET of the discharge circuit 22 does not work, and charge does not move from the power supply voltage 65 to the output 53 of the voltage dividing circuit.

  In this state, when the enable signal is raised, the stable charging time is not reached and the acceleration charging time 81 is reached, the enable inversion signal 59 becomes “Low”, and the voltage dividing input circuit 15 is turned on. At the same time, the enable signal becomes “Low”, the switch is turned off, the discharge circuit 22 is closed, and the output 53 of the voltage dividing circuit cannot move to the ground potential 67, and the potential of the output 53 of the voltage dividing circuit is maintained. The

  In the direct voltage dividing circuit 11, since the divided voltage 53 is initially low, the same enable signal 61 becomes “High” so that the comparison circuit 12 is activated, and the comparison circuit output 55 is “High”. It becomes.

  Since the comparison circuit output 55 of the comparison circuit 12 is “High”, the NOT circuit output 57 logically inverted by the NOT circuit 17 becomes “Low”, so that the clock of the D-type flip-flop 13 is not input. Since the reset input is also the enable inversion signal 56, the Q output 62 of the D-type flip-flop 13 remains “Low” even when “High”. As a result, a result obtained by ANDing the AND circuit 14 with the comparison circuit output 55 of the comparison circuit 12 remains “Low” and becomes a detection result 58.

  On the other hand, if the Q output 62 of the D-type flip-flop 13 is “Low”, the NOT circuit output 63 logically inverted by the NOT circuit 18 becomes “High”. Since the comparison circuit output 55 of the comparison circuit 12 is also “High” as described above, the result of taking the NAND that is the logical product inversion circuit in the AND circuit 19 is also “Low”, and the acceleration charge suppression signal 64 is turned OFF. . As a result, the acceleration charging circuit 21 in which the acceleration charge suppression signal 64 is the gate input of the PMOSFET starts to operate, the power supply voltage 65 is directly connected to the output 53 of the voltage dividing circuit, and charge flows out to the output 53 of the voltage dividing circuit and accelerates. Charged.

  As a result, when the acceleration charging is performed and the divided voltage 53 is higher than the reference voltage 54, the direct voltage dividing circuit 11 ends the accelerated charging time 82, the comparison circuit 12 is activated, and the comparison circuit output 55 is “ It becomes “Low” and the stabilization time 83 starts.

  As a result, the comparison circuit output 55 of the comparison circuit 12 also becomes “Low”, the NOT circuit output 57 logically inverted by the NOT circuit 17 becomes “High”, the clock of the D-type flip-flop 13 is input, and the reset input also Since the enable inversion signal 56 is “High”, and the power supply voltage 68 that is “High” is the input D, the Q output 62 of the D-type flip-flop 13 becomes “High”. Nevertheless, the AND result of the logical product in the AND circuit 14 with the comparison circuit output 55 of the comparison circuit 12 remains “Low” and becomes the detection result 58.

  On the other hand, when the Q output 62 of the D-type flip-flop 13 is “High”, the NOT circuit output 63 logically inverted by the NOT circuit 18 becomes “Low”, and the comparison circuit output 55 of the comparison circuit 12 is also “Low”. As a result, the NAND circuit 19 takes the NAND which is the logical product inversion circuit, and the result is “High”, and the acceleration charge suppression signal 64 is turned ON. As a result, the acceleration charging circuit 21 in which the acceleration charging suppression signal 64 is the gate input of the PMOSFET is stopped, the power supply voltage 65 is not directly connected to the output 53 of the voltage dividing circuit, and charge flows to the output 53 of the voltage dividing circuit. Disappear.

  Thereafter, the Q output 62 of the D-type flip-flop 13 becomes “High” and a reset signal is input, that is, it remains “High” until the enable inversion signal 56 becomes “Low”.

  As a result, finally, the divided voltage 53 is stably divided in the ratio of the measured voltage-side resistors 71, 72, 73 and the ground-side resistor 74, and the stabilization time 83 ends. Enter 86.

  If the reference voltage 54, which is a threshold value, is higher than the divided voltage 53 after the stabilization time has elapsed, that is, the comparison (+) time 84, 86, the comparison circuit output 55 of the comparison circuit 12 becomes "High" and the D-type flip-flop Since the Q output 62 of the group 13 continues to be “High”, the detection result 58 output from the AND circuit 14 eventually becomes “High”. Further, the Q output 62 of the D-type flip-flop 13 is AND circuit 19 even if the NOT circuit output 63 logically inverted by the NOT circuit 18 becomes “Low” and the comparison circuit output 55 of the comparison circuit 12 is “High”. The result of taking the NAND which is the logical product inversion circuit becomes “High”, and the acceleration charge suppression signal 64 remains ON.

  On the other hand, if the reference voltage 54, which is a threshold value, is lower than the output 53 of the voltage dividing circuit after the stabilization time has elapsed, that is, the comparison circuit output 55 of the comparison circuit 12 becomes “Low” during the comparison (−) time 85, and D Even if the Q output 62 of the flip-flop 13 continues to be “High”, the detection result 58 output from the AND circuit 14 eventually becomes “Low”. Further, since the NOT circuit output 63 logically inverted by the NOT circuit 18 is also “Low”, and the comparison circuit output 55 of the comparison circuit 12 is “Low”, the AND circuit 19 uses the NAND that is the logical product inversion circuit. The result obtained is “High”, and the acceleration charge suppression signal 64 remains ON.

  Finally, when the enable signal becomes “Low”, the inverted signal 59 of the enable signal becomes “High” and the voltage dividing input circuit 15 is turned OFF, so that the divided voltage is directly supplied to the ground potential 52 by the voltage dividing circuit 11. Since the enable inversion signal 59 becomes “High” at the same time as the voltage drop of the voltage 53, the voltage dividing input circuit 15 is turned off and directly becomes the ground potential 52 by the voltage dividing circuit 11, and the residual charge at the output 53 of the voltage dividing circuit. Flows to the ground potential 52, the output 53 of the voltage dividing circuit becomes a low voltage which is the ground potential, and the gate input of the NMOSFET which is the discharge circuit 22 is turned ON by the enable inversion signal 66, so the output 53 of the voltage dividing circuit Is directly connected to the ground potential 67, the residual charge at the output 53 of the voltage dividing circuit is accelerated to the ground potential 67 and discharged, and the output 53 of the voltage dividing circuit is grounded. Become accelerated to a low voltage is position. As a result, it is possible to prevent a malfunction that occurs when the output 53 of the voltage dividing circuit is not lowered at the start of the operation and the residual charge remains and is higher than the reference voltage 54.

  Further, since the same enable signal 61 is “Low”, the comparison circuit 12 stops, the comparison circuit output 55 becomes “Low”, and the Q output 62 of the D-type flip-flop 13 of the D-type flip-flop 13 is also an enable inversion signal. 56 becomes “High”, a reset input is input and becomes “Low”, and the detection result 58 that is the result of AND that is the logical product of the AND circuit 14 from the comparison circuit output 55 of the comparison circuit 12 also becomes “Low”. The comparison time ends, and 87 is reached after the operation ends.

  After the operation is completed 87, the output 63 of the NOT circuit logically inverted by the NOT circuit 18 of the Q output 62 of the D-type flip-flop 13 also becomes “High”, and the NAND circuit 19 performs a logical product from the comparison circuit output 55 of the comparison circuit 12. Acceleration charge suppression signal 64, which is the result of NAND that is the inversion of, also becomes “High”, thereby stopping the operation of acceleration charge circuit 21 in which acceleration charge suppression signal 64 is the gate input of PMOSFET. As a result, the PMOSFET of the voltage drop circuit 21 remains OFF, and charges do not move from the power supply voltage 65 to the output 53 of the voltage dividing circuit.

In this way, since the output 53 of the voltage dividing circuit becomes a potential close to the reference voltage 54 which is the threshold value during the acceleration charging time 82, the ratio of the measured voltage side resistors 71, 72, 73 and the ground side resistor 74 is calculated from this potential. The stabilization time 83 in which the pressure is divided is extremely short. In addition, since the accelerated charging time 82 is sufficiently short, the comparison time can be entered in a time much shorter than the stabilization time 182 of the conventional circuit even if both the times are combined. In addition, it is not necessary to determine whether or not the circuit is stable as in the case of the delay circuit 113 in the conventional circuit, and since it is determined whether or not the stabilization time has been completed by the self circuit, it is necessary to provide a margin time. There is no, it can be operated quickly.

It is a circuit diagram showing one embodiment of the present invention. 2 is a timing chart of the circuit of FIG. 1 relating to the present invention. It is a circuit diagram which shows a prior art. It is a timing chart of the circuit of FIG. 3 regarding a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Voltage divider circuit 12 Comparison circuit 13 D type flip-flop 14 AND circuit 15 Voltage divider input circuit 17 NOT circuit 18 NOT circuit 19 NAND circuit 21 Acceleration charging circuit 22 Discharge circuit 51 Voltage to be measured 52 Ground potential 53 Output of voltage divider circuit 54 Reference voltage 55 Comparison circuit output 56 Enable inversion signal 57 NOT circuit output 58 Detection result 59 Enable inversion signal 60 Divided input voltage 61 Enable signal 62 D-type flip-flop Q output 63 NOT circuit output 64 Acceleration charge suppression signal 65 Power supply voltage 66 Enable inversion signal 67 Ground potential 68 Power supply voltage 71, 72, 73 Voltage-side resistance to be measured 74 Ground-side resistance 81 Before operation 82 Accelerated charging time 83 Stabilization time 84, 86 Comparison (+) time 85 Comparison (-) time 87 Operation 111 voltage divider after completion 12 Comparison circuit 113 Delay circuit 114 AND circuit 115 Voltage division input circuit 151 Voltage to be measured 152 Ground potential 153 Voltage division circuit output 154 Reference voltage 155 Comparison circuit output 156 Enable signal 157 Delay enable signal 158 Detection result 159 Enable inversion signal 160 minutes Voltage input voltage 161 Enable signal 171, 172, 173 Measured voltage side resistance 174 Ground side resistance 181 Before operation start 182 Stabilization time 183, 185 Comparison (+) time 184 Comparison (-) time 186 After operation end

Claims (4)

When outputting a detection result using a voltage dividing circuit that provides a divided voltage obtained by dividing the voltage to be measured by the ratio of the resistance to the ground potential, and a comparison circuit that compares the output of the voltage dividing circuit with a reference voltage In the voltage detection circuit that is activated by the enable signal and outputs a detection signal that is larger or smaller than the reference voltage having the measured voltage as a threshold,
A D-type flip-flop having a power supply voltage as a D input, an inverted signal of the comparison circuit output as a clock, and an enable inverted signal as a reset input;
A detection output circuit that uses the Q output of the D-type flip-flop as a detection signal by a logical product with the output of the comparison circuit;
An acceleration charging circuit that serves as a control signal for controlling connection from the power supply voltage to the divided voltage by a negative logical product of the inverted signal of the D-type flip-flop Q output and the comparison circuit output;
A voltage detection circuit comprising: Further, the operation of the comparison circuit is performed by the enable signal, and the discharge circuit that sets the switch connected to the ground potential from the divided voltage by the enable inversion signal as an OFF signal,
A voltage dividing input circuit having an ON signal as a switch connected to the voltage dividing circuit from the voltage to be measured by an enable signal;
The voltage detection circuit according to claim 1, further comprising:   3. The voltage detection circuit according to claim 2, wherein the acceleration charging circuit, the discharging circuit, and the voltage dividing input circuit comprise MOSFETs.   The acceleration charging circuit is composed of a circuit that generates an inverted signal of the D-type flip-flop Q output and a NAND signal of the output of the comparison circuit, and this NAND signal is a gate input of the PMOSFET connected from the power supply voltage to the divided voltage, 4. The discharge circuit comprises a circuit in which an enable inversion signal is a gate input of an NMOSFET, and the voltage dividing input circuit comprises a circuit in which an enable inversion signal is a gate input of a PMOSFET. Voltage detection circuit.

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