JP2010147389A - Plasma damage evaluation method, and method for manufacturing semiconductor device employing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To accurately evaluate plasma damage that a gate insulating film receives when forming an interlayer insulating film. <P>SOLUTION: A plasma damage evaluation method includes: a step of forming a gate insulating film 13 on a semiconductor substrate 10; a step of forming a gate electrode 14 on the gate insulating film 13; a step of forming a diffusion layer 12 inside the semiconductor substrate 10; a step of removing an interlayer insulating film 15 to expose an upper surface of the gate electrode 14; a second measuring step of measuring electrical characteristics of the gate insulating film 13 by electrifying the exposed gate electrode 14; and an evaluation step of comparing a measurement result in a first measuring step with a result of the measurement in the second measuring step. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a plasma damage evaluation method and a semiconductor device manufacturing method using the same.

  In recent years, with the progress of miniaturization of large scale integrated circuits (Large Scale Integration, LSI), a low dielectric constant film (Low-k insulating film) whose dielectric constant is smaller than that of a silicon oxide film is used as a wiring interlayer insulating film. Yes. The low dielectric constant film is mainly formed by using a plasma chemical vapor deposition (CVD) method. Therefore, there is a problem that electrons and ions generated by the plasma conditions at the time of forming the low dielectric constant film adversely affect the gate insulating film.

  Therefore, the technique of Patent Document 1 is known as a method for evaluating plasma damage. Patent Document 1 discloses a gate insulating film formed on a semiconductor substrate, a gate electrode formed on the gate insulating film, a TEG (Test Element Group) conductor pattern connected to the gate electrode, and a TEG conductor pattern. A semiconductor device is described that includes an interlayer insulating film formed thereon, and holes and grooves formed in the interlayer insulating film by dry etching. And it is described that by having the said structure, the area which affects the plasma damage amount can be limited.

Patent Document 2 describes a method for evaluating plasma damage by sequentially forming a gate insulating film and a gate electrode formed on a semiconductor substrate and directly applying plasma to the gate electrode. Thus, it is described that the damage to the insulating film caused by the charge directly entering the contact hole or the through hole in the plasma process can be detected with high sensitivity.
JP 2007-116042 A JP 2000-150606 A

  In the technique described in Patent Document 1, the obtained evaluation result is the sum of the plasma damage that occurs during the formation of the interlayer insulating film and the plasma damage that occurs during dry etching. Therefore, it is difficult to evaluate only the plasma damage when forming the interlayer insulating film.

  In the case of using the method disclosed in Patent Document 2, an interlayer insulating film is not actually formed. Therefore, it is impossible to accurately evaluate the plasma damage when forming the interlayer insulating film.

According to the present invention, forming a damage evaluation element having a diffusion layer, a test gate insulating film, and a test gate electrode on a substrate;
A first measurement step of energizing the formed test gate electrode to measure electrical characteristics of the test gate insulating film;
Forming an interlayer insulating film covering the test gate electrode by a plasma vapor phase method;
Removing the interlayer insulating film and exposing an upper surface of the test gate electrode;
A second measurement step of measuring the electrical characteristics of the test gate insulating film by energizing the exposed test gate electrode;
An evaluation step for comparing the measurement result obtained in the first measurement step with the measurement result obtained in the second measurement step;
A plasma damage evaluation method is provided.

According to the present invention, a step of forming a damage evaluation element having a diffusion layer, a test gate insulating film, and a test gate electrode on a substrate;
Forming a semiconductor element having the diffusion layer, the product gate insulating film, and the product gate electrode on the substrate;
A first measurement step of energizing the formed test gate electrode to measure electrical characteristics of the test gate insulating film;
Forming a test interlayer insulating film covering the test gate electrode by a plasma vapor phase method;
Removing the test interlayer insulating film and exposing an upper surface of the test gate electrode;
A second measurement step of measuring the electrical characteristics of the test gate insulating film by energizing the exposed test gate electrode;
An evaluation step for comparing the measurement result obtained in the first measurement step with the measurement result obtained in the second measurement step;
When the evaluation result obtained in the evaluation step satisfies a predetermined threshold, forming a product interlayer insulating film that covers the product gate electrode under plasma conditions in which the test interlayer insulating film is formed;
A method for manufacturing a semiconductor device is provided.

  According to the present invention, before and after the step of forming the interlayer insulating film by the plasma CVD method, the electrical characteristics of the gate insulating film are measured and compared. Thereby, it is possible to grasp how much the plasma during the formation of the interlayer insulating film deteriorates the electrical characteristics of the gate insulating film. Therefore, it is possible to accurately evaluate the plasma damage when forming the interlayer insulating film.

  According to the present invention, the plasma damage that the gate insulating film undergoes when forming the interlayer insulating film can be evaluated by an accurate and simple method.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

(First embodiment)
Hereinafter, the plasma damage evaluation method of the present embodiment will be specifically described.

  FIG. 1 is a diagram for explaining an evaluation method according to the first embodiment of the present invention. FIGS. 1A to 1C are cross-sectional views of a test semiconductor device in each step of the evaluation method of the present embodiment. FIGS. 1D to 1F are top views of the test semiconductor device in each step of the evaluation method of the present embodiment. As shown in the drawing, in the method of this embodiment, a test semiconductor device having a damage evaluation element is formed on the test semiconductor substrate 10. FIG. 1A corresponds to FIG. 1D, FIG. 1B corresponds to FIG. 1E, and FIG. 1C corresponds to FIG. 1F.

  The method according to the present embodiment is a damage evaluation element having a diffusion layer 12, a gate insulating film 13 (test gate insulating film), and a gate electrode 14 (test gate electrode) on a semiconductor substrate 10 such as a silicon substrate. A first measuring step of energizing the formed gate electrode 14 to measure the electrical characteristics of the gate insulating film 13, and an interlayer insulating film 15 covering the gate electrode 14 by plasma CVD. A step of removing the interlayer insulating film 15 to expose the upper surface of the gate electrode 14; a second measuring step of measuring the electrical characteristics of the gate insulating film 13 by energizing the exposed gate electrode 14; And an evaluation step for comparing the measurement result obtained in the first measurement step with the measurement result obtained in the second measurement step.

  In the present embodiment, the step of forming the damage evaluation element includes the step of forming the diffusion layer 12 in the semiconductor substrate 10, the step of forming the gate insulating film 13 on the diffusion layer 12, and the step of forming on the gate insulating film 13. Forming a gate electrode 14. In the first and second measurement steps, the leakage current between the gate electrode 14, the gate insulating film 13 and the diffusion layer 12 is measured. In the evaluation step, the leakage current measured in the first measurement step and the first The leakage current measured in the second measurement process is compared.

  Hereinafter, each step will be described in detail.

  First, as shown in FIGS. 1A and 1D, an element isolation layer 11 and a diffusion layer 12 are formed in a semiconductor substrate 10. Next, after forming the gate insulating film 13 on the element isolation layer 11 and the diffusion layer 12, the gate electrode 14 is formed on the gate insulating film 13.

  Here, the gate electrode 14 is formed of polysilicon or a metal layer. Examples of the metal layer include a layer made of any of aluminum, hafnium, lanthanum, titanium, tantalum, and copper.

  Further, the gate electrode 14 is formed above the element isolation layer 11 and the diffusion layer 12 across the boundary between the element isolation layer 11 and the diffusion layer 12. At this time, the gate electrode 14 is formed so that the area of the gate electrode 14 on the element isolation layer 11 is larger than the area of the gate electrode 14 on the diffusion layer 12 in plan view. The width of the gate electrode 14 on the diffusion layer 12 is preferably equal to the width of the product transistor. The area ratio between the gate electrode 14 on the diffusion layer 12 and the gate electrode 14 on the element isolation layer 11 is the antenna ratio of the gate wiring layer in the semiconductor device as a product, that is, the portion located on the substrate and the element isolation. It can also be designed appropriately according to the area ratio with the portion located on the film.

  Furthermore, as illustrated in FIG. 1D, the gate electrode 14 may have a shape in which a rectangle having a relatively large area and a rectangle having a relatively small area are joined in plan view. At this time, a rectangular gate electrode having a relatively large area is formed on the element isolation layer 11, and a rectangular gate electrode having a relatively small area is formed on the diffusion layer 12. By doing so, the tester can be easily brought into contact with the gate electrode 14 in the first and second measurement steps. Further, the flatness of CMP can be improved in the removal of the interlayer insulating film 15 described later.

  In FIG. 1D, the diffusion layer 12 is formed so as to extend in the semiconductor substrate 10 while being covered with the gate electrode 14 at the center. However, the end portion of the gate electrode 14 may be covered with the diffusion layer 12 and the diffusion layer 12 may be extended into the semiconductor substrate 10.

  Next, in the structure shown in FIGS. 1A and 1D, a leakage current is measured by applying a voltage between the gate electrode 14, the gate insulating film 13, and the diffusion layer 12 (first measurement). Process). As a method for measuring the leakage current, there is a method for gradually increasing the voltage applied between the gate electrode 14, the gate insulating film 13, and the diffusion layer 12 and measuring the value of the current flowing from the gate electrode 14 to the semiconductor substrate 10. .

  Next, an interlayer insulating film 15 is formed by plasma CVD so as to cover the semiconductor substrate 10, the element isolation layer 11, the diffusion layer 12, and the gate electrode 14 (FIGS. 1B and 1E). As the plasma, for example, high-density plasma such as ICP (Inductively Coupled Plasma) or ECR (Electron Cyclotron Resonance) plasma can be used.

  Examples of the interlayer insulating film 15 include a low dielectric constant film having a relative dielectric constant of 3.9 or less, a silicon oxide film, a silicon nitride film, a silicon carbide film, and a silicon carbonitride film.

  Thereafter, as shown in FIGS. 1C and 1F, the interlayer insulating film 15 is removed by CMP to expose the gate electrode 14. At this time, the surface of the gate electrode 14 may be planarized by subsequent polishing by a CMP method.

  Here, in the step of forming the gate electrode 14 described above, the gate electrode 14 is preferably formed so as to cover 30% or more of the surface area of the semiconductor substrate 10. By doing so, the flatness of CMP is improved, and it can be prevented that the gate electrode 14 disappears due to excessive polishing or the interlayer insulating film 15 remains without being removed. Therefore, the gate electrode 14 can be uniformly exposed in the surface of the semiconductor substrate 10.

  Next, in the structure shown in FIG. 1C and FIG. 1F, a leakage current is measured by applying a voltage between the exposed gate electrode 14, gate insulating film 13, and diffusion layer 12 (first). Second measuring step). At this time, it is preferable to employ the same method as the first measurement step as a method for measuring the leakage current.

  Next, the leakage currents obtained in the first measurement process and the second measurement process are compared with each other. Specifically, the difference between the leak current measured in the second measurement process and the leak current measured in the first measurement process is detected. By doing so, it is possible to detect how much the plasma during the formation of the interlayer insulating film 15 has lowered the insulating property of the gate insulating film 13. When the difference between the two is equal to or greater than a predetermined value, it is evaluated that the gate insulating film 13 has been damaged by the plasma CVD method.

  It continues and demonstrates the effect of this embodiment. According to this embodiment, before and after the step of forming the interlayer insulating film 15 by the plasma CVD method, the electrical characteristics of the gate insulating film 13 are measured and compared. Thereby, it is possible to grasp how much the plasma during the formation of the interlayer insulating film 15 deteriorates the electrical characteristics of the gate insulating film 13. Therefore, it is possible to accurately evaluate the plasma damage when the interlayer insulating film 15 is formed.

  In the plasma CVD method, electrons flying from plasma or positive ions such as argon and helium may reach the surface of the semiconductor substrate 10 with high energy. In that case, the plasma potential on the surface of the semiconductor substrate 10 becomes non-uniform, whereby charges are transferred from the gate electrode 14 to the inside of the semiconductor substrate 10 and moved from a place with a high plasma potential to a place with a low plasma potential. When the gate electrode 14 or a wiring connected to the gate electrode 14 exists on the semiconductor substrate 10, ions and electrons flow out from the metal constituting the gate electrode 14 and the wiring toward the semiconductor substrate 10. As a result, a large voltage is applied to the gate insulating film 13 existing between the gate electrode 14 and the semiconductor substrate 10, and as a result, a dielectric breakdown occurs and a leakage current increases. Thus, when the leakage current of the gate insulating film 13 increases, a malfunction occurs in the operation as a function switch of the semiconductor device. Therefore, the circuit does not operate normally, and the operation of the semiconductor device is abnormal.

  However, in this embodiment, before and after the step of forming the interlayer insulating film 15, the leakage currents between the gate electrode 14, the gate insulating film 13, and the diffusion layer 12 are measured and compared. As a result, it is possible to grasp how much the ions and electrons generated under the plasma conditions during the formation of the interlayer insulating film 15 have lowered the insulating property of the gate insulating film 13. Therefore, it is possible to easily and accurately evaluate the characteristics of the manufactured transistor and to provide a semiconductor device with good quality.

(Second Embodiment)

  FIG. 2 is a diagram illustrating an evaluation method according to the second embodiment. FIG. 2A is a cross-sectional view of a test semiconductor device used in the evaluation method of this embodiment. FIG. 2B is a top view of the test semiconductor device used in the evaluation method of this embodiment.

  As shown in FIG. 2B, in the present embodiment, a semiconductor device having a plurality of damage evaluation elements is formed on the test semiconductor substrate 10. In this embodiment, a plurality of gate electrodes 14 extending from the diffusion layer 12 to the element isolation layer 11 are formed so as to have different areas. Further, the method further includes a step of forming a dummy electrode 17 adjacent to the gate electrode 14. In the first and second measurement steps, the plurality of gate electrodes 14 are energized, respectively, and the leakage currents in the plurality of damage evaluation elements are individually measured. Others are the same as in the first embodiment.

  The dummy electrode 17 is formed in a place where the evaluation is not hindered, specifically in a space between the plurality of gate electrodes 14. The dummy electrode 17 may be formed on the element isolation layer 11. In the present embodiment, “adjacent” means that the dummy electrode 17 is arranged in parallel with the gate electrode 14 at a predetermined interval. By doing so, planarization by CMP can be improved.

  The dummy electrode 17 is preferably formed so that the gate electrode 14 and the dummy electrode 17 cover 30% or more of the surface area of the semiconductor substrate 10. By doing so, planarization by CMP can be further improved.

  In the evaluation process of this embodiment, the evaluation results of a plurality of damage evaluation elements having different areas of the gate electrode 14 are compared with each other. In these damage evaluation elements, the area of the gate electrode 14 formed on the diffusion layer 12 is the same, but the area of the gate electrode 14 formed on the element isolation layer 11 is different. Therefore, the plasma damage generated in the gate insulating film 13 varies depending on the area of the gate electrode 14. Therefore, by comparing the evaluation results with each other, it is possible to evaluate the magnitude of the plasma damage received by the gate insulating film 13 due to the difference in antenna ratio.

  As described above, in this embodiment, planarization by CMP can be improved by forming the dummy electrode 17 around the gate electrode 14. Therefore, it can be prevented that the gate electrode 14 disappears due to excessive polishing and the interlayer insulating film 15 is not removed and remains on the surface of the gate electrode 14. Accordingly, it is possible to stably evaluate plasma damage.

  In the present embodiment, a plurality of damage evaluation elements having different areas of the gate electrode 14 in plan view are formed. By doing so, the magnitude of the plasma damage received by the gate insulating film 13 due to the difference in antenna ratio can be accurately evaluated.

(Third embodiment)
FIG. 3 is a diagram for explaining an evaluation method according to the third embodiment. FIGS. 3A and 3B are cross-sectional views of a test semiconductor device used in the evaluation method of this embodiment.

  In the present embodiment, in addition to the steps described in the first embodiment, a step of filling the gate electrode 25 with the buried insulating film 24 before forming the interlayer insulating film 26 and a buried portion located above the gate electrode 25 are performed. A step of removing the insulating film 24 and planarizing the upper surface of the gate electrode 25. In the first measurement step, the leakage current between the gate electrode 25, the gate insulating film 23, and the diffusion layer 22 from which the buried insulating film 24 has been removed is measured. Others are the same as in the first embodiment.

  Hereinafter, this embodiment will be described in detail. First, as shown in FIG. 3A, the element isolation layer 21 and the diffusion layer 22 are formed in the semiconductor substrate 20. Next, a gate insulating film 23 is formed on the element isolation layer 21 and the diffusion layer 22.

  Next, after forming the gate electrode 25 on the gate insulating film 23, the gate electrode 25 is embedded with the embedded insulating film 24. Here, the buried insulating film 24 can be formed of a silicon nitride film by LP (Low-Pressure) -CVD, for example. Thereafter, the surface of the gate electrode 25 is planarized while removing the buried insulating film 24 by CMP.

  Next, in the structure shown in FIG. 3A, a leakage current is measured by applying a voltage between the gate electrode 25, the gate insulating film 23, and the diffusion layer 22 (first measurement step).

  Next, an interlayer insulating film 26 is formed by plasma CVD so as to cover the diffusion layer 22, the gate electrode 25, and the buried insulating film 24 (FIG. 3B).

  Thereafter, the interlayer insulating film 26 is removed by a CMP method, and the surfaces of the gate electrode 25 and the buried insulating film 24 are exposed. At this time, the exposed surface of the gate electrode 25 is planarized by subsequent polishing by a CMP method.

  Next, a voltage is applied between the exposed gate electrode 25, gate insulating film 23, and diffusion layer 22 to measure the leakage current (second measurement step). At this time, it is preferable to employ the same method as the first measurement step as a method for measuring the leakage current.

  Next, the leakage currents obtained in the first current measurement step and the second current measurement step are compared with each other. By doing so, plasma damage generated in the gate insulating film 23 when the interlayer insulating film 26 is formed can be evaluated.

  As described above, in this embodiment, the surface of the gate electrode 25 is previously planarized by the CMP method, and then the interlayer insulating film 26 is formed. Thus, in the step of removing the interlayer insulating film 26, the interlayer insulating film 26 can be smoothly removed from the surface of the gate electrode 25 while preventing the gate electrode 25 from being lost due to excessive polishing. Accordingly, it is possible to stably evaluate plasma damage.

(Fourth embodiment)
FIG. 4 is a diagram for explaining an evaluation method according to the fourth embodiment of the present invention. 4A to 4C are cross-sectional views of the test semiconductor device in each step of the evaluation method of this embodiment. 4D to 4F are top views of the test semiconductor device in each step of the evaluation method of the present embodiment. As shown in the drawing, in the method of the present embodiment, a test semiconductor device having a damage evaluation transistor on a semiconductor substrate 30 is formed. 4 (a) corresponds to FIG. 4 (d), FIG. 4 (b) corresponds to FIG. 4 (e), and FIG. 4 (c) corresponds to FIG. 4 (f).

  Specifically, the step of forming the element for damage evaluation includes the step of forming the gate insulating film 33 on the semiconductor substrate 30, the step of forming the gate electrode 34 on the gate insulating film 33, the source / drain, Forming a second diffusion layer 35, and forming a source electrode 36a and a drain electrode 36b on the second diffusion layer 35.

  In the step of forming the interlayer insulating film 37, the interlayer insulating film 37 is formed so as to cover the periphery of the source electrode 36a and the drain electrode 36b. In the step of exposing the gate electrode 34, the upper surfaces of the source electrode 36a and the drain electrode 36b are exposed. In the first and second measurement steps, the threshold value of the transistor between the gate electrode 34 and the source electrode 36a or the drain electrode 36b is measured. In the evaluation step, the threshold value measured in the first measurement step is compared with the threshold value measured in the second measurement step.

  Hereinafter, each step will be described in detail.

  First, as shown in FIGS. 4A and 4D, the element isolation layer 31 is formed in the semiconductor substrate 30. Next, an n-type impurity is implanted into the semiconductor substrate 30 to form an n-type diffusion layer (first diffusion layer) 32, and then a gate insulating film 33 is formed on the n-type diffusion layer 32. Next, after forming a gate electrode 34 on the gate insulating film 33, impurities are implanted using the gate electrode 34 as a mask to form a p-type diffusion layer (second diffusion layer) 35. Next, a source electrode 36 a and a drain electrode 36 b are formed on the p-type diffusion layer 35.

  Here, the source electrode 36a and the drain electrode 36b can be formed from the same film. The gate electrode 34, the source electrode 36a, and the drain electrode 36b are formed from polysilicon or metal. Examples of the metal layer include a layer made of any of aluminum, hafnium, lanthanum, titanium, tantalum, copper, and the like.

Next, in the structure shown in FIGS. 4A and 4D, the threshold value of the transistor between the gate electrode 34 and the source electrode 36a or the drain electrode 36b is measured (first measurement step). The measurement method of the threshold value of the transistor, for example, there is a method of measuring the drain current _{I DS} while sweeping the voltage _{V GS} between the gate electrode 34-the source electrode 36b relative to the voltage _{V DS} between the source electrode 36a- drain electrode 36b .

  Next, an interlayer insulating film 37 is formed by plasma CVD so as to cover the semiconductor substrate 30, the element isolation layer 31, the gate electrode 34, the source electrode 36a, the drain electrode 36b, and the p-type diffusion layer 35 (FIG. 4B). ), (E)). As the plasma, for example, high-density plasma such as ICP or ECR plasma can be used.

  Here, examples of the interlayer insulating film 37 include a low dielectric constant film having a relative dielectric constant of 3.9 or less, a silicon oxide film, a silicon nitride film, a silicon carbide film, and a silicon carbonitride film.

  Thereafter, as shown in FIGS. 4C and 4F, the interlayer insulating film 37 is removed by CMP to expose the gate electrode 34, the source electrode 36a, and the drain electrode 36b, respectively. At this time, the surfaces of the gate electrode 34, the source electrode 36a, and the drain electrode 36b are planarized by subsequent polishing by the CMP method.

  Here, the gate electrode 34, the source electrode 36a, and the drain electrode 36b are preferably formed so as to cover 30% or more of the surface area of the semiconductor substrate 30 in plan view. By doing so, the flatness of CMP is improved. Accordingly, it is possible to prevent any of the gate electrode 34, the source electrode 36a, and the drain electrode 36b from being lost due to excessive polishing, or the interlayer insulating film 37 from remaining without being removed. Therefore, the gate electrode 34, the source electrode 36a, and the drain electrode 36b can be uniformly exposed in the plane of the semiconductor substrate 30.

  Next, in the structure shown in FIGS. 4C and 4F, the threshold value of the transistor between the exposed gate electrode 34 and the source electrode 36a or the drain electrode 36b is measured (second measurement step). . At this time, it is preferable to employ the same method as the first measurement step as the method for measuring the threshold value of the transistor.

  Next, the threshold values of the transistors obtained in the first measurement process and the second measurement process are compared with each other. Specifically, the difference between the threshold value of the transistor measured in the second measurement step and the threshold value of the transistor measured in the first measurement step is detected. In this way, it is possible to detect how much the transistor characteristics are deteriorated due to the accumulation of plasma in the gate insulating film 33 when the interlayer insulating film 37 is formed. When the difference between the two is equal to or greater than a predetermined value, it is evaluated that the gate insulating film 33 has been damaged by the plasma vapor phase method.

  It continues and demonstrates the effect of this embodiment. According to this embodiment, before and after the step of forming the interlayer insulating film 37 by the plasma CVD method, the electrical characteristics of the gate insulating film 33 are measured and compared. Thereby, it is possible to grasp how much the plasma during the formation of the interlayer insulating film 37 deteriorates the electrical characteristics of the gate insulating film 33. Therefore, it is possible to accurately evaluate the plasma damage when the interlayer insulating film 37 is formed.

  In the plasma CVD method, electrons flying from plasma or positive ions such as argon and helium may reach the surface of the semiconductor substrate 30 with high energy. In that case, the plasma potential on the surface of the semiconductor substrate 30 becomes non-uniform, whereby charges are transferred from the gate electrode 34 to the inside of the semiconductor substrate 30 and moved from a place with a high plasma potential to a place with a low plasma potential. As a result, electrons and ions are trapped in the gate insulating film 33, and the threshold voltage required for operating the transistor is shifted. When such a threshold shift occurs, a malfunction occurs in the operation of a transistor serving as a function switch of the semiconductor device. For this reason, the circuit does not operate normally, and the operation of the semiconductor device is abnormal.

  However, in this embodiment, before and after the step of forming the interlayer insulating film 37, the threshold value of the transistor between the gate electrode 34 and the source electrode 36a or the drain electrode 36b is measured and compared. Thereby, it is possible to grasp how much the threshold shift of the transistor has occurred. Therefore, it is possible to easily and accurately evaluate the characteristics of the manufactured transistor and to provide a semiconductor device with good quality.

  In this embodiment, before and after the step of forming the interlayer insulating film 37, the leakage current between the gate electrode 34, the gate insulating film 33, and the n-type diffusion layer (first diffusion layer) 32 is measured, You may compare both. By doing so, it is also possible to grasp how much the ions or electrons generated under the plasma conditions at the time of forming the interlayer insulating film 37 have lowered the insulating property of the gate insulating film 33.

(Fifth embodiment)
FIG. 5 is a diagram for explaining an evaluation method according to the fifth embodiment. FIG. 5A is a cross-sectional view of a test semiconductor device used in the evaluation method of this embodiment. FIG. 5B is a top view of the test semiconductor device used in the evaluation method of the present embodiment.

  As shown in FIG. 5B, in this embodiment, a semiconductor device having a plurality of damage evaluation transistors is formed on a test semiconductor substrate 30. In the present embodiment, the areas of the plurality of gate electrodes 34 on the element isolation layer 31 are formed so as to be different from each other in plan view. In addition, the source electrode 36a and the drain electrode 36b of the evaluation transistor are formed with the same area, but the areas of the source electrode 36a and the drain electrode 36b of the evaluation transistor are different between the evaluation transistors. In addition to the steps described in the fourth embodiment, this embodiment further includes a step of forming dummy electrodes 399 adjacent to the gate electrode 34, the source electrode 36a, and the drain electrode 36b, respectively. In the first and second measurement steps, each of the plurality of gate electrodes 34 and the source electrode 36a or the drain electrode 36b is energized, and the threshold values of the transistors in the plurality of damage evaluation transistors are individually measured. Others are the same as in the fourth embodiment.

  The dummy electrode 399 is formed in a place where evaluation is not hindered, specifically in a space between a plurality of damage evaluation elements. The dummy electrode 399 is preferably formed on the element isolation layer 31. In this embodiment, “adjacent” means that the dummy electrode 399 is arranged in parallel with each of the gate electrode 34, the source electrode 36 a, and the drain electrode 36 b with a predetermined interval. By doing so, planarization by CMP can be improved.

  The dummy electrode 399 is preferably formed so that the gate electrode 34, the source electrode 36a, the drain electrode 36b, and the dummy electrode 399 cover 30% or more of the surface area of the semiconductor substrate 30 in plan view. By doing so, planarization by CMP can be further improved.

  In the evaluation process of this embodiment, the evaluation results of a plurality of evaluation transistors having different areas of the gate electrode 34 are compared with each other. In these evaluation transistors, the area of the source electrode 36a and the drain electrode 36b is the same, but the area of the gate electrode 34 is different. Therefore, the plasma damage generated in the gate insulating film 33 differs individually. Therefore, by comparing the evaluation results with each other, it is possible to evaluate the magnitude of the plasma damage received by the gate insulating film 33 due to the difference in antenna ratio.

  As described above, in this embodiment, since planarization by CMP can be improved, any of the gate electrode 34, the source electrode 36a, and the drain electrode 36b disappears due to excessive polishing, or the interlayer insulating film 37 is removed. It is possible to prevent the remaining on the surface of the gate electrode 34 without being performed. Accordingly, it is possible to stably evaluate plasma damage.

  In the present embodiment, by forming a plurality of damage evaluation elements having different areas of the gate electrode 34 in plan view, the magnitude of plasma damage received by the gate insulating film 33 due to the difference in antenna ratio can be accurately evaluated. be able to.

(Sixth embodiment)
FIG. 6 is a cross-sectional view of a test semiconductor device used in the evaluation method of this embodiment. In this embodiment, in addition to the steps described in the fourth embodiment, a step of embedding the gate electrode 46, the source electrode 47a, and the drain electrode 47b with the embedded insulating film 45 before the step of forming the interlayer insulating film 37, respectively. Removing the buried insulating film 45 located above the gate electrode 46, the source electrode 47a, and the drain electrode 47b, and planarizing the upper surfaces of the gate electrode 46, the source electrode 47a, and the drain electrode 47b, respectively. Further included. In the first measurement step, the threshold value of the transistor between the planarized gate electrode 46 and the source electrode 47a or the drain electrode 47b is measured. Others are the same as in the fourth embodiment.

  Hereinafter, this embodiment will be described in detail. First, the element isolation layer 41 is formed in the semiconductor substrate 40. Next, an n-type impurity is implanted into the semiconductor substrate 40 to form an n-type diffusion layer (first diffusion layer) 42. Next, after forming a gate insulating film 44 on the n-type diffusion layer 42, a gate electrode 46 is formed on the gate insulating film 44. Next, impurities are implanted using the gate electrode 46 as a mask to form a p-type diffusion layer (second diffusion layer) 43. Next, a source electrode 47 a and a drain electrode 47 b are formed in the p-type diffusion layer 43.

  Next, the gate electrode 46, the source electrode 47 a, and the drain electrode 47 b are embedded with a buried insulating film 45. Here, the buried insulating film 45 can be formed of, for example, a silicon nitride film by LP (Low-Pressure) -CVD. Thereafter, the buried insulating film 45 is removed by CMP to expose the surfaces of the gate electrode 46, the source electrode 47a, and the drain electrode 47b.

  Next, in the structure shown in FIG. 6, the threshold value of the transistor between the gate electrode 46 and the source electrode 47a or the drain electrode 47b is measured (first measurement step).

  Next, an interlayer insulating film (not shown) is formed by plasma CVD so as to cover the surfaces of the gate electrode 46, the source electrode 47a, the drain electrode 47b, and the buried insulating film 45, respectively.

  Thereafter, the interlayer insulating film is removed by CMP to expose the surfaces of the gate electrode 46, the source electrode 47a, the drain electrode 47b, and the buried insulating film 45, respectively.

  Next, the threshold value of the transistor between the exposed gate electrode 46 and the source electrode 47a or the drain electrode 47b is measured (second measurement step). At this time, it is preferable to employ the same method as the first measurement step as the method for measuring the threshold value of the transistor.

  Next, the threshold values of the transistors obtained in the first measurement process and the second measurement process are compared with each other. By doing so, it is possible to evaluate plasma damage generated in the gate insulating film 44 when the interlayer insulating film is formed.

  Also in this embodiment, the leakage current obtained before and after the formation of the interlayer insulating film is measured by applying a voltage between the gate electrode 46, the gate insulating film 44, and the n-type diffusion layer 42 to measure the leakage current. You may compare with each other.

  As described above, in this embodiment, the surfaces of the gate electrode 46, the source electrode 47a, and the drain electrode 47b are planarized in advance by the CMP method, and then the interlayer insulating film is formed. Thereby, in the step of removing the interlayer insulating film, it is possible to prevent the gate electrode 46 from being lost due to excessive polishing, and to smoothly remove the interlayer insulating film from the surface of the gate electrode 46. Accordingly, it is possible to stably evaluate plasma damage.

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

  For example, the test gate insulating film may be formed on a test semiconductor substrate, or may be formed on a product semiconductor substrate. When the test gate insulating film is formed on the product semiconductor substrate together with the product gate insulating film, it is preferable to form the test gate insulating film on the dicing line because it can be easily separated from the final product by dicing.

  In the fourth, fifth, and sixth embodiments, the first diffusion layer is n-type and the second diffusion layer is p-type. However, the first diffusion layer is p-type and the second diffusion layer is the second diffusion layer. The layer may be n-type.

  The present invention is not limited to an interlayer insulating film used for CMOS logic, but includes, for example, DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), flash memory, FRAM (Ferro Electric Random Access Memory). In an interlayer insulating film used in a semiconductor product having a memory circuit such as a magnetic random access memory), a resistance change memory, a semiconductor product having a logic circuit such as a microprocessor, or a hybrid semiconductor product in which these are simultaneously mounted. In contrast, it is possible to evaluate plasma damage. In addition, the present invention can evaluate plasma damage to a semiconductor device, an electronic circuit device, an optical circuit device, a quantum circuit device, a micromachine, or the like having an interlayer insulating film at least partially.

  Moreover, the semiconductor device for products can also be manufactured using the plasma damage evaluation method of the present invention. FIG. 7 is a flowchart for explaining an example of the manufacturing method of the semiconductor device. Hereinafter, an example of a manufacturing method of a semiconductor device for products using the plasma damage evaluation method of the present invention will be described with reference to FIG.

  First, a damage evaluation element and a product semiconductor element are manufactured (S10, S11). Each of the damage evaluation element and the product semiconductor element includes a diffusion layer 12, a gate insulating film 13, and a gate electrode 14 on a semiconductor substrate 10 as shown in FIG.

  Next, a voltage is applied between the gate electrode 14 of the damage evaluation element, the gate insulating film 13 and the diffusion layer 12 to measure the leakage current. In this way, the electrical characteristics of the gate insulating film 13 are measured (S12, first measurement process). Next, an interlayer insulating film 15 is formed by plasma vapor deposition so as to cover the gate electrode 14 of the element for damage evaluation (S13, FIG. 1B).

  Next, the interlayer insulating film 15 of the element for damage evaluation is removed, and the upper surface of the gate electrode 14 is exposed as shown in FIG. 1C (S14). Next, a leakage current is measured by applying a voltage between the exposed gate electrode 14, the gate insulating film 13 and the diffusion layer 12 of the damage evaluation element (S15, second measurement step).

  Next, the measurement result of the leakage current obtained in S12 and the measurement result of the leakage current obtained in S15 are compared (S16, evaluation step). As a result of comparison, when the difference between the two exceeds a predetermined value, it is evaluated that plasma damage has been received (S17Y).

  Next, the plasma conditions in S13 are controlled (S18), and the interlayer insulating film 15 is formed again under the controlled plasma conditions using another damage evaluation element. In S17, for example, plasma power and pressure are controlled.

  As a result, in S16, when the difference between the measurement result of the leakage current obtained in S12 and the measurement result of the leakage current obtained in S15 satisfies a predetermined value, it is evaluated that the plasma damage is not received (S17N). Then, an interlayer insulating film 15 is formed on the product semiconductor element under the plasma conditions evaluated as having not been damaged by plasma (S19). Next, a product semiconductor device is completed through an arbitrary manufacturing process (S20).

  Note that the structure of the damage evaluation element and the semiconductor element may be the structure shown in FIG. 4 instead of the structure shown in FIG. That is, the gate insulating film 33, the gate electrode 34, the n-type diffusion layer 32, the p-type diffusion layer 35, the source electrode 36a, and the drain electrode 36b may be formed on the substrate 30. In this case, in S12 and S15, the threshold value of the transistor between the gate electrode 34 of the damage evaluation element and the source electrode 36a or the drain electrode 36b can be measured. In this case, in S16, the threshold value measured in S12 may be compared with the threshold value measured in S15. As a result of comparison, when the difference between the two is equal to or greater than a predetermined value, it is evaluated that plasma damage has been received (S17Y). When the difference between the two is smaller than the predetermined value, it may be evaluated that plasma damage has been received (S17N). Other operations are as described above.

Furthermore, the present invention is also applicable to the following aspects.
(1) a step of forming a diffusion layer in the semiconductor substrate, a step of forming a gate insulating film on the diffusion layer, a step of forming a gate electrode on the gate insulating film, and on the semiconductor substrate and the gate electrode For the structure formed using the step of exposing the gate electrode by the step of forming an interlayer insulating film and the step of removing the interlayer insulating film by chemical mechanical polishing (CMP), the gate electrode-the gate insulation A method of evaluating plasma damage generated in the gate insulating film during the formation of the interlayer insulating film by measuring a leakage current between the film and the diffusion layer.
(2) A method for evaluating plasma damage when forming an interlayer insulating film according to (1), using a structure in which the gate electrode according to (1) occupies a ratio of 30% or more of the surface of the semiconductor substrate.
(3) forming an n-type diffusion layer in the semiconductor substrate, forming a gate insulating film on the n-type diffusion layer, forming a gate electrode on the gate insulating film, and in the semiconductor substrate Forming a p-type diffusion layer, forming a source / drain electrode on the p-type diffusion layer, forming an interlayer insulating film on the semiconductor substrate, the gate electrode, the source / drain electrode, and the interlayer insulation. For the structure formed using the step of exposing the gate electrode, the source, and the drain electrode by the step of removing the film by chemical mechanical polishing (CMP), the gate electrode-the gate insulating film-the diffusion layer The gate current, the source, and the drain electrode are measured to measure the threshold current of the transistor between the gate electrode, the source, and the drain electrode. How to evaluate the plasma damage that occurs to the gate insulating film.
(4) forming a p-type diffusion layer in the semiconductor substrate, forming a gate insulating film on the p-type diffusion layer, forming a gate electrode on the gate insulating film, and in the semiconductor substrate Forming an n-type diffusion layer, forming a source / drain electrode on the n-type diffusion layer, forming an interlayer insulating film on the semiconductor substrate, the gate electrode, the source / drain electrode, and the interlayer insulation. For the structure formed using the step of exposing the gate electrode, the source, and the drain electrode by the step of removing the film by chemical mechanical polishing (CMP), the gate electrode-the gate insulating film-the diffusion layer The gate current, the source, and the drain electrode are measured to measure the threshold current of the transistor between the gate electrode, the source, and the drain electrode. How to evaluate the plasma damage that occurs to the gate insulating film.
(5) From (3) to (4), using the structure in which the gate electrode, the source, and the drain electrode according to (3) to (4) occupy 30% or more of the surface of the semiconductor substrate. A method for evaluating plasma damage during formation of the interlayer insulating film.
(6) The step of embedding the gate insulating film and the gate electrode in (1) to (4) in the insulating film, the step of removing a part of the gate electrode by CMP, and the steps of claims 3 to 4 The step of embedding the source and drain electrodes in the insulating film, the step of removing a part of the source and drain electrodes by CMP, the step of forming the interlayer insulating film, and the CMP of the formed interlayer insulating film And measuring the leakage current between the gate electrode, the gate insulating film, and the diffusion layer for the structure formed by using the step of removing the transistor between the gate electrode, the source, and the drain electrode. A method for evaluating plasma damage generated in the gate insulating film during the formation of the interlayer insulating film by measuring the threshold value.
(7) The method according to (1) to (6), wherein the plasma damage generated in the gate insulating film is changed by changing the area of the gate electrode to evaluate the magnitude of the plasma damage.
(8) The gate electrode according to (1) to (7), or the source and drain electrodes according to (4) to (7) are made of polysilicon, according to (1) to (7) A method to evaluate plasma damage.
(9) The plasma according to (1) to (7), wherein the gate electrode according to (1) to (7) or the source and drain electrodes according to (4) to (7) are made of metal. How to evaluate damage.

  Of course, the above-described embodiments can be combined within a range in which the contents do not conflict with each other. In the above-described embodiment, the structure of each part has been specifically described. However, the structure and the like can be variously changed within a range that satisfies the present invention.

It is a figure explaining the evaluation method of a 1st embodiment. 1A to 1C are cross-sectional views of a test semiconductor device in each step of the evaluation method according to the first embodiment. FIGS. 1D to 1F are top views of the semiconductor device in each step of the evaluation method according to the first embodiment. It is a figure explaining the evaluation method of 2nd Embodiment. FIG. 2A is a cross-sectional view of a test semiconductor device used in the evaluation method of the second embodiment. FIG. 2B is a top view of the test semiconductor device used in the evaluation method of the second embodiment. It is sectional drawing of the semiconductor device for a test used with the evaluation method of 3rd Embodiment. It is a figure explaining the evaluation method of 4th Embodiment. 4A to 4C are cross-sectional views of the test semiconductor device in each step of the evaluation method according to the fourth embodiment. 4D to 4F are top views of the test semiconductor device in each step of the evaluation method according to the fourth embodiment. It is a figure explaining the evaluation method of 5th Embodiment. FIG. 5A is a cross-sectional view of a test semiconductor device used in the evaluation method of the fifth embodiment. FIG. 5B is a top view of a test semiconductor device used in the evaluation method of the fifth embodiment. It is sectional drawing of the semiconductor device for a test used with the evaluation method of 6th Embodiment. It is a flowchart explaining an example of the manufacturing method of the semiconductor device of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 11 Element isolation layer 12 Diffusion layer 13 Gate insulating film 14 Gate electrode 15 Interlayer insulating film 17 Dummy electrode 20 Semiconductor substrate 21 Element isolation layer 22 Diffusion layer 23 Gate insulating film 24 Buried insulating film 25 Gate electrode 26 Interlayer insulating film 30 Semiconductor substrate 31 Element isolation layer 32 n-type diffusion layer (first diffusion layer)
33 Gate insulating film 34 Gate electrode 35 p-type diffusion layer (second diffusion layer)
36a Source electrode 36b Drain electrode 37 Interlayer insulating film 399 Dummy electrode 40 Semiconductor substrate 41 Element isolation layer 42 n-type diffusion layer (first diffusion layer)
43 p-type diffusion layer (second diffusion layer)
44 Gate insulating film 45 Buried insulating film 46 Gate electrode 47a Source electrode 47b Drain electrode

Claims (21)

Forming a damage evaluation element having a diffusion layer, a test gate insulating film, and a test gate electrode on a substrate;
A first measurement step of energizing the formed test gate electrode to measure electrical characteristics of the test gate insulating film;
Forming an interlayer insulating film covering the test gate electrode by a plasma vapor phase method;
Removing the interlayer insulating film and exposing an upper surface of the test gate electrode;
A second measurement step of measuring the electrical characteristics of the test gate insulating film by energizing the exposed test gate electrode;
An evaluation step for comparing the measurement result obtained in the first measurement step with the measurement result obtained in the second measurement step;
Plasma damage evaluation method including   The plasma damage evaluation method according to claim 1, wherein the substrate is a test substrate.   3. The plasma damage evaluation method according to claim 1, wherein in the step of exposing the test gate electrode, the test gate electrode is exposed by a chemical mechanical polishing method.   4. The plasma damage evaluation method according to claim 1, wherein the test gate electrode is made of polysilicon.   The plasma damage evaluation method according to claim 1, wherein the test gate electrode has a metal layer. The step of forming the damage evaluation element comprises:
Forming a diffusion layer in the substrate;
Forming the test gate insulating film on the diffusion layer;
Forming the test gate electrode on the test gate insulating film;
The plasma damage evaluation method according to claim 1, comprising: In the first and second measurement steps, a leakage current between the test gate electrode, the test gate insulating film and the diffusion layer is measured,
The plasma damage evaluation method according to claim 1, wherein in the evaluation step, the leakage current measured in the first measurement step is compared with the leakage current measured in the second measurement step.   The plasma damage evaluation method according to claim 6 or 7, wherein, in the step of forming the test gate electrode, the test gate electrode is formed so that the test gate electrode covers 30% or more of a surface area of the substrate. . The step of forming the element for damage evaluation further includes a step of forming an element isolation layer in the substrate,
In the step of forming the damage evaluation element, a plurality of test gate electrodes extending from the diffusion layer to the element isolation layer are formed to have different areas.
The plasma damage evaluation method according to any one of claims 6 to 8, wherein current is supplied to each of the plurality of test gate electrodes in the first and second measurement steps.   The plasma damage evaluation method according to claim 6, further comprising a step of forming a dummy electrode adjacent to the test gate electrode.   The plasma damage evaluation method according to claim 10, wherein the test gate electrode and the dummy electrode are formed so that the test gate electrode and the dummy electrode cover 30% or more of the surface area of the substrate. Burying the test gate electrode with a buried insulating film before the step of forming the interlayer insulating film;
Removing the buried insulating film located above the test gate electrode and planarizing the upper surface of the test gate electrode;
Further including
The leak current between the test gate electrode, the test gate insulating film, and the diffusion layer from which the buried insulating film has been removed is measured in the first measuring step. The plasma damage evaluation method as described. The step of forming the damage evaluation element comprises:
Forming the test gate insulating film on the substrate;
Forming the test gate electrode on the test gate insulating film;
Forming the diffusion layer to be a source / drain in the substrate;
Forming a source electrode and a drain electrode on the diffusion layer;
The plasma damage evaluation method according to any one of claims 1 to 5, further comprising: In the step of forming the interlayer insulating film, the interlayer insulating film is formed so as to cover the periphery of the source electrode and the drain electrode,
In the step of exposing the test gate electrode, the upper surfaces of the source electrode and the drain electrode are exposed,
In the first and second measurement steps, a threshold value of a transistor between the test gate electrode and the source electrode or the drain electrode is measured,
The plasma damage evaluation method according to claim 13, wherein in the evaluation step, the threshold value measured in the first measurement step is compared with the threshold value measured in the second measurement step.   The plasma damage evaluation method according to claim 14, wherein in the step of exposing the test gate electrode, the source electrode and the drain electrode are exposed by a chemical mechanical polishing method.   The test gate electrode, the source electrode, and the drain electrode are formed so that the test gate electrode, the source electrode, and the drain electrode cover 30% or more of the surface area of the substrate in a plan view. The plasma damage evaluation method according to any one of 15 to 15.   The plasma damage evaluation method according to claim 13, further comprising a step of forming a dummy electrode adjacent to each of the test gate electrode, the source electrode, and the drain electrode.   The test gate electrode, the source electrode, the drain electrode, and the dummy so that the test gate electrode, the source electrode, the drain electrode, and the dummy electrode cover 30% or more of the surface area of the substrate in plan view. The plasma damage evaluation method according to claim 17, wherein an electrode is formed. Embedding the test gate electrode, the source electrode, and the drain electrode with a buried insulating film before the step of forming the interlayer insulating film,
The buried insulating film located above the test gate electrode, the source electrode, and the drain electrode is removed, and the upper surfaces of the test gate electrode, the source electrode, and the drain electrode are planarized, respectively. And a process of
Further including
The plasma damage evaluation method according to any one of claims 13 to 18, wherein in the first measurement step, a threshold value of a transistor between the flattened gate electrode for testing and the source electrode or the drain electrode is measured.   The plasma damage evaluation method according to claim 13, wherein the source electrode and the drain electrode are formed of the same film. Forming a damage evaluation element having a diffusion layer, a test gate insulating film, and a test gate electrode on a substrate;
Forming a semiconductor element having the diffusion layer, the product gate insulating film, and the product gate electrode on the substrate;
A first measurement step of energizing the formed test gate electrode to measure electrical characteristics of the test gate insulating film;
Forming a test interlayer insulating film covering the test gate electrode by a plasma vapor phase method;
Removing the test interlayer insulating film and exposing an upper surface of the test gate electrode;
A second measurement step of measuring the electrical characteristics of the test gate insulating film by energizing the exposed test gate electrode;
An evaluation step for comparing the measurement result obtained in the first measurement step with the measurement result obtained in the second measurement step;
When the evaluation result obtained in the evaluation step satisfies a predetermined threshold, forming a product interlayer insulating film that covers the product gate electrode under plasma conditions in which the test interlayer insulating film is formed;
A method of manufacturing a semiconductor device including:

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