JP2010140364A - Processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a processor allowing transfer of a processing circuit to a low power operation state without deteriorating detection accuracy of an ON/OFF state of a switch to reduce power consumption. <P>SOLUTION: This processor includes a timing control circuit 30 controlling timing for pulling up four switches 51-54 by a pull-up circuit 20. When a CPU (Central Processing Unit) 10 is in a sleep mode, the timing control circuit 30 generates a shorter-period connection signal than a connection signal from the CPU 10, and outputs it to the pull-up circuit 20. When the CPU 10 is in the sleep mode, a parallel/serial conversion circuit 40 detects state changes of the switches 51-54, and notifies the CPU 10 about the state changes by an interrupt. The CPU 10 having received the notification transfers from the sleep mode to a normal mode, and starts arithmetic processing corresponding to the states of the switches 51-54. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a processing apparatus that performs processing according to the on / off states of a plurality of switches, and more particularly to a processing apparatus that can reduce power consumption when there is no change in the state of the switches.

  Conventionally, electronic devices have been provided with a plurality of various switches such as push switches or dial switches for receiving user operations. A processing circuit such as a CPU (Central Processing Unit) or MPU (Micro Processing Unit) mounted on an electronic device needs to perform processing according to a user's operation. Need to be monitored.

  FIG. 11 is a block diagram showing a configuration of a conventional processing apparatus. In the figure, reference numeral 101 denotes a processing device that performs various arithmetic processes according to the on / off states of a plurality (four in FIG. 11) of switches 51 to 54. The four switches 51 to 54 are switches that are switched to two on / off states, such as push switches, for example. One end is connected to the four terminal portions 31 to 34 of the processing apparatus 101 and the other end is set to the ground potential. It is connected.

  The processing device 101 includes a CPU 110 that performs arithmetic processing, a pull-up circuit 20 that performs pull-up to a power supply potential, circuit elements such as resistors R1 to R4, resistors R11 to R14, capacitors C1 to C4, and diodes D1 to D4. It is configured with. Terminal portions 31 to 34 to which switches 51 to 54 are respectively connected are connected to the ground potential via capacitors C1 to C4, respectively, and are connected to cathodes of diodes D1 to D4, respectively. The anodes of the diodes D1 to D4 are connected to the input terminals SW1 to SW4 of the CPU 110 via resistors R11 to R14, respectively, and are connected in common to the output of the pull-up circuit 20 via the resistors R1 to R4, respectively. ing. The pull-up circuit 20 is controlled to be connected to the power supply potential by the CPU 110 and connects (pulls up) the resistors R1 to R4 to the power supply potential in accordance with a control signal from the CPU 110.

  When the pull-up circuit 20 performs pull-up by a control signal from the CPU 110 in a state where all the switches 51 to 54 are off, the input potential to the four input terminals SW1 to SW4 of the CPU 110 is the power supply potential (“H”). It becomes. On the other hand, when any one of the switches 51 to 54 is turned on, the input potentials of the input terminals SW1 to SW4 of the CPU 110 corresponding to the switches 51 to 54 become the ground potential (“L”). Therefore, the CPU 110 can detect the on / off states of the switches 51 to 54 by monitoring the potentials of the input terminals SW1 to SW4, and can perform arithmetic processing according to the states of the switches 51 to 52.

Further, in Patent Document 1, by connecting resistors that are cheaper than semiconductor components such as backflow prevention diodes to a plurality of switches in the matrix switch circuit, signals flow back in the matrix switch circuit and input to the control unit. When a signal is mistakenly input to the port, it is erroneously input and the control unit determines that the signal is below a predetermined threshold level and ignores it, and erroneously recognizes the ON state of the switch based on the erroneously input signal. There has been proposed a switch operating device capable of preventing the above.
JP 2001-176349 A

  In the conventional processing apparatus (see FIG. 11) 101, the CPU 110 performs arithmetic processing according to the state of the switches 51 to 54. When the state of the switches 51 to 54 does not change over a long period of time after the arithmetic processing ends, It is desirable to stop processing and reduce power consumption. Therefore, the CPU 110 switches between a low power operation state (hereinafter referred to as a sleep mode) in which processing can be stopped and power consumption can be reduced, and a high power operation state (hereinafter referred to as a normal mode) in which processing is performed and high power consumption. When the state of the switches 51 to 54 does not change, the normal mode is shifted to the sleep mode. When any of the switches 51 to 54 is turned on, a current flows from the pull-up circuit 20 to the ground potential via the resistors R1 to R4, the diodes D1 to D4, and the switches 51 to 54, so that the CPU 110 enters the sleep mode. After the transition, it is desirable to stop the pull-up by the pull-up circuit 20.

  However, since the state of the switches 51 to 54 cannot be detected when the pull-up by the pull-up circuit 20 is stopped, the CPU 110 needs to periodically output a control signal so that the pull-up circuit 20 performs the pull-up. . For this reason, the CPU 110 needs to perform pull-up by periodically operating the pull-up circuit 20 even in the sleep mode. However, the CPU 110 operates to control the pull-up circuit 20 periodically. Therefore, there is a problem that the average current consumption in the sleep mode of the CPU 110 increases.

  In order to improve this problem, the average current consumption can be reduced by increasing the period for detecting the state of the switches 51 to 54 in the sleep mode and reducing the operation frequency of the CPU 110. However, if the frequency of detecting the state of the switches 51 to 54 is lowered, there is a problem that the response to the switch operation performed by the user is deteriorated and the operability of the processing device is lowered.

  Further, the switch operating device described in Patent Document 1 intermittently outputs a pulsed high-active output signal from the control unit to the matrix switch circuit, and recognizes the voltage state of the input port at that time, This is a configuration for determining which switch is turned on. Therefore, in order to determine the state of the switch, the control unit needs to perform operations such as output of the pulse signal and recognition of the voltage state, which have the same problems as the conventional processing apparatus shown in FIG. .

  The present invention has been made in view of such circumstances, and an object of the present invention is to bring a processing circuit such as a CPU into a low power operation state without degrading the detection accuracy of the on / off state of the switch. It is an object of the present invention to provide a processing apparatus that can be shifted and can reduce power consumption.

  The processing device according to the present invention is a processing device that performs arithmetic processing in accordance with the on / off states of a plurality of switches, and is connected to the plurality of switches via resistors, and the plurality of switches are connected to a power supply potential or the A potential connection circuit that connects to a fixed potential having a smaller absolute value than the power supply potential; a timing control circuit that outputs a pulse signal that defines connection timing so that the connection is intermittently performed by the potential connection circuit; and the potential A conversion circuit that acquires the state of each of the switches based on the potential between the switch and the resistor when the connection circuit makes a connection, converts the information related to the acquired states into a serial signal, and outputs the serial signal Operating in a low power operation state with low power consumption or a high power operation state with high power consumption, and in this high power operation state, the conversion circuit outputs A processing circuit that performs the arithmetic processing based on an al signal, and the processing circuit includes a generation unit that generates the pulse signal in the high power operation state, and the pulse signal generated by the generation unit is generated. The timing control circuit has generation means for generating the pulse signal when the processing circuit is in the low power operation state, and the conversion circuit is provided by the processing circuit. It has a detection means for detecting a change in the state of the switch in the low power state, and a notification means for notifying the processing circuit when the detection means detects a change in the state.

  In the processing device according to the present invention, when the processing circuit is in the low power operation state, the generation unit of the processing circuit outputs a pulse signal having a longer connection cycle than the pulse signal generated in the high power operation state. The generation unit of the timing control circuit generates a pulse signal having a shorter cycle than the pulse signal in accordance with the pulse signal generated by the generation unit of the processing circuit. And

  In the processing device according to the present invention, when the processing circuit is in the low power operation state, the generation unit of the timing control circuit generates the pulse signal according to the pulse width of the pulse signal generated by the generation unit of the processing circuit. It is characterized in that the period of the pulse signal to be determined is determined.

  The processing apparatus according to the present invention is characterized in that when the processing circuit is in the low power operation state, the generation means of the processing circuit does not generate the pulse signal.

  In the processing device according to the present invention, the processing circuit and the conversion circuit can perform serial communication in both directions, and the processing circuit converts the setting information related to the cycle of the pulse signal by serial communication. When the processing circuit is in the low power operation state, the conversion circuit supplies setting information from the processing circuit to the timing control circuit, and the generation means of the timing control circuit The period of the pulse signal to be generated is determined according to setting information from the conversion circuit.

  Further, the processing device according to the present invention causes the processing circuit to transition from the low power operation state to the high power operation state when notified of a change in the state of the switch from the notification means of the conversion circuit. It is characterized by being.

In the present invention, a pulse signal that defines the timing of connection to a potential connection circuit (so-called pull-up circuit or pull-down circuit) that connects a plurality of switches to a power supply potential or a fixed potential (ground potential) through a resistor is provided. A timing control circuit for output is provided separately from a processing circuit such as a CPU. In addition, a conversion circuit is provided separately from the processing device that acquires potentials indicating the on / off states of the plurality of switches, converts this information into serial signals, and outputs the serial signals to the processing circuit. The processing circuit operates in a low power operation state or a high power operation state, and performs arithmetic processing according to the on / off state of the switch in the high power operation state.
In this configuration, when the processing circuit is operating in a high power operation state, the processing circuit determines a connection timing by the potential connection circuit, and a pulse signal is used as a control signal for causing the potential connection circuit to perform connection intermittently. The generated pulse signal is supplied to the timing control circuit. The timing control circuit outputs the pulse signal generated by the processing circuit to the potential connection circuit. Thereby, when performing arithmetic processing, the processing circuit can control the operation of the potential connection circuit. The conversion circuit acquires the switch state at this timing, converts it into a serial signal, and outputs it to the processing circuit.
When the processing circuit is operating in the low power operation state, the timing control circuit determines the connection timing by the potential connection circuit, generates a pulse signal, and outputs the pulse signal to the potential connection circuit. Therefore, the frequency with which the processing circuit operates in the low power operation state can be reduced. In this case, the conversion circuit detects the switch state and notifies the processing circuit of the change of the switch state using an interrupt or the like. Thereby, the processing circuit can return from the low power operation state to the high power operation state, and perform arithmetic processing according to the switch state.

In the present invention, when operating in the low power operation state, the processing circuit generates a pulse signal having a cycle longer than the connection cycle of the pulse signal generated in the high power operation state and outputs the pulse signal to the timing control circuit. To do. As a result, the processing circuit can reduce the operation frequency in the low power operation state, reduce the average current consumption, output a pulse signal to the potential connection circuit, and adjust the connection timing by the potential connection circuit. Can be controlled.
However, when the potential connection circuit is operated in accordance with the pulse signal output from the processing circuit in the low power operation state, the frequency of the switch state detection is lower than that in the high power operation state. Therefore, the timing control circuit generates a pulse signal having a shorter cycle based on the pulse signal from the processing circuit, and supplies the pulse signal to the potential connection circuit. Thereby, it is possible to avoid a decrease in the frequency of detecting the state of the switch.

  In the present invention, when the timing control circuit is configured to generate a pulse signal having a short cycle based on the pulse signal from the processing circuit as described above, the timing control circuit is configured to generate a pulse signal pulse from the processing circuit. The period of the pulse signal to be generated is determined according to the width. The processing circuit can indirectly control the connection operation by the potential connection circuit by increasing or decreasing the pulse width, and can indirectly control the cycle of detecting the switch state.

  In the present invention, the processing circuit does not generate a pulse signal when operating in a low power operation state. In this case, the timing control circuit determines a connection cycle by the potential connection circuit by itself and generates a pulse signal. Thereby, since the processing circuit does not need to generate a pulse signal, it is not necessary to operate in a low power operation state, and the average current consumption can be reduced.

  In the present invention, when the processing circuit is configured not to generate a pulse signal in the low power operation state, the processing circuit transmits period setting information to the conversion circuit by serial communication, and the conversion circuit Information is provided to the timing control circuit. As a result, the timing control circuit can generate a pulse signal having a period set by the processing circuit, and the processing circuit transmits the setting by serial communication in the high power operation state, so that The connection of the potential connection circuit can be indirectly controlled, and the switch state detection cycle can be indirectly controlled.

  In the present invention, when the switch circuit is notified of the switch state change, the processing circuit shifts from the low power operation state to the high power operation state and starts arithmetic processing. Accordingly, the processing circuit can perform arithmetic processing according to the state of the switch changed by the notification from the conversion circuit even when the state of the switch is changed during the low power operation state.

  In the case of the present invention, when the processing circuit is operating in the low power operation state, the timing control circuit determines the connection timing by the potential connection circuit, generates a pulse signal, outputs it to the potential connection circuit, and converts it. By adopting a configuration in which the circuit detects the switch state and notifies the processing circuit of the change of the switch state using an interrupt or the like, it is possible to reduce the operation that the processing circuit conventionally performed in the low power operation state. Therefore, the average current consumption of the processing circuit can be reduced, and the processing circuit can respond to the switch state by notifying the processing circuit from the conversion circuit without reducing the frequency of the switch state detection in the low power operation state. Arithmetic processing can be performed.

(Embodiment 1)
Hereinafter, the present invention will be specifically described with reference to the drawings showing embodiments thereof. FIG. 1 is a block diagram showing a configuration of a processing apparatus according to Embodiment 1 of the present invention. In the figure, reference numeral 1 denotes a processing device that performs various arithmetic processes in accordance with the on / off states of the four switches 51 to 54. The processing device 1 can be used as an ECU (Electronic Control Unit) that controls an in-vehicle device such as a lamp, a wiper, or a power window mounted on the vehicle. In this case, the processing device 1 is provided near the driver's seat in the vehicle. Arithmetic processing can be performed in accordance with user operations on the plurality of switches, and on-vehicle equipment can be controlled based on the processing results.

  The switches 51 to 54 are switches that are switched between two on / off states, such as push switches, and are energized in the on state and shut off in the off state. One end of each of the four switches 51 to 54 is connected to the four terminal portions 31 to 34 of the processing apparatus 1, and the other end is connected to the ground potential. When the switches 51 to 54 are on, the terminal portion 31 is connected. ˜34 are connected to ground potential. For example, when the processing apparatus 1 is used as an ECU of a vehicle, the switches 51 to 54 are a lamp on / off switch, a switch for operating a wiper, a power window opening / closing switch, or the like.

  The processing apparatus 1 includes a CPU (Central Processing Unit) 10 that performs various arithmetic processing, a pull-up circuit 20 that connects (pull-up) each switch 51 to 54 to a power supply potential, and the pull-up circuit 20 performs pull-up. The timing control circuit 30 that outputs a connection signal (pulse signal) that defines the timing to be performed, and the on / off states of the switches 51 to 54 are acquired, and the acquired information on the plurality of switch states is converted into serial signals to the CPU 10. And a parallel / serial conversion circuit 40 that outputs to and a circuit element such as resistors R1 to R4, resistors R11 to R14, capacitors C1 to C4, and diodes D1 to D4.

  The terminal portions 31 to 34 of the processing apparatus 1 to which the switches 51 to 54 are respectively connected are connected to the ground potential via the capacitors C1 to C4, respectively, and are connected to the cathodes of the diodes D1 to D4, respectively. The anodes of the diodes D1 to D4 are connected to the parallel input terminals SW1 to SW4 of the parallel / serial conversion circuit 40 via the resistors R11 to R14, respectively, and are pulled up via the pullup resistors R1 to R4. Connected to the circuit 20.

  Capacitors C1 to C4 are for removing a high-frequency voltage change (noise) by dulling a steep change in voltage caused by turning on and off the switches 51 to 54. The diodes D1 to D4 are used for preventing backflow, that is, preventing current from flowing into the inside from the terminal portions 31 to 34 of the processing apparatus 1. The resistors R11 to R14 are for protecting the input terminals SW1 to SW4 of the parallel / serial conversion circuit 40.

  The pull-up circuit 20 can be configured using, for example, a MOS (Metal Oxide Semiconductor) transistor, the source of the MOS transistor is connected to the power supply potential, the drain is connected to the resistors R1 to R4, and the voltage applied to the gate is determined. By changing according to the connection signal from the timing control circuit 30 and switching the MOS transistor on / off, the power supply potential and the resistors R1 to R4 can be connected / cut off. The pull-up circuit 20 is a circuit that pulls up the switches 51 to 54 connected to the terminal units 31 to 34 of the processing apparatus 1 periodically (intermittently) according to a connection signal from the timing control circuit 30. .

  The timing control circuit 30 is supplied with a pulse signal as a connection signal from the CPU 10 that defines the timing at which the pull-up circuit 20 performs the pull-up, and generates a new connection signal based on the given connection signal. By outputting to the circuit 20, the operation of the pull-up circuit 20 is controlled. Although the details will be described later, the timing control circuit 30 outputs the connection signal supplied from the CPU 10 to the pull-up circuit 20 as it is when the CPU 10 is operating in the normal mode. When the CPU 10 is operating in the sleep mode, the timing control circuit 30 performs pull-up at a cycle shorter than the cycle of the connection signal given from the CPU 10 in order to increase the frequency of pull-up by the pull-up circuit 20. A connection signal is generated and output.

  The parallel / serial conversion circuit 40 has four input terminals SW1 to SW4, that is, a circuit having parallel input terminals SW1 to SW4, and whether or not the input potential to each of the input terminals SW1 to SW4 exceeds a threshold value. That is, by determining whether the input potential is “H” or “L”, the on / off states of the switches 51 to 54 are acquired as digital data “0” or “1” parallel data. The parallel / serial conversion circuit 40 has a function of performing bi-directional serial communication with the CPU 10, converts the acquired parallel data regarding the states of the switches 51 to 54 into serial data, and uses the converted data as a serial signal. It transmits to CPU10. Note that the acquisition of the states of the switches 51 to 54 by the parallel / serial conversion circuit 40 is performed during a period in which the switches 51 to 54 are pulled up to the power supply potential by the pull-up circuit 20.

  Although details will be described later, the parallel / serial conversion circuit 40 has a function of detecting a change in the input potential to the input terminals SW1 to SW4, that is, a change in the state of the switches 51 to 54 when the CPU 10 is in the sleep mode. is doing. When the state change of the switches 51 to 54 is detected, the parallel / serial conversion circuit 40 can notify the state change by outputting a signal for interrupting the CPU 10.

  The CPU 10 periodically outputs a connection signal for causing the timing control circuit 30 to perform the pull-up of the pull-up circuit 20, a function of performing serial communication with the parallel / serial conversion circuit 40, and serial communication. It has a function of performing various arithmetic processes according to the on / off states of the switches 51 to 54 included in the received data.

  For example, when the on / off state of the switches 51 to 54 is changed by a user operation, the CPU 10 starts arithmetic processing for performing a predetermined operation of the device in accordance with the changed switches 51 to 54. At this time, the power consumption of the CPU 10 increases because an internal arithmetic circuit and the like operate. Thereafter, when the arithmetic processing corresponding to the switch state change is completed, the CPU 10 does not need to perform the arithmetic processing until the next state change of the switches 51 to 54 occurs. Operates in sleep mode to reduce power consumption. That is, the CPU 10 performs arithmetic processing according to the state of the switches 51 to 54, and the normal mode (high power operation state) with a large amount of power consumption and the sleep mode (low power consumption) without performing the arithmetic processing. The operation is performed while switching between the power operation states.

  FIG. 2 is a timing chart for explaining the operation of the processing apparatus 1 according to the first embodiment of the present invention. The change in the potential input to one of the input terminals SW1 to SW4 and the CPU 10 is a timing control circuit. 30 illustrates an example of a connection signal output to 30, a connection signal output from the timing control circuit 30 to the pull-up circuit 20, an interrupt signal output from the parallel / serial conversion circuit 40 to the CPU 10, and an operation mode of the CPU 10. is there.

  In the sleep mode, the CPU 10 outputs a pulse signal having an “H” level pulse with a cycle of 100 ms to the timing control circuit 30 as a connection signal. When the CPU 10 is in the sleep mode, the timing control circuit 30 generates a connection signal having an “H” level pulse having a period (about 50 ms) that is approximately half of the connection signal supplied from the CPU 10 and outputs the connection signal to the pull-up circuit 20. To do. The pull-up circuit 20 connects (pulls up) the switches 51 to 54 to the power supply potential when the connection signal supplied from the timing control circuit 30 is at “H” level regardless of the operation mode of the CPU 10.

  The parallel / serial conversion circuit 40 acquires the on / off states of the switches 51 to 54 corresponding to the input potentials of the input terminals SW1 to SW4 during the period when the pullup circuit 20 performs the pullup. The state change of the switches 51 to 54 is detected by determining whether or not the changed state has changed with respect to the previous acquisition state. For example, as shown in FIG. 2, when the input voltage of the input terminals SW1 to SW4 changes from “H” level to “L” level, the timing at which the pull-up circuit 20 performs pull-up (that is, the timing control circuit 30 outputs). The parallel / serial conversion circuit 40 detects a change in the state of the switches 51 to 54 at the timing when the connection signal is “H” level.

  The parallel / serial conversion circuit 40 that has detected a change in the state of the switches 51 to 54 outputs a pulse signal of “H” level for a predetermined period to the CPU 10 as an interrupt signal. The CPU 10 shifts from the sleep mode to the normal mode by an interrupt signal from the parallel / serial conversion circuit 40, acquires the state of each of the switches 51 to 54 by serial communication with the parallel / serial conversion circuit 40, and responds to the change in state. Perform the operation processing.

  In the normal mode, the CPU 10 performs arithmetic processing according to the states of the switches 51 to 54 and supplies a pulse signal having an “H” level pulse with a cycle of 50 ms to the timing control circuit 30 as a connection signal. The timing control circuit 30 outputs the connection signal given from the CPU 10 to the pull-up circuit 20 as it is, and the pull-up circuit 20 performs pull-up according to the given connection signal.

  The parallel / serial conversion circuit 40 acquires the ON / OFF states of the switches 51 to 54 corresponding to the input potentials of the input terminals SW1 to SW4 during the period in which the pullup circuit 20 performs the pullup, and acquires The status information of each of the switches 51 to 54 is converted into a serial signal and transmitted to the CPU 10 by serial communication. The CPU 10 performs arithmetic processing according to the state of each of the switches 51 to 54 received from the parallel / serial conversion circuit 40 by serial communication. Thereafter, the CPU 10 shifts from the normal mode to the sleep mode when all the arithmetic processes to be performed in accordance with the states of the switches 51 to 54 are completed.

  FIG. 3 is a flowchart showing a procedure of processing performed by the CPU 10 of the processing apparatus 1 according to Embodiment 1 of the present invention. After the processing device 1 is activated, the CPU 10 first operates in the sleep mode (step S1), and determines whether or not an interrupt from the parallel / serial conversion circuit 40 is given (step S2). When no interrupt is given (S2: NO), the CPU 10 further determines whether or not a predetermined time (100 ms) has elapsed (step S3). When the predetermined time has elapsed (S3: YES), the CPU 10 outputs a pulse signal of “H” level to the timing control circuit 30 as a connection signal (step S4), and returns to step S1. When the predetermined time has not elapsed (S3: NO), the CPU 10 waits until the predetermined time elapses.

  When an interrupt is given from the parallel / serial conversion circuit 40 (S2: YES), the CPU 10 shifts from the sleep mode to the normal mode (step S5) and switches 51 to 54 through serial communication with the parallel / serial conversion circuit 40. Is obtained (step S6), and arithmetic processing according to the states of the switches 51 to 54 is performed (step S7). Next, the CPU 10 ends all the arithmetic processes to be performed in accordance with the states of the switches 51 to 54, and determines whether or not it is possible to transition to the sleep mode (step S8). If all the arithmetic processes have not been completed and the transition to the sleep mode is not possible (S8: NO), it is further checked whether or not a predetermined time (50 ms) has passed (step S9). ).

  If the predetermined time has not elapsed (S9: NO), the CPU 10 returns to step S7 and continues the calculation process. When the predetermined time has elapsed (S9: YES), the CPU 10 outputs a pulse signal of “H” level to the timing control circuit 30 as a connection signal (step S10), and returns to step S6. Further, when all the arithmetic processes according to the states of the switches 51 to 54 are completed and the transition to the sleep mode is possible (S8: YES), the CPU 10 shifts from the normal mode to the sleep mode (step S11), the process is terminated. It is assumed that the CPU 10 starts the process of step S1 after the process is completed, that is, repeatedly performs the process of the flowchart shown in FIG.

  FIG. 4 is a flowchart showing a procedure of processing performed by the timing control circuit 30 of the processing apparatus 1 according to Embodiment 1 of the present invention. The timing control circuit 30 first determines whether or not the operation of the CPU 10 is in the sleep mode (step S21). Whether or not the CPU 10 performed by the timing control circuit 30 is in the sleep mode may be determined based on, for example, a change in a connection signal supplied from the CPU 10, and a change in the operation mode from the CPU 10 directly or directly to the timing control circuit 30. It may be configured to be notified indirectly.

  When the CPU 10 is in the sleep mode (S21: YES), the timing control circuit 30 generates a connection signal having a half cycle (50 ms) with respect to the cycle (100 ms) of the connection signal supplied from the CPU 10 (step S22). When the CPU 10 is not in the sleep mode (S21: NO) and is in the normal mode, the timing control circuit 30 sets the connection signal supplied from the CPU 10 as a connection signal to the pull-up circuit 20 (step S23). The timing control circuit 30 outputs the connection signal generated in step S22 or the connection signal obtained in step S23 to the pull-up circuit 20 (step S24), and ends the process. Note that the timing control circuit 30 repeatedly performs the processing of the flowchart shown in FIG.

  FIG. 5 is a flowchart showing a procedure of processing performed by the parallel / serial conversion circuit 40 of the processing device 1 according to the first embodiment of the present invention. The parallel / serial conversion circuit 40 first determines whether or not the pull-up circuit 20 has pulled up (step S31). Whether or not the pull-up circuit 20 has pulled up may be determined, for example, by the parallel / serial conversion circuit 40 acquiring a connection signal output from the timing control circuit 30, and input from the input terminals SW1 to SW4. You may judge based on an electric potential. When pull-up by the pull-up circuit 20 is not performed (S31: NO), the parallel / serial conversion circuit 40 waits until pull-up is performed.

  When pull-up is performed by the pull-up circuit 20 (S31: YES), the parallel / serial conversion circuit 40 further determines whether or not the operation mode of the CPU 10 is the sleep mode (step S32). When the CPU 10 is in the sleep mode (S32: YES), the parallel / serial conversion circuit 40 acquires the input potentials of the input terminals SW1 to SW4 (step S33), and compares the input potential with, for example, the previously acquired input potential. , That is, whether or not there is a change in the state of the switches 51 to 54 is determined (step S34).

  When there is a change in the state of the switches 51 to 54 (S34: YES), the parallel / serial conversion circuit 40 issues an interrupt to the CPU 10 to notify the change of state (step S35) and ends the process. If there is no change in the state of the switches 51 to 54 (S34: NO), the parallel / serial conversion circuit 40 ends the process.

  When the CPU 10 is not in the sleep mode (S32: NO) and is in the normal mode, the parallel / serial conversion circuit 40 acquires the input potentials of the input terminals SW1 to SW4 (step S36), and based on the acquired input potentials. Parallel / serial conversion is performed to convert the parallel information indicating the determined state of each of the switches 51 to 54 into a serial signal (step S37), the serial signal is transmitted to the CPU 10 (step S38), and the process ends. The parallel / serial conversion circuit 40 repeatedly performs the processing of the flowchart shown in FIG. 5 as in the case of the CPU 10 and the timing control circuit 30.

  The processing apparatus 1 according to the first embodiment having the above configuration includes the timing control circuit 30 that controls the timing at which the pull-up circuit 20 pulls up the four switches 51 to 54, and when the CPU 10 is in the sleep mode, The timing control circuit 30 generates a connection signal for performing pull-up at a cycle shorter than the cycle of the connection signal provided from the CPU 10 and outputs the connection signal to the pull-up circuit 20, so that the CPU 10 receives the connection signal in the sleep mode. The frequency of operations for generation and output can be reduced as compared to the normal mode. Therefore, current consumption accompanying the operation of the CPU 10 in the sleep mode can be reduced.

  When the CPU 10 is in the sleep mode, the parallel / serial conversion circuit 40 detects the state change of the switches 51 to 54 and notifies the CPU 10 of the state change by an interrupt. Even if the operation frequency of the CPU 10 in the sleep mode is reduced by shifting to the mode and starting the arithmetic processing, the processing device without reducing the frequency of state detection of the switches 51 to 54 1 can perform arithmetic processing according to the state of the switches 51 to 54.

  Even when the number of switches mounted is increased or decreased by adopting a configuration in which the parallel / serial conversion circuit 40 converts a plurality of inputs from the plurality of switches 51 to 54 into serial signals and transmits them to the CPU 10, It is not necessary to change the hardware configuration of the CPU 10, and the configuration of the parallel / serial conversion circuit 40 may be changed. Therefore, the CPU 10 having a large circuit scale can modify the number of switches capable of detecting the state by modifying the software and changing the configuration of the parallel / serial conversion circuit 40 having a small circuit scale. Can be increased.

  In the present embodiment, the timing control circuit 30 generates a connection signal having a half cycle of the connection signal output from the CPU 10 and outputs the connection signal to the pull-up circuit 20. However, the present invention is not limited to this. The timing control circuit 30 may generate and output a connection signal having another period such as 1/3 or 1/4 of the connection signal of the CPU 10. For example, in FIG. 2, the CPU 10 may output a connection signal having a cycle of 200 ms in the sleep mode, and the timing control circuit 30 may generate a connection signal having a cycle of 50 ms.

  Moreover, although the processing apparatus 1 was set as the structure which detects the state of the four switches 51-54, it is not restricted to this, It is good also as a structure which detects the state of three or less or five or more switches. The processing apparatus 1 includes the pull-up circuit 20 that pulls up the switches 51 to 54 to the power supply potential. However, the present invention is not limited to this, and the switches 51 to 54 are connected to the ground potential (or a fixed potential lower than the power supply potential). ) May be provided with a pull-down circuit that pulls down. The pull-up circuit 20 is configured to perform pull-up using a MOS transistor, but is not limited thereto, and may be configured to perform pull-up using another switching element such as a bipolar transistor or a relay.

(Modification)
In the processing device 1 according to the first embodiment described above, a configuration in which a connection signal having a predetermined cycle (half cycle) with respect to the cycle of the connection signal of the CPU 10 is generated when the timing control circuit 30 is in the sleep mode. However, it is not limited to this. The CPU 10 can control the cycle of the connection signal generated by the timing control circuit 30 in the sleep mode.

  FIG. 6 is a schematic diagram for explaining a method of controlling the period of the connection signal of the timing control circuit 30 performed by the CPU 10 of the processing apparatus 1 according to the modification of the first embodiment of the present invention. The correspondence between the “H” level pulse width of the signal and the period of the connection signal output from the timing control circuit 30 is shown in the table. The CPU 10 of the processing device 1 according to the modification can change the pulse width of the “H” level of the connection signal output in the sleep mode to, for example, 10 ms, 8 ms, or 6 ms. In addition, the timing control circuit 30 changes the cycle of the connection signal output to the pull-up circuit 20 to, for example, 50 ms, 40 ms, or 30 ms in accordance with the “H” level pulse width of the connection signal given from the CPU 10. Can do.

  Thus, in the processing device 1 according to the modification, the CPU 10 can control the frequency of state detection of the switches 51 to 54 in the sleep mode by changing the pulse width of the connection signal output to the timing control circuit 30.

(Embodiment 2)
FIG. 7 is a block diagram showing a configuration of the processing apparatus 201 according to Embodiment 2 of the present invention. FIG. 8 is a timing chart for explaining the operation of the processing apparatus 201 according to the second embodiment of the present invention. The processing device 1 according to the first embodiment is configured such that the CPU 10 generates a connection signal and outputs it to the timing control circuit 30 even in the sleep mode. On the other hand, the processing device 201 according to the second embodiment has a configuration in which the CPU 210 does not generate a connection signal at all in the sleep mode.

  In the normal mode, the CPU 210 outputs a connection signal having a period of about 50 ms to the timing control circuit 230. The timing control circuit 230 outputs the connection signal given from the CPU 210 to the pull-up circuit 20 as it is. The parallel / serial conversion circuit 240 acquires the state of the switches 51 to 54 during the period when the pull-up circuit 20 is performing pull-up, converts the state into a serial signal, and transmits the serial signal to the CPU 210 by serial communication.

  On the other hand, in the sleep mode, the CPU 210 does not generate a connection signal (outputs a connection signal that does not change at a constant “L” level). The timing control circuit 230 itself generates a connection signal having a period of about 50 ms and outputs it to the pull-up circuit 20 regardless of the connection signal from the CPU 210. The parallel / serial conversion circuit 240 detects a change in the state of the switches 51 to 54 during the period during which the pull-up circuit 20 performs the pull-up, and if the state of the switches 51 to 54 has changed, this is interrupted to the CPU 210. Notify that.

  In addition, the CPU 210 and the parallel / serial conversion circuit 240 can perform bidirectional serial communication. The CPU 210 sets the cycle setting that defines the cycle of the connection signal generated by the timing control circuit 230 in the sleep mode by serial communication. It can be transmitted to the conversion circuit 240. The parallel / serial conversion circuit 240 gives the cycle setting given from the CPU 210 to the timing control circuit 230, and the timing control circuit 230 generates and outputs a connection signal corresponding to the given cycle setting. As a result, the CPU 210 can indirectly control the frequency of state detection of the switches 51 to 54 in the sleep mode by giving a period setting to the parallel / serial conversion circuit 240 in advance in the normal mode.

  In the processing apparatus 201 according to the second embodiment having the above configuration, when the CPU 210 is in the sleep mode, the timing control circuit 230 generates a connection signal and outputs the connection signal to the pull-up circuit 20. Does not need to operate in the sleep mode to generate the connection signal, and the operation of the CPU 210 can be completely stopped in the sleep mode, so that the current consumption of the CPU 210 in the sleep mode can be reduced.

  In this embodiment, the CPU 210 transmits a cycle setting to the parallel / serial conversion circuit 240 by serial communication, and the parallel / serial conversion circuit 240 gives the cycle setting to the timing control circuit 230, and the given cycle setting is set. The connection signal is generated and output by the timing control circuit 230. However, the present invention is not limited to this, and the CPU 210 may directly apply the cycle setting to the timing control circuit 230. Alternatively, the CPU 210 may generate the connection signal having a predetermined period and output it instead of providing the period setting to the parallel / serial conversion circuit 230.

  In addition, since the other structure of the processing apparatus 201 which concerns on Embodiment 2 is the same as that of the processing apparatus 1 which concerns on Embodiment 1, the same code | symbol is attached | subjected to the same location and detailed description is abbreviate | omitted. To do.

(Modification)
9 and 10 are block diagrams showing a configuration of a processing apparatus 201a according to a modification of the second embodiment of the present invention. The processing apparatus 201a according to the modification includes an ASIC (Application Specific Integrated) in which the pull-up circuit 20, the timing control circuit 230, and the parallel / serial conversion circuit 240 of the processing apparatus 201 according to the second embodiment illustrated in FIG. Circuit) 270. The configuration and operation of each circuit of the processing device 201a are the same as those of the processing device 201 shown in FIG.

  The ASIC 270 is connected to a terminal 271 for pull-up by the pull-up circuit 20 to which the pull-up resistors R1 to R4 are connected, and to the switches 51 to 54 via resistors R11 to R14 and diodes D1 to D4. , Terminals 272 to 275 for applying input potentials to the input terminals SW1 to SW4 of the parallel / serial conversion circuit 240, a terminal 276 to which a connection signal from the CPU 210 to the timing control circuit 230 is input, and the CPU 210 and parallel / serial conversion. The circuit 240 includes a terminal 277 for performing bidirectional serial communication, and a terminal 278 for outputting an interrupt signal from the parallel / serial conversion circuit 240 to the CPU 210.

  In this configuration, the cycle setting is transmitted from the CPU 210 to the parallel / serial conversion circuit 240 of the ASIC 270 by serial communication, and the parallel / serial conversion circuit 240 gives the cycle setting to the timing control circuit 230, whereby the switches 51 to 51 in the sleep mode are set. The CPU 210 can indirectly control the period of state detection 54.

  On the other hand, when the CPU 210 and the timing control circuit 230 are configured to directly set the cycle setting from the CPU 210 to the timing control circuit 230, the cycle setting is input to the timing control circuit 230 in the ASIC 270 in order to transmit and receive data. It is necessary to further provide a terminal for this purpose, and it is necessary to connect this terminal and the CPU 210 with a signal line. However, by adopting a configuration in which the cycle setting is given from the CPU 210 to the timing control circuit 230 via the parallel / serial conversion circuit 240 as described above, the number of terminals of the ASIC 270 can be reduced, and the wiring between the CPU 210 and the ASIC 270 can be reduced. The effect that the number can be reduced is obtained.

  Similarly, in the processing apparatus 1 according to the first embodiment, the pull-up circuit 20, the timing control circuit 30, and the parallel / serial conversion circuit 40 can be made into an ASIC.

It is a block diagram which shows the structure of the processing apparatus which concerns on Embodiment 1 of this invention. It is a timing chart for demonstrating operation | movement of the processing apparatus which concerns on Embodiment 1 of this invention. It is a flowchart which shows the procedure of the process which CPU of the processing apparatus which concerns on Embodiment 1 of this invention performs. It is a flowchart which shows the procedure of the process which the timing control circuit of the processing apparatus which concerns on Embodiment 1 of this invention performs. It is a flowchart which shows the procedure of the process which the parallel / serial conversion circuit of the processing apparatus which concerns on Embodiment 1 of this invention performs. It is a schematic diagram for demonstrating the control method of the period of the connection signal of the timing control circuit which CPU of the processing apparatus which concerns on the modification of Embodiment 1 of this invention performs. It is a block diagram which shows the structure of the processing apparatus which concerns on Embodiment 2 of this invention. It is a timing chart for demonstrating operation | movement of the processing apparatus which concerns on Embodiment 2 of this invention. It is a block diagram which shows the structure of the processing apparatus which concerns on the modification of Embodiment 2 of this invention. It is a block diagram which shows the structure of the processing apparatus which concerns on the modification of Embodiment 2 of this invention. It is a block diagram which shows the structure of the conventional processing apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Processing apparatus 10 CPU (processing circuit, production | generation means)
20 Pull-up circuit (potential connection circuit)
30 Timing control circuit (generation means)
31-34 terminal 40 parallel / serial conversion circuit (conversion circuit, detection means, notification means)
51-54 Switch C1-C4 Capacitor D1-D4 Diode R1-R4, R11-R14 Resistor 201, 201a Processing device 210 CPU (Processing circuit, generation means)
230 Timing control circuit (generation means)
240 Parallel / serial conversion circuit (conversion circuit, detection means, notification means)
270 ASIC
271 to 278 terminals

Claims (6)

In a processing device that performs arithmetic processing according to the on / off states of a plurality of switches
A potential connection circuit connected to each of the plurality of switches via a resistor, and connecting the plurality of switches to a power supply potential or a fixed potential having an absolute value smaller than the power supply potential;
A timing control circuit that outputs a pulse signal that defines the connection timing so that the potential connection circuit performs connection intermittently;
When the potential connection circuit makes a connection, it acquires the state of the switch based on the potential between the switch and the resistor, converts the acquired information about the plurality of states into a serial signal, and outputs it A conversion circuit;
A processing circuit that operates in a low-power operation state with low power consumption or a high-power operation state with high power consumption, and performs the arithmetic processing based on a serial signal output from the conversion circuit in the high-power operation state. Prepared,
The processing circuit has generation means for generating the pulse signal in the high power operation state, and the pulse signal generated by the generation means is provided to the timing control circuit,
The timing control circuit has a generating means for generating the pulse signal when the processing circuit is in the low power operation state,
The conversion circuit includes:
Detecting means for detecting a change in the state of the switch when the processing circuit is in the low power state;
And a notifying means for notifying the processing circuit when the detecting means detects a change in state. When the processing circuit is in the low power operating state,
The processing circuit generating means generates a pulse signal having a longer connection cycle than a pulse signal generated in the high power operation state,
The generation unit of the timing control circuit is configured to generate a pulse signal having a shorter cycle than the pulse signal according to the pulse signal generated by the generation unit of the processing circuit. Processing equipment. When the processing circuit is in the low power operating state,
The generation unit of the timing control circuit determines the period of the pulse signal to be generated according to the pulse width of the pulse signal generated by the generation unit of the processing circuit. Processing equipment. When the processing circuit is in the low power operating state,
The processing apparatus according to claim 1, wherein the generation unit of the processing circuit does not generate the pulse signal. The processing circuit and the conversion circuit can perform serial communication in both directions,
The processing circuit is configured to provide setting information related to the period of the pulse signal to the conversion circuit by serial communication,
When the processing circuit is in the low power operating state,
The conversion circuit provides setting information from the processing circuit to the timing control circuit,
The processing apparatus according to claim 4, wherein the generation unit of the timing control circuit determines a period of a pulse signal to be generated in accordance with setting information from the conversion circuit. 2. The processing circuit is configured to shift from the low power operation state to the high power operation state when notified of a change in the state of the switch from a notification unit of the conversion circuit. The processing apparatus according to any one of claims 5 to 5.

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