JP2010140261A - Information processor, error correction method and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To correct errors equal to or more than the number of bits correctable by an ECC (error correcting code). <P>SOLUTION: In the error correction method, when reading data from a storage area, a bit error is detected using the error correcting code, and bit error information including information about a correct value and the location of the bit error detected in a bit error detection step is written into a predetermined alternative area. When retrieving the alternative area and deciding that the bit error information exists (step S102/Yes) when reading the data from the storage area (step S101), the data are corrected based on the bit error information (step S104). <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an information processing apparatus, an error correction method, and a program, and more particularly, to a bit error detection and correction technique using an error correction code (ECC).

As a technique related to the present invention, there is one described in Patent Document 1. However, as is clear from the description in paragraph 0008 and the like, Patent Document 1 is a page whose processing target is “for missing bits that cannot be handled by error correction”, that is, a page included in a defective block. On the other hand, an object of the present invention is “a normal area that is not an error-correctable defect”, and the present invention and Patent Document 1 are completely different in this respect.
JP 2005-196658 A

  In the technical field of flash memory in which data can be electrically written and erased, there is a method of performing error correction using an error correcting code (hereinafter referred to as ECC (error correcting code)). Such a general error correction method (related technology of the present invention) will be described with reference to FIG.

  In FIG. 11, an arithmetic unit such as a CPU reads data into a memory having an ECC function (step S1101), performs ECC calculation (step S1102), and determines whether or not an error can be corrected (step S1103). . If the error can be corrected, the read data is error-corrected (step S1105). If the error cannot be corrected, an abnormal process is executed (step S1104).

  However, the error correction as described above has the following problems.

  The first problem is that if the number of bits for error correction is increased, the calculation becomes heavy, and therefore the number of bits cannot be easily increased in consideration of performance.

  The second problem is that because bit corruption within a specified number is a specification, if a number of bit corruption occurs when replacement processing is performed for each page or block, the efficiency becomes worse. .

  In view of the above circumstances, an object of the present invention is to provide an information processing apparatus, an error correction method, and a program that perform error correction of more bits than can be corrected by ECC.

  In order to achieve the above object, an information processing apparatus, an error correction method, and a program having the following configurations are provided.

  Bit error detection means for detecting a bit error using an error correction code when data is read from a storage area, and bit error information including the location of the bit error detected by the bit error detection means and correct value information. Based on the bit error information when the bit error information writing means for writing to a predetermined alternative area and the next time the data is read from the storage area and the alternative area is searched and the bit error information is determined to be present An information processing apparatus comprising: data correction means for correcting data.

  Bit error detection step for detecting a bit error using an error correction code when data is read from a storage area, and bit error information including information on the location and correct value of the bit error detected by the bit error detection step A bit error information writing step for writing to a predetermined alternative area, and when the data is read from the storage area next time, when the alternative area is searched to determine that the bit error information exists, the bit error information is And a data correction step for correcting the data based on the error correction method.

  A bit error detection means for detecting a bit error using an error correction code when data is read from the storage area, and information on the location and correct value of the bit error detected by the bit error detection means. A bit error information writing means for writing bit error information to a predetermined alternative area; and when the data is read from the storage area next time, the alternative area is searched to determine that the bit error information is present An error correction program which functions as data correction means for correcting data based on bit error information.

  According to the present invention, it is possible to provide an information processing apparatus, an error correction method, and a program that perform error correction more than the number of bits that can be corrected by ECC.

Hereinafter, embodiments of the present invention will be described in detail.
Conventionally, as in a NAND flash memory, a bit error caused by repeated reading (read disturb error) or a bit error caused by data change (data retention) due to loss of electrons from the FG There was a problem with the reliability of the data. These are not defects, but data retention characteristics of the flash memory, and can be used again as a normal area after erasure. Usually, error correction by ECC is used to correct garbled bits to improve reliability.

  However, the possibility of the above-described bit error exceeding the error correction capability of ECC was not zero. For example, when an ECC capable of correcting 1-bit error and capable of detecting 2-bit error is used, a change up to 1 bit can be corrected, but if another 1-bit error occurs, data is lost. . Important data needed to be processed in advance, such as saving to another area within a 1-bit error. On the other hand, it is possible to install ECC with error correction capability of 2 bits or more, but there are problems such as an increase in calculation amount for error correction and an increase in redundant area, which affects performance and price. Can be considered.

  Therefore, paying attention to the fact that the probability of two or more bit errors occurring at the same time is extremely low, if a bit error has occurred within the range that can be corrected by ECC, the bit error occurrence location and the corrected data are pre- Record in advance in a redundant area or another area. After the data is read from the flash memory, if there is correction information for the address, the information is read and the data is corrected. At this point, since the error has been corrected, even if a bit error further occurs, error correction by ECC becomes possible. In the case of an ECC capable of correcting 1 bit, correction of 2 bits or more is possible, and a bit error exceeding the ECC correction capability can be corrected. When there is no error even for one bit, the calculation amount remains the same as before and is extremely efficient.

  The present embodiment is characterized in that in a flash memory which is an electrically erasable and rewritable memory, error correction more than the number of bits that can be corrected by ECC can be performed by using a few redundant areas.

  The features of this embodiment will be briefly described with reference to FIG. In ECC, it is assumed that 1-bit error correction and 2-bit or more error detection can be performed using a Hamming code or the like. Further, it is assumed that a 1-bit error has occurred and the bit error correction information has been written in advance.

  In FIG. 1, data is read from the flash memory (step S101), and then the flash memory is searched for correction information (step S102). If there is correction information, the data read from the flash is modified based on the correction information (steps S103 and S104). Next, ECC calculation is performed (step S105). Since the error has already been corrected in the above data, no bit error is detected by ECC. In other words, by applying this method and writing error correction information in advance, it is possible to correct data correctly even if another 1-bit error bit occurs in the presence of this 1-bit error. It becomes.

  Referring to FIG. 2, the minimum configuration of this embodiment is shown. In FIG. 2, a CPU 201 is connected to a RAM 202, a ROM 204, and a NAND flash memory 203. The CPU 201 can execute various programs stored in the ROM 204 and perform processing such as ECC calculation.

  FIG. 3 shows a page structure of a kind of NAND called a small page. FIG. 3 shows how to use a page, which is a read unit of the NAND flash memory 203. In addition to the main area for storing data, there is a redundant area (spare area), which is a feature of the NAND flash memory.

  Referring to FIG. 3, one page is composed of a 512-byte data storage area (main area) and a 16-byte redundant area (spare area). And a place for storing correction information according to the present embodiment. A defective block refers to a block including a missing bit or a block in which an erase error has occurred. The bad block mark is an identifier that is written when an event recognized as a bad block is found / occurred, and is used to identify that the block is not used thereafter.

  Usually, the ECC code of the main area and the mark in the case of a defective block are stored in the spare area. The location for storing the correction information may be another page or another block of the same device, or may be another device. In the present embodiment, a case will be described in which correction information is also stored in the spare area in order to make use of the features. An example of correction information is described in FIG.

  FIG. 4 shows an embodiment comprising 2 bytes of position information and 1 byte of correction value as the correction information format. Since the data area is 512 bytes, meaningful values as position information are 0 to 511. Accordingly, in the case of 0xFFFF (decimal number 65535) in hexadecimal which is a value immediately after erasure, it is assumed that there is no erasure information.

  Next, the operation of the apparatus shown in FIGS. 2 to 4 will be described using a specific example (FIG. 5) and a flowchart (FIG. 6). FIG. 5 shows specific numerical values in FIGS. 3 and 4 to show an example of the operation. FIG. 6 shows a detailed flowchart.

  The operation will be described with reference to FIG. Reading operation for normal pages Reading operation when 1-bit corruption occurs Reading operation when 1-bit corruption occurs Reading operation when 2-bit corruption occurs Reading operation when 2-bit corruption occurs A reading operation when 3-bit corruption occurs will be described in order. In the present embodiment, the constant M is a constant value that indicates how many bits can be corrected beyond the correction range by the ECC code, and is variable depending on the correction information implementation method. In the present embodiment, since the 1 bit can be corrected excessively, the constant M is 1.

<Reading operation for normal page (no bit corruption)>
In step S602, N is initialized to 0. In the case of normal operation, the value N is not used thereafter. In step S603, data is read from the NAND flash memory 203. In step S604, it is confirmed whether there is correction information. If there is no correction information, ECC is calculated in step S605. Since there is no bit corruption this time, both steps S606 and 607 are NO, and the process ends.

<Read operation when 1-bit corruption occurs>
In step S602, N is initialized to 0. In step S603, data is read from the NAND flash memory 203. In step S604, it is confirmed whether there is correction information. If there is no correction information, ECC is calculated in step S605. Since there is no 2-bit error in step S606, the determination is NO and the process proceeds to step S607. Since an ECC error has occurred for the first time this time, the answer is YES, and N and M are compared in step S612. Since N is 0 and M is 1, correction information is additionally written in step S613. As a specific example, FIG. 5 shows that the corrected information 0x39 is written when the value of the 100th byte is garbled as 0x38. After writing the correction information, the process ends at step S615.

<Reading operation when 1 bit is garbled>
In step S602, N is initialized to 0. In step S603, data is read from the NAND flash memory 203. In step S604, it is confirmed whether there is correction information. Since the position information is not 0xFFFF but 0x0064, it is determined that there is correction information. In step S608, correction information is read, and in step S609, the data read in step S603 is corrected. In order to indicate that the correction has been made, 1 is added to N in step S610. In step S611, whether or not there is further correction information is confirmed. However, since there is only one in the description of the present embodiment, the answer is YES, and ECC is calculated in step S605. Since the information is corrected, NO is determined in Steps S606 and S607 because there is no ECC error, and the process ends.

<Read operation when 2-bit corruption occurs>
In step S602, N is initialized to 0. In step S603, data is read from the NAND flash memory 203. In step S604, it is confirmed whether there is correction information. Since the position information is not 0xFFFF but 0x0064, it is determined that there is correction information. In step S608, correction information is read, and in step S609, the data read in step S603 is corrected. In order to indicate that the correction has been made, 1 is added to N in step S610. In step S611, whether or not there is further correction information is confirmed. However, since there is only one in the description of the present embodiment, the answer is YES, and ECC is calculated in step S605. Although 2 bits are garbled, since 1 bit has been corrected, the determination of 2-bit error is NO in step S606, and the process proceeds to step S607. In step S607, if the second bit error is not present in the corrected one byte, a one bit error is detected, and the process proceeds to step S612. In the present embodiment, since 1-bit additional correction is allowed, in step S612, N is not smaller than M compared to N = 1 and M = 1, so the process proceeds to NO and ends as it is.

<Reading operation when 2 bits are garbled>
In the present description where M = 1, the case is the same as when 2-bit corruption occurs. When M is 1 or more, the processing is the same as the reading operation in which 1-bit corruption occurs.

<Read operation when 3-bit corruption occurs>
In step S602, N is initialized to 0. In step S603, data is read from the NAND flash memory 203. In step S604, it is confirmed whether there is correction information. Since the position information is not 0xFFFF but 0x0064, it is determined that there is correction information. In step S608, correction information is read, and in step S609, the data read in step S603 is corrected. In order to indicate that the correction has been made, 1 is added to N in step S610. In step S611, whether or not there is further correction information is confirmed. However, since there is only one in the description of the present embodiment, the answer is YES, and ECC is calculated in step S605. In step S606, a check for garbled 2-bit data is performed. In the present embodiment, 1 bit out of 3 bits has been corrected, but the remaining 2 bits correspond to a case other than the corrected byte area, so the determination in step S6060 is YES, and the correction is impossible. Proceeding to S614, abnormal processing is performed. Examples of the abnormal processing include, for example, notifying an application that an error that cannot be corrected has occurred, and setting all 0 as data to be returned.

  The configuration of the present embodiment described above has the following effects.

  The first effect is that error correction exceeding the error correction capability of ECC becomes possible by additionally writing correction information.

  The second effect is that the error correction capability can be enhanced without modifying the ECC. When the ECC correction capability is increased, the amount of calculation and the amount of ECC code are expected to increase. There is almost no effect on the reading and writing performance of a normal area where no occurrence occurs. Therefore, according to the above-described embodiment, it is possible to perform error correction with high reliability without impairing the performance of an electronic device equipped with a flash memory as a storage area and without significantly changing existing processing.

<Other Embodiments According to the Present Invention>
Further, another embodiment according to the present invention will be described. The basic configuration for error correction is as described above. However, in the above embodiment, there is room for further improvement in the way of holding correction information and the processing at the time of erasure.

  The flow of processing at the time of erasing is shown in FIG. Since the correction information in each embodiment of the present invention is for a normal page block, it is also necessary to delete the error correction information at the same time when erasing the block being corrected. It differs from the patent document 1 quoted as.

  As shown in FIG. 7, as a process at the time of block erasing, first, an alternative area is searched for whether there is correction information of the block. If there is not, the block erasure process of step S704 is completed and the process ends. If there is, the correction information needs to be erased in step S703.

  In the previous embodiment, the correction information is stored in the spare area of the page, but in this case, the correction information is deleted together with the deletion of the block, so that a special process corresponding to step S703 in FIG. 7 is unnecessary. There is a notable feature. When correction information is stored in another block of the NAND, only batch erasure can be performed. Therefore, correction information other than that to be erased must be copied to another block and deleted.

  Here, an example in which “erased information” is additionally written will be shown as an example of correction information deletion. When the storage device is not the same device and the same page, it differs from the previous embodiment in that information indicating the page number is added and a validity flag indicating validity is added. Reference numeral 801 in FIG. 8 shows the format. Reference numeral 802 indicates an embodiment when an error occurs in the 100th byte of 400 pages. Thereafter, when a block including 400 pages is erased, 0 indicating “invalid” is designated in the valid flag as indicated by reference numeral 803. Such a format is particularly effective when another device having excellent additional write characteristics, such as a NOR flash, is selected as a storage location for correction information.

  In the present embodiment, it is assumed that there is one device. However, in the actual embodiment, the number is not limited to one. If there are a plurality of devices, it can be easily estimated that it is necessary to assign a device number in addition to the page number, and this is within the scope of the present invention.

  Another embodiment of the correction information format is further shown. FIG. 9 shows an example in which correction information is recorded twice. When the correction information itself is garbled later, if the correction information falls within the ECC correctable range, it is possible to prevent the data on the page from being lost. FIG. 10 is obtained by adding an error correction code related to the correction information to the correction information. Again, when the correction information itself is garbled later, it is possible to prevent the data on the page from being lost.

  Thus, in this embodiment, since error correction is performed on a normal area, it is necessary to delete correction information when the block is erased. However, after erasing, there is an effect that it can be used as a normal area without bit corruption.

  The preferred embodiment of the present invention has been described above, but the present invention is not limited to this, and various modifications can be made without departing from the scope of the invention.

  It should be noted that the present invention is effective when applied to an electronic device using a flash memory such as a mobile phone, and particularly to a device that requires reliability of data to be stored, such as a device that stores data such as paid music and images. It is.

It is a flowchart which shows the flow of the error correction method which concerns on embodiment of this invention. It is a block diagram which shows the structure of the error correction apparatus with which the error correction method which concerns on embodiment of this invention is applied. 1 is a conceptual diagram showing a structure for each read unit (page) of a NAND flash memory according to an embodiment of the present invention. It is a conceptual diagram which shows the structure of the correction information format which concerns on embodiment of this invention. It is a conceptual diagram for demonstrating the specific example based on embodiment of this invention. It is a flowchart for demonstrating the specific example based on embodiment of this invention. It is a flowchart which shows the flow of the error correction method which concerns on other embodiment of this invention. Other embodiments of the invention It is a conceptual diagram which shows the page structure concerning other embodiment (thing which records correction information doubly) of this invention. It is a conceptual diagram which shows the page structure concerning other embodiment (thing which gives an error correction code | cord | chord to correction information) of this invention. It is a flowchart which shows the flow of the error correction method based on the technique relevant to this invention.

Explanation of symbols

201 CPU
202 RAM
203 NAND flash memory 204 ROM

Claims (10)

A bit error detection means for detecting a bit error using an error correction code when data is read from the storage area;
Bit error information writing means for writing bit error information including information on the location and correct value of the bit error detected by the bit error detection means in a predetermined alternative area;
Next, when data is read from the storage area, when the alternative area is searched and the bit error information is determined to be present, data correction means for correcting data based on the bit error information;
An information processing apparatus comprising: The storage area comprises a redundant area for each reading unit,
The information processing apparatus according to claim 1, wherein the error information writing unit uses the redundant area as the alternative area.   The information processing apparatus according to claim 1 or 2, wherein the bit error detection means detects and corrects a bit error using an error correction code after the data correction by the data correction means.   The bit error information writing means adds bit error information related to the bit error to the alternative area when the bit error detection means detects a bit error after the night correction of the data to the data correction means. The information processing apparatus according to claim 3, wherein writing is performed.   5. The erasure processing unit according to claim 1, further comprising an erasure processing unit that deletes the bit error information written in the alternative region by the bit error information writing unit when erasing data in the storage area. The information processing apparatus according to any one of claims.   6. The information according to claim 5, wherein the erasure processing unit additionally writes the information indicating that the bit error information has been deleted into an alternative area of a read unit different from a read unit that is a data erasure target. Processing equipment.   7. The information processing apparatus according to claim 1, wherein the bit error information writing unit writes the bit error information in two or more alternative areas.   8. The bit error information writing unit assigns an error correction code to the bit error information and writes the assigned error correction code in the alternative area. 9. Information processing device. A bit error detection step for detecting a bit error using an error correction code when data is read from the storage area;
A bit error information writing step of writing bit error information including information on a location and a correct value of the bit error detected in the bit error detection step in a predetermined alternative area;
Next, when data is read from the storage area, a data correction step of correcting the data based on the bit error information when the alternative area is searched and the bit error information is determined to be present,
An error correction method comprising: Information processing device
A bit error detection means for detecting a bit error using an error correction code when data is read from the storage area;
Bit error information writing means for writing bit error information including information on the location and correct value of the bit error detected by the bit error detection means in a predetermined alternative area;
Next, when data is read from the storage area, when the alternative area is searched and it is determined that there is the bit error information, it functions as data correction means for correcting data based on the bit error information. An error correction program.

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