JP2010140192A - Barrel shifter device and barrel shifting method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a barrel shifter device and a barrel shifting method for achieving a P bit barrel shifter whose bit width is wider by adding a few pieces of hardware to a plurality of N bit barrel shifters. <P>SOLUTION: This barrel shifter device includes: P pieces of Mto1 selectors 2; and a shift quantity control part 3 for generating the select signal of each Mto1 selector 2 based on a shift direction and shift width, and the low order (K mod N) bit-th shift results of M pieces of N bit barrel shifters 1 are connected to the low order K-th Mto1 selector 2, and when the select signal of the low order K-th Mto1 selector 2 is in an L level, the low order K-th Mto1 selector 2 selects the low order (K mod N)th shift result of the low order R(when K/N≥L, R=K/N-L, when K/N<L, R=K/N-L+M)th N bit barrel shifter 1, and obtains the selection result of the low order K-th Mto1 selector 2 as the low order K bit-th shift result of a P bit barrel shifter 10. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a barrel shifter in which a plurality of barrel shifters are combined, and more particularly, to a barrel shifter device and a barrel shift method for realizing a combination of a plurality of barrel shifters and a barrel shifter wider than a bit width at a low cost.

  Various general-purpose processors and DSPs (Digital Signal Processors) have been mounted with bit shifters for realizing numerical shift and rotation.

  Bit shifters have been used for speeding up multiplication and division of numerical values, extraction of desired bit patterns from numerical values, synthesis of bit patterns, serial parallel conversion, and the like.

  Until now, in order to save hardware resources, a 1-bit shifter that implements shift and rotation in 1-bit units has been implemented in a processor.

  However, in recent years, with the progress of semiconductor scaling rules, hardware resource restrictions have become milder, and a barrel shifter that realizes shifting and rotation of arbitrary bits at a time is mounted on a processor. As a result, high-speed operations such as multiplication and division of numerical values, extraction of desired bit patterns from numerical values, synthesis of bit patterns, serial parallel conversion, etc. are realized, and decimal point alignment in floating point arithmetic and normalization of floating point arithmetic results Processing can be performed at high speed.

  FIG. 27 shows a configuration example of a standard barrel shifter as disclosed in Non-Patent Document 1. The barrel shifter 100 performs left / right rotation and left / right logical shift on 4-bit input data (In [3: 0]). As shown in FIG. 27, the 4-bit barrel shifter 100 has four 2to1 selectors cascaded in two stages, and each of the four 2to1 selectors at each stage outputs (or inputs) the 2to1 selector at the same bit position in the previous stage. Data) or the output (or input data) of the 2to1 selector at a position 1 to 2 bits away.

  Each 2to1 selector 101 in the 0th stage selects data at the same bit position of input data (In [3: 0]) or input data at a bit position one bit apart. On the other hand, each 2to1 selector 102 in the first stage selects data at the same bit position of the previous 2to1 selector 101 or data at a bit position two bits away from the previous 2to1 selector 101.

  In general, an N-bit barrel shifter cascades N 2to1 selectors in (log2N) stages, and the N 2to1 selectors in each stage are outputs (or input data) of the 2to1 selector at the same bit position in the previous stage, Select the output (or input data) of the 2to1 selector at a position 1 to 2 ^ (log2N-1) bits away.

  Further, the shift amount control unit 103 determines the control signal (s0) of the 2-to-1 selector at each stage from the shift direction (lr0, left: 1, right: 0) and the shift width (sw0 [1: 0]) of the 4-bit barrel shifter. [1: 0]). In FIG. 27, the connection between the shift amount control unit 103 and the 2to1 selectors 101 and 102 is omitted.

  Each of the N 2to1 selectors in the (log2N) stages constituting the N-bit barrel shifter generally supports only one of left or right rotation (shift). Therefore, if the direction in which the input data (In) is to be shifted (Ir0, left: 1, right: 0) and the shift direction of the 2to1 selector do not match, as shown in FIG. In (103), (N-sw0) is calculated, and the result is used as the control signal (s0) of the 2to1 selector, thereby realizing horizontal rotation (shift). In FIG. 28, the “3′b100” portion of “3′b100” which is one of the inputs to the sub indicates that it is a 3-bit input, and the “100” portion has a 3-bit value. 100. Similarly, the “1′b” portion of “1′b0” included in the other of the inputs to the sub indicates that it is a 1-bit input, and the “0” portion has a 1-bit value of 0. It is shown that. The same applies to other figures in this specification.

  Next, the zero mask controller 104 shifts the lower bit of the shift result at the time of the left logical shift from 0 to the right logical shift from the shift direction (lr0), rotate flag (rot0) and shift width (sw0) of the 4-bit barrel shifter. A 4-bit zero mask (ZM0) for inserting 0 into the upper bits of the time shift result is generated.

  FIG. 29 shows details of the zero mask control unit 104. First, as shown in FIG. 29, the zero mask control unit 104 uses the zero mask generation unit 105 to convert the shift direction (lr0) and shift width (sw0) of the 4-bit barrel shifter into lower bits of the shift result at the left logical shift. A 4-bit left zero mask (LZM0) for inserting 0 and a 4-bit zero mask (RZM0) for inserting 0 into the upper bits of the shift result at the right logical shift are generated.

  Then, based on the shift direction (lr0, left: 1, right: 0), the left zero mask (LZM0) or the right zero mask (RZM0) is selected by the selector 106, and the rotate flag (rot0, rotate: 1, logical shift: 0) Based on the above, the selector 107 selects the selection result of the selector 106 or the one mask for rotation (ONE) in which all bits are 1.

  Finally, the AND circuit 108 calculates the logical product of the zero mask (ZM0) generated by the zero mask control unit 104 and the shift result of the output of the first stage 2to1 selector 102, and outputs the result as the shift result (Out).

  As described above, the 4-bit barrel shifter 100 realizes left / right rotation and left / right logical shift.

  On the other hand, in recent years, there is an increasing number of mountings in which a plurality of (M, M: integers of 2 or more) N (powers of 2) bit barrel shifters are combined and used as a barrel shifter having a wider bit width. For example, Non-Patent Document 2 discloses a shift function in units of 4 × 16 bits, 2 × 32 bits, and 1 × 64 bits, and 4 × 32 bits and 2 × 64 bits. Patent Document 1 discloses a barrel shifter having M stages of N-bit barrel shifter unit circuits.

  As an example of the invention disclosed in Non-Patent Document 2 and Patent Document 1, FIG. 30 shows a general configuration example of an 8-bit barrel shifter in which two 4-bit barrel shifters are combined. The 8-bit barrel shifter 200 is a combination of two 4-bit barrel shifters 201 and 202 that perform left / right rotation and left / right logical shift on 4-bit input data (In [3: 0]).

  As shown in FIG. 30, the 8-bit barrel shifter 200 includes six 2-to-1 selectors in addition to the two 4-bit barrel shifters 201 and 202 and the shift amount control units 205a and 205b and the zero mask control units 206a and 206b corresponding thereto. 203, eight 2to1 selectors 204, and the shift amount for generating the control signals (s3) of the eight selectors 204 from the shift direction (lr3) and the shift width (sw3 [2: 0]) of the 8-bit barrel shifter Based on the control unit 205c, the shift direction (lr3) of the 8-bit barrel shift, the rotate flag (rot3), and the shift width (sw3), the lower bit of the shift result at the time of the left logical shift is 0, and the shift result of the right logical shift The zero mask control unit 206c that generates an 8-bit zero mask (ZM3) for inserting zeros into the higher-order bits and the zero mask control unit 206 8 AND circuits 207 for calculating the logical product of the romask (ZM3) and the outputs of the 8 2to1 selectors 204.

  The shift amount control unit 205c and the zero mask control unit 206c are substantially the same as the shift amount control unit 103 and the zero mask control unit 104 of FIG. 27 except for the difference in the number of bits. However, the shift amount control unit 205c is different from the shift amount control unit 103 in that only the control signals (s3) of the eight 2to1 selectors 204 are generated. Although not shown in FIG. 30, the shift direction (lr1, lr2), the shift width (sw1, sw2) input to the shift amount control units 205a, 205b and the zero mask control units 206a, 206b at the time of 8-bit barrel shifter, and A selector is provided for switching the rotation flag (rot1, rot2) to the shift direction (lr3), shift width (sw3) and rotation flag (rot3) of the 8-bit barrel shifter.

  The 2to1 selector 203 added to the 0th stage and the 1st stage 2to1 selectors 201 and 202 is such that the position of the output (or input data) of the 2to1 selector at a position 1 to 2 bits away from the previous stage is a 4-bit barrel shifter. And 8 bit barrel shifter are added to select them. On the other hand, eight 2to1 selectors 204 added as the second stage are added to select the shift result of the 4-bit barrel shifter at a position 4 bits away, which is necessary for the 8-bit barrel shifter.

Generally, when constructing a P (= M × N) -bit barrel shifter using M N-bit barrel shifters, (M × (N + log2N-1)) 2to1 selectors are added. A shift amount control unit for controlling the 2to1 selector, a zero mask generation unit that generates a P-bit zero mask, and a P-bit AND circuit that calculates the logical product of the zero mask and the added 2to1 selector selection result are required. Become.
Japanese Patent No. 3272724 Matthew R. Pillmeier, atc, "Design Alternatives for Barrel Shifters", Proceedings of the SPIE, Vol.4791, pp.436-446, 2002 Intel.Corp, "IA-32 Intel Architecture Software Developer's Manual Volume 1: Basic Architecture", http: //download.intel.com/jp/developer/jpdoc/IA32_Arh_Dev_Man_Vol1_Online_i.pdf, 2004 ARM.Limited, "Cortex-A8 Technical Reference Manual", Rev.r1p1, http://infocenter.arm.com/help/topic/com.arm.doc.ddi0344b/DDI0344.pdf, 2006

As described above, there is an increasing number of implementations that combine a plurality (M: integer greater than or equal to 2) N (powers of 2) bit barrel shifters and use them as P (= M × N) bit barrel shifters with a wider bit width.
On the other hand, in such an implementation, as shown in FIG. 30, (M × (N + log2N-1)) 2to1 selectors and shift amount control for controlling the added 2to1 selectors Part, a zero mask control part for generating a P bit zero mask, and a P bit AND circuit for calculating the logical product of the zero mask and the selection result of the added 2to1 selector.

  For this reason, it cannot be said that the additional hardware cost for making a barrel shifter with a wider bit width by combining a plurality of barrel shifters is necessarily low. Further, there is a problem that the additional hardware cost increases as the number of barrel shifters to be combined (M) and the bit width (N) increase.

  In recent years, mobile devices such as mobile phone terminals are also required to perform various media processing at high speed. As disclosed in Non-Patent Document 3, this is the same as SSE (Streaming SIMD Extensions). The SIMD (Single instruction multiple data) type execution unit is incorporated. In such a mobile device, it is necessary to configure the device with a minimum amount of hardware in order to reduce hardware costs and thus reduce power consumption. For this reason, even when a barrel shifter having a wider bit width is made by combining a plurality of barrel shifters, it is required to keep the number of additional hardware required as small as possible.

  The present invention has been made in view of such a problem. By adding a small amount of hardware to a plurality (M: an integer greater than or equal to 2) N (powers of 2) bit barrel shifters, the bit width can be increased. It is an object of the present invention to provide a barrel shifter device and a barrel shift method that realize a wide P (= M × N) bit barrel shifter at low cost.

  To achieve the above object, the present invention provides, as a first aspect, a barrel shifter device that performs barrel shift of P (= M × N) bits by combining M N (powers of 2) bit barrel shifters, And a shift amount control unit that generates a select signal of each Mto1 selector based on the shift direction and the shift width. The lower K-th Mto1 selector includes M N-bit barrel shifters. When the shift result of the lower (K mod N) bit is connected and the select signal of the lower Kth Mto1 selector generated by the shift amount control unit is L, the lower Kth Mto1 selector (R = K / NL if K / N ≧ L, R = K / N-L + M if K / N <L) Lower (K mod N) th shift result of the Nth bit barrel shifter And select the result of the lower Kth Mto1 selector as the P bit barrel shifter. There is provided a barrel shifter apparatus characterized by position to the shift result of K-th bit.

  In order to achieve the above object, the present invention provides, as a second aspect, a barrel shift method for performing barrel shift of P (= M × N) bits by combining M N (power of 2) bit barrel shifters. The shift result of the lower (K mod N) bits of the M N-bit barrel shifters is connected to the lower K-th selector among the P Mto1 selectors, and is generated based on the shift direction and the shift width. When the select signal of the lower Kth Mto1 selector is L, the lower Kth Mto1 selector selects the lower R (if K / N ≧ L, R = K / NL, and K / N <L R = K / N-L + M) selects the lower (K mod N) th shift result of the Nth bit barrel shifter, and selects the lower Kth Mto1 selector as the lower Kth bit of the P bit barrel shifter. Providing a barrel shift method characterized by a shift result It is.

  According to the present invention, P (= M × N) having a wider bit width can be obtained by adding a small amount of hardware to a plurality (M: an integer of 2 or more) N (power of 2) bit barrel shifters. It is possible to provide a barrel shifter device and a barrel shift method that realize a bit barrel shifter at low cost.

  As shown in FIG. 1, a P-bit barrel shifter 10 as a barrel shifter device according to the present invention performs a barrel shift of P (= M × N) bits by combining M N (powers of 2) bit barrel shifters 1. The device includes P Mto1 selectors 2 and a shift amount control unit 3 that generates a select signal of each Mto1 selector 2 based on the shift direction and the shift width. Is connected to the shift result of the lower (K mod N) bit of the M N-bit barrel shifters 1 and the select signal of the lower K-th Mto1 selector 2 generated by the shift amount control unit 3 is L In addition, the lower Kth Mto1 selector 2 has a lower R (R = K / NL if K / N ≧ L, R = K / N-L + M if K / N <L) th N Select the lower (K mod N) shift result of bit barrel shifter 1 and select the lower K number Mto1 selection result selector 2 and characterized by a shift result of the lower K-th bit of P-bit barrel shifter 10.

  The input to the Mto1 selector 2 that selects data at positions 1 to (N-1) bits apart at the boundary of M N-bit barrel shifters 1 is different for M N-bit barrel shifters and P-bit barrel shifters. However, with such a configuration, it is not necessary to add an Mto1 selector to select them. This makes it possible to minimize the number of additional hardware required when configuring a P-bit barrel shifter by combining a plurality of N-bit barrel shifters.

  Hereinafter, preferred embodiments of the present invention will be described.

[First Embodiment]
A first embodiment in which the present invention is suitably implemented will be described.
FIG. 2 shows the configuration of the P-bit barrel shifter according to this embodiment. A P-bit barrel shifter 300 as a barrel shifter device has a wider bit width of P (= M × N) bits by combining M (M: integer greater than or equal to 2) N (power of 2) bit barrel shifters 301. ing.

  Here, the configuration shown in FIG. 2 is an example using M N-bit barrel shifters based on the left shift (right shift is realized by applying the left shift). There may be.

The P-bit barrel shifter 300 is configured by adding P Mto1 selectors 302, a shift amount control unit 303, a zero mask control unit 304, and P AND circuits 305 to the M N-bit barrel shifters 301. ing. The N-bit barrel shifter 301 corresponds to the N-bit barrel shifter 1 in FIG. The P Mto1 selectors 302 correspond to the Mto1 selector 2 in FIG. Further, the shift amount control unit 303 corresponds to the shift amount control unit 3 in FIG.
The shift amount control unit 303 generates select signals for the P Mto1 selectors 302 from the shift direction (lrP, left: 1, right: 0) of the P-bit barrel shifter 300 and the shift amount swP (P> swP ≧ 0). To do. The zero mask control unit 304 generates a P bit zero mask used at the time of logical shift from the shift direction (lrP), the shift amount (swP), and the rotate flag (rotP) of the P bit barrel shifter 300. The AND circuit 305 calculates the logical product of the selection results of the P Mto1 selectors 302 and the zero mask.

FIG. 3 shows the configuration of the N-bit barrel shifter 301. The N-bit barrel shifter 301 has a configuration in which the 4-bit barrel shifter shown in FIG. 27 is expanded to N bits, and performs a left-right logical shift in addition to a left-right rotation.
The N-bit barrel shifter 301 includes a 2to1 selector 3010, a shift amount control unit 3011, a zero mask control unit 3012, and an AND circuit 3013.
N 2 to 1 selectors 3010 are cascaded N (Q = [log2N], [log2N] is a maximum integer not exceeding log2N) stages per stage. In FIG. 3, the connection between the shift amount control unit 3011 and the 2to1 selector 3010 at each stage is omitted.

  FIG. 4 shows the configuration of the zero mask control unit 3012. The zero mask control unit 3012 uses an N-bit left zero mask (LZM) to insert a low-order bit 0 of the shift result in the left logical shift based on the shift direction (lr) and the shift width (sw) of the N-bit barrel shifter. ) And an N-bit right zero mask (RZM) for inserting the upper bit 0 of the shift result at the time of the right logical shift is generated by the zero mask generation unit 3014. Then, based on the shift direction (lr, left: 1, right: 0), the selector 3015 selects the left zero mask (LZM) or the right zero mask (RZM), and the rotate flag (rot, rotate: 1, logical shift: 0) ), The selector 3016 selects the selection result of the selector 3015 or the one mask (ONE) in which all the bits for rotation are 1, and outputs the selection result as a zero mask.

  The basic operation principle of the P-bit barrel shifter will be described using an 8-bit barrel shifter in which two 4-bit barrel shifters are combined as an example. Select signal used when combining 8-bit barrel shifter and two 4-bit barrel shifters with the shift result when 8-bit data of abcdefgh is rotated left by 0-7 bits and two 4-bit barrel shifters This is shown in FIG.

  The select signal controls eight selectors for selecting one of the shift results of the two 4-bit barrel shifters (corresponding to P Mto1 selectors 302 in FIG. 2). When the select signal is 0, the selectors of the lower 0-3 bits respectively select the shift result of the right (self) 4-bit barrel shifter. When the select signal is 1, the shift result of the 4-bit barrel shift on the left side (one right side of itself, in this case folded back to the left side) is selected.

  On the other hand, when the select signal is 0, the lower fourth to seventh bit selectors respectively select the shift result of the left (self) 4-bit barrel shifter. When the select signal is 1, the shift result of the right side (one right side of itself) 4-bit barrel shifter is selected.

  In FIG. 5, since the barrel shifter based on the left rotation is combined, when the select signal is 1, the shift result of the barrel shifter on the right one side from itself is selected, but the right rotation is the basis. When combining barrel shifters, the shift result of the barrel shifter on the left side of itself is selected.

  In FIG. 5, two 4-bit barrel shifters are combined. However, for example, when M N-bit barrel shifters are combined, the select signal is expanded to S (= [log2M]) bits.

  When the select signal is 0, the shift result of its own barrel shifter is expanded, and when the select signal is L (M> L ≧ 0), the shift result of the L right barrel shifter is selected. . However, if there is no L right barrel shifter, the right barrel shifter is folded back to the left barrel shifter (assuming there is a left end barrel shifter right next to the right end barrel shifter) and the Lth barrel shifter Select the shift result.

  As shown in FIG. 5, at the time of left 0-bit shift, the shift results of the two 4-bit barrel shifters match the shift results of the 8-bit barrel shifter, so the two 4-bit barrel shifter shift results are directly shifted by the 8-bit barrel shifter. The selection may be made as a result, and the select signal at each bit position is 0000 | 0000.

  At the time of left 1-bit shift, the lower 3rd to 1st bits (bcd, fgh) of the shift results of two 4-bit barrel shifters coincide with the shift results of the 8-bit barrel shifter. On the other hand, in order to make each lower 0 bit (a, e) coincide with the shift result of the 8-bit barrel shifter, it is necessary to exchange each lower 0 bit (a, e).

  Specifically, the lower 0 bit (a) of the left 4-bit barrel shifter is selected as the lower 0 bit of the right 4-bit barrel shifter, and the lower 0 bit (e) of the right 4-bit barrel shifter is The lower 0 bit of the 4-bit barrel shifter may be selected. For this purpose, the select signal at each bit position is 0001 | 0001.

  During the left 2-bit shift, the lower 3rd to 2nd bits (cd, gh) of the shift results of the two 4-bit barrel shifters coincide with the shift results of the 8-bit barrel shifter. On the other hand, it is necessary to exchange each lower 1 to 0th bit (ab, ef).

  Specifically, the lower 1 to 0 bits (ab) of the left 4-bit barrel shifter are selected as the lower 1 to 0 bits of the right 4-bit barrel shifter, and the lower 1 to 0 bits of the right 4-bit barrel shifter (ef) may be selected as the lower 1 to 0th bits of the left 4-bit barrel shifter. For this purpose, the select signal at each bit position is 0011 | 0011.

  Similarly, an 8-bit barrel shifter is realized by selecting the shift results of two 4-bit barrel shifters based on the select signal shown in FIG. The select signals supplied to the two 4-bit barrel shifters are similar signals, and one 4-bit select signal may be distributed to selectors that select the shift results of the two 4-bit barrel shifters.

In the following, the details of the generalized P-bit barrel shifter 300 of FIG. 2 that implements the basic operating principle described in the example of FIG. 5 will be described.
First, a method for connecting the shift results of the M N-bit barrel shifters 301 and the P Mto1 selectors 302 will be described.
The lower K (P> K ≧ 0) Mto1 selector is connected to the shift result of the lower (K% N,%: remainder) bits of each of the M bit barrel shifters, and the select signal of the Kth Mto1 selector Is L (M> L ≧ 0), the lower Kth Mto1 selector is lower S (S = K / NL, if S <0, S = K / N-L + M) th The lower (K% N) th shift result of the N-bit barrel shifter is selected.

  Taking the K (K = P−1) th Mto1 selector in FIG. 2 as an example, when the select signal L of the Mto1 selector is 0, the lower order (N− 1) Select the shift result of the bit, and if the select signal L is 1, select the shift result of the lower (N-1) th bit of the lower (M-2) th N-bit barrel shifter and select When the signal L is (M−1), the lower (N−1) -th bit shift result of the lower 0th N-bit barrel shifter is selected.

  Taking the K (K = P-2) th Mto1 selector in FIG. 2 as an example, when the select signal L of the Mto1 selector is 0, the lower order (N− 2) Select the shift result of the bit, and if the select signal L is 1, select the shift result of the lower (N-2) th bit of the lower (M-2) th N-bit barrel shifter and select When the signal L is (M−1), the shift result of the lower (N−2) th bit of the lower 0th N-bit barrel shifter is selected.

  Taking the K (K = PN-1) th Mto1 selector in FIG. 2 as an example, when the select signal L of the Mto1 selector is 0, the lower order (N− 1) Select the shift result of the bit, and if the select signal L is 1, select the shift result of the lower (N-1) th bit of the lower (M-3) th N-bit barrel shifter and select When the signal L is (M−1), the lower (N−1) -th bit shift result of the lower (M−1) -th N-bit barrel shifter is selected.

  Taking the K (K = PN-2) th Mto1 selector in FIG. 2 as an example, when the select signal L of the Mto1 selector is 0, the lower order (N− 2) Select the shift result of the bit, and if the select signal L is 1, select the shift result of the lower (N-2) th bit of the lower (M-3) th N-bit barrel shifter and select When the signal L is (M-1), the lower (N-2) -th bit shift result of the lower (M-1) -th N-bit barrel shifter is selected.

  Taking the K (K = N-1) th Mto1 selector in FIG. 2 as an example, when the select signal L of the Mto1 selector is 0, the lower (N-1) th bit of the lower 0th N-bit barrel shifter If the select signal L is 1, the lower (M−1) th N-bit barrel shifter lower (N−1) bit shift result is selected and the select signal L is ( M-2), the shift result of the lower (N-1) th bit of the lower second N-bit barrel shifter is selected, and when the select signal L is (M-1), the lower 1 The shift result of the lower (N-1) th bit of the Nth N-bit barrel shifter is selected.

  Taking the K (K = N-2) th Mto1 selector in FIG. 2 as an example, when the select signal L of the Mto1 selector is 0, the lower (N-2) th bit of the lower 0th N-bit barrel shifter If the select signal L is 1, the lower (M−1) th N-bit barrel shifter lower (N−2) -bit shift result is selected, and the select signal L is ( M-2), the shift result of the lower (N-2) bit of the lower second N-bit barrel shifter is selected, and when the select signal L is (M-1), the lower 1 The shift result of the lower (N-2) th bit of the Nth N-bit barrel shifter is selected.

  Next, each select signal L (M> L ≧ 0) of the P Mto1 selectors 302 generated by the shift amount control unit 303 will be described. Here, the select signal L is a signal composed of H (= [log2M]) bits.

  As described with reference to FIG. 5, among the M Mto1 selectors 302 shown in FIG. 2, N sets of select signals L are distributed to N Mto1 selectors immediately below the M barrel shifters. do it.

  Generally, the same select signal L is distributed to the Mto1 selectors having the same (K% N) among the lower K (P> K ≧ 0) Mto1 selectors.

  Instead of directly generating the N sets of select signals L from the shift direction (lrP) of the P-bit barrel shifter and the shift amount swP (P> swP ≧ 0), the zero mask generated by the zero mask generation unit 3012 of the N-bit barrel shifter is generated. By diverting, the hardware cost for generating N sets of select signals L is reduced.

  In the following, the regularity of the N sets of select signals L will be described, and a part thereof will be described as being equivalent to the zero mask generated by the zero mask control unit 3012 of the N-bit barrel shifter. A method for generating N sets of select signals L will be described.

  FIG. 6 shows N sets of select signals L generated by the shift amount control unit 303 at the time of left rotation (shift) when eight 4-bit barrel shifters are combined. FIG. 7 shows a right zero mask (RZM) and a left zero mask (LZM) generated when the N-bit barrel shifter 301 is rotated left (shifted).

  As shown in FIG. 6, four sets of select signals are generated in order to combine eight 4-bit barrel shifters. Each select signal requires 3 bits for selecting the shift result of eight 4-bit barrel shifters. Also, the bit strings obtained by extracting the lower 2 bits, the lower 1 bits, and the lower 0 bits of the four sets of select signals are collected on the right side of the table.

  Referring to FIGS. 6 and 7, the vertical line portion in FIG. 6 has the same bit pattern as the right zero mask RZM, and the shaded portion in FIG. 6 has the same bit pattern as the left zero mask LZM. Therefore, the left and right zero masks (LZM, RZM) generated by the 4-bit barrel shifter in FIG. 7 are used for generating the select signal L at the left rotation (shift).

  In the example of FIG. 6, to generate the lower 0 bit of the select signal L, if the lower 2nd bit (swP [2]) of the shift amount is 0, the right zero mask (RZM) is selected and shifted. When the lower 2nd bit (swP [2]) of the quantity is 1, the left zero mask (LZM) is selected.

  In general, when the P-bit barrel shifter shifts swP (P> swP ≧ 0) bits to the left, the shift amount swP is used as the lower 0th bit of the select signal of the lower K (P> K ≧ 0) Mto1 selector. When the low-order Q (= [log2N]) bit of 0 is 0, the low-order (K% N) bit of the right zero mask (RZM) selected using the left and right zero mask selectors of any N-bit barrel shifter is selected. . When the lower Q bit of the shift amount swP is 1, the left and right zero mask selector of any N-bit barrel shifter is used as the lower 0 bit of the select signal of the lower K (P> K ≧ 0) Mto1 selector The lower (K% N) bit of the left zero mask (LZM) selected in the above is selected.

  As shown in FIG. 8, the selection of RZM or LZM is performed by using the select signal of the left and right zero mask selector 400 for selecting RZM or LZM of the zero mask control unit of the N-bit barrel shifter as the lower Q of the shift amount swP. It is only necessary to add a selector 402 for switching to the bit to the configuration shown in FIG. The selector 402 is switched by a mode signal that becomes 1 when the P-bit barrel shifter is executed.

  In the example of FIG. 6, when the lower third bit of the shift amount (swP [3: 2]) is 00 to generate the lower first bit of the select signal L, 0000 is selected and shifted. RZM is selected when the lower 3rd and 2nd bits (swP [3: 2]) of the amount is 01, and the lower 3rd and 2nd bits (swP [3: 2]) of the shift amount are 10. 1111 is selected and LZM is selected when the lower 3rd and second bits (swP [3: 2]) of the shift amount is 11. For these selections, four 4to1 selectors are mounted and swP [3: 2] only needs to be used as the selection signal.

  In the example of FIG. 6, in order to generate the lower second bit of the select signal L, the logical product of the lower third to second bits (swP [3: 2]) of the shift amount is ResA, and the lower shift amount If the 4th bit (swP [4]) and ResA are 00, select 0000; if the lower 4th bit of the shift amount (swP [4]) and ResA are 01, select RZM; If the lower 4th bit of the shift amount (swP [4]) and ResA are 10, 1111 is selected, and if the lower 4th bit of the shift amount (swP [4]) and ResA is 11, LZM is selected. Select.

  In general, when the P-bit barrel shifter shifts swP (P> swP ≧ 0) bits to the left, the lower T (Q> T> 0) bit of the select signal of the lower Kth Mto1 selector is the shift amount swP The result of the logical product of the bit values from the lower Q (= [log2N]) bit to the lower (Q + T-1) bit is ResA, and ResA and the lower (Q + T) bit are 00 When all bits 0 (ZERO) are selected, when ResA and the lower (Q + T) bit are 01, RZM is selected, and when ResA and the lower (Q + T) bit are 10, In this case, all bits 1 (ONE) are selected, and if ResA and the lower (Q + T) bit are 11, LZM is selected.

  As shown in FIG. 9, the lower (H-1) (H = [log2M]) to 0th bit of the select signal L is generated by an AND element 403 with a T (H> T ≧ 1) bit input for generating ResA. This is realized by mounting (H−1) sets of N 4to1 selectors 404 and sw [Q + T] and ResA as the select signals.

  The zero mask (LZM, RZM) used by the shift amount control unit 303 may be any one of M N-bit barrel shifters. In FIG. 2, the zero mask and control wiring between the shift amount control unit 303 and the N-bit barrel shifter 301 are not clearly shown.

  FIG. 10 shows N sets of select signals L generated by the shift amount control unit 303 at the time of right rotation (shift) when eight 4-bit barrel shifters are combined. FIG. 11 shows a right zero mask (RZM) and a left zero mask (LZM) generated by the N-bit barrel shifter 301 at the time of right rotation (shift).

  As shown in FIG. 10, four sets of select signals are generated in order to combine eight 4-bit barrel shifters. Each select signal requires 3 bits each for selecting the shift result of eight 4-bit barrel shifters. Also, the bit strings obtained by extracting the lower 2 bits, the lower 1 bits, and the lower 0 bits of the four sets of select signals are collected on the right side of the table.

  10 and 11, the vertical line portion in FIG. 10 has the same bit pattern as the right zero mask (RZM), and the shaded portion in FIG. 10 has the same bit pattern as the left zero mask (LZM). Therefore, the zero mask (RZM, LZM) generated by the 4-bit barrel shifter is used to generate the select signal L at the time of right rotation (shift).

  In the example of FIG. 10, when the lower second bit (swP [2]) of the shift amount is 0 to generate the lower 0 bit of the select signal L, the left zero mask (LZM) is selected, When the lower second bit (swP [2]) of the shift amount is 1, the right zero mask (RZM) is selected.

  Generally, when the P-bit barrel shifter shifts swP (P> swP ≧ 0) bits to the right, the shift amount swP is used as the lower 0th bit of the select signal of the lower K (P> K ≧ 0) Mto1 selector. When the low-order Q (= [log2N]) bit of 0 is 0, the low-order (K% N) bit of the left zero mask (LZM) selected using the left and right zero mask selectors of any N-bit barrel shifter is selected. . When the lower Q bit of the shift amount swP is 1, the right zero mask (RZM) selected using the left and right zero mask selectors of any N-bit barrel shifter is used as the lower 0 bit of the select signal of the lower K-th Mto1 selector. ) The lower (K% N) bit is selected.

  As shown in FIG. 12, the selection of RZM and LZM is an extension of the selection circuit for RZM and LZM during left rotation (shift) shown in FIG. To calculate the negative exclusive OR (XNOR) 503 of the lower Q bits of the shift amount swP and the shift direction (lrP) of the P bit barrel shifter, and to select RZM and LZM that the N bit barrel shifter has A selector 502 for switching the select signal of the left and right zero mask selector 501 to the negative exclusive OR 503 is required. The selector 501 is switched by a mode signal that becomes 1 when the P-bit barrel shifter is executed.

  In the example of FIG. 10, when the lower 3rd and 2nd bits (swP [3: 2]) of the shift amount are 00 to generate the lower 1st bit of the select signal L, 0000 is selected and shifted. LZM is selected when the lower 3rd and 2nd bits (swP [3: 2]) of the amount is 01, and the lower 3rd and 2nd bits (swP [3: 2]) of the shift amount are 10. 1111 is selected, and when the third and second bits (swP [3: 2]) of the shift amount is 11, RZM is selected. For these selections, it is only necessary to implement four 4to1 selectors and use swP [3: 2] as the selection signal.

  In the example of FIG. 10, in order to generate the lower 2 bits of the select signal L, the logical product of the lower 3rd to 2nd bits (swP [3: 2]) of the shift amount is ResA, and the lower shift bit is generated. If the fourth bit (swP [4]) and ResA are 00, select 0000; if the lower 4th bit of the shift amount (swP [4]) and ResA are 01, select LZM; When the lower 4th bit of the shift amount (swP [4]) and ResA are 10, 1111 is selected, and when the lower 4th bit of the shift amount (swP [4]) and ResA are 11, RZM Select.

  In general, when the P-bit barrel shifter shifts swP bits to the right, the lower T bit of the select signal of the lower Kth Mto1 selector is lower than the lower Q (= [log2N]) bits of the shift amount swP. If the result of the logical product of the bits up to the (Q + T-1) bit is ResA, if ResA and the lower (Q + T) bit are 00, all bits 0 (ZERO) are selected, and ResA and When the lower (Q + T) bit is 01, LZN is selected. When ResA and the lower (Q + T) bit are 10, all bits 1 (ONE) are selected, and ResA and lower When the (Q + T) bit is 11, RZM is selected.

  As shown in FIG. 13, the lower (H-1) (H = [log2M]) to 0th bit of the select signal L is generated by selecting the RZM and LZM during the left rotation (shift) shown in FIG. This is achieved by extending the circuit. Based on the shift direction (lrP) of the P-bit barrel shifter, the selection signal (Sel4 [1: 0]) generated from [swP [Q + T], ResA] is switched. Specifically, when the shift direction is left, Sel4 is generated with a straight arrow, and when the shift direction is right, Sel4 is generated with a crossing arrow.

  As shown in FIG. 13, a T bit input AND element 504 for generating ResA in FIG. 9 and (H−1) sets of N 4to1 selectors 505 include the lower (Q + T) bit of the shift amount swP. And ResA are added with a decoder 506 that generates a control signal (sel4) of N 4to1 selectors 505, thereby generating lower (H-1) to 0th bits of the select signal L.

  Next, the zero mask control unit 304 that generates a P bit zero mask used at the time of logical shift from the shift direction (lrP), the shift amount (swP), and the rotation flag (rotP) of the P bit barrel shifter 300 will be described.

FIG. 14 shows the configuration of the zero mask control unit 304. The zero mask control unit 304 generates a left zero mask (LZM) and a right zero mask (RZM) from the shift direction (lrP) and shift amount (swP) of the P-bit barrel shifter, and the generated zero mask ( The left and right zero mask selectors 601 that select LZM and RZM) based on the shift direction lrP, and the shift mask selector 602 that selects the selection result or all bit masks (ONE) based on the rotate flag rotP.
The zero mask control unit 304 uses the selection result of the shift mask selector 602 as a zero mask (ZMP), calculates a logical sum with the selection results of the P Mto1 selectors 302 by the AND circuit 305, and finally shifts the P bit barrel shifter Get (Out).

  FIG. 15 shows the configuration of the zero mask generation unit 600. Based on the subtractor 603 for calculating (P-swP) and the shift direction lrP of the P-bit barrel shifter, the zero mask generation unit 600 selects the shift amount swP of the P-bit barrel shifter when shifting left, and (P-swP) when shifting right ), A decoder 605 that performs decoding based on the selection result swZ, and a negation circuit 606 that inverts each bit of the decoding result LZM.

  The barrel shift apparatus according to the present embodiment includes the zero mask control unit 304 and the AND circuit 305, so that when the left-right logical shift across two or more N-bit barrel shifters is executed, 0 is added to the upper bit or the lower bit of the shift result. Can be inserted.

  Thus, when the barrel shift apparatus according to the present embodiment configures a P (= M × N) bit barrel shifter in which M N-bit barrel shifters are combined, the same results are obtained from the shift results of M N-bit barrel shifters. The Mto1 selector that selects bit position data or bit position data separated by N × R (M> R ≧ 1) bits is individually controlled according to the shift direction and the shift width swP. The input to the Mto1 selector that selects data at positions 1 to (N−1) bits apart at the boundary of M N-bit barrel shifters is different for M N-bit barrel shifters and P-bit barrel shifters, There is no need to add M × (N-1) 2to1 selectors.

  In addition, from the shift result of M N-bit barrel shifters, the selection signal of the Mto1 selector that selects the data at the same bit position or the data at the bit positions separated by N × R (M> R ≧ 1) bits is sent to The hardware cost for generating the select signal can be reduced by using the N-bit left zero mask, the N-bit right zero mask, and the N-bit left and right zero mask selector.

[Second Embodiment]
A second embodiment in which the present invention is suitably implemented will be described. FIG. 16 shows the configuration of the P-bit barrel shifter according to this embodiment. A P-bit barrel shifter 700 as a barrel shifter device combines a plurality of (M) N-bit barrel shifters 701 to realize a P (= M × N) bit barrel shifter with a wider bit width at a low cost.

  Here, the configuration shown in FIG. 16 is an example using M N-bit barrel shifters based on the left shift (the right shift is realized by applying the left shift), but the configuration based on the right shift. It may be.

  In this embodiment, by extending the zero mask control unit of M N-bit barrel shifters, it is possible to perform zero mask processing at the time of logical shift in the P-bit barrel shifter device according to the first embodiment shown in FIG. The zero mask control unit 304 and the P AND circuits 305 are reduced.

  The operation principle of the barrel shifter device according to this embodiment will be described by taking an 8-bit barrel shifter in which two 4-bit barrel shifters are combined as an example. In each of the 8-bit barrel shifter and the two 4-bit barrel shifters, the shift result when the abcdefgh 8-bit data is simply left / right logically shifted by 0 to 7 bits and the two 4-bit barrel shifters are combined. The shift results (combination results) are shown in FIGS.

  As can be seen from FIG. 17 and FIG. 18, the left and right logical shifts in the 8-bit barrel shifter do not coincide with each 4-bit barrel shifter simply by combining the left and right logical shifts. To match the result of the 8-bit barrel shifter combining two 4-bit barrel shifters with the result of the left / right logical shift in the 8-bit barrel shifter, the left / right logical shift results of the two 4-bit barrel shifters are shown in FIG. It is necessary to perform control so as to be as shown in FIG. 19 and 20 also show a zero mask used by the 4-bit barrel shifter at that time.

  In FIG. 19 at the time of left logical shift, when the shift amount is 3 (011) or less, only the left 4-bit barrel shifter performs left logical shift, and the right 4-bit barrel shifter performs control to perform left rotation. The 8-bit barrel shifter matches the left logical shift result of the combination result. When the shift amount is 4 (100) or more, control is performed so that all the bits of the result of the left 4-bit barrel shifter are 0, and the right 4-bit barrel shifter is controlled to perform the left logical shift. Thus, the 8-bit barrel shifter matches the left logical shift result of the combination result.

  In FIG. 20 at the time of right logical shift, when the shift amount is 3 (011) or less, only the right 4-bit barrel shifter performs right logical shift, and the left 4-bit barrel shifter performs control to perform right rotation. The 8-bit barrel shifter matches the right logical shift result of the combination result. When the shift amount is 4 (100) or more, control is performed so that all bits of the result of the right 4-bit barrel shifter become 0, and the left 4-bit barrel shifter is controlled to perform the right logical shift. Thus, the 8-bit barrel shifter matches the right logical shift result of the combination result.

  In the following description, the generalized P-bit barrel shifter 700 of FIG. 16 will be described based on the basic operation principle described with reference to FIGS.

  As shown in FIG. 16, the P-bit barrel shifter 700 includes an M number of N (powers of 2) bit barrel shifters 701, a P (= M × N) number of Mto1 selectors 702, and a P bit barrel shifter shift direction (lrP). And the shift amount control unit 703 that generates the select signals of the P Mto1 selectors 702 from the shift amount swP and the zero mask control unit of the N-bit barrel shifter 701 are expanded and controlled so that the P-bit barrel shifter And a zero mask extension unit 704 that realizes a logical shift. The N-bit barrel shifter 701 corresponds to the N-bit barrel shifter 1 in FIG. The P Mto1 selectors 702 correspond to the Mto1 selector 2 in FIG. Further, the shift amount control unit 703 corresponds to the shift amount control unit 3 in FIG.

  FIG. 21 shows an expanded zero mask control unit of the N-bit barrel shifter 701 in order to expand the zero mask control unit of the N-bit barrel shifter 701 and execute a logical shift in the P-bit barrel shifter 700.

  In the zero mask control unit 800 shown in FIG. 21, a selector group is added to the zero mask control unit 3012 of the N-bit barrel shifter shown in FIG. These added selector group control signals sel_lr, sel_sw, sel_lzm, and sel_rot are converted to a P-bit barrel shifter rotation flag (rotP), shift direction (lrP), shift amount (zero) by the zero mask extension unit 704 shown in FIG. Generate from swP).

  First, the configuration of the zero mask control unit 800 of the M N-bit barrel shifters shown in FIG. 21 will be described.

  As shown by the zero masks in FIGS. 19 and 20, in order to make the shift result of the M N-bit barrel shifters and the result of the P-bit barrel shift coincide with each other when the logical shift is executed, The zero mask (ZM) generated by the zero mask control unit 800 of each N-bit barrel shifter is selected from among all bits 1 (ONE), all bits 0 (ZERO), left zero mask (LZM), and right zero mask (RZM). The configuration specified in is required.

  First, in order to set the zero mask (ZM) to all bits 1 (ONE), the control signal of the selector 801 for designating the zero mask (ZM) to all bits 1 (ONE) during rotation is set to the rotate control signal (sel_rot). A selector 802 to be generated based on this is added, and when sel_rot is 1, all bits 1 (ONE) are set to zero mask (ZM). As a result, when the P-bit barrel shifter performs a logical shift, even if rot is 0, all bits 1 (ONE) can be selected as a zero mask (ZM).

  Next, in order to set the zero mask (ZM) to all bits 0 (ZERO), the shift direction control signal (sel_Lr) is set so that the left zero mask (LZM) generated by the zero mask generation unit 803 is 11. Based on the selector 804 that sets the shift direction to be input to the zero mask generation unit 803 to the left (1) and the shift amount input to the zero mask generation unit 803 based on the shift amount control signal (sel_sw). 111) and a selector 806 that selects 0 only for the most significant bit of the left zero mask (11... 000) generated by the zero mask generation unit 803 based on the left zero mask control signal (sel_lzm). The selection result of the selector 806 and the control signal of the selector 807 that selects the right zero mask are selected based on the shift direction control signal (sel_lr). To add a selector 808 for.

  Finally, in order to set the zero mask (ZM) to the left zero mask (LZM) or the right zero mask (RZM), the shift direction control signal (sel_lr) is 0, the shift amount control signal (sel_sw) is 0, and the rotate control signal ( This is realized by setting sel_rot) to 0 and the left zero mask control signal (sel_lzm) to 0.

  In FIG. 21, the left zero mask (LZM) is extended to set all bits to 0 (ZERO). However, the right zero mask (RZM) may be extended.

  In the following, the zero mask extension 704 in FIG. 16 that generates various control signals (sel_lr, sel_sw, sel_lzm, sel_rzm, sel_rot) in FIG. 21 from the rotation flag (rotP) and shift amount (swP) of the P-bit barrel shifter will be described. Details will be described.

  First, a configuration method of the zero mask extension unit 704 will be described using a 16-bit barrel shifter in which four 4-bit barrel shifters are combined as an example. FIG. 22 shows a shift result obtained by logically shifting the 16-bit data consisting of a to p by 0 to 16 bits to the left and the zero mask used by each 4-bit barrel shifter at that time.

  Referring to the zero mask shown in FIG. 22, the vertical line portion is all bits 1 (ONE), the shaded portion is all bits 0 (ZERO), and the other portions are left generated during normal left logical shift. It is a zero mask (LZM).

  Focusing on the zero mask of the lower third (leftmost) 4-bit barrel shifter in Fig. 22, the left zero mask (LZM) is selected when the lower third and second bits of the shift amount (sw [3: 2]) are 00 If sw [3: 2] is equal to or greater than 01, all bits 0 (ZERO) are selected.

  Focusing on the zero mask of the lower second 4-bit barrel shifter in FIG. 22, when the lower third and second bits (sw [3: 2]) of the shift amount are 00, all bits 1 (ONE) are selected and sw [ When 3: 2] is 01, the left zero mask (LZM) is selected, and when sw [3: 2] is 10 or more, all bits 0 (ZERO) are selected.

  Focusing on the zero mask of the lower first 4-bit barrel shifter in FIG. 22, when the lower third and second bits (sw [3: 2]) of the shift amount are 01 or less, all bits 1 (ONE) are selected and sw When [3: 2] is 10, the left zero mask (LZM) is selected, and when SW [3: 2] is 11, all bits 0 (ZERO) are selected.

  Looking at the zero mask of the lower 0th (rightmost) 4-bit barrel shifter in FIG. 22, when the lower 3rd and 2nd bits (sw [3: 2]) of the shift amount are 10 or less, all bits 1 (ONE) are set. If sw [3: 2] is 11, the left zero mask (LZM) is selected.

  To summarize the above, the zero mask of the lower B (M> B ≧ 0) 4-bit barrel shifter is based on the magnitude relationship between the lower third and second bits of the shift amount and B, all bits 1 (ONE), all bits It can be seen that 0 (ZERO) and the left zero mask (LZM) are selected.

  In general, when performing swP (P> swP ≧ 0) bit left logical shift, the zero mask of the lower B (M> B ≧ 0) th N-bit barrel shifter is (N × (MB−1))> swP , The rotation control signal (sel_rot) to the barrel shifter zero mask controller 800 is set to 1 so that all bits are 1 (ONE), and (N × (MB))> swP ≧ (N × (MB-1 )), The rotation control signal (sel_rot) to the zero shift control unit 800 of the barrel shifter is set to 0, the shift control signal (sel_sw) is set to 0, and the shift amount control direction control signal is set so that the left zero mask (LZM) is obtained. When (sel_lr) is set to 0, the left shift control signal (sel_lzm) is set to 0, and swP ≧ (N × (MB)), the zero shift control unit 800 of the barrel shifter is set so that all bits are 0 (ZERO). Rotation control signal (sel_rot) is set to 0, shift amount control signal (sel_sw) is set to 1, and shift direction control signal (sel_lr) is set to 1. Left shift control signal (sel_lzm) to the 1 constitutes a zero mask control unit 704.

  FIG. 23 shows a circuit configuration for realizing the above function. Shown is a circuit for controlling the zero mask control unit 800 of the lower B (M> B ≧ 0) th N-bit barrel shifter among the M N-bit barrel shifters, and the zero mask extension unit 704 includes M N-bit barrel shifters. In order to control the zero mask control unit of the bit barrel shifter, the circuit of FIG.

As shown in FIG. 23, to compare the magnitude relationship (large or equal: 0, small: 1) between the shift amount (swP) and (N × (MB-1)) or (N × (MB)). Subtracters 900 and 901, a selector 902 that selects f0 or 1 as a rotation control signal (sel_rot) based on the rotation flag (rotP) of the P-bit barrel shifter, and a negative logical product of magnitude relations (f0, f1) The AND circuit 903 to be calculated constitutes a set of circuits.
Here, since (N × (MB-1)) or (N × (MB)) is a constant for each zero mask control unit of each N-bit barrel shifter, it is calculated online by the zero mask extension unit 704 (one by one at the time of shift execution). No need to calculate).

  Next, a configuration method of the zero mask extension unit 704 will be described by taking as an example a case where 16-bit data composed of a to p is logically shifted by 0 to 16 bits to the right in a 16-bit barrel shifter in which four 4-bit barrel shifters are combined. FIG. 24 shows the result of the right logical shift and the zero mask used by each 4-bit barrel shifter at that time.

  Referring to the zero mask shown in FIG. 24, the vertical line part is all bits 1 (ONE) and the shaded part is 0 (ZERO), and the other part is a right zero mask (RZM generated during normal right logical shift). ).

  Focusing on the zero mask of the lower third (leftmost) 4-bit barrel shifter in FIG. 24, when the lower third and second bits (sw [3: 2]) of the shift amount are 11, the right zero mask is selected and sw When [3: 2] is 10 or less, all bits 1 (ONE) are selected.

  Paying attention to the zero mask of the lower second 4-bit barrel shifter in FIG. 24, when the lower third and second bits (sw [3: 2]) of the shift amount are 01 or less, all bits 1 (ONE) are selected and sw When [3: 2] is 10, the right zero mask (RZM) is selected, and when sw [3: 2] is 11, all bits 0 (ZERO) are selected.

  Focusing on the zero mask of the lower first 4-bit barrel shifter in FIG. 24, when the lower third and second bits (sw [3: 2]) of the shift amount are 00, all bits 1 (ONE) are selected and sw [ When 3: 2] is 01, the right zero mask (RZM) is selected, and when sw [3: 2] is 10 or more, all bits 0 (ZERO) are selected.

  Focusing on the zero mask of the lower 0th (rightmost) 4-bit barrel shifter in Fig. 24, if the lower 3rd and 2nd bits (sw [3: 2]) of the shift amount are 00, the right zero mask (RZM) is selected. If sw [3: 2] is equal to or greater than 01, all bits 0 (ZERO) are selected.

To summarize the above, the zero mask of the lower B (M> B ≧ 0) 4-bit barrel shifter is based on the magnitude relationship between the lower third and second bits of the shift amount and B, all bits 1 (ONE), all bits It can be seen that 0 (ZERO) and right zero mask (RZM) are selected.
In general, when swP (P> swP ≧ 0) bit right logical shift is performed, if the zero master of the lower B (M> B ≧ 0) th N-bit barrel shifter is (N × B)> swP Is set so that the rotation control signal (sel_rot) to the zero mask controller 800 of the barrel shifter is 1 so that all bits are 1 (ONE), and (N × (B + 1))> swP ≧ (N × B). Rotate control signal (sel_rot) to zero mask control unit 800 of the barrel shifter is set to 0, shift amount control signal (sel_sw) is set to 0, shift direction control signal (sel_lr) is set to 0 so that the right zero mask (RZM) is obtained. When the left shift control signal (sel_lzm) is 0 and swP ≧ (N × (B-1)), the rotation control signal (sel_rot to the zero master control unit 800 of the barrel shifter is set so that all bits are 0 (ZERO). ) To 0, shift amount control signal (sel_sw) to 1, shift direction control signal (sel_lr) to 1, left shift control signal (Sel_lzm) and to the 1, it may be configured to zero mask control unit 704.

  FIG. 25 shows a circuit configuration for realizing the above function. FIG. 25 shows a circuit for controlling the zero mask controller 800 of the lower B (M> B ≧ 0) -th N-bit barrel shifter among the M N-bit barrel shifters, and the left logical shift shown in FIG. The control circuit is expanded so that it can also be used for the right logic shift. Note that the zero mask extension unit 704 is configured to have M sets of the circuit of FIG. 25 in order to control the zero mask control units of M N-bit barrel shifters.

  As described above, the zero bit control unit of the N-bit barrel shifter is expanded as shown in FIG. 21, and the zero mask extension unit 704 as shown in FIG. 25 for controlling the zero mask control unit is used, so that the P bit barrel shifter shown in FIG. Thus, the zero mask control unit 304 and the P AND circuits 305 for performing the zero mask process at the time of logical shift in FIG.

  On the other hand, like the shift amount control unit 303 in FIG. 2, the shift amount control unit 703 in FIG. 16 extends one of the zero mask control units of the M N-bit barrel shifters as shown in FIG. Is used as the 0th bit of the control signals of the P Mto1 selectors 702 in FIG.

  Further, as shown in FIG. 13, by using the right zero mask (RZM) and the left zero mask (LZM) generated by the zero mask control unit, the control signals (H−1) ˜ of the control signals of the P Mto1 selectors 702 in FIG. This is used to generate the first bit. Here, H = [log2M].

  For this reason, the zero mask processing at the time of logic shift in the P bit barrel shifter by the extension of the zero mask control unit of the N bit barrel shifter and the generation of control signals for the P Mto1 selectors using one of the zero mask control units of the N bit barrel shifter Both use the zero mask (ZM) output from the zero mask control unit of the N-bit barrel shifter and the left and right zero masks (LZM, RZM), and therefore cannot be implemented simply in combination.

  Accordingly, paying attention to the generation pattern of the zero mask used at the time of the left / right logical shift shown in FIGS. 22 and 24, the zero mask control unit 800 of FIG. 21 is expanded as follows.

  When the left logical shift is performed, the lower 3rd to 1st 4-bit barrel shifter in FIG. 22 may select all bits 0 (ZERO) as a logical shift zero mask (ZM) depending on the shift amount. On the other hand, the lower 0th 4-bit barrel shifter does not select all bits 0 (ZERO) as a zero mask (ZM) for logical shift.

  The lower 0th 4-bit barrel shifter selects the left zero mask (LZM) or all bits 1 (ONE) as the zero mask (ZM) according to the shift amount. The selection of all bits 1 (ONE) is shown in FIG. Therefore, sel_sw, sel_lzm, and sel_lr may be set to 0 so that the output of the selector 807 becomes a left zero mask (LZM) regardless of the shift amount.

  By doing so, the left and right zero masks (LZM, RZM) desired by the shift amount control unit 703 are obtained from the zero mask generation unit 803 of FIG. 21 of the lower 0th 4-bit barrel shifter at the time of the left logical shift. Obtainable. Further, regardless of the shift amount, the left / right zero mask (LZM, RZM) selection result desired by the shift amount control unit 703 can be obtained from the selector 807 in FIG.

In order to realize this, the lower zeroth zero mask control unit of the M N barrel shifters is expanded as shown in FIG. As shown in FIG. 26, the selector 1100 and the negative exclusive OR 1101 are added to the zero mask controller shown in FIG. 21 in order to generate a desired zero mask by the shift amount controller 703. In addition, in order to obtain the desired left and right zero mask (LZM, RZM) selection result regardless of the shift amount, the output (SWZM) of the selector 1102 in FIG. 16 is used to generate the 0th bit of the control signal of the P Mto1 selectors 702 in FIG.
Add to the zero mask controller.

  Further, the left and right zero masks (LZM, RZM) generated by the zero mask generation unit 803 of the lower zeroth zero mask control unit are generated from the (H-1) to the first bit of the control signals of the P Mto1 selectors 702 in FIG. It is used for. Here, H = [log2M].

  When performing the right logical shift, the lower 2 to 0th 4-bit barrel shifter in FIG. 24 may select all bits 0 (ZERO) as a logical shift zero mask (ZM) depending on the shift amount. On the other hand, the lower third 4-bit barrel shifter does not select all bits 0 (ZERO) as a zero mask (ZM) for logical shift.

  The lower third 4-bit barrel shifter selects the right zero mask (RZM) or all bits 1 (ONE) as the zero mask (ZM) according to the shift amount. Therefore, sel_sw, sel_lzm, and sel_lr may be set to 0 so that the output of the selector 807 becomes a right zero mask (RZM) regardless of the shift amount.

  By doing so, the right and left zero masks (LZM, RZM) desired by the shift amount control unit 703 are obtained from the zero mask generation unit 803 of FIG. 21 of the lower 0th 4-bit barrel shifter at the time of the right logical shift. be able to. Furthermore, regardless of the shift amount, the selection result of the left and right zero masks (LZM, RZM) desired by the shift amount control unit 703 can be obtained from the selector 807 in FIG.

  In order to realize the above, the lower (M−1) th zero mask control unit of the M N-bit barrel shifters is expanded as shown in FIG. As shown in FIG. 26, in order to generate a desired zero mask by the shift amount control unit 703, a selector 1100 and a negative exclusive OR 1101 are added to the zero mask control unit shown in FIG. In addition, in order to obtain the desired left and right zero mask (LZM, RZM) selection result regardless of the shift amount, the output (SWZM) of the selector 1102 in FIG. 16 is used to generate the 0th bit of the control signal of the P Mto1 selectors 702 in FIG.

  Further, the left and right zero masks (LZM, RZM) generated by the zero mask generation unit 803 of the lower (M-1) th zero mask control unit are used as control signals (H-1) to 1 bit of the P Mto1 selectors 702 in FIG. It is used for eye generation. Here, H = [log2M].

  As described above, in the case of the left logical shift and the right logical shift, the zero mask (ZM) and the left and right zero masks (which can be used by the shift amount control unit 703 that generates the control signals of the P Mto1 selectors 702 in FIG. The N-bit barrel shifter that generates (LZM, RZM) is different. The lower 0th N-bit barrel shifter at the left logical shift, and the lower (M-1) th N-bit barrel shifter at the right logical shift.

  Therefore, the shift zero mask (SWZM) and the left and right zero masks (LZM, RZM) generated by the zero mask control unit of the lower (M-1) th N bit barrel shifter are selected according to the shift direction (lrP) of the P bit barrel shifter. A selector to be added is added to the zero mask control unit 703. Thereby, even during the logical shift, a desired shift zero mask (SWZM) can be provided to the shift amount control unit.

  In this way, each N-bit zero mask has a left / right zero mask and all N bits according to the shift width of the P-bit barrel shifter in a zero mask control unit that generates an N-bit zero mask for logical shift of M N-bit barrel shifters. Zero mask control for generating a P bit zero mask for a P bit barrel shifter by extending each M number of zero mask control units to 0 or all N bits 1 and providing a zero mask extension unit for controlling the zero mask control unit And P-bit AND circuits can be reduced.

  Each of the above embodiments is a preferred example of the present invention, and the present invention is not limited to these and can be variously modified.

It is a figure which shows the structure of the P bit barrel shifter which concerns on this invention. 1 shows a configuration of a P-bit barrel shifter according to a first embodiment in which the present invention is preferably implemented. It is a figure which shows the structure of an N bit barrel shifter. It is a figure which shows the structure of the zero mask control part of an N bit barrel shifter. It is a figure which shows the select signal utilized at the time of left rotation (shift) combining two 4-bit barrel shifters. It is a figure which shows the control signal of the 4to1 selector at the time of combining eight 8-bit barrel shifters and carrying out left rotation (shift). It is a figure which shows the right-and-left zero mask produced | generated at the time of left rotation (shift) with a 4-bit barrel shifter. It is a figure which shows the structure of the zero mask control part of the N bit barrel shifter applied to the P bit barrel shifter (only the left rotation (shift) is executed) according to the first embodiment. It is a figure which shows the structure of the shift amount control part applied to the P bit barrel shifter (only the left rotation (shift) is performed) which concerns on 1st Embodiment. It is a figure which shows the control signal of a 4to1 selector at the time of combining eight 8-bit barrel shifters and carrying out a right rotation (shift). It is a figure which shows the right-and-left zero mask produced | generated at the time of a right rotation (shift) with a 4-bit barrel shifter. It is a figure which shows the structure of the zero mask control part of the N bit barrel shifter applied to P bit barrel shifter (execution of right-and-left rotation (shift)) which concerns on 1st Embodiment. It is a figure which shows the structure of the shift amount control part applied to P bit barrel shifter (execution of right-and-left rotation (shift)) which concerns on 1st Embodiment. It is a figure which shows the structure of the zero mask control part applied to the P bit barrel shifter which concerns on 1st Embodiment. It is a figure which shows the structure of the zero mask production | generation part applied to the P bit barrel shifter which concerns on 1st Embodiment. It is a figure which shows the structure of the P bit barrel shifter which concerns on 2nd Embodiment which implemented this invention suitably. It is a figure which shows the result of having carried out the left logical shift simply by combining two 4-bit barrel shifters. It is a figure which shows the result of having carried out the right logic shift by simply combining two 4-bit barrel shifters. It is a figure which shows the left logical shift result of two 4-bit barrel shifters with which the P bit barrel shifter which concerns on 2nd Embodiment is provided. It is a figure which shows the right logical shift result of two 4-bit barrel shifters with which the P bit barrel shifter which concerns on 2nd Embodiment is provided. It is a figure which shows the structure of the zero mask control part of the N bit barrel shifter applied to the P bit barrel shifter which concerns on 2nd Embodiment. It is a figure which shows the result of having carried out the left logical shift combining 4 4-bit barrel shifters. It is a figure which shows the structure of the zero mask extension part applied to P bit barrel shifter (only the left logical shift is performed) concerning 2nd Embodiment. It is a figure which shows the result of having carried out the right logic shift combining 4 4-bit barrel shifters. It is a figure which shows the structure of the zero mask extension part applied to the P bit barrel shifter (execution of a left-right logical shift) concerning a 2nd embodiment. It is a figure which shows the structure of the zero mask control part of the N bit barrel shifter applied to the P bit barrel shifter which concerns on 2nd Embodiment. It is a figure which shows the structure of a 4-bit barrel shifter. It is a figure which shows the structure of the shift amount control part of a 4-bit barrel shifter. It is a figure which shows the structure of the zero mask control part of a 4-bit barrel shifter. It is a figure which shows the structure of the 8-bit barrel shifter which combined two 4-bit barrel shifters.

Explanation of symbols

1, 301, 701 N-bit barrel shifter 2, 302, 702 Mto1 selector 3, 103, 205, 303, 703, 3011 Shift amount control unit 10, 300, 700 P-bit barrel shifter 100, 201, 202 4-bit barrel shifter 101, 102, 3010 2to1 selector 104, 206, 304, 800, 803, 3012 Zero mask control unit 105, 600, 3014 Zero mask generation unit 106, 400, 500, 601, 807, 3015 Left and right zero mask selectors 107, 401, 501, 602, 801, 3016 One mask selector 108, 207, 305, 3013 AND circuit 200 8-bit barrel shifter 203, 204, 402, 502, 604, 802, 804, 805, 806, 808, 902, 903, 10 0,1001,1100,1101,1102 selector 403,504 T-bit input of the AND element 404,505 4-to-1 selector 503 negative exclusive 603,900,901 subtractor 605 decoder 606 NOT circuit 704 zero mask extension

Claims (11)

A barrel shifter device that performs barrel shift of P (= M × N) bits by combining M N (powers of 2) bit barrel shifters,
P Mto1 selectors,
A shift amount control unit that generates a select signal of each Mto1 selector based on a shift direction and a shift width;
The lower Kth Mto1 selector is connected to the lower (K mod N) bit shift result of M N-bit barrel shifters,
When the select signal of the lower K-th Mto1 selector generated by the shift amount control unit is L, the lower K-th Mto1 selector has the lower R (R = K / NL, K if K / N ≧ L, K When / N <L, the lower (K mod N) th shift result of the (R = K / N-L + M) th N-bit barrel shifter is selected, and the selection result of the lower Kth Mto1 selector is selected as P A barrel shifter device characterized in that a shift result of the lower K bits of the bit barrel shifter is used. Each of the N-bit barrel shifters
In addition to rotating in the horizontal direction, it is possible to perform a logical shift in the horizontal direction,
An N-bit zero mask generator for generating an N-bit left zero mask for left logical shift and an N-bit right zero mask for right logical shift;
An N-bit N-bit left and right zero mask selector for selecting the N-bit left zero mask and the N-bit right zero mask;
An N-bit N-bit shift mask selector that selects a selection result of the N-bit left and right zero mask selector and an N-bit one mask in which all bits for rotation in the left-right direction are 1.
2. The barrel shifter device according to claim 1, further comprising an N-bit AND circuit that generates a logical product of a selection result of the N-bit shift mask selector and a shift result of the N-bit barrel shifter. The shift amount control unit
Using the N-bit left zero mask, the N-bit right zero mask, and the N-bit left and right zero mask selector included in any of the N-bit barrel shifters, H (= [log2M], [log2M] of the lower K-th Mto1 selector is Generate a select signal consisting of (the largest integer not exceeding log2M) bits,
The lower 0th bit of the select signal of the lower Kth Mto1 selector when shifting the swP bit to the left is the lower Q of the shift amount swP (= [log2N], [log2N] is the largest integer not exceeding log2N) bits When the eye is 0, the lower (K mod N) bit of the N bit right zero mask selected using the N bit left and right zero mask selector is selected, and the lower Q bit of the shift amount swP is 1. In this case, the lower (K mod N) bit of the N bit left zero mask selected using the N bit left and right zero mask selector is selected,
When the lower K bit of the select signal of the lower K-th Mto1 selector when shifting the swP bit to the right is used, when the lower Q bit of the shift amount swP is 0, the N-bit left and right zero mask selector is used. When the lower (K mod N) bit of the selected N bit left zero mask is selected and the lower Q bit of the shift amount swP is 1, the N bit selected using the N bit left and right zero mask selector 3. The barrel shifter device according to claim 2, wherein the lower (K mod N) bit of the right zero mask is selected. All the bits from the lower Q bit to the lower (Q + T-1) bit of the shift amount swP are the lower T bits of the select signal of the lower K-th Mto1 selector when shifting the swP bits to the left If it is not 1 and the lower (Q + T) bit is 0, 0 is selected, and all the bits from the lower Q bit to the lower (Q + T-1) bit of the shift amount swP are 1 If the low-order (Q + T) bit is 1, the low-order (K mod N) bit of the N-bit right zero mask is selected, and the low-order (Q + T-1) When all the bits up to the 1st bit are 1 and the lower (Q + T) bit is 0, select 1, and from the lower Q bit of the shift amount swP, the lower (Q + T -1) When all the bits up to the first bit are 1 and the lower (Q + T) bit is 1, select the lower (K mod N) bit of the N bit left zero mask,
All the bits from the lower Q bit to the lower (Q + T-1) bit of the shift amount swP are 1 as the lower T bits of the select signal of the lower Kth Mto1 selector when shifting the swP bits to the right If the lower (Q + T) bit is 0, 0 is selected, and all the bits from the lower Q bit to the lower (Q + T-1) bit of the shift amount swP are 1 If the low-order (Q + T) bit is 1, the low-order (K mod N) bit of the N-bit left zero mask is selected, and the low-order (Q + T-1) If all the bits up to the 1st bit are 1 and the lower (Q + T) bit is 0, select 1 and select the lower (Q + T- 1) When all the bits up to the first bit are 1 and the lower (Q + T) bit is 1, the lower (K mod N) bit of the N bit right zero mask is selected. The barrel shifter device according to claim 3.   A P-bit zero mask generator for generating a P-bit left zero mask for left logical shift and a P-bit right zero mask for right logical shift; and a P-bit left and right zero mask selector for selecting the P-bit left zero mask and the P-bit right zero mask A P-bit P-bit shift mask selector that selects a selection result of the P-bit left and right zero mask selector and a P-bit one mask in which all the bits for rotation in the left-right direction are 1, and the P Mto1 selectors 5. A P-bit AND circuit that generates a logical product of an output and a selection result of the P-bit shift mask selector, and performs a logical shift in the left-right direction in addition to the rotate in the left-right direction. The barrel shifter apparatus of any one of Claims.   Each of the N bit barrel shifters includes a zero mask generation control signal selector that selects a control signal of the N bit zero mask generation unit so that at least one of the N bit left zero mask and the N bit right zero mask is all zero. Left and right zero mask control signal selector for selecting the control signal of the N bit left and right zero mask selector so as to select the N bit left zero mask or the N bit right zero mask whose all bits are 0, and a shift executed by each N bit barrel shifter 5. A shift mode selector that selects a shift mode that designates whether the rotation is a rotation or a logical shift, and a zero mask extension that generates the M zero mask control signals. The barrel shifter apparatus of any one of Claims. When performing A-bit left / right rotation, the zero mask extension unit controls the shift mode selector so that the shift mode of each N-bit barrel shifter is left / right rotation,
When an A-bit left logical shift is performed, if (N × (M−B−1))> A for the lower B-th N-bit barrel shifter, the shift mode is left rotate. Thus, when the zero mask extension controls the shift mode selector and (N × (MB))> A ≧ (N × (MB−1)), the shift mode is left logical shift. The zero mask extension unit controls the shift mode selector so that, when A ≧ (N × (MB)), the N bit zero mask generation unit of the lower Bth N bit barrel shifter The zero mask extension unit controls the zero mask generation control signal selector so that at least one of at least one of the N bit left zero mask and the N bit right zero mask to be generated becomes 0, and the N bit left and right set Kuta is to select the N-bit left zero mask or said N-bit right zero mask is all zero, the zero mask expansion unit controls the left and right zero mask control signal selector,
When performing an A-bit right logical shift, if (N × B)> A with respect to the lower B-th N-bit barrel shifter, the zero mask extension is set so that the shift mode is right rotate. If the shift mode selector is controlled and (N × (B + 1))> A ≧ (N × B), the zero mask extension unit controls the shift mode selector so that the shift mode is a right logical shift. , A ≧ (N × (B + 1)), at least one of the N-bit left zero mask and the N-bit right zero mask generated by the N-bit zero mask generation unit of the lower B-th N-bit barrel shifter is A P-bit zero mask control unit controls the zero mask generation control signal selector so that all bits become zero, and the N bit left zero mask and the N bit right zero mask are controlled. The zero mask extension unit controls the zero mask generation control signal selector so that at least one of all the bits of the N bit is zero, and the N bit left and right zero mask selector 7. The barrel shifter according to claim 6, wherein the zero mask extension unit controls the left and right zero mask control signal selectors so as to select an N-bit right zero mask. The shift amount control unit
When the left logical shift is executed, the selection result of the N-bit left zero mask, the N-bit right zero mask, and the N-bit left and right zero mask of the lower 0th N-bit barrel shifter is used to combine the N-bit barrel shifter with the P-bit barrel shifter. Realize logical shift,
When executing the right logical shift, the N bit barrel shifter is combined using the N bit left mask, the N bit right zero mask, and the N bit left and right zero mask selection results of the lower (M-1) th N bit barrel shifter. 8. The barrel shifter device according to claim 7, wherein a logical shift of the P-bit barrel shifter is realized. A barrel shift method for performing barrel shift of P (= M × N) bits by combining M N (power of 2) bit barrel shifters,
The shift result of the lower (K mod N) bits of the M N-bit barrel shifters is connected to the lower K-th selector among the P Mto1 selectors,
When the select signal of the lower Kth Mto1 selector generated based on the shift direction and the shift width is L, the lower Kth Mto1 selector selects the lower R (if K / N ≧ L, R = K / When NL, K / N <L, R = K / N-L + M) Selects the lower (K mod N) th shift result of the Nth bit shifter and shifts the lower Kth Mto1 selector Is a result of shifting the lower K bits of the P-bit barrel shifter. An N-bit left zero mask for left logical shift, an N-bit right zero mask for right logical shift, an N-bit left and right zero mask selector for selecting the N-bit left zero mask and the N-bit right zero mask, which are included in any of the N-bit barrel shifters; Is used to generate a select signal consisting of the H (= [log2M]) bits of the lower K-th Mto1 selector,
The lower 0 bit of the select signal of the lower Kth Mto1 selector when shifting the swP bit to the left is the N bit when the lower Q (= [log2N]) bit of the shift amount swP is 0. When the lower (K mod N) bit of the N bit right zero mask selected using the left and right zero mask selector is selected and the lower Q bit of the shift amount swP is 1, the N bit left and right zero mask selector is used. Selecting the lower (K mod N) bit of the N bit left zero mask selected in

When the lower K bit of the select signal of the lower K-th Mto1 selector when shifting the swP bit to the right is used, when the lower Q bit of the shift amount swP is 0, the N-bit left and right zero mask selector is used. When the lower (K mod N) bit of the selected N bit left zero mask is selected and the lower Q bit of the shift amount swP is 1, the N bit selected using the N bit left and right zero mask selector 10. The barrel shift method according to claim 9, wherein the lower (K mod N) bit of the right zero mask is selected. All the bits from the lower Q bit to the lower (Q + T-1) bit of the shift amount swP are the lower T bits of the select signal of the lower K-th Mto1 selector when shifting the swP bits to the left If it is not 1 and the lower (Q + T) bit is 0, 0 is selected, and all the bits from the lower Q bit to the lower (Q + T-1) bit of the shift amount swP are 1 If the low-order (Q + T) bit is 1, the low-order (K mod N) bit of the N-bit right zero mask is selected, and the low-order (Q + T-1) When all the bits up to the 1st bit are 1 and the lower (Q + T) bit is 0, select 1, and from the lower Q bit of the shift amount swP, the lower (Q + T -1) When all the bits up to the first bit are 1 and the lower (Q + T) bit is 1, select the lower (K mod N) bit of the N bit left zero mask,
All the bits from the lower Q bit to the lower (Q + T-1) bit of the shift amount swP are 1 as the lower T bits of the select signal of the lower Kth Mto1 selector when shifting the swP bits to the right If the lower (Q + T) bit is 0, 0 is selected, and all the bits from the lower Q bit to the lower (Q + T-1) bit of the shift amount swP are 1 If the low-order (Q + T) bit is 1, the low-order (K mod N) bit of the N-bit left zero mask is selected, and the low-order (Q + T-1) If all the bits up to the 1st bit are 1 and the lower (Q + T) bit is 0, select 1 and select the lower (Q + T- 1) When all the bits up to the first bit are 1 and the lower (Q + T) bit is 1, the lower (K mod N) bit of the N bit right zero mask is selected. The barrel shift method according to claim 10.

Images