JP2006338684A - Processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a processor which executes an SIMD operation with high flexibility with less constraints regarding a position of an operand to be an object for the SIMD operation. <P>SOLUTION: The processor has a decoding part 20 and an operation part 40, etc., when the decode part 20 decodes instructions "vhaddh Rc, Ra, Rb", an arithmetic logic/comparison arithmetic unit 41, etc. (i) add high-order 16 bits of a register Ra to high-order 16 bits of a register Rb, store the result in high-order 16 bits of a register Rc, in parallel with this, (ii) add low-order 16 bits of the register Ra to the high-order 16 bits of the register Rb and store the result in low-order 16 bits of the register Rc. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a processor such as a DSP or a CPU, and more particularly to a processor that executes SIMD type instructions.

  Conventionally, as processors that support SIMD (Single Instruction Multiple Data) type instructions, there are Pentium (registered trademark) / III // 4 MMX / SSE / SSE2 of Intel Corporation.

  For example, in the case of MMX, the same operation can be executed with one instruction for up to eight integers stored in a 64-bit MMX register.

  However, the conventional processor as described above has a problem that there are many restrictions on the position of the operand to be subjected to the SIMD operation.

  For example, in a state in which numerical values A and B are stored in the upper and lower digits of the first register and numerical values C and D are stored in the upper and lower digits of the second register, respectively, When a conventional processor executes a SIMD type addition instruction with オ ペ ラ ン ド as an operand, the obtained addition values are A + C and B + D. In other words, an addition value between the data stored in the upper digits of both registers and an addition value between the data stored in the lower digits of both registers are obtained, and the operation target is uniquely determined by the data storage position in the registers. Will be decided.

  Therefore, for example, when it is desired to obtain addition values of A + D and B + C for the first register and the second register as described above, the upper digit data and the lower digit data stored in one register are obtained. Execute SIMD type addition instruction after changing data storage location, or execute normal SISD (Single Instruction Single Data) type addition instruction twice without using SIMD type addition instruction There is a need to.

  By the way, with the recent digitalization of communication, in the field of image processing and sound processing that require digital signal processing such as Fourier transform and filter processing, it is necessary to perform the same arithmetic processing on a plurality of data. However, in that case, for example, there are many cases where a process such as performing the same operation on data located symmetrically from the center position in the data arrangement is required. In such a case, the two types of operands to be operated are arranged in reverse order, for example, data stored in one upper digit and data stored in the other lower digit in two registers. You have to do the operation.

  However, in the SIMD calculation by the conventional processor, as described above, the operands to be calculated need to be arranged in the same order. Therefore, the operands need to be rearranged, which is often used for digital signal processing. There is a problem that it takes a long time.

  Therefore, the present invention has been made in view of such a situation, and an object of the present invention is to provide a processor that executes a highly flexible SIMD operation with few restrictions on the position of an operand to be subjected to SIMD operation. To do. More specifically, for example, an object of the present invention is to provide a processor suitable for multimedia use that executes digital signal processing at high speed.

  In order to achieve the above object, a processor according to the present invention is a processor that executes a SIMD type instruction that calculates a plurality of data with one instruction, and includes a decoding means for decoding the instruction, and a decoding result by the decoding means And an execution means for executing an instruction, wherein the execution means specifies a first data group consisting of an instruction code for specifying the type of operation and a sequence of n (≧ 2) pieces of data. And a second operand designating a second data group consisting of a sequence of n data, when the SIMD type instruction is decoded by the decoding means, the n data constituting the first data group An operation specified by the instruction code for each of n sets of the i-th data in the sequence and the j-th data in the sequence of n data constituting the second data group. Was carried out, the i = 1, 2, ..., n, wherein said a j = constant.

  For example, the n is 2, the first data group is composed of first data and second data, the second data group is composed of first data and second data, The execution means performs the calculation on a set of the first data of the first data group and the first data of the second data group, and the second data and second of the first data group. The calculation is performed on a set of the data group and the first data.

  Here, the type of operation specified by the instruction code is multiplication, product-sum or product-difference, and the instruction includes a third operand that specifies third data for storing the result of the operation. The means may store the lower part or the upper part of each result obtained by performing the calculation on the two sets in the third data.

  Further, for example, the n is 4, the first data group is composed of a sequence of first to fourth data, and the second data group is composed of a sequence of first to fourth data, The execution means includes a set of the first data of the first data group and the first data of the second data group, the second data of the first data group and the first data of the second data group, A set of the third data of the first data group and the first data of the second data group, and the fourth data of the first data group and the first data of the second data group, The above operation is performed on a set of

  Here, the type of operation specified by the instruction code is multiplication, product-sum or product-difference, and the instruction includes a third operand that specifies third data for storing the result of the operation. The means may store the lower part or the upper part of each result obtained by performing the calculation on the four sets in the third data.

  The present invention can be realized not only as a processor that executes such characteristic instructions, but also as an arithmetic processing method for a plurality of data or the like, or as a program including characteristic instructions. You can also Needless to say, such a program can be distributed via a recording medium such as a CD-ROM or a transmission medium such as the Internet.

  The processor according to the present invention is a processor that executes a SIMD type instruction that calculates a plurality of data with one instruction, and not only two pieces of data in the same order but also one data row with respect to two data rows. The calculation is executed in parallel on the data set having the same calculation target (fixed position). Therefore, the calculation with a common data element is repeated for a plurality of data elements, but the processing speed is increased and a processor suitable for multimedia processing or the like is realized.

  Here, when the type of operation is multiplication, sum of products or product difference, only the lower part of each obtained operation result is output, only the upper part is output, or only part of the operation results are output. It may be output. As a result, in the inner product of complex numbers, etc., the bit cut-out processing required when handling integer data or fixed-point data is executed together with the calculation, so that an operation using two-dimensional data such as a complex number, for example, two-dimensional Image processing using coordinates, audio signal processing using a two-dimensional representation of amplitude and phase, and the like are accelerated.

  As described above, the processor according to the present invention has higher parallelism than ordinary microcomputers, high-speed AV media signal processing, and a common core processor for mobile phones, mobile AV devices, digital TVs, DVDs, and the like. It can be said that the practical value is extremely high today when the appearance of high performance and high cost performance multimedia equipment is desired.

  The architecture of the processor according to the present invention will be described. The instructions of this processor have higher parallelism than ordinary microcomputers, and are general-purpose processors developed for the AV media signal processing technology field. By using a common core for mobile phones, mobile AV devices, digital TVs, DVDs, etc., software reusability can be improved. In addition, this processor can realize a lot of media processing with high performance and high cost performance, and provides a high-level language development environment for the purpose of improving development efficiency.

  FIG. 1 is a schematic block diagram of the processor. The processor 1 includes an instruction control unit 10, a decoding unit 20, a register file 30, a calculation unit 40, an I / F unit 50, an instruction memory unit 60, a data memory unit 70, an expansion register unit 80, and an I / O interface unit 90. Composed. The arithmetic unit 40 includes arithmetic logic / comparison arithmetic units 41 to 43 for executing arithmetic operations of SIMD type instructions, a multiplication / product-sum arithmetic unit 44, a barrel shifter 45, a divider 46 and a converter 47. The multiplication / product-sum calculator 44 accumulates up to 65 bits so as not to degrade the bit precision. Further, the multiplication / product-sum operation unit 44 can execute SIMD type instructions similarly to the arithmetic logic / comparison operation units 41 to 43. Further, the processor 1 can execute a maximum of three arithmetic logic / comparison operation instructions in parallel.

  FIG. 2 shows a schematic diagram of the arithmetic logic / comparison arithmetic units 41-43. Each of the arithmetic logic / comparison arithmetic units 41 to 43 includes an ALU unit 41a, a saturation processing unit 41b, and a flag unit 41c. The ALU unit 41a includes an arithmetic operation unit, a logical operation unit, a comparator, and a TST unit. The corresponding arithmetic data has a bit width of 8 bits (4 arithmetic units are used in parallel), 16 bits (2 arithmetic units are used in parallel), and 32 bits (32-bit data processing in all arithmetic units). Further, for the arithmetic operation result, overflow detection and condition flag generation are performed by the flag unit 41c and the like. The arithmetic unit, the comparator, and the TST unit are subjected to arithmetic right shift, saturation by the saturation processing unit 41b, maximum / minimum value detection, and absolute value generation processing.

  FIG. 3 is a block diagram showing the configuration of the barrel shifter 45. The barrel shifter 45 includes selectors 45a and 45b, an upper barrel shifter 45c, a lower barrel shifter 45d, and a saturation processing unit 45e, and executes an arithmetic shift (shift of 2's complement system) or logical shift (unsigned shift) of data. Normally, 32-bit or 64-bit data is input / output. For the data to be shifted stored in the registers 30a and 30b, the shift amount is designated by another register or an immediate value. The data is arithmetically or logically shifted from the left 63 bits to the right 63 bits and output with an input bit length.

  In addition, the barrel shifter 45 can shift 8, 16, 32, and 64-bit data with respect to the SIMD type instruction. For example, a shift of 8-bit data can be processed in 4 parallel.

  Arithmetic shift is a shift of 2's complement system, and alignment of decimal point at the time of addition or subtraction, multiplication by power of 2 (2, 2 squared, 2 (-1) power, 2 (-2) Etc.) etc.

  FIG. 4 is a block diagram showing the configuration of the converter 47. The converter 47 includes a saturation block (SAT) 47a, a BSEQ block 47b, an MSKGEN block 47c, a VSUMB block 47, a BCNT block 47e, and an IL block 47f.

  The saturation block (SAT) 47a performs saturation processing on the input data. By having two blocks that saturate 32-bit data, two parallel SIMD instructions are supported.

The BSEQ block 47b counts consecutive 0s or 1s from the MSB.
The MSKGEN block 47c outputs the designated bit interval as 1, and outputs the other as 0.

  The VSUMB block 47d divides input data into designated bit widths and outputs the sum.

The BCNT block 47e counts the number of bits that are 1 in the input data.
The IL block 47f divides the input data into a designated bit width and outputs a value obtained by replacing each data block.

  FIG. 5 is a block diagram showing a configuration of the divider 46. The divider 46 sets the dividend to 64 bits and the divisor to 32 bits, and outputs the quotient and the remainder each 32 bits. 34 cycles are required to find the quotient and the remainder. Both signed and unsigned data can be handled. However, the setting of the presence / absence of a sign is common to the dividend and the divisor. In addition, it has a function of outputting an overflow flag and a division by zero flag.

  FIG. 6 is a block diagram showing a configuration of the multiplication / product-sum calculator 44. The multiplier / product-sum calculator 44 includes two 32-bit multipliers (MUL) 44a and 44b, three 64-bit adders (Adder) 44c to 44e, a selector 44f, and a saturation processing unit (Saturation) 44g. Multiply and multiply and accumulate.

32 × 32 bit signed multiplication, product sum, product difference operation 32 × 32 bit unsigned multiplication 16 × 16 bit 2 parallel signed multiplication, product sum, product difference operation 32 × 16 bit 2 parallel signed multiplication, product sum, product difference operation

  These operations are performed on data in integer and fixed-point format (h1, h2, w1, w2). Also, rounding and saturation are performed for these operations.

  FIG. 7 is a block diagram illustrating a configuration of the instruction control unit 10. The instruction control unit 10 includes an instruction cache 10a, an address management unit 10b, instruction buffers 10c to 10e, a jump buffer 10f, and a rotation unit (rotation) 10g, and supplies instructions at normal time and branch time. By having three 128-bit instruction buffers (instruction buffers 10c to 10e), the maximum number of parallel executions is supported. Regarding branch processing, a branch destination address is stored in advance in a TAR register, which will be described later, via the jump buffer 10f or the like before branch execution (settar instruction). Branch is performed using the branch destination address stored in the TAR register.

  The processor 1 is a processor having a VLIW architecture. Here, the VLIW architecture is an architecture that stores a plurality of instructions (load, store, operation, branch, etc.) in one instruction word and executes them all at the same time. The programmer can process the issue groups in parallel by describing instructions that can be executed in parallel as one issue group. In this specification, the issue group delimiters are indicated by “;;”. A notation example is shown below.

(Example 1)
mov r1, 0x23 ;;

  This instruction description means that only the instruction mov is executed.

(Example 2)
mov r1, 0x38
add r0, r1, r2
sub r3, r1, r2 ;;

  These instruction descriptions mean that instructions mov, add, and sub are executed in parallel.

  The instruction control unit 10 identifies the issue group and sends it to the decoding unit 20. The decoding unit 20 analyzes the instruction of the issuing group and controls necessary resources.

Next, the registers included in the processor 1 will be described.
The register set of the processor 1 is as shown in Table 1 below.

  The flag set of the processor 1 (flags managed by a condition flag register or the like described later) is as shown in Table 2 below.

  FIG. 8 is a diagram illustrating the structure of the general-purpose registers (R0 to R31) 30a. The general-purpose registers (R0 to R31) 30a constitute a part of the context of the task to be executed and are a 32-bit register group for storing data or addresses. The general-purpose registers R30 and R31 are used by hardware as a global pointer and a stack pointer, respectively.

  FIG. 9 is a diagram illustrating the structure of the link register (LR) 30c. In connection with the link register (LR) 30c, the processor 1 also includes a save register (SVR) not shown. The link register (LR) 30c is a 32-bit register that stores a return address at the time of a function call. The save register (SVR) is a 16-bit register that saves the condition flag (CFR.CF) of the condition flag register at the time of function call. The link register (LR) 30c is also used for increasing the loop speed, similarly to a branch register (TAR) described later. The lower 1 bit is always read as 0, but 0 must be written when writing.

  For example, when the call (brl, jmpl) instruction is executed, the processor 1 returns the address to the link register (LR) 30c and saves the condition flag (CFR.CF) to the save register (SVR). . When the jmp instruction is executed, the return address (branch destination address) is extracted from the link register (LR) 30c, and the program counter (PC) is restored. Further, when the ret (jmpr) instruction is executed, the branch destination address (return address) is extracted from the link register (LR) 30c and stored (returned) in the program counter (PC). Further, the condition flag is extracted from the save register (SVR) and stored (returned) in the condition flag area CFR.CF of the condition flag register (CFR) 32.

  FIG. 10 is a diagram showing the structure of the branch register (TAR) 30d. The branch register (TAR) 30d is a 32-bit register that stores a branch target address. Mainly used to speed up loops. The lower 1 bit is always read as 0, but 0 must be written when writing.

  For example, when a jmp, jloop instruction is executed, the processor 1 extracts the branch destination address from the branch register (TAR) 30d and stores it in the program counter (PC). When the instruction at the address stored in the branch register (TAR) 30d is stored in the branch instruction buffer, the branch penalty is zero. By storing the top address of the loop in the branch register (TAR) 30d, the speed of the loop can be increased.

  FIG. 11 is a diagram showing the structure of the program status register (PSR) 31. The program status register (PSR) 31 is a 32-bit register that constitutes a part of the context of the task to be executed and stores the processor status information shown below.

  Bit SWE: indicates an LP (Logical Processor) switching enable of VMP (Virtual Multi-Processor). “0” indicates that LP switching is not permitted, and “1” indicates that LP switching is permitted.

  Bit FXP: indicates a fixed point mode. “0” indicates mode 0, and “1” indicates mode 1.

  Bit IH: This is an interrupt processing flag and indicates that maskable interrupt processing is in progress. “1” indicates that interrupt processing is in progress, and “0” indicates that interrupt processing is not in progress. Set automatically when an interrupt occurs. It is used to determine whether the place where the rti instruction has returned from the interrupt is processing another interrupt or program.

  Bit EH: a flag indicating that an error or NMI is being processed. “0” indicates that an error / NMI interrupt is not being processed, and “1” indicates that an error / NMI interrupt is being processed. When EH = 1, if an asynchronous error or NMI occurs, it is masked. When VMP is enabled, VMP plate switching is masked.

  Bit PL [1: 0]: indicates a privilege level. “00” indicates privilege level 0, that is, processor abstraction level, “01” indicates privilege level 1 (cannot be set), “10” indicates privilege level 2, that is, system program level, and “11” indicates Indicates privilege level 3, that is, the user program level.

  Bit LPIE3: indicates LP specific interrupt 3 enable. “1” indicates interrupt permission, and “0” indicates interrupt disapproval.

  Bit LPIE2: indicates LP specific interrupt 2 enable. “1” indicates interrupt permission, and “0” indicates interrupt disapproval.

  Bit LPIE1: Indicates LP specific interrupt 1 enable. “1” indicates interrupt permission, and “0” indicates interrupt disapproval.

  Bit LPIE0: indicates LP specific interrupt 0 enable. “1” indicates interrupt permission, and “0” indicates interrupt disapproval.

  Bit AEE: indicates misalignment exception enable. “1” indicates that misalignment exception is permitted, and “0” indicates that misalignment exception is not permitted.

  Bit IE indicates level interrupt enable. “1” indicates that a level interrupt is permitted, and “0” indicates that a level interrupt is not permitted.

  Bit IM [7: 0]: indicates an interrupt mask. Levels 0-7 are defined and can be masked at individual levels. Level 0 is the highest level. Only the interrupt request having the highest level among the interrupt requests not masked by the IM is accepted by the processor 1. When an interrupt request is accepted, the level below the accepted level is automatically masked by hardware. IM [0] is a level 0 mask, IM [1] is a level 1 mask, IM [2] is a level 2 mask, IM [3] is a level 3 mask, and IM [ 4] is a level 4 mask, IM [5] is a level 5 mask, IM [6] is a level 6 mask, and IM [7] is a level 7 mask.

  reserved: Indicates a reserved bit. 0 is always read. When writing, it is necessary to write 0.

  FIG. 12 is a diagram showing the structure of the condition flag register (CFR) 32. The condition flag register (CFR) 32 is a 32-bit register that constitutes a part of the context of the task to be executed, and includes a condition flag (condition flag), an operation flag (operation flag), and a vector condition flag (vector). Condition flag), a bit position designation field for operation instructions, and a SIMD data alignment information field.

  Bit ALN [1: 0]: indicates an alignment mode. Sets the alignment mode of the valnvc instruction.

  Bit BPO [4: 0]: indicates a bit position. Used in instructions that require bit position specification.

  Bits VC0 to VC3: Vector condition flags. The LSB side byte or halfword sequentially corresponds to VC0, and the MSB side corresponds to VC3.

  Bit OVS: an overflow flag (summary). Set when saturation occurs or overflow is detected. If not detected, the value before instruction execution is held. Clearing must be done by software.

  Bit CAS: carry flag (summary). Set when a carry occurs with the addc instruction or a borrow occurs with the subc instruction. If no carry occurs with the addc instruction or a borrow does not occur with the subc instruction, the value before the instruction execution is retained. Clearing must be done by software.

  Bits C0 to C7: Condition flags. The value of the flag C7 is always 1. Reflecting the FALSE condition (writing 0) to the flag C7 is ignored.

  reserved: Indicates a reserved bit. 0 is always read. When writing, it is necessary to write 0.

  FIG. 13 is a diagram showing the structure of the accumulator (M0, M1) 30b. This accumulator (M0, M1) 30b constitutes a part of the context of the task to be executed, and is a 32-bit register MH0-MH1 (multiplication / multiplication / sum of products register (high order) shown in FIG. 13 (a). 32 bits)) and the 32-bit register ML0-ML1 multiplication / division / product-sum register (lower 32 bits) shown in FIG. 13 (b).

  Registers MH0-MH are used to store the upper 32 bits of the result in multiply instructions. In the product-sum instruction, it is used as the upper 32 bits of the accumulator. Further, when handling a bit stream, it can be used in combination with a general-purpose register. Registers ML0-ML1 are used in the multiply instruction to store the lower 32 bits of the result. In the product-sum instruction, it is used as the lower 32 bits of the accumulator.

  FIG. 14 is a diagram showing the structure of the program counter (PC) 33. This program counter (PC) 33 is a 32-bit counter that constitutes a part of the context of the task to be executed and holds the address of the instruction being executed. 0 is always stored in the lower 1 bit.

  FIG. 15 is a diagram showing the structure of the PC save register (IPC) 34. The PC save register (IPC) 34 is a 32-bit register that constitutes a part of the context of the task to be executed. The lower 1 bit is always read as 0, but 0 must be written when writing. There is.

  FIG. 16 is a diagram showing the structure of the PSR save register (IPSR) 35. The PSR save register (IPSR) 35 is a 32-bit register that constitutes a part of the context of the task to be executed and saves the program status register (PSR) 31. 0 is always read out from the portion corresponding to the reserved bit of (PSR) 31, but it is necessary to write 0 when writing.

  Next, the memory space of the processor 1 will be described. In the processor 1, a 4 GB linear memory space is divided into 32, and an instruction SRAM (Static RAM) and a data SRAM are allocated to a 128 MB unit space. With this 128 MB space as one block, a block to be accessed in the SAR (SRAM Area Register) is set. When the accessed address is a space set by the SAR, the instruction SRAM / data SRAM is directly accessed. When the accessed address is not the space set by the SAR, an access request is sent to the bus controller (BCU). Take out. An on-chip memory (OCM), an external memory, an external device, an I / O port, and the like are connected to the BCU, and reading and writing can be performed on these devices.

  FIG. 17 is a timing chart showing the pipeline operation of the processor 1. As shown in the figure, the processor 1 basically includes a five-stage pipeline of instruction fetch, instruction allocation (dispatch), decode, execution, and write.

  FIG. 18 is a timing chart showing each pipeline operation when an instruction is executed by the processor 1. In the instruction fetch stage, the instruction memory at the address specified by the program counter (PC) 33 is accessed, and the instruction is transferred to the instruction buffers 10c to 10e and the like. In the instruction allocation stage, branch destination address information is output to a branch system instruction, an input register control signal is output, a variable length instruction is allocated, and the instruction is transferred to an instruction register (IR). In the decode stage, IR is input to the decode unit 20 and an arithmetic unit control signal and a memory access signal are output. In the execution stage, the operation is executed, and the operation result is output to the data memory or the general-purpose register (R0 to R31) 30a. In the write stage, data transfer and operation results are stored in general purpose registers.

  The processor 1 can perform the above-described processing in a maximum of three in parallel using the VLIW architecture. Therefore, the processor 1 executes the operations shown in FIG. 18 in parallel at the timing shown in FIG.

Next, the instruction set of the processor 1 configured as described above will be described.
Tables 3 to 5 below are tables in which instructions executed by the processor 1 are classified by category.

  Note that “operator” in the table indicates an arithmetic unit used by the instruction. The meaning of the abbreviation of the arithmetic unit is as follows. That is, “A” is an ALU instruction, “B” is a branch instruction, “C” is a conversion instruction, “DIV” is a division instruction, “DBGM” is a debug instruction, “M” is a memory access instruction, “S1”, “ “S2” means a shift instruction, and “X1” and “X2” mean a multiplication instruction.

  FIG. 20 is a diagram showing a format of instructions executed by the processor 1. The formats include a 16-bit instruction format shown in FIG. 20A and a 32-bit instruction format shown in FIG.

  In addition, the meaning of the symbol in the figure is as follows. That is, “E” is an end bit (parallel execution boundary), “F” is a format bit (00, 01, 10:16 bit instruction format, 11:32 bit instruction format), and “P” is a predicate (execution condition: "OP" means an operation code field, "R" means a register field, "I" means an immediate field, and "D" a displacement field. Note that the “E” field is unique to VLIW, and an instruction with E = 0 is executed in parallel with the next instruction. That is, a VLIW having a variable parallelism is realized by the “E” field.

  FIG. 21 to FIG. 36 are diagrams for explaining the schematic functions of the instructions executed by the processor 1. That is, FIG. 21 is a diagram for explaining instructions belonging to the category “ALUadd (addition) system”, FIG. 22 is a diagram for explaining instructions belonging to the category “ALUsub (subtraction) system”, and FIG. FIG. 24 is a diagram illustrating instructions belonging to the category “ALUlogic (logical operation) system, etc.”, FIG. 24 is a diagram illustrating instructions belonging to the category “CMP (comparison operation) system”, and FIG. FIG. 26 is a diagram illustrating instructions belonging to the category “mac (product-sum operation) system”, and FIG. 27 is a category “msu (product-difference operation)”. FIG. 28 is a diagram illustrating instructions belonging to the category “MEMld (memory read) system”, and FIG. 29 is a category “MEMstore (memory write) system”. Diagram explaining the instruction to which it belongs FIG. 30 is a diagram for explaining instructions belonging to the category “BRA (branch) system”, and FIG. 31 is a diagram for explaining instructions belonging to the category “BSasl (arithmetic barrel shift) system, etc.” 32 is a diagram for explaining instructions belonging to the category “BSlsr (logical barrel shift) system, etc.”, FIG. 33 is a diagram for explaining instructions belonging to the category “CNVvaln (arithmetic conversion) system”, and FIG. FIG. 35 is a diagram illustrating instructions belonging to the category “SATvlpk (saturation processing) system”, and FIG. 36 is a diagram illustrating the category “ETC”. It is a figure explaining the command which belongs to (other) type | system | group.

  In these figures, item “SIMD” indicates the type of instruction (distinguishing between SISD (SINGLE) and SIMD), item “size” indicates the size of each operand to be operated, and item “SIMD” "Instruction" indicates the opcode of the instruction, item "operand" indicates the operand of the instruction, item "CFR" indicates a change in the condition flag register, and item "PSR" indicates a change in the processor status register The item “representative operation” indicates an outline of the operation, the item “operation unit” indicates the operation unit to be used, and the item “3116” indicates the size of the instruction.

  37 to 748 are diagrams illustrating detailed functions of instructions executed by the processor 1. The meanings of various symbols used in the description of the instructions are as shown in Tables 6 to 10 below.

FIG. 37 to FIG. 119 are diagrams for explaining a command related to “load”.
120 to 184 are diagrams for explaining a “store” related command.
FIG. 185 to FIG. 186 are diagrams for explaining instructions related to “memory (etc)”.
FIG. 187 to FIG. 206 are diagrams for explaining instructions related to “external register”.
FIG. 207 to FIG. 247 are diagrams for explaining “branch” related instructions.
FIG. 248 to FIG. 264 are diagrams for explaining commands related to “VMP / interupt”.
265 to 258 are diagrams for explaining instructions related to “program interrupt”.
FIG. 259 to FIG. 303 are diagrams for explaining “arithmetic” related instructions.
304 to 317 are diagrams for explaining “logic” related instructions.
FIG. 318 to FIG. 359 are diagrams for explaining instructions related to “compare”.
360 to 420 are diagrams for explaining instructions related to “move”.
FIG. 421 is a diagram illustrating “nop” related instructions.
FIG. 422 to FIG. 441 are diagrams for explaining a command related to “shift (S1)”.
FIG. 442 to FIG. 460 are diagrams for explaining a command related to “shift (S2)”.
FIG. 461 to FIG. 380 are diagrams for explaining “extract” related instructions.
FIG. 471 to FIG. 474 are diagrams for explaining “mask” related instructions.
FIG. 475 to FIG. 480 are diagrams for explaining “saturation” related instructions.
481 to 512 are diagrams for explaining a command related to “conversion”.
FIG. 513 to FIG. 516 are diagrams for explaining instructions related to “bit count”.
FIG. 517 to FIG. 520 are diagrams for explaining commands related to “etc”.
FIG. 521 to FIG. 526 are diagrams illustrating instructions related to “mul (X1)”.
FIG. 527 to FIG. 531 are diagrams for explaining an instruction related to “mul (X2)”.
FIG. 532 to FIG. 543 are diagrams for explaining a command related to “mac (X1)”.
FIG. 544 to FIG. 547 are diagrams for explaining commands related to “mac (X2)”.
FIG. 548 to FIG. 559 are diagrams for explaining instructions related to “msu (X1)”.
560 to 563 are diagrams for explaining an instruction related to “msu (X2)”.
FIG. 564 to FIG. 565 are diagrams for explaining “divide” related commands.
FIG. 566 to FIG. 569 are diagrams for explaining “debug” related instructions.
570 to 615 are diagrams for explaining instructions related to “SIMD arithmetic”.
FIGS. 616 to 639 are diagrams for explaining instructions related to “SIMD compare”.
FIG. 640 to FIG. 664 are diagrams for explaining commands related to “SIMD shift (S1)”.
FIG. 665 to FIG. 675 are diagrams for explaining instructions related to “SIMD shift (S2)”.
FIG. 676 to FIG. 680 are diagrams for explaining instructions related to “SIMD saturation”.
681 to 682 are diagrams for explaining instructions related to “SIMD etc”.
FIGS. 683 to 699 are diagrams for explaining instructions related to “SIMD mul (X2)”.
700 to 728 are diagrams for explaining instructions related to “SIMD mac (X2)”.
FIG. 729 to FIG. 748 are diagrams for explaining instructions related to “SIMD msu (X2)”.

  Next, the operation of the processor 1 will be described for some characteristic instructions.

(1) Instructions for performing SIMD binary operations by crossing operands First, among two parallel SIMD operations, instructions for performing operations on operands having a cross positional relationship will be described.

[Instruction vxaddh]
The instruction vxaddh is a SIMD type instruction that adds two sets of operands in a cross positional relationship in units of half words (16 bits). For example,
vxaddh Rc, Ra, Rb
If so, the processor 1 uses an arithmetic logic / comparison unit 41 or the like to
(I) The upper 16 bits of the register Ra and the lower 16 bits of the register Rb are added, and the result is stored in the upper 16 bits of the register Rc.
(Ii) Add the lower 16 bits of the register Ra and the upper 16 bits of the register Rb, and store the result in the lower 16 bits of the register Rc.

  Such an instruction is effective when adding (or subtracting) values multiplied by the same coefficient in advance in order to reduce multiplication by a symmetric filter (coefficient which is symmetrical from the center).

  Note that the processor 1 executes the same processing as this addition instruction for a subtraction instruction (vxsubh or the like).

[Instruction vxmul]
The instruction vxmul is a SIMD type instruction that multiplies two sets of operands in a cross positional relationship in units of halfwords (16 bits) and leaves (stores in SIMD) each lower halfword of the result. For example,
vxmul Rc, Ra, Rb
If so, the processor 1 uses the multiplication / product-sum calculator 44 or the like,
(I) Multiply the upper 16 bits of the register Ra and the lower 16 bits of the register Rb, store the multiplication result in the upper 16 bits of the arithmetic register MHm and the upper 16 bits of the arithmetic register MLm, and 16 bits are stored in the upper 16 bits of the register Rc, and in parallel,
(Ii) Multiply the lower 16 bits of the register Ra by the upper 16 bits of the register Rb, store the multiplication result in the lower 16 bits of the operation register MHm and the lower 16 bits of the operation register MLm, and The 16 bits are stored in the lower 16 bits of the register Rc.

  Such an instruction is effective for inner products of complex numbers. Extracting the lower order of the result is effective when handling integer data (mainly images).

[Instruction vxfmulh]
The instruction vxmulh is an SIMD type instruction that multiplies two sets of operands in a cross positional relationship in units of halfwords (16 bits) and leaves the upper halfwords of those results (stores them in SIMD). For example,
vxfmulh Rc, Ra, Rb
If so, the processor 1 uses the multiplication / product-sum calculator 44 or the like,
(I) Multiply the upper 16 bits of the register Ra and the lower 16 bits of the register Rb and store the multiplication result in the upper 16 bits of the arithmetic register MHm and the upper 16 bits of the arithmetic register MLm. 16 bits are stored in the upper 16 bits of the register Rc, and in parallel,
(Ii) Multiply the lower 16 bits of the register Ra and the upper 16 bits of the register Rb, store the multiplication result in the lower 16 bits of the arithmetic register MHm and the lower 16 bits of the arithmetic register MLm, and The 16 bits are stored in the lower 16 bits of the register Rc.

  Such an instruction is effective for inner products of complex numbers. Extracting the top of the result is effective when dealing with fixed-point data. It can be applied to a standard format (MSB stuffing) called Q31 / Q15.

[Instruction vxfmulw]
The instruction vxfmulw is a SIMD type instruction that multiplies two sets of operands in a cross positional relationship in units of half words (16 bits) and leaves only one multiplication result (non-SIMD storage). For example,
vxfmulh Rc, Ra, Rb
If so, the processor 1 uses the multiplication / product-sum calculator 44 or the like,
(I) Multiply the upper 16 bits of the register Ra and the lower 16 bits of the register Rb, store the multiplication result in the upper 16 bits of the arithmetic register MHm and the upper 16 bits of the arithmetic register MLm, and the multiplication result (word ) Is stored in the register Rc, and in parallel therewith,
(Ii) Multiply the lower 16 bits of the register Ra by the upper 16 bits of the register Rb, and store the multiplication result in the lower 16 bits of the arithmetic register MHm and the lower 16 bits of the arithmetic register MLm (not stored in the register Rc) ).

  Such an instruction is effective when the precision is insufficient at 16 bits and SIMD cannot be maintained (such as audio).

[Instruction vxmac]
The instruction vxmac is a SIMD type instruction that performs a product-sum operation on two pairs of operands in a cross positional relationship in units of halfwords (16 bits) and leaves each of the lower halfwords of those results (stores in SIMD). is there. For example,
vxmac Mm, Rc, Ra, Rb, Mn
If so, the processor 1 uses the multiplication / product-sum calculator 44 or the like,
(I) Multiply the upper 16 bits of the register Ra and the lower 16 bits of the register Rb, add the multiplication result and 32 bits consisting of the upper 16 bits of the operation registers MHn and MLn, and add the 32 bits of the addition result Store in the 32-bit area consisting of the upper 16 bits of the arithmetic registers MHm and MLm, and store the lower 16 bits of the addition result in the upper 16 bits of the register Rc.
(Ii) Multiply the lower 16 bits of the register Ra by the upper 16 bits of the register Rb, add the multiplication result and 32 bits consisting of the lower 16 bits of the operation registers MHn and MLn, and add the 32 bits of the addition result The lower 16 bits of the addition result are stored in the lower 16 bits of the register Rc, while being stored in a 32-bit area consisting of the lower 16 bits of the arithmetic registers MHm and MLm.

  Such an instruction is effective for inner products of complex numbers. Extracting the lower order of the result is effective when handling integer data (mainly images).

[Instruction vxfmach]
The instruction vxmac is a SIMD type instruction that performs a product-sum operation on two sets of operands in a cross positional relationship in units of halfwords (16 bits) and leaves each of the higher halfwords of those results (stores them in SIMD). is there. For example,
vxfmach Mm, Rc, Ra, Rb, Mn
If so, the processor 1 uses the multiplication / product-sum calculator 44 or the like,
(I) Multiply the upper 16 bits of the register Ra and the lower 16 bits of the register Rb, add the multiplication result and 32 bits consisting of the upper 16 bits of the operation registers MHn and MLn, and add the 32 bits of the addition result In addition to storing in the 32-bit area consisting of the upper 16 bits of the arithmetic registers MHm and MLm, the upper 16 bits of the addition result are stored in the upper 16 bits of the register Rc.
(Ii) Multiply the lower 16 bits of the register Ra by the upper 16 bits of the register Rb, add the multiplication result and 32 bits consisting of the lower 16 bits of the operation registers MHn and MLn, and add the 32 bits of the addition result The upper 16 bits of the addition result are stored in the lower 16 bits of the register Rc, while being stored in the 32-bit area consisting of the lower 16 bits of the arithmetic registers MHm and MLm.

  Such an instruction is effective for inner products of complex numbers. Extracting the top of the result is effective when dealing with fixed-point data. It can be applied to a standard format (MSB stuffing) called Q31 / Q15.

[Instruction vxfmacw]
The instruction vxfmach is a SIMD type instruction that multiplies two sets of operands in a cross positional relationship in units of halfwords (16 bits) and leaves only one multiplication result (non-SIMD storage). For example,
vxfmach Mm, Rc, Ra, Rb, Mn
If so, the processor 1 uses the multiplication / product-sum calculator 44 or the like,
(I) Multiply the upper 16 bits of the register Ra and the lower 16 bits of the register Rb, add the multiplication result and 32 bits consisting of the upper 16 bits of the operation registers MHn and MLn, and add the 32 bits of the addition result In addition to storing in the 32-bit area consisting of the upper 16 bits of the arithmetic registers MHm and MLm, 32 bits of the addition result are stored in the register Rc.
(Ii) Multiply the lower 16 bits of the register Ra by the upper 16 bits of the register Rb, add the multiplication result and 32 bits consisting of the lower 16 bits of the operation registers MHn and MLn, and add the 32 bits of the addition result Store in the 32-bit area consisting of the lower 16 bits of the arithmetic registers MHm and MLm (not stored in the register Rc).

  Such an instruction is effective when the precision is insufficient at 16 bits and SIMD cannot be maintained (such as audio).

  Note that the processor 1 executes the same processing as the product-sum instruction for product difference instructions (vxmsu, vxmsuh, vxmsuw, etc.).

  Further, the processor 1 not only performs operations (addition, subtraction, multiplication, product-sum, product-difference by two parallel SIMD) on the two sets of operands having the cross positional relationship as described above, but n sets obtained by expanding this May be provided with a function for executing operations on the operands (4 parallel, 8 parallel SIMD, etc.).

For example, the four byte data currently stored in the register Ra are Ra1, Ra2, Ra3, Ra4 from the top, and the four byte data stored in the register Rb are Rb1, Rb2, Rb3, Rb4 from the top. In this case, a SIMD operation instruction using the register Ra and the register Rb as operands, and an instruction for executing operations on byte data having a cross positional relationship as described below in parallel may be provided. That means
(I) Instructions with 1 Symmetric Crossing A 4-parallel SIMD type operation instruction for Ra1 and Rb4, Ra2 and Rb3, Ra3 and Rb2, and Ra4 and Rb1 may be provided.
(Ii) Two-symmetrical cross instruction It is possible to provide four parallel SIMD type arithmetic instructions for Ra1 and Rb2, Ra2 and Rb1, Ra3 and Rb4, and Ra4 and Rb3.
(Iii) Double-crossing instruction It is possible to provide four parallel SIMD type arithmetic instructions for Ra1 and Rb3, Ra2 and Rb4, Ra3 and Rb1, and Ra4 and Rb2, respectively.

  These types of 4-parallel SIMD type operations can be applied to any of addition, subtraction, multiplication, product-sum, and product-difference similarly to the above-described 2-parallel SIMD type operations. Further, with respect to multiplication, product sum, and product difference, similar to the above-described 2-parallel SIMD type operation instructions (vxmul, vxfmulh, vxfmulw, etc.), only the lower byte of each of the four operation results can be stored in the register Rc or the like. There may be provided an instruction for SIMD storing only the upper byte of each of the four calculation results in the register Rc or the like, or storing only two of the four calculation results in the register Rc or the like.

It should be noted that the three types of operations on the data having the cross positional relationship as described above can be expressed as follows when generalized. That is, now, the set of data to be calculated is jth in the arrangement of the i-th data and the n data constituting the second data group in the arrangement of the n data constituting the first data group. As the second data,
In the above (i) 1-symmetric cross instruction, j = n−i + 1 holds.
In the above (ii) 2-symmetric cross instruction, j = i − (− 1) ^ (i mod 2) holds,
In the above (iii) double cross instruction, j = n−i + 1 + (− 1) ^ (i mod 2) holds. Here, “^” means power and “mod” means remainder.

  The above instruction is effective when computing two complex numbers simultaneously, such as inner product of complex numbers.

(2) Instruction for Performing SIMD Binary Operation with One Operand Fixed Next, an operation instruction performed with one operand fixed (with one operand in common) out of two parallel SIMD operations will be described.

[Instruction vhaddh]
The instruction vhaddh is a SIMD type instruction that adds two sets of operands that share one operand (the upper 16 bits in the register) in units of half words (16 bits). For example,
vhaddh Rc, Ra, Rb
If so, the processor 1 uses an arithmetic logic / comparison unit 41 or the like to
(I) The upper 16 bits of the register Ra and the upper 16 bits of the register Rb are added, and the result is stored in the upper 16 bits of the register Rc.
(Ii) Add the lower 16 bits of the register Ra and the upper 16 bits of the register Rb, and store the result in the lower 16 bits of the register Rc.

  Such an instruction is effective when the two arrays are misaligned by addition / subtraction between the elements of the two arrays and it is difficult to apply SIMD.

  Note that the processor 1 executes the same processing as this addition instruction for a subtraction instruction (vhsubh or the like).

[Instruction vhmul]
The instruction vhmul multiplies two sets of operands that share one operand (the upper 16 bits in the register) in units of halfwords (16 bits), and leaves the lower halfwords of those results (SIMD storage). ) SIMD type instructions. For example,
vhmul Rc, Ra, Rb
If so, the processor 1 uses the multiplication / product-sum calculator 44 or the like,
(I) Multiply the upper 16 bits of the register Ra and the upper 16 bits of the register Rb and store the multiplication result in the upper 16 bits of the arithmetic register MHm and the upper 16 bits of the arithmetic register MLm. 16 bits are stored in the upper 16 bits of the register Rc, and in parallel,
(Ii) Multiply the lower 16 bits of the register Ra by the upper 16 bits of the register Rb, store the multiplication result in the lower 16 bits of the operation register MHm and the lower 16 bits of the operation register MLm, and The 16 bits are stored in the lower 16 bits of the register Rc.

  Such an instruction is effective when multiplying all elements by a coefficient such as gain control, when the loop is expanded by iteration and parallel processing is performed by SIMD, and when it is difficult to apply SIMD. Basically, it is used as a pair (alternate) with the following lower fixed instructions. Extracting the lower order of the result is effective when handling integer data (mainly images).

[Instruction vhfmulh]
The instruction vhmulh multiplies two sets of operands that share one operand (upper 16 bits in the register) in units of halfwords (16 bits), and leaves the upper halfwords of those results (SIMD storage). ) SIMD type instructions. For example,
vhfmulh Rc, Ra, Rb
If so, the processor 1 uses the multiplication / product-sum calculator 44 or the like,
(I) Multiply the upper 16 bits of the register Ra and the upper 16 bits of the register Rb, store the multiplication result in the upper 16 bits of the arithmetic register MHm and the upper 16 bits of the arithmetic register MLm, and 16 bits are stored in the upper 16 bits of the register Rc, and in parallel,
(Ii) Multiply the lower 16 bits of the register Ra and the upper 16 bits of the register Rb, store the multiplication result in the lower 16 bits of the arithmetic register MHm and the lower 16 bits of the arithmetic register MLm, and The 16 bits are stored in the lower 16 bits of the register Rc.

  Such an instruction is valid as described above. Extracting the top of the result is effective when dealing with fixed-point data. It can be applied to a standard format (MSB stuffing) called Q31 / Q15.

[Instruction vhfmulw]
The instruction vhfmulw is a SIMD type that multiplies two operands that share one operand (upper 16 bits in the register) in units of halfword (16 bits) and leaves only one multiplication result (non-SIMD storage). It is an instruction. For example,
vhfmulh Rc, Ra, Rb
If so, the processor 1 uses the multiplication / product-sum calculator 44 or the like,
(I) Multiply the upper 16 bits of the register Ra and the upper 16 bits of the register Rb, store the multiplication result in the upper 16 bits of the arithmetic register MHm and the upper 16 bits of the arithmetic register MLm, and the multiplication result (word ) Is stored in the register Rc, and in parallel therewith,
(Ii) Multiply the lower 16 bits of the register Ra by the upper 16 bits of the register Rb, and store the multiplication result in the lower 16 bits of the arithmetic register MHm and the lower 16 bits of the arithmetic register MLm (not stored in the register Rc) ).

  Such an instruction is effective in ensuring accuracy.

[Instruction vhmac]
The instruction vhmac performs a product-sum operation on two sets of operands that share one operand (the upper 16 bits in the register) in units of halfwords (16 bits), and leaves each of the lower halfwords of those results ( This is an SIMD type instruction (stored in SIMD). For example,
vhmac Mm, Rc, Ra, Rb, Mn
If so, the processor 1 uses the multiplication / product-sum calculator 44 or the like,
(I) Multiply the upper 16 bits of the register Ra and the upper 16 bits of the register Rb, add the multiplication result and 32 bits consisting of the upper 16 bits of the operation registers MHn and MLn, and add the 32 bits of the addition result Store in the 32-bit area consisting of the upper 16 bits of the arithmetic registers MHm and MLm, and store the lower 16 bits of the addition result in the upper 16 bits of the register Rc.
(Ii) Multiply the lower 16 bits of the register Ra by the upper 16 bits of the register Rb, add the multiplication result and 32 bits consisting of the lower 16 bits of the operation registers MHn and MLn, and add the 32 bits of the addition result The lower 16 bits of the addition result are stored in the lower 16 bits of the register Rc, while being stored in a 32-bit area consisting of the lower 16 bits of the arithmetic registers MHm and MLm.

  Such an instruction is effective when it is difficult to apply SIMD when the loop is expanded by iteration using FIR (filter) or the like and parallel processing is performed using SIMD. Basically, it is used as a pair (alternate) with the following lower fixed instructions. Extracting the lower order of the result is effective when handling integer data (mainly images).

[Instruction vhfmach]
The instruction vhmac performs a product-sum operation on two sets of operands that share one operand (the upper 16 bits in the register) in units of halfwords (16 bits), and leaves each of the upper halfwords of those results ( This is an SIMD type instruction (stored in SIMD). For example,
vhfmach Mm, Rc, Ra, Rb, Mn
If so, the processor 1 uses the multiplication / product-sum calculator 44 or the like,
(I) Multiply the upper 16 bits of the register Ra and the upper 16 bits of the register Rb, add the multiplication result and 32 bits consisting of the upper 16 bits of the operation registers MHn and MLn, and add the 32 bits of the addition result In addition to storing in the 32-bit area consisting of the upper 16 bits of the arithmetic registers MHm and MLm, the upper 16 bits of the addition result are stored in the upper 16 bits of the register Rc.
(Ii) Multiply the lower 16 bits of the register Ra by the upper 16 bits of the register Rb, add the multiplication result and 32 bits consisting of the lower 16 bits of the operation registers MHn and MLn, and add the 32 bits of the addition result The upper 16 bits of the addition result are stored in the lower 16 bits of the register Rc, while being stored in the 32-bit area consisting of the lower 16 bits of the arithmetic registers MHm and MLm.

  Such an instruction is valid as described above. Extracting the top of the result is effective when dealing with fixed-point data. It can be applied to a standard format (MSB stuffing) called Q31 / Q15.

[Instruction vhfmacw]
The instruction vhfmach is a SIMD type that multiplies two operands that share one operand (upper 16 bits in the register) in halfword (16 bits) units and leaves only one multiplication result (non-SIMD storage). It is an instruction. For example,
vhfmach Mm, Rc, Ra, Rb, Mn
If so, the processor 1 uses the multiplication / product-sum calculator 44 or the like,
(I) Multiply the upper 16 bits of the register Ra and the upper 16 bits of the register Rb, add the multiplication result and 32 bits consisting of the upper 16 bits of the operation registers MHn and MLn, and add the 32 bits of the addition result In addition to storing in the 32-bit area consisting of the upper 16 bits of the arithmetic registers MHm and MLm, 32 bits of the addition result are stored in the register Rc.
(Ii) Multiply the lower 16 bits of the register Ra by the upper 16 bits of the register Rb, add the multiplication result and 32 bits consisting of the lower 16 bits of the operation registers MHn and MLn, and add the 32 bits of the addition result Store in the 32-bit area consisting of the lower 16 bits of the arithmetic registers MHm and MLm (not stored in the register Rc).

Such an instruction is effective in ensuring accuracy.
Note that the processor 1 executes the same processing as the product-sum instruction for product difference instructions (vhmsu, vhmsuh, vhmsuw, etc.).

  In these instructions, the upper 16 bits in the register are fixed (shared), but the lower 16 bits in the register are fixed (shared) (vladdh, vlsubh, vlmul, vlfmulh, vlfmulw, vlmulw, vlmac, (vlmsu, vlfmach, vlmsuh, vlfmacw, vlmsuw, etc.), the processor 1 executes the same processing as these operation instructions. Such an instruction is effective when used as a pair with the upper fixed instruction.

  Further, the processor 1 performs only operations (addition, subtraction, multiplication, product sum, product difference by two parallel SIMD) on two sets of operands that share one operand (the upper 16 bits in the register) as described above. Instead, it may have a function of executing operations (4 parallel, 8 parallel SIMD operations, etc.) on n sets of operands that are expanded from this.

For example, the four byte data stored in the register Ra are Ra1, Ra2, Ra3, and Ra4 from the top, and the four byte data stored in the register Rb are Rb1, Rb2, Rb3, and Rb4 from the top. In this case, a SIMD operation instruction having the register Ra and the register Rb as operands, and an instruction for executing an operation on byte data sharing one operand (one byte in the register) as follows in parallel is provided. May be. That means
(I) Highest level fixed instruction Ra1 and Rb1, Ra2 and Rb1, Ra3 and Rb1, and Ra4 and Rb1 may be provided as 4-parallel SIMD type operation instructions.
(I) Middle-upper fixed instructions Ra1 and Rb2, Ra2 and Rb2, Ra3 and Rb2, and Ra4 and Rb2 may each be provided with a 4-parallel SIMD type arithmetic instruction.
(I) Middle and lower order fixed instructions Ra1 and Rb3, Ra2 and Rb3, Ra3 and Rb3, Ra4 and Rb3 may be provided as 4-parallel SIMD type operation instructions.
(I) The lowest fixed instruction Ra1 and Rb4, Ra2 and Rb4, Ra3 and Rb4, Ra4 and Rb4 may be provided as 4-parallel SIMD type operation instructions.

  These types of 4-parallel SIMD type operations can be applied to any of addition, subtraction, multiplication, product-sum, and product-difference similarly to the above-described 2-parallel SIMD type operations. Further, for multiplication, sum of products, and product difference, similar to the above-described two-parallel SIMD type operation instructions (vhmul, vhfmulh, vhfmulw, etc.), only the lower byte of each of the four operation results can be stored in the register Rc or the like. There may be provided an instruction for SIMD storing only the upper byte of each of the four calculation results in the register Rc or the like, or storing only two of the four calculation results in the register Rc or the like. Such an instruction is effective in the following cases. In other words, this is effective when performing the calculation for each element while shifting the two elements one element at a time. This is because it is necessary to calculate one deviation, two deviations, and three deviations.

  The above generalized operation with one of the operands fixed is expressed as follows. That is, the processor 1 includes a first operand that specifies a first data group that includes a sequence of n (≧ 2) data and a second operand that specifies a second data group that includes a sequence of n data. For a SIMD type instruction to be included, from a set of i-th data in the first data group and j-th data in the second data group when i = 1, 2,..., N, j = constant values. An operation may be performed on each of the n sets.

(3) Instruction for executing SIMD binary operation and bit-shifting the result Next, of 2 parallel SIMD operations, an instruction for performing an operation on operands in a cross positional relationship will be described.

[Instruction vaddsh]
The instruction vaddsh is a SIMD type instruction that adds two sets of operands in units of halfwords (16 bits) and arithmetically shifts the result by one bit to the right. For example,
vaddsh Rc, Ra, Rb
If so, the processor 1 uses an arithmetic logic / comparison unit 41 or the like to
(I) The upper 16 bits of the register Ra and the upper 16 bits of the register Rb are added, and a value obtained by arithmetically shifting the result by one bit is stored in the upper 16 bits of the register Rc.
(Ii) Add the lower 16 bits of the register Ra and the lower 16 bits of the register Rb, and store the result obtained by arithmetically shifting the result by one bit to the lower 16 bits of the register Rc.

  Such an instruction is effective for ensuring accuracy by shifting down before it is not reduced to 16-bit accuracy by addition. Some cases require rounding. FFT (butterfly) is frequently used because addition and subtraction of complex numbers are repeated.

  Note that the processor 1 executes the same processing as this addition instruction for a subtraction instruction (vsubsh or the like).

  Further, the processor 1 performs not only operations on the above two sets of operands (addition and subtraction by 2-parallel SIMD), but also operations on n sets of operands (4-parallel, 8-parallel SIMD operations, etc.) that are expanded. May be provided with a function of executing

  For example, the four byte data currently stored in the register Ra are Ra1, Ra2, Ra3, Ra4 from the top, and the four byte data stored in the register Rb are Rb1, Rb2, Rb3, Rb4 from the top. In this case, a SIMD operation instruction having operands of the register Ra and the register Rb and an instruction for performing the following operation and bit shift may be provided. That is, a 4-parallel SIMD type operation instruction for Ra1 and Rb1, Ra2 and Rb2, Ra3 and Rb3, and Ra4 and Rb4 may be provided. For example, an instruction vaddsb that adds four operands in byte units and arithmetically shifts the result by one bit to the right.

  Such an instruction is also effective in ensuring accuracy. Used mainly for averaging (vertical averaging).

  Further, the characteristic instruction for performing such SIMD operation and shift is not limited to the instruction for shifting by one bit in the right direction as described above. That is, the shift amount may be either fixed or variable, and may be either the right direction or the left direction. Further, bits spilled during the right shift may be rounded (for example, instruction vaddsrh or instruction vaddsrb).

  (4) An instruction to add a SIMD (vector) data to make it scalar or vector

  Next, a SIMD type instruction for making vector data scalar or vector reduction will be described.

[Instruction vsumh]
The instruction vsumh is a SIMD type instruction that adds two SIMD data (vector data) in units of halfwords (16 bits) to make a scalar. For example,
vsumh Rb, Ra
If so, the processor 1 adds the upper 16 bits of the register Ra and the lower 16 bits of the register Ra using the arithmetic logic / comparison unit 41 and the like, and stores the result in the register Rb.

  Such an instruction can be used for various purposes. For example, the average (horizontal average) and the results of individual calculations (sum of products, addition) are added.

[Instruction vsumh2]
The instruction vsumh2 is a SIMD type instruction that adds elements to each of two sets each including two SIMD data (vector data) in units of bytes to make a scalar. For example,
vsumh2 Rb, Ra
If so, the processor 1 uses an arithmetic logic / comparison unit 41 or the like to
(I) Add the most significant byte and the middle high-order byte of the register Ra and store the result in the high-order 16 bits of the register Rb.
(Ii) The middle lower byte and the least significant byte of the register Ra are added together and the result is stored in the lower 16 bits of the register Rb.

  Such a command is effective as a command for image processing, motion compensation (MC), and half-pel.

  The processor 1 performs not only the above-described operation for converting the 2-parallel SIMD data into a scalar, but also the operation for converting the n-parallel SIMD data including n (4, 8, etc.) elements, which is an extension of the 2-parallel SIMD data, into a scalar. A function to be executed may be provided.

  For example, when the four byte data stored in the register Ra is set to Ra1, Ra2, Ra3, Ra4 from the top, the Ra1, Ra2, Ra3, and Ra4 are added together and the result is stored in the register Rb. Instructions may be provided.

  Further, the processor 1 may not only simply convert a vector composed of a plurality of element data into a scalar composed of one element data, but also reduce the number of vectors so as to reduce the number of element data.

  Further, the type of calculation is not limited to addition, but may be calculation for calculating an average value. Such an instruction is effective for averaging, addition of calculation results, and the like.

(5) Other SIMD Instructions Next, other SIMD type instructions not belonging to the above classification will be described.

[Instruction vexth]
The instruction vexth is a SIMD type instruction that sign-extends each of two SIMD data in units of half words (16 bits). For example,
vexth Mm, Rb, Ra
If so, the processor 1 uses the saturation block (SAT) 47a of the converter 47, etc.
(I) The upper 16 bits of the register Ra are sign-extended to 32 bits, and the result is stored in the upper 16 bits of the arithmetic register MHm and the upper 16 bits of the arithmetic register MLm.
(Ii) The lower 16 bits of the register Ra are sign-extended to 32 bits, and the result is stored in the lower 16 bits of the arithmetic register MHm and the lower 16 bits of the arithmetic register MLm.
(Iii) 32 bits of the register Ra are stored in the register Rb.

  Note that sign extension refers to increasing the length of data while maintaining code information, for example, converting a signed numeric value expressed in half words into the same numeric value expressed in words. Specifically, it is a process of filling up the higher bits expanded with the value of the sign bit (most significant bit) of the original data.

  Such an instruction is effective for transferring SIMD data to an accumulator (when accuracy is required).

[Instruction vasubb]
The instruction vassub is a SIMD type instruction that subtracts four sets of SIMD data in units of bytes and stores the four codes obtained as a result in the condition flag register. For example,
Vasubb Rc, Rb, Ra
If so, the processor 1 uses an arithmetic logic / comparison unit 41 or the like to
(I) The most significant 8 bits of the register Ra is subtracted from the most significant 8 bits of the register Rb, the result is stored in the most significant 8 bits of the register Rc, and the sign thereof is stored in the VC3 of the condition flag register (CFR) 32 Store and in parallel,
(Ii) Subtract the upper 8 bits of the register Ra from the upper 8 bits of the register Rb, store the result in the upper 8 bits of the register Rc, and store the sign in the VC2 of the condition flag register (CFR) 32 Store and in parallel,
(Iii) The lower 8 bits of the register Ra are subtracted from the lower 8 bits of the register Rb, the result is stored in the 8 lower bits of the register Rc, and the sign is stored in the VC1 of the condition flag register (CFR) 32 Store and in parallel,
(Iv) The least significant 8 bits of the register Ra are subtracted from the least significant 8 bits of the register Rb, the result is stored in the least significant 8 bits of the register Rc, and the sign thereof is stored in the VC0 of the condition flag register (CFR) 32 Store.

  Such an instruction is effective when 9-bit precision is temporarily required to obtain the absolute value difference sum.

[Instruction vabsum]
The instruction vabssum is a SIMD type instruction that adds the absolute value of each of four sets of SIMD data in units of bytes and adds the result to the other 4-byte data. For example,
vabsumb Rc, Ra, Rb
If so, the processor 1 uses the arithmetic logic / comparison unit 41 or the like to calculate the absolute value of the most significant 8 bits, the absolute value of the middle and upper 8 bits, the absolute value of the middle and lower 8 bits, and the least significant 8 bits of the register Ra. The absolute value is added, the result is added to 32 bits of the register Rb, and the obtained result is stored in the register Rc. The processor 1 specifies the absolute value of each byte stored in the register Ra by the flags VC0 to VC3 of the condition flag register (CFR) 32.

  Such an instruction is used in combination with the instruction vasubb, so that after calculating the difference of each set for a plurality of sets of data, a value obtained by summing the absolute values of the respective differences is obtained. This is effective when calculating the sum of absolute differences of motion prediction.

(6) Other Instructions Related to Mask Operations, etc. Next, instructions that are not SIMD type instructions but perform characteristic processing will be described.

[Instruction addmsk]
The instruction addmsk is an instruction that masks and adds some bits (upper order) of one of two operands. For example,
addmsk Rc, Ra, Rb
If so, the processor 1 is stored in the register Ra and the register Rb only by the arithmetic logic / comparison calculator 41, the converter 47, etc. within the range (lower bits) designated by the BPO of the condition flag register (CFR) 32. The added data is added and stored in the register Rc, and the value of the register Ra is stored in the register Rc as it is for the unspecified range (upper bit).

  Such an instruction is effective as a response to modulo addressing (common in DSP). This is necessary for rearranging data into a specific pattern in advance for preparation of butterfly computation.

  Note that the processor 1 executes the same processing as the addition instruction for the subtraction instruction (submsk or the like).

[Instruction mskbrvh]
The instruction mskbrvh is an instruction that performs bit concatenation with the other operand after reversing a part (lower order) of one of the two operands (in reverse order of the bit sequence). For example,
mskbrvh Rc, Ra, Rb
If so, the processor 1 reverses the lower 16 bits of the register Rb with the converter 47 and the like, and then at the bit position designated by the BPO of the condition flag register (CFR) 32, the data of the register Ra and the register Rb And the result are stored in the register Rc. At this time, the lower part of the upper 16 bits of the register Rb is masked to 0 from the position specified by BP0.

  Such an instruction corresponds to reverse addressing and is necessary for rearranging data in a specific pattern in advance for preparation of butterfly computation.

  Note that the processor 1 executes the same processing as this instruction not only for the 16 bits in the reverse order but also for an instruction (such as mskbrvb) that reverses the area of 1 byte or the like.

[Instruction msk]
The instruction msk is an instruction that masks (sets to 0) an area sandwiched between two designated bit positions among bits constituting an operand, or masks the outside of the area. For example,
msk Rc, Ra, Rb
If so, the processor 1 uses the converter 47 or the like to
(I) When Rb [12: 8] ≧ Rb [4: 0],
Of the 32 bits stored in the register Ra, the 8th to 12th 5 bits Rb [12: 8] of the register Rb from the bit position specified by the 0th to 4th 5 bits Rb [4: 0] of the register Rb. The bit position specified by is kept as it is, and the other bits are masked (set to 0) and stored in the register Rc.
(Ii) When Rb [12: 8] <Rb [4: 0],
Of the 32 bits stored in the register Ra, the 0th to 4th 5 bits Rb [4: 0] of the register Rb from the bit position specified by the 8th to 12th 5 bits Rb [12: 8] of the register Rb. The bit position designated by (1) is masked (set to 0), the other bits are left as they are, and stored in the register Rc.

  Such an instruction can be used for bit field extraction and insertion (assembly). It can be used when VLD / VLC is performed by software.

[Instruction bseq]
The instruction bseq is an instruction that counts the number of sign bits that are consecutive from one bit below the MSB of the operand. For example,
bseq Rb, Ra
If so, the processor 1 uses the BSEQ block 47b of the converter 47 to count the number of consecutive sign bits from one bit below the register Ra, and stores the result in the register Rb. When the value of the register Ra is 0, 0 is stored in the register Rb.

  Such an instruction can be used to detect significant digits. In order to increase the dynamic range, some floating point operations may be performed. For example, it can be used for normalizing and calculating all data according to data having the most significant digits in the array.

[Instruction ldbp]
The instruction ldbp is an instruction for sign-extending 2-byte data from the memory and loading the register. For example,
ldbp Rb: Rb + 1, (Ra, D9)
If so, the processor 1 sign-extends two byte data from the address obtained by adding the displacement value (D9) to the value of the register Ra by the I / F unit 50 or the like, and assigns it to each of the register Ra and the register (Ra + 1). Load it.

Such instructions speed up data supply.
The processor 1 not only loads the two registers but also loads the upper halfword and the lower halfword of one register (ldbh, etc.) in the same manner as this load instruction (sign extension is performed). Load).
[Instruction rde]
The instruction rde is an instruction that reads the value of the external register and generates an error exception when reading fails. For example,
rde C0: C1, Rb, (Ra, D5)
If so, the processor 1 uses the I / F unit 50 or the like as a value obtained by adding the displacement value (D5) to the value of the register Ra as an external register number, and registers the value of the external register (extended register unit 80) as a register. In addition to reading into Rb, the success / failure of reading is output to the condition flags C0 and C1 of the condition flag register (CFR) 32. An extension register error exception occurs on failure.

  Such an instruction is effective as an instruction for controlling the hard accelerator. If hardware returns an error, an exception is raised and reflected in the flag.

  The processor 1 executes not only reading from the external register but also writing (instruction wete) to the external register in the same manner as the read instruction (setting a flag and generating an exception).

[Instruction addarrvw]
The instruction adddarww is an instruction that performs addition of absolute value rounding (rounding away from zero). For example,
addarrvw Rc, Rb, Ra
If so, the processor 1 adds 32 bits of the register Ra and 32 bits of the register Rb by the arithmetic logic / comparison unit 41 or the like, and if the result is positive, rounds up the bits to be rounded. If the result is negative, round down the bits to be rounded. Specifically, the values of the registers Ra and Rb are added, and 1 is added when the value of the register Ra is positive. In the case of performing absolute value rounding, a value obtained by padding bits lower than the bit to be rounded with 1 is stored in the register Rb.

  Such an instruction is effective for addition IDCT (Inverse Discrete Cosine Transform) of absolute value rounding (rounding away from zero).

  The present invention can be used as a processor such as a DSP or a CPU, particularly as a processor for executing SIMD instructions, for example, as a core processor common to a mobile phone, a mobile AV device, a digital TV, a DVD, or the like.

1 is a schematic block diagram of a processor according to the present invention. A schematic diagram of an arithmetic logic / comparison arithmetic unit of the processor is shown. It is a block diagram which shows the structure of the barrel cutter of the processor. It is a block diagram which shows the structure of the converter of the processor. It is a block diagram which shows the structure of the divider of the processor. It is a block diagram which shows the structure of the multiplication / product-sum calculator of the processor. It is a block diagram which shows the structure of the instruction control part of the processor. It is a figure which shows the structure of the general purpose register | resistor (R0-R31) of the processor. It is a figure which shows the structure of the link register (LR) of the processor. It is a figure which shows the structure of the branch register (TAR) of the processor. It is a figure which shows the structure of the program status register (PSR) of the processor. It is a figure which shows the structure of the condition flag register (CFR) of the processor. It is a figure which shows the structure of the accumulator (M0, M1) of the processor. It is a figure which shows the structure of the program counter (PC) of the processor. It is a figure which shows the structure of the register | resistor for PC saving (IPC) of the processor. It is a figure which shows the structure of the PSR save register (IPSR) of the processor. FIG. 10 is a timing chart showing a pipeline operation of the processor. FIG. 10 is a timing chart showing each pipeline operation when an instruction is executed by the processor. It is a figure which shows the parallel operation | movement of the processor. It is a figure which shows the format of the command which the processor performs. It is a figure explaining the instruction which belongs to the category "ALUadd (addition) system". It is a figure explaining the instruction which belongs to the category "ALUsub (subtraction) system". It is a figure explaining the instruction which belongs to a category "ALUlogic (logic operation) system etc.". It is a figure explaining the instruction which belongs to the category "CMP (comparison operation) system". It is a figure explaining the instruction which belongs to the category "mul (multiplication) system". It is a figure explaining the instruction which belongs to the category "mac (product-sum operation) system". It is a figure explaining the instruction which belongs to the category "msu (product difference operation) system". It is a figure explaining the instruction which belongs to the category "MEMld (memory read) system". It is a figure explaining the instruction which belongs to the category "MEMstore (memory writing) system". It is a figure explaining the instruction which belongs to the category "BRA (branch) system". It is a figure explaining the instruction which belongs to the category "BSasl (arithmetic barrel shift) system etc.". It is a figure explaining the instruction which belongs to the category "BSlsr (logical barrel shift) system etc.". It is a figure explaining the instruction which belongs to the category "CNVvaln (arithmetic conversion) system". It is a figure explaining the instruction which belongs to the category "CNV (general conversion) system". It is a figure explaining the instruction which belongs to the category "SATvlpk (saturation processing) system". It is a figure explaining the instruction which belongs to a category "ETC (others) system". FIG. 6 is a diagram for explaining an instruction “ld Rb, (Ra, D10)”. FIG. 6 is a diagram for explaining an instruction “ld Rb3, (Ra3, D5)”. FIG. 6 is a diagram for explaining an instruction “ld Rb, (GP, D13)”. FIG. 5 is a diagram for explaining an instruction “ld Rb2, (GP, D6)”. FIG. 6 is a diagram for explaining an instruction “ld Rb2, (GP)”. FIG. 6 is a diagram for explaining an instruction “ld Rb, (SP, D13)”. FIG. 11 is a diagram for explaining an instruction “ld Rb2, (SP, D6)”. FIG. 6 is a diagram for explaining an instruction “ld Rb2, (SP)”. FIG. 6 is a diagram for explaining an instruction “ld Rb, (Ra +) I10”. FIG. 6 is a diagram for explaining an instruction “ld Rb, (Ra +)”. FIG. 6 is a diagram for explaining an instruction “ld Rb2, (Ra2 +)”. FIG. 6 is a diagram for explaining an instruction “ld Rb, (Ra)”. FIG. 6 is a diagram for explaining an instruction “ld Rb2, (Ra2)”. FIG. 6 is a diagram for explaining an instruction “ldh Rb, (Ra, D9)”. FIG. 10 is a diagram for explaining an instruction “ldh Rb3, (Ra3, D4)”. FIG. 6 is a diagram for explaining an instruction “ldh Rb, (GP, D12)”. FIG. 6 is a diagram for explaining an instruction “ldh Rb2, (GP, D5)”. FIG. 10 is a diagram for explaining an instruction “ldh Rb2, (GP)”. FIG. 6 is a diagram for explaining an instruction “ldh Rb, (SP, D12)”. FIG. 6 is a diagram for explaining an instruction “ldh Rb2, (SP, D5)”. FIG. 11 is a diagram for explaining an instruction “ldh Rb2, (SP)”. FIG. 11 is a diagram for explaining an instruction “ldh Rb, (Ra +) I9”. FIG. 6 is a diagram for explaining an instruction “ldh Rb, (Ra +)”. FIG. 6 is a diagram for explaining an instruction “ldh Rb2, (Ra2 +)”. FIG. 10 is a diagram for explaining an instruction “ldh Rb, (Ra)”. FIG. 6 is a diagram for explaining an instruction “ldh Rb2, (Ra2)”. FIG. 6 is a diagram for explaining an instruction “ldhu Rb, (Ra, D9)”. FIG. 6 is a diagram for explaining an instruction “ldhu Rb, (GP, D12)”. FIG. 6 is a diagram for explaining an instruction “ldhu Rb, (SP, D12)”. FIG. 6 is a diagram for explaining an instruction “ldhu Rb, (Ra +) I9”. FIG. 11 is a diagram for explaining an instruction “ldhu Rb, (Ra +)”. FIG. 6 is a diagram for explaining an instruction “ldhu Rb, (Ra)”. FIG. 5 is a diagram for explaining an instruction “ldb Rb, (Ra, D8)”. FIG. 6 is a diagram for explaining an instruction “ldb Rb, (GP, D11)”. FIG. 10 is a diagram for explaining an instruction “ldb Rb, (SP, D11)”. FIG. 6 is a diagram for explaining an instruction “ldb Rb, (Ra +) I8”. FIG. 6 is a diagram for explaining an instruction “ldb Rb, (Ra +)”. FIG. 6 is a diagram for explaining an instruction “ldb Rb, (Ra)”. FIG. 6 is a diagram for explaining an instruction “ldbu Rb, (Ra, D8)”. FIG. 10 is a diagram for explaining an instruction “ldbu Rb, (GP, D11)”. FIG. 6 is a diagram for explaining an instruction “ldbu Rb, (SP, D11)”. FIG. 6 is a diagram for explaining an instruction “ldbu Rb, (Ra +) I8”. FIG. 6 is a diagram for explaining an instruction “ldbu Rb, (Ra +)”. FIG. 6 is a diagram for explaining an instruction “ldbu Rb, (Ra)”. FIG. 6 is a diagram for explaining an instruction “ldp Rb: Rb + 1, (Ra, D11)”. FIG. 6 is a diagram illustrating an instruction “ldp Rb: Rb + 1, (GP, D14)”. FIG. 6 is a diagram for explaining an instruction “ldp Rb: Rb + 1, (SP, D14)”. FIG. 6 is a diagram for explaining an instruction “ldp Rb: Rb + 1, (SP, D7)”. FIG. 6 is a diagram for explaining an instruction “ldp Rb: Rb + 1, (SP)”. FIG. 6 is a diagram for explaining an instruction “ldp Rb: Rb + 1, (Ra +) I11”. FIG. 6 is a diagram for explaining an instruction “ldp Rb2: Rb2 + 1, (Ra2 +)”. FIG. 6 is a diagram for explaining an instruction “ldp Rb: Rb + 1, (Ra +)”. FIG. 6 is a diagram for explaining an instruction “ldp Rb: Rb + 1, (Ra)”. FIG. 6 is a diagram for explaining an instruction “ldp LR: SVR, (Ra, D14)”. FIG. 6 is a diagram for explaining an instruction “ldp LR: SVR, (Ra)”. FIG. 6 is a diagram for explaining an instruction “ldp LR: SVR, (GP, D14)”. FIG. 6 is a diagram for explaining an instruction “ldp LR: SVR, (SP, D14)”. FIG. 6 is a diagram for explaining an instruction “ldp LR: SVR, (SP, D7)”. FIG. 6 is a diagram for explaining an instruction “ldp LR: SVR, (SP)”. FIG. 10 is a diagram for explaining an instruction “ldp TAR: UDR, (Ra, D11)”. FIG. 6 is a diagram for explaining an instruction “ldp TAR: UDR, (GP, D14)”. FIG. 6 is a diagram for explaining an instruction “ldp TAR: UDR, (SP, D14)”. FIG. 6 is a diagram for explaining an instruction “ldhp Rb: Rb + 1, (Ra, D10)”. FIG. 6 is a diagram illustrating an instruction “ldhp Rb: Rb + 1, (Ra +) I10”. FIG. 6 is a diagram for explaining an instruction “ldhp Rb2: Rb2 + 1, (Ra2 +)”. FIG. 6 is a diagram for explaining an instruction “ldhp Rb: Rb + 1, (Ra +)”. FIG. 6 is a diagram for explaining an instruction “ldhp Rb: Rb + 1, (Ra)”. FIG. 6 is a diagram for explaining an instruction “ldbp Rb: Rb + 1, (Ra, D9)”. FIG. 6 is a diagram for explaining an instruction “ldbp Rb: Rb + 1, (Ra +) I9”. FIG. 6 is a diagram for explaining an instruction “ldbp Rb: Rb + 1, (Ra +)”. FIG. 6 is a diagram for explaining an instruction “ldbp Rb: Rb + 1, (Ra)”. FIG. 6 is a diagram for explaining an instruction “ldbh Rb, (Ra +) I7”. FIG. 6 is a diagram for explaining an instruction “ldbh Rb, (Ra +)”. FIG. 6 is a diagram illustrating an instruction “ldbh Rb, (Ra)”. FIG. 6 is a diagram for explaining an instruction “ldbuh Rb, (Ra +) I7”. FIG. 6 is a diagram for explaining an instruction “ldbuh Rb, (Ra +)”. FIG. 6 is a diagram for explaining an instruction “ldbuh Rb, (Ra)”. FIG. 11 is a diagram for explaining an instruction “ldbhp Rb: Rb + 1, (Ra +) I7”. FIG. 6 is a diagram for explaining an instruction “ldbhp Rb: Rb + 1, (Ra +)”. FIG. 6 is a diagram for explaining an instruction “ldbhp Rb: Rb + 1, (Ra)”. FIG. 6 is a diagram for explaining an instruction “ldbuhp Rb: Rb + 1, (Ra +) I7”. FIG. 6 is a diagram for explaining an instruction “ldbuhp Rb: Rb + 1, (Ra +)”. FIG. 6 is a diagram illustrating an instruction “ldbuhp Rb: Rb + 1, (Ra)”. FIG. 6 is a diagram illustrating an instruction “st (Ra, D10), Rb”. FIG. 5 is a diagram for explaining an instruction “st (Ra3, D5), Rb3”. FIG. 6 is a diagram for explaining an instruction “st (GP, D13), Rb”. FIG. 6 is a diagram for explaining an instruction “st (GP, D6), Rb2”. FIG. 6 is a diagram illustrating an instruction “st (GP), Rb2”. FIG. 6 is a diagram for explaining an instruction “st (SP, D13), Rb”. FIG. 6 is a diagram for explaining an instruction “st (SP, D6), Rb2”. FIG. 6 is a diagram illustrating an instruction “st (SP), Rb2”. FIG. 6 is a diagram for explaining an instruction “st (Ra +) I10, Rb”. FIG. 6 is a diagram for explaining an instruction “st (Ra +), Rb”. FIG. 6 is a diagram for explaining an instruction “st (Ra2 +), Rb2”. FIG. 6 is a diagram for explaining an instruction “st (Ra), Rb”. FIG. 6 is a diagram for explaining an instruction “st (Ra2), Rb2”. FIG. 6 is a diagram for explaining an instruction “sth (Ra, D9), Rb”. FIG. 6 is a diagram for explaining an instruction “sth (Ra3, D4), Rb3”. FIG. 6 is a diagram for explaining an instruction “sth (GP, D12), Rb”. FIG. 6 is a diagram for explaining an instruction “sth (GP, D5), Rb2”. FIG. 6 is a diagram illustrating an instruction “sth (GP), Rb2”. FIG. 6 is a diagram for explaining an instruction “sth (SP, D12), Rb”. FIG. 6 is a diagram illustrating an instruction “sth (SP, D5), Rb2”. FIG. 6 is a diagram illustrating an instruction “sth (SP), Rb2”. FIG. 6 is a diagram illustrating an instruction “sth (Ra +) I9, Rb”. FIG. 6 is a diagram illustrating an instruction “sth (Ra +), Rb”. FIG. 6 is a diagram for explaining an instruction “sth (Ra2 +), Rb2”. FIG. 6 is a diagram illustrating an instruction “sth (Ra), Rb”. FIG. 5 is a diagram for explaining an instruction “sth (Ra2), Rb2”. FIG. 6 is a diagram for explaining an instruction “stb (Ra, D8), Rb”. FIG. 6 is a diagram for explaining an instruction “stb (GP, D11), Rb”. FIG. 6 is a diagram illustrating an instruction “stb (SP, D11), Rb”. FIG. 6 is a diagram for explaining an instruction “stb (Ra +) I8, Rb”. FIG. 6 is a diagram for explaining an instruction “stb (Ra +), Rb”. FIG. 6 is a diagram illustrating an instruction “stb (Ra), Rb”. FIG. 6 is a diagram for explaining an instruction “stp (Ra, D11), Rb: Rb + 1”. FIG. 6 is a diagram for explaining an instruction “stp (GP, D14), Rb: Rb + 1”. FIG. 10 is a diagram for explaining an instruction “stp (SP, D14), Rb: Rb + 1”. FIG. 6 is a diagram for explaining an instruction “stp (SP, D7), Rb: Rb + 1”. FIG. 6 is a diagram for explaining an instruction “stp (SP), Rb: Rb + 1”. FIG. 6 is a diagram for explaining an instruction “stp (Ra +) I11, Rb: Rb + 1”. FIG. 6 is a diagram for explaining an instruction “stp (Ra +), Rb: Rb + 1”. FIG. 6 is a diagram for explaining an instruction “stp (Ra2 +), Rb2: Rb2 + 1”. FIG. 6 is a diagram illustrating an instruction “stp (Ra), Rb: Rb + 1”. FIG. 6 is a diagram for explaining an instruction “stp (Ra, D11), LR: SVR”. FIG. 6 is a diagram for explaining an instruction “stp (Ra), LR: SVR”. FIG. 6 is a diagram for explaining an instruction “stp (GP, D14), LR: SVR”. FIG. 6 is a diagram for explaining an instruction “stp (SP, D14), LR: SVR”. FIG. 6 is a diagram for explaining an instruction “stp (SP, D7), LR: SVR”. FIG. 6 is a diagram for explaining an instruction “stp (SP), LR: SVR”. FIG. 6 is a diagram for explaining an instruction “stp (Ra, D11), TAR: UDR”. FIG. 6 is a diagram for explaining an instruction “stp (GP, D14), TAR: UDR”. FIG. 6 is a diagram for explaining an instruction “stp (SP, D14), TAR: UDR”. FIG. 6 is a diagram for explaining an instruction “sthp (Ra, D10), Rb: Rb + 1”. FIG. 6 is a diagram for explaining an instruction “sthp (Ra +) I10, Rb: Rb + 1”. FIG. 6 is a diagram for explaining an instruction “sthp (Ra +), Rb: Rb + 1”. FIG. 6 is a diagram for explaining an instruction “sthp (Ra2 +), Rb2: Rb2 + 1”. FIG. 6 is a diagram for explaining an instruction “sthp (Ra), Rb: Rb + 1”. FIG. 6 is a diagram for explaining an instruction “stbp (Ra, D9), Rb: Rb + 1”. FIG. 6 is a diagram for explaining an instruction “stbp (Ra +) I9, Rb: Rb + 1”. FIG. 6 is a diagram for explaining an instruction “stbp (Ra +), Rb: Rb + 1”. FIG. 4 is a diagram for explaining an instruction “stbp (Ra), Rb: Rb + 1”. FIG. 6 is a diagram for explaining an instruction “stbh (Ra +) I7, Rb”. FIG. 6 is a diagram illustrating an instruction “stbh (Ra +), Rb”. FIG. 6 is a diagram for explaining an instruction “stbh (Ra), Rb”. FIG. 6 is a diagram illustrating an instruction “stbhp (Ra +) I7, Rb: Rb + 1”. FIG. 6 is a diagram for explaining an instruction “stbhp (Ra +), Rb: Rb + 1”. FIG. 5 is a diagram illustrating an instruction “stbhp (Ra), Rb: Rb + 1”. FIG. 6 is a diagram for explaining an instruction “dpref (Ra, D8)”. FIG. 6 is a diagram for explaining an instruction “ldstb Rb, (Ra)”. FIG. 10 is a diagram for explaining an instruction “rd C0: C1, Rb, (D11)”. FIG. 6 is a diagram for explaining an instruction “rd C0: C1, Rb, (Ra, D5)”. FIG. 6 is a diagram for explaining an instruction “rd C0: C1, Rb, (Ra)”. FIG. 6 is a diagram for explaining an instruction “rd C0: C1, Rb2, (Ra2)”. FIG. 6 is a diagram for explaining an instruction “rd C2: C3, Rb, (Ra, D5)”. FIG. 6 is a diagram for explaining an instruction “rd C2: C3, Rb, (Ra)”. FIG. 6 is a diagram for explaining an instruction “rde C0: C1, Rb, (Ra, D5)”. FIG. 6 is a diagram for explaining an instruction “rde C0: C1, Rb, (Ra)”. FIG. 6 is a diagram for explaining an instruction “rde C2: C3, Rb, (Ra, D5)”. FIG. 6 is a diagram for explaining an instruction “rde C2: C3, Rb, (Ra)”. FIG. 6 is a diagram illustrating an instruction “wt C0: C1, (D11), Rb”. FIG. 6 is a diagram for explaining an instruction “wt C0: C1, (Ra, D5), Rb”. FIG. 6 is a diagram for explaining an instruction “wt C0: C1, (Ra), Rb”. FIG. 6 is a diagram illustrating an instruction “wt C0: C1, (Ra2), Rb2”. FIG. 10 is a diagram for explaining an instruction “wt C2: C3, (Ra, D5), Rb”. FIG. 6 is a diagram for explaining an instruction “wt C2: C3, (Ra), Rb”. FIG. 6 is a diagram for explaining an instruction “wte C0: C1, (Ra, D5), Rb”. FIG. 6 is a diagram illustrating an instruction “wte C0: C1, (Ra), Rb”. FIG. 6 is a diagram for explaining an instruction “wte C2: C3, (Ra, D5), Rb”. FIG. 6 is a diagram for explaining an instruction “wte C2: C3, (Ra), Rb”. It is a figure explaining instruction “br D20”. FIG. 11 is a diagram for explaining an instruction “br D9”. FIG. 10 is a diagram for explaining an instruction “brl D20”. FIG. 10 is a diagram for explaining an instruction “call D20”. FIG. 11 is a diagram for explaining an instruction “brl D9”. FIG. 10 is a diagram for explaining an instruction “call D9”. FIG. 6 is a diagram for explaining an instruction “jmp LR”. FIG. 6 is a diagram for explaining an instruction “jmp TAR”. FIG. 6 is a diagram for explaining an instruction “jmpl LR”. FIG. 6 is a diagram for explaining an instruction “call LR”. FIG. 6 is a diagram illustrating an instruction “jmpl TAR”. FIG. 6 is a diagram for explaining an instruction “call TAR”. FIG. 6 is a diagram for explaining an instruction “jmpr LR”. FIG. 6 is a diagram for explaining an instruction “ret”. FIG. 6 is a diagram for explaining an instruction “jmpf LR”. FIG. 6 is a diagram for explaining an instruction “jmpf C6, C2: C4, TAR”. FIG. 6 is a diagram for explaining an instruction “jmpf Cm, TAR”. FIG. 6 is a diagram for explaining an instruction “jmpf TAR”. FIG. 6 is a diagram illustrating an instruction “jloop C6, TAR, Ra, I8”. FIG. 6 is a diagram for explaining an instruction “jloop C6, TAR, Ra”. FIG. 6 is a diagram for explaining an instruction “jloop C6, TAR, Ra2”. FIG. 6 is a diagram for explaining an instruction “jloop C6, TAR, Ra2, −1”. FIG. 6 is a diagram for explaining an instruction “jloop C6, Cm, TAR, Ra, I8”. FIG. 6 is a diagram for explaining an instruction “jloop C6, Cm, TAR, Ra”. FIG. 6 is a diagram illustrating an instruction “jloop C6, Cm, TAR, Ra2”. FIG. 6 is a diagram for explaining an instruction “jloop C6, Cm, TAR, Ra2, −1”. FIG. 6 is a diagram for explaining an instruction “jloop C6, C2: C4, TAR, Ra, I8”. It is a figure explaining the instruction “jloop C6, C2: C4, TAR, Ra”. FIG. 10 is a diagram for explaining an instruction “jloop C6, C2: C4, TAR, Ra2”. FIG. 6 is a diagram for explaining an instruction “jloop C6, C2: C4, TAR, Ra2, −1”. FIG. 6 is a diagram for explaining an instruction “jloop C5, LR, Ra, I8”. FIG. 6 is a diagram for explaining an instruction “jloop C5, LR, Ra”. It is a figure explaining instruction “settar D9”. It is a figure explaining instruction “settar C6, Cm, D9”. FIG. 7 is a diagram for explaining an instruction “settar C6, D9”. FIG. 6 is a diagram illustrating an instruction “settar C6, C2: C4, D9”. FIG. 6 is a diagram for explaining an instruction “settar C6, C4, D9”. FIG. 10 is a diagram for explaining an instruction “setlr D9”. FIG. 7 is a diagram for explaining an instruction “setlr C5, D9”. FIG. 10 is a diagram for explaining an instruction “setbb TAR”. FIG. 10 is a diagram for explaining an instruction “setbb LR”. FIG. 10 is a diagram for explaining an instruction “intd”. FIG. 10 is a diagram for explaining an instruction “inte”. FIG. 6 is a diagram for explaining an instruction “vmpswd”. FIG. 6 is a diagram illustrating an instruction “vmpswe”. FIG. 6 is a diagram for explaining an instruction “vmpsleep”. FIG. 6 is a diagram for explaining an instruction “vmpwait”. FIG. 6 is a diagram illustrating an instruction “vmpsus”. FIG. 10 is a diagram for explaining an instruction “rti”. FIG. 6 is a diagram illustrating an instruction “piNl (pi0l, pi1l, pi2l, pi3l, pi4l, pi5l, pi6l, pi7l)”. FIG. 7 is a diagram for explaining an instruction “piN (pi0, pi1, pi2, pi3, pi4, pi5, pi6, pi7)”. FIG. 6 is a diagram for explaining an instruction “scN (sc0, sc1, sc2, sc3, sc4, sc5, sc6, sc7)”. FIG. 6 is a diagram for explaining an instruction “add Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “add Rc3, Ra3, Rb3”. FIG. 6 is a diagram for explaining an instruction “add Ra2, Rb2”. FIG. 6 is a diagram illustrating an instruction “add Rb, Ra, I12”. FIG. 6 is a diagram for explaining an instruction “add Ra2, I5”. FIG. 11 is a diagram for explaining an instruction “add SP, I19”. FIG. 10 is a diagram for explaining an instruction “add SP, I11”. FIG. 6 is a diagram illustrating an instruction “addu Rb, GP, I13”. FIG. 10 is a diagram for explaining an instruction “addu Rb, SP, I13”. FIG. 6 is a diagram for explaining an instruction “addu Ra3, SP, I6”. FIG. 6 is a diagram for explaining an instruction “addvw Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “addvh Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “addc Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “adds Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “addsr Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “s1add Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “s1add Rc3, Ra3, Rb3”. FIG. 6 is a diagram for explaining an instruction “s2add Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “s2add Rc3, Ra3, Rb3”. FIG. 6 is a diagram for explaining an instruction “addmsk Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “addarvw Rc, Ra, Rb”. FIG. 6 is a diagram illustrating an instruction “sub Rc, Rb, Ra”. FIG. 6 is a diagram illustrating an instruction “sub Rc3, Rb3, Ra3”. FIG. 6 is a diagram for explaining an instruction “sub Rb2, Ra2”. FIG. 6 is a diagram for explaining an instruction “sub Rb, Ra, I12”. FIG. 6 is a diagram for explaining an instruction “sub Ra2, I5”. FIG. 10 is a diagram for explaining an instruction “sub SP, I19”. FIG. 10 is a diagram for explaining an instruction “sub SP, I11”. FIG. 6 is a diagram for explaining an instruction “subc Rc, Rb, Ra”. FIG. 6 is a diagram illustrating an instruction “subvw Rc, Rb, Ra”. FIG. 6 is a diagram for explaining an instruction “subvh Rc, Rb, Ra”. FIG. 6 is a diagram illustrating an instruction “subs Rc, Rb, Ra”. FIG. 6 is a diagram for explaining an instruction “submsk Rc, Rb, Ra”. FIG. 6 is a diagram for explaining an instruction “rsub Rb, Ra, I8”. FIG. 6 is a diagram illustrating an instruction “rsub Ra2, I4”. FIG. 6 is a diagram for explaining an instruction “rsub Ra2, Rb2”. FIG. 6 is a diagram for explaining an instruction “neg Rb, Ra”. FIG. 6 is a diagram for explaining an instruction “neg Ra2”. FIG. 6 is a diagram illustrating an instruction “negvh Rb, Ra”. FIG. 6 is a diagram for explaining an instruction “negvw Rb, Ra”. FIG. 6 is a diagram for explaining an instruction “abs Rb, Ra”. FIG. 6 is a diagram illustrating an instruction “absvw Rb, Ra”. FIG. 5 is a diagram for explaining an instruction “absvh Rb, Ra”. FIG. 6 is a diagram for explaining an instruction “max Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “min Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “and Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “and Ra2, Rb2”. FIG. 6 is a diagram for explaining an instruction “and Rb, Ra, I8”. FIG. 6 is a diagram illustrating an instruction “andn Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “andn Ra2, Rb2”. FIG. 6 is a diagram for explaining an instruction “andn Rb, Ra, I8”. FIG. 6 is a diagram for explaining an instruction “or Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “or Ra2, Rb2”. FIG. 6 is a diagram for explaining an instruction “or Rb, Ra, I8”. FIG. 6 is a diagram for explaining an instruction “xor Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “xor Ra2, Rb2”. FIG. 6 is a diagram for explaining an instruction “xor Rb, Ra, I8”. FIG. 6 is a diagram for explaining an instruction “not Rb, Ra”. FIG. 6 is a diagram for explaining an instruction “not Ra2”. FIG. 6 is a diagram for explaining an instruction “cmpCC Cm, Ra, Rb”. FIG. 6 is a diagram illustrating an instruction “cmpCC C6, Ra2, Rb2”. FIG. 6 is a diagram for explaining an instruction “cmpCC”. FIG. 6 is a diagram for explaining an instruction “cmpCC C6, Ra2, I4”. FIG. 6 is a diagram for explaining an instruction “cmpCC”. FIG. 6 is a diagram for explaining an instruction “cmpCC”. FIG. 6 is a diagram for explaining an instruction “cmpCCn Cm, Ra, Rb, Cn”. FIG. 6 is a diagram for explaining an instruction “cmpCCn Cm, Ra, I5, Cn”. FIG. 6 is a diagram for explaining an instruction “cmpCCn Cm: Cm + 1, Ra, Rb, Cn”. FIG. 6 is a diagram for explaining an instruction “cmpCCn Cm: Cm + 1, Ra, I5, Cn”. FIG. 6 is a diagram for explaining an instruction “cmpCCa Cm: Cm + 1, Ra, Rb, Cn”. FIG. 6 is a diagram for explaining an instruction “cmpCCa Cm: Cm + 1, Ra, I5, Cn”. FIG. 6 is a diagram for explaining an instruction “cmpCCo Cm: Cm + 1, Ra, Rb, Cn”. FIG. 6 is a diagram for explaining an instruction “cmpCCo Cm: Cm + 1, Ra, I5, Cn”. FIG. 5 is a diagram for explaining an instruction “tstz Cm, Ra, Rb”. FIG. 6 is a diagram illustrating an instruction “tstz C6, Ra2, Rb2”. It is a figure explaining instruction “tstz Cm, Ra, I5”. FIG. 6 is a diagram illustrating an instruction “tstz C6, Ra2, I4”. FIG. 6 is a diagram for explaining an instruction “tstz Cm: Cm + 1, Ra, Rb”. FIG. 10 is a diagram for explaining an instruction “tstz Cm: Cm + 1, Ra, I5”. FIG. 6 is a diagram for explaining an instruction “tstzn Cm, Ra, Rb, Cn”. FIG. 6 is a diagram for explaining an instruction “tstzn Cm, Ra, I5, Cn”. FIG. 6 is a diagram for explaining an instruction “tstzn Cm: Cm + 1, Ra, Rb, Cn”. FIG. 6 is a diagram for explaining an instruction “tstzn Cm: Cm + 1, Ra, I5, Cn”. FIG. 6 is a diagram for explaining an instruction “tstza Cm: Cm + 1, Ra, Rb, Cn”. FIG. 5 is a diagram for explaining an instruction “tstza Cm: Cm + 1, Ra, I5, Cn”. FIG. 6 is a diagram for explaining an instruction “tstzo Cm: Cm + 1, Ra, Rb, Cn”. FIG. 6 is a diagram for explaining an instruction “tstzo Cm: Cm + 1, Ra, I5, Cn”. FIG. 6 is a diagram for explaining an instruction “tstn Cm, Ra, Rb”. FIG. 6 is a diagram illustrating an instruction “tstn C6, Ra2, Rb2”. FIG. 6 is a diagram for explaining an instruction “tstn Cm, Ra, I5”. FIG. 6 is a diagram illustrating an instruction “tstn C6, Ra2, I4”. FIG. 6 is a diagram for explaining an instruction “tstn Cm: Cm + 1, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “tstn Cm: Cm + 1, Ra, I5”. FIG. 6 is a diagram for explaining an instruction “tstnn Cm, Ra, Rb, Cn”. FIG. 10 is a diagram for explaining an instruction “tstnn Cm, Ra, I5, Cn”. FIG. 6 is a diagram for explaining an instruction “tstnn Cm: Cm + 1, Ra, Rb, Cn”. FIG. 6 is a diagram for explaining an instruction “tstnn Cm: Cm + 1, Ra, I5, Cn”. FIG. 6 is a diagram for explaining an instruction “tstna Cm: Cm + 1, Ra, Rb, Cn”. FIG. 6 is a diagram for explaining an instruction “tstna Cm: Cm + 1, Ra, I5, Cn”. FIG. 6 is a diagram for explaining an instruction “tstno Cm: Cm + 1, Ra, Rb, Cn”. FIG. 6 is a diagram for explaining an instruction “tstno Cm: Cm + 1, Ra, I5, Cn”. FIG. 6 is a diagram for explaining an instruction “mov Rb, Ra”. FIG. 6 is a diagram for explaining an instruction “mov Ra2, Rb”. FIG. 6 is a diagram for explaining an instruction “mov Ra, I16”. FIG. 6 is a diagram for explaining an instruction “mov Ra2, I8”. FIG. 6 is a diagram for explaining an instruction “mov Rb, TAR”. FIG. 6 is a diagram for explaining an instruction “mov Rb2, TAR”. FIG. 6 is a diagram for explaining an instruction “mov Rb, LR”. FIG. 10 is a diagram for explaining an instruction “mov Rb2, LR”. It is a figure explaining instruction “mov Rb, SVR”. FIG. 6 is a diagram for explaining an instruction “mov Rb, PSR”. FIG. 6 is a diagram for explaining an instruction “mov Rb, CFR”. FIG. 6 is a diagram for explaining an instruction “mov Rb, MH0”. FIG. 6 is a diagram for explaining an instruction “mov Rb2, MH0”. FIG. 6 is a diagram for explaining an instruction “mov Rb, MH1”. FIG. 6 is a diagram for explaining an instruction “mov Rb2, MH1”. FIG. 6 is a diagram for explaining an instruction “mov Rb, ML0”. FIG. 6 is a diagram for explaining an instruction “mov Rb, ML1”. FIG. 10 is a diagram for explaining an instruction “mov Rb, IPC”. FIG. 6 is a diagram for explaining an instruction “mov Rb, IPSR”. FIG. 6 is a diagram for explaining an instruction “mov Rb, PC”. FIG. 6 is a diagram for explaining an instruction “mov Rb, EPC”. FIG. 6 is a diagram for explaining an instruction “mov Rb, EPSR”. FIG. 6 is a diagram illustrating an instruction “mov Rb, PSR0”. FIG. 6 is a diagram for explaining an instruction “mov Rb, PSR1”. FIG. 6 is a diagram illustrating an instruction “mov Rb, PSR2”. FIG. 10 is a diagram for explaining an instruction “mov Rb, PSR3”. FIG. 10 is a diagram illustrating an instruction “mov Rb, CFR0”. FIG. 6 is a diagram for explaining an instruction “mov Rb, CFR1”. FIG. 6 is a diagram illustrating an instruction “mov Rb, CFR2”. FIG. 10 is a diagram for explaining an instruction “mov Rb, CFR3”. FIG. 6 is a diagram for explaining an instruction “mov LR, Rb”. FIG. 6 is a diagram for explaining an instruction “mov LR, Rb2”. FIG. 6 is a diagram for explaining an instruction “mov TAR, Rb”. FIG. 6 is a diagram for explaining an instruction “mov TAR, Rb2”. FIG. 6 is a diagram for explaining an instruction “mov SVR, Rb”. FIG. 6 is a diagram for explaining an instruction “mov PSR, Rb”. FIG. 6 is a diagram for explaining an instruction “mov CFR, Rb”. FIG. 10 is a diagram for explaining an instruction “mov MH0, Rb”. FIG. 6 is a diagram for explaining an instruction “mov MH0, Rb2”. FIG. 6 is a diagram for explaining an instruction “mov MH1, Rb”. FIG. 6 is a diagram for explaining an instruction “mov MH1, Rb2”. FIG. 10 is a diagram for explaining an instruction “mov ML0, Rb”. FIG. 6 is a diagram for explaining an instruction “mov ML1, Rb”. FIG. 6 is a diagram for explaining an instruction “mov IPC, Rb”. FIG. 10 is a diagram for explaining an instruction “mov IPSR, Rb”. FIG. 6 is a diagram for explaining an instruction “mov EPC, Rb”. FIG. 6 is a diagram for explaining an instruction “mov EPSR, Rb”. FIG. 6 is a diagram for explaining an instruction “mov PSR0, Rb”. FIG. 6 is a diagram for explaining an instruction “mov PSR1, Rb”. FIG. 6 is a diagram for explaining an instruction “mov PSR2, Rb”. FIG. 6 is a diagram for explaining an instruction “mov PSR3, Rb”. FIG. 10 is a diagram illustrating an instruction “mov CFR0, Rb”. FIG. 6 is a diagram for explaining an instruction “mov CFR1, Rb”. FIG. 10 is a diagram for explaining an instruction “mov CFR2, Rb”. FIG. 6 is a diagram for explaining an instruction “mov CFR3, Rb”. FIG. 6 is a diagram for explaining an instruction “mvclovs Cm: Cm + 1”. It is a figure explaining the instruction “movcf Ci, Cj, Cm, Cn”. FIG. 10 is a diagram for explaining an instruction “mvclcas Cm: Cm + 1”. FIG. 11 is a diagram for explaining an instruction “sethi Ra, I16”. FIG. 6 is a diagram for explaining an instruction “setlo Ra, I16”. FIG. 6 is a diagram for explaining an instruction “vcchk”. FIG. 10 is a diagram for explaining an instruction “nop”. FIG. 6 is a diagram for explaining an instruction “asl Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “asl Rb, Ra, I5”. FIG. 6 is a diagram for explaining an instruction “asl Ra2, I4”. FIG. 7 is a diagram for explaining an instruction “aslvw Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “aslvw Rb, Ra, I5”. FIG. 6 is a diagram for explaining an instruction “aslvh Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “aslvh Rb, Ra, I5”. FIG. 6 is a diagram for explaining an instruction “asr Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “asr Rb, Ra, I5”. FIG. 6 is a diagram for explaining an instruction “asr Ra2, I4”. FIG. 6 is a diagram illustrating an instruction “asrvw Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “asrvh Rc, Ra, Rb”. FIG. 10 is a diagram for explaining an instruction “lsl Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “lsl Rc, Ra, I5”. FIG. 6 is a diagram illustrating an instruction “lsl Ra2, I4”. FIG. 6 is a diagram for explaining an instruction “lsr Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “lsr Rb, Ra, I5”. It is a figure explaining command "rol Rc, Ra, Rb". It is a figure explaining command "rol Rb, Ra, I5". FIG. 6 is a diagram for explaining an instruction “ror Rb, Ra, I5”. FIG. 6 is a diagram for explaining an instruction “aslp Mm, Ra, Mn, Rb”. FIG. 6 is a diagram for explaining an instruction “aslp Mm, Rb, Mn, I6”. FIG. 6 is a diagram for explaining an instruction “aslp Mm, Rc, MHn, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “aslp Mm, Rb, MHn, Ra, I6”. FIG. 6 is a diagram for explaining an instruction “aslpvw Mm, Ra, Mn, Rb”. FIG. 6 is a diagram for explaining an instruction “aslpvw Mm, Rb, Mn, I6”. FIG. 6 is a diagram for explaining an instruction “asrp Mm, Ra, Mn, Rb”. FIG. 6 is a diagram illustrating an instruction “asrp Mm, Rb, Mn, I6”. FIG. 6 is a diagram for explaining an instruction “asrp Mm, Rc, MHn, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “asrp Mm, Rb, MHn, Ra, I6”. FIG. 5 is a diagram for explaining an instruction “asrpvw Mm, Ra, Mn, Rb”. FIG. 6 is a diagram for explaining an instruction “lslp Mm, Ra, Mn, Rb”. FIG. 6 is a diagram for explaining an instruction “lslp Mm, Rb, Mn, I6”. FIG. 6 is a diagram for explaining an instruction “lslp Mm, Rc, MHn, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “lslp Mm, Rb, MHn, Ra, I6”. FIG. 6 is a diagram for explaining an instruction “lsrp Mm, Ra, Mn, Rb”. FIG. 6 is a diagram for explaining an instruction “lsrp Mm, Rb, Mn, I6”. FIG. 6 is a diagram for explaining an instruction “lsrp Mm, Rc, MHn, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “lsrp Mm, Rb, MHn, Ra, I6”. FIG. 6 is a diagram illustrating an instruction “extr Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “extr Rb, Ra, Ib5, Ia5”. FIG. 10 is a diagram for explaining an instruction “ext Rb, Ra, I5”. FIG. 10 is a diagram for explaining an instruction “exth Ra2”. FIG. 6 is a diagram for explaining an instruction “extb Ra2”. FIG. 6 is a diagram for explaining an instruction “extru Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “extru Rb, Ra, Ib5, Ia5”. FIG. 6 is a diagram illustrating an instruction “extu Rb, Ra, I5”. It is a figure explaining instruction "exthu Ra2". It is a figure explaining instruction “extbu Ra2”. FIG. 6 is a diagram for explaining an instruction “mskgen Rc, Rb”. FIG. 6 is a diagram illustrating an instruction “mskgen Rb, Ib5, Ia5”. FIG. 6 is a diagram for explaining an instruction “msk Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “msk Rb, Ra, Ib5, Ia5”. FIG. 6 is a diagram for explaining an instruction “satw Mm, Rb, Mn”. FIG. 10 is a diagram for explaining an instruction “sath Rb, Ra”. FIG. 6 is a diagram for explaining an instruction “sat12 Rb, Ra”. FIG. 6 is a diagram for explaining an instruction “sat9 Rb, Ra”. FIG. 6 is a diagram for explaining an instruction “satb Rb, Ra”. FIG. 6 is a diagram for explaining an instruction “satbu Rb, Ra”. FIG. 6 is a diagram for explaining an instruction “extw Mm, Rb, Ra”. FIG. 6 is a diagram for explaining an instruction “vintllh Rc, Ra, Rb”. FIG. 6 is a diagram illustrating an instruction “vintlhh Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vintllb Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vintlhb Rc, Ra, Rb”. FIG. 6 is a diagram illustrating an instruction “valn Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “valn1 Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “valn2 Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “valn3 Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “valnvc1 Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “valnvc2 Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “valnvc3 Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “valnvc4 Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vxchngh Rb, Ra”. FIG. 6 is a diagram for explaining an instruction “byterev Rb, Ra”. FIG. 6 is a diagram illustrating an instruction “vstovb Rb, Ra”. FIG. 6 is a diagram for explaining an instruction “vstovh Rb, Ra”. FIG. 6 is a diagram for explaining an instruction “vlunpkh Rb: Rb + 1, Ra”. FIG. 6 is a diagram for explaining an instruction “vlunpkhu Rb: Rb + 1, Ra”. FIG. 6 is a diagram illustrating an instruction “vlunpkb Rb: Rb + 1, Ra”. FIG. 6 is a diagram illustrating an instruction “vlunpkbu Rb: Rb + 1, Ra”. It is a figure explaining instruction “vhunpkh Rb: Rb + 1, Ra”. FIG. 6 is a diagram for explaining an instruction “vhunpkb Rb: Rb + 1, Ra”. FIG. 6 is a diagram illustrating an instruction “vunpk1 Rb, Mn”. FIG. 6 is a diagram illustrating an instruction “vunpk2 Rb, Mn”. FIG. 6 is a diagram for explaining an instruction “vlpkh Rc, Rb, Ra”. FIG. 6 is a diagram illustrating an instruction “vlpkhu Rc, Rb, Ra”. FIG. 6 is a diagram illustrating an instruction “vlpkb Rc, Rb, Ra”. FIG. 6 is a diagram illustrating an instruction “vlpkbu Rc, Rb, Ra”. It is a figure explaining instruction “vhpkh Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vhpkb Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vexth Mm, Rb, Ra”. FIG. 6 is a diagram for explaining an instruction “bseq0 Rb, Ra”. FIG. 6 is a diagram for explaining an instruction “bseq1 Rb, Ra”. FIG. 6 is a diagram for explaining an instruction “bseq Rb, Ra”. FIG. 6 is a diagram for explaining an instruction “bcnt1 Rb, Ra”. FIG. 6 is a diagram for explaining an instruction “rndvh Rb, Ra”. FIG. 6 is a diagram for explaining an instruction “mskbrvb Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “mskbrvh Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “movp Rc: Rc + 1, Ra, Rb”. It is a figure explaining the instruction “hmul Mm, Rc, Ra, Rb”. FIG. 6 is a diagram illustrating an instruction “lmul Mm, Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “fmulhh Mm, Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “fmulhhr Mm, Rc, Ra, Rb”. FIG. 6 is a diagram illustrating an instruction “fmulhw Mm, Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “fmulhww Mm, Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “mul Mm, Rc, Ra, Rb”. FIG. 7 is a diagram for explaining an instruction “mul Mm, Rb, Ra, I8”. It is a figure explaining instruction "mulu Mm, Rc, Ra, Rb". FIG. 10 is a diagram for explaining an instruction “mulu Mm, Rb, Ra, I8”. FIG. 6 is a diagram for explaining an instruction “fmulww Mm, Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “hmac Mm, Rc, Ra, Rb, Mn”. FIG. 6 is a diagram for explaining an instruction “hmac M0, Rc, Ra, Rb, Rx”. FIG. 6 is a diagram for explaining an instruction “lmac Mm, Rc, Ra, Rb, Mn”. FIG. 6 is a diagram for explaining an instruction “lmac M0, Rc, Ra, Rb, Rx”. FIG. 6 is a diagram for explaining an instruction “fmachh Mm, Rc, Ra, Rb, Mn”. FIG. 6 is a diagram for explaining an instruction “fmachh M0, Rc, Ra, Rb, Rx”. FIG. 6 is a diagram for explaining an instruction “fmachhr Mm, Rc, Ra, Rb, Mn”. FIG. 6 is a diagram for explaining an instruction “fmachhr M0, Rc, Ra, Rb, Rx”. FIG. 6 is a diagram for explaining an instruction “fmachw Mm, Rc, Ra, Rb, Mn”. FIG. 6 is a diagram for explaining an instruction “fmachw M0, Rc, Ra, Rb, Rx”. FIG. 6 is a diagram for explaining an instruction “fmachww Mm, Rc, Ra, Rb, Mn”. FIG. 6 is a diagram for explaining an instruction “fmachww M0, Rc, Ra, Rb, Rx”. FIG. 6 is a diagram for explaining an instruction “mac Mm, Rc, Ra, Rb, Mn”. FIG. 6 is a diagram for explaining an instruction “mac M0, Rc, Ra, Rb, Rx”. FIG. 6 is a diagram for explaining an instruction “fmacww Mm, Rc, Ra, Rb, Mn”. FIG. 6 is a diagram for explaining an instruction “fmacww M0, Rc, Ra, Rb, Rx”. FIG. 6 is a diagram for explaining an instruction “hmsu Mm, Rc, Ra, Rb, Mn”. FIG. 6 is a diagram illustrating an instruction “hmsu M0, Rc, Ra, Rb, Rx”. FIG. 6 is a diagram illustrating an instruction “lmsu Mm, Rc, Ra, Rb, Mn”. FIG. 4 is a diagram for explaining an instruction “lmsu M0, Rc, Ra, Rb, Rx”. FIG. 6 is a diagram for explaining an instruction “fmsuhh Mm, Rc, Ra, Rb, Mn”. FIG. 6 is a diagram for explaining an instruction “fmsuhh M0, Rc, Ra, Rb, Rx”. FIG. 6 is a diagram for explaining an instruction “fmsuhhr Mm, Rc, Ra, Rb, Mn”. FIG. 6 is a diagram for explaining an instruction “fmsuhhr M0, Rc, Ra, Rb, Rx”. FIG. 6 is a diagram for explaining an instruction “fmsuhw Mm, Rc, Ra, Rb, Mn”. FIG. 6 is a diagram for explaining an instruction “fmsuhw M0, Rc, Ra, Rb, Rx”. FIG. 6 is a diagram for explaining an instruction “fmsuhww Mm, Rc, Ra, Rb, Mn”. FIG. 6 is a diagram for explaining an instruction “fmsuhww M0, Rc, Ra, Rb, Rx”. FIG. 6 is a diagram for explaining an instruction “msu Mm, Rc, Ra, Rb, Mn”. FIG. 6 is a diagram for explaining an instruction “msu M0, Rc, Ra, Rb, Rx”. FIG. 6 is a diagram for explaining an instruction “fmsuww Mm, Rc, Ra, Rb, Mn”. FIG. 6 is a diagram for explaining an instruction “fmsuww M0, Rc, Ra, Rb, Rx”. FIG. 6 is a diagram for explaining an instruction “div MHm, Rc, MHn, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “divu MHm, Rc, MHn, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “dbgm0”. FIG. 6 is a diagram for explaining an instruction “dbgm1”. FIG. 10 is a diagram for explaining an instruction “dbgm2 I15”. It is a figure explaining instruction "dbgm3 I15". FIG. 6 is a diagram for explaining an instruction “vaddh Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vxaddh Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vhaddh Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vladdh Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vaddhvh Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vxaddhvh Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vhaddhvh Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vladdhvh Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vsaddh Rb, Ra, I8”. FIG. 6 is a diagram for explaining an instruction “vaddsh Rc, Ra, Rb”. FIG. 6 is a diagram illustrating an instruction “vaddsrh Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vaddhvc Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vaddrhvc Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vaddb Rc, Ra, Rb”. FIG. 6 is a diagram illustrating an instruction “vsaddb Rb, Ra, I8”. FIG. 6 is a diagram illustrating an instruction “vaddsb Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vaddsrb Rc, Ra, Rb”. FIG. 6 is a diagram illustrating an instruction “vsubh Rc, Rb, Ra”. FIG. 6 is a diagram for explaining an instruction “vxsubh Rc, Rb, Ra”. FIG. 6 is a diagram illustrating an instruction “vhsubh Rc, Rb, Ra”. FIG. 6 is a diagram illustrating an instruction “vlsubh Rc, Rb, Ra”. FIG. 6 is a diagram illustrating an instruction “vsubhvh Rc, Rb, Ra”. FIG. 6 is a diagram illustrating an instruction “vxsubhvh Rc, Rb, Ra”. FIG. 6 is a diagram for explaining an instruction “vhsubhvh Rc, Rb, Ra”. FIG. 6 is a diagram illustrating an instruction “vlsubhvh Rc, Rb, Ra”. FIG. 6 is a diagram for explaining an instruction “vssubh Rb, Ra, I8”. FIG. 6 is a diagram illustrating an instruction “vsubb Rc, Rb, Ra”. FIG. 6 is a diagram for explaining an instruction “vssubb Rb, Ra, I8”. FIG. 6 is a diagram illustrating an instruction “vsubsh Rc, Rb, Ra”. FIG. 6 is a diagram for explaining an instruction “vsrsubh Rb, Ra, I8”. FIG. 6 is a diagram for explaining an instruction “vsrsubb Rb, Ra, I8”. FIG. 6 is a diagram illustrating an instruction “vsumh Rb, Ra”. FIG. 6 is a diagram illustrating an instruction “vsumh2 Rb, Ra”. FIG. 6 is a diagram illustrating an instruction “vsumrh2 Rb, Ra”. FIG. 6 is a diagram for explaining an instruction “vnegh Rb, Ra”. FIG. 6 is a diagram for explaining an instruction “vneghvh Rb, Ra”. FIG. 6 is a diagram for explaining an instruction “vnegb Rb, Ra”. FIG. 6 is a diagram for explaining an instruction “vabshvh Rb, Ra”. It is a figure explaining instruction "vasubb Rc, Rb, Ra". FIG. 6 is a diagram illustrating an instruction “vsgnh Rb, Ra”. FIG. 6 is a diagram for explaining an instruction “vmaxh Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vmaxb Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vminh Rc, Ra, Rb”. FIG. 5 is a diagram for explaining an instruction “vminb Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vsel Rc, Ra, Rb”. FIG. 6 is a diagram illustrating an instruction “vmovt Rb, Ra”. FIG. 6 is a diagram for explaining an instruction “vscmpeqb Ra, I5”. FIG. 6 is a diagram for explaining an instruction “vscmpneb Ra, I5”. FIG. 6 is a diagram for explaining an instruction “vscmpgtb Ra, I5”. FIG. 6 is a diagram for explaining an instruction “vscmpleb Ra, I5”. It is a figure explaining instruction “vscmpgeb Ra, I5”. FIG. 6 is a diagram illustrating an instruction “vscmpltb Ra, I5”. FIG. 6 is a diagram illustrating an instruction “vscmpeqh Ra, I5”. FIG. 6 is a diagram for explaining an instruction “vscmpneh Ra, I5”. FIG. 6 is a diagram for explaining an instruction “vscmpgth Ra, I5”. FIG. 6 is a diagram illustrating an instruction “vscmpleh Ra, I5”. It is a figure explaining instruction “vscmpgeh Ra, I5”. FIG. 6 is a diagram for explaining an instruction “vscmplth Ra, I5”. FIG. 6 is a diagram for explaining an instruction “vcmpeqh Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vcmpneh Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vcmpgth Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vcmpleh Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vcmpgeh Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vcmplth Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vcmpeqb Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vcmpneb Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vcmpgtb Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vcmpleb Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vcmpgeb Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vcmpltb Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vaslh Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vaslh Rb, Ra, I4”. FIG. 6 is a diagram for explaining an instruction “vaslvh Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vaslvh Rb, Ra, I4”. FIG. 6 is a diagram for explaining an instruction “vasrh Rb, Ra, I4”. FIG. 6 is a diagram for explaining an instruction “vasrvh Rc, Ra, Rb”. FIG. 6 is a diagram illustrating an instruction “vlslh Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vlslh Rb, Ra, I4”. FIG. 6 is a diagram for explaining an instruction “vlsrh Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vlsrh Rb, Ra, I4”. FIG. 5 is a diagram for explaining an instruction “vrolh Rc, Ra, Rb”. It is a figure explaining command "vrolh Rb, Ra, I4". FIG. 6 is a diagram for explaining an instruction “vrorh Rb, Ra, I4”. FIG. 6 is a diagram for explaining an instruction “vasrh Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vaslb Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vaslb Rb, Ra, I3”. FIG. 6 is a diagram for explaining an instruction “vasrb Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vasrb Rb, Ra, I3”. FIG. 6 is a diagram for explaining an instruction “vlslb Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vlslb Rb, Ra, I3”. FIG. 6 is a diagram for explaining an instruction “vlsrb Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vlsrb Rb, Ra, I3”. FIG. 5 is a diagram for explaining an instruction “vrolb Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vrolb Rb, Ra, I3”. FIG. 6 is a diagram for explaining an instruction “vrorb Rb, Ra, I3”. FIG. 6 is a diagram for explaining an instruction “vasl Mm, Ra, Mn, Rb”. FIG. 6 is a diagram for explaining an instruction “vasl Mm, Rb, Mn, I5”. FIG. 6 is a diagram for explaining an instruction “vaslvw Mm, Ra, Mn, Rb”. FIG. 6 is a diagram for explaining an instruction “vaslvw Mm, Rb, Mn, I5”. FIG. 6 is a diagram for explaining an instruction “vasr Mm, Ra, Mn, Rb”. FIG. 6 is a diagram for explaining an instruction “vasr Mm, Rb, Mn, I5”. FIG. 6 is a diagram for explaining an instruction “vasrvw Mm, Ra, Mn, Rb”. FIG. 6 is a diagram for explaining an instruction “vlsl Mm, Ra, Mn, Rb”. FIG. 6 is a diagram for explaining an instruction “vlsl Mm, Rb, Mn, I5”. FIG. 6 is a diagram for explaining an instruction “vlsr Mm, Ra, Mn, Rb”. FIG. 6 is a diagram for explaining an instruction “vlsr Mm, Rb, Mn, I5”. FIG. 6 is a diagram illustrating an instruction “vsath Mm, Rb, Mn”. FIG. 6 is a diagram for explaining an instruction “vsath12 Rb, Ra”. FIG. 6 is a diagram for explaining an instruction “vsath9 Rb, Ra”. FIG. 6 is a diagram for explaining an instruction “vsath8 Rb, Ra”. It is a figure explaining instruction “vsath8u Rb, Ra”. FIG. 6 is a diagram for explaining an instruction “vrndvh Rb, Mn”. FIG. 6 is a diagram illustrating an instruction “vabssumb Rc, Ra, Rb”. FIG. 10 is a diagram for explaining an instruction “vmul Mm, Rc, Ra, Rb”. FIG. 6 is a diagram illustrating an instruction “vxmul Mm, Rc, Ra, Rb”. FIG. 6 is a diagram illustrating an instruction “vhmul Mm, Rc, Ra, Rb”. FIG. 10 is a diagram for explaining an instruction “vlmul Mm, Rc, Ra, Rb”. FIG. 10 is a diagram for explaining an instruction “vfmulh Mm, Rc, Ra, Rb”. FIG. 6 is a diagram illustrating an instruction “vxfmulh Mm, Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vhfmulh Mm, Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vlfmulh Mm, Rc, Ra, Rb”. FIG. 6 is a diagram illustrating an instruction “vfmulhr Mm, Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vxfmulhr Mm, Rc, Ra, Rb”. FIG. 6 is a diagram illustrating an instruction “vhfmulhr Mm, Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vlfmulhr Mm, Rc, Ra, Rb”. FIG. 10 is a diagram for explaining an instruction “vfmulw Mm, Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vxfmulw Mm, Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vhfmulw Mm, Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vlfmulw Mm, Rc, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vpfmulhww Mm, Rc: Rc + 1, Ra, Rb”. FIG. 6 is a diagram for explaining an instruction “vmac Mm, Rc, Ra, Rb, Mn”. FIG. 6 is a diagram for explaining an instruction “vmac M0, Rc, Ra, Rb, Rx”. FIG. 6 is a diagram for explaining an instruction “vxmac Mm, Rc, Ra, Rb, Mn”. FIG. 6 is a diagram for explaining an instruction “vxmac M0, Rc, Ra, Rb, Rx”. FIG. 5 is a diagram for explaining an instruction “vhmac Mm, Rc, Ra, Rb, Mn”. FIG. 6 is a diagram for explaining an instruction “vhmac M0, Rc, Ra, Rb, Rx”. FIG. 6 is a diagram for explaining an instruction “vlmac Mm, Rc, Ra, Rb, Mn”. FIG. 6 is a diagram for explaining an instruction “vlmac M0, Rc, Ra, Rb, Rx”. FIG. 6 is a diagram illustrating an instruction “vfmach Mm, Rc, Ra, Rb, Mn”. FIG. 6 is a diagram for explaining an instruction “vfmach M0, Rc, Ra, Rb, Rx”. FIG. 6 is a diagram illustrating an instruction “vxfmach Mm, Rc, Ra, Rb, Mn”. FIG. 6 is a diagram illustrating an instruction “vxfmach M0, Rc, Ra, Rb, Rx”. FIG. 6 is a diagram illustrating an instruction “vhfmach Mm, Rc, Ra, Rb, Mn”. FIG. 6 is a diagram for explaining an instruction “vhfmach M0, Rc, Ra, Rb, Rx”. FIG. 6 is a diagram for explaining an instruction “vlfmach Mm, Rc, Ra, Rb, Mn”. FIG. 6 is a diagram for explaining an instruction “vlfmach M0, Rc, Ra, Rb, Rx”. FIG. 6 is a diagram for explaining an instruction “vfmachr Mm, Rc, Ra, Rb, Mn”. FIG. 6 is a diagram for explaining an instruction “vfmachr M0, Rc, Ra, Rb, Rx”. FIG. 6 is a diagram for explaining an instruction “vxfmachr Mm, Rc, Ra, Rb, Mn”. FIG. 6 is a diagram for explaining an instruction “vxfmachr M0, Rc, Ra, Rb, Rx”. FIG. 6 is a diagram for explaining an instruction “vhfmachr Mm, Rc, Ra, Rb, Mn”. FIG. 6 is a diagram for explaining an instruction “vhfmachr M0, Rc, Ra, Rb, Rx”. FIG. 6 is a diagram for explaining an instruction “vlfmachr Mm, Rc, Ra, Rb, Mn”. FIG. 6 is a diagram for explaining an instruction “vlfmachr M0, Rc, Ra, Rb, Rx”. FIG. 6 is a diagram for explaining an instruction “vfmacw Mm, Rc, Ra, Rb, Mn”. FIG. 6 is a diagram for explaining an instruction “vxfmacw Mm, Rc, Ra, Rb, Mn”. FIG. 6 is a diagram for explaining an instruction “vhfmacw Mm, Rc, Ra, Rb, Mn”. FIG. 5 is a diagram for explaining an instruction “vlfmacw Mm, Rc, Ra, Rb, Mn”. FIG. 6 is a diagram for explaining an instruction “vpfmachww Mm, Rc: Rc + 1, Ra, Rb, Mn”. FIG. 6 is a diagram for explaining an instruction “vmsu Mm, Rc, Ra, Rb, Mn”. FIG. 6 is a diagram for explaining an instruction “vmsu M0, Rc, Ra, Rb, Rx”. FIG. 6 is a diagram for explaining an instruction “vxmsu Mm, Rc, Ra, Rb, Mn”. FIG. 6 is a diagram for explaining an instruction “vxmsu M0, Rc, Ra, Rb, Rx”. FIG. 6 is a diagram for explaining an instruction “vhmsu Mm, Rc, Ra, Rb, Mn”. FIG. 6 is a diagram for explaining an instruction “vhmsu M0, Rc, Ra, Rb, Rx”. FIG. 6 is a diagram for explaining an instruction “vlmsu Mm, Rc, Ra, Rb, Mn”. FIG. 6 is a diagram for explaining an instruction “vlmsu M0, Rc, Ra, Rb, Rx”. FIG. 6 is a diagram for explaining an instruction “vfmsuh Mm, Rc, Ra, Rb, Mn”. FIG. 6 is a diagram for explaining an instruction “vfmsuh M0, Rc, Ra, Rb, Rx”. FIG. 7 is a diagram for explaining an instruction “vxfmsuh Mm, Rc, Ra, Rb, Mn”. FIG. 6 is a diagram for explaining an instruction “vxfmsuh M0, Rc, Ra, Rb, Rx”. FIG. 6 is a diagram for explaining an instruction “vhfmsuh Mm, Rc, Ra, Rb, Mn”. FIG. 6 is a diagram for explaining an instruction “vhfmsuh M0, Rc, Ra, Rb, Rx”. FIG. 6 is a diagram for explaining an instruction “vlfmsuh Mm, Rc, Ra, Rb, Mn”. FIG. 6 is a diagram for explaining an instruction “vlfmsuh M0, Rc, Ra, Rb, Rx”. FIG. 6 is a diagram for explaining an instruction “vfmsuw Mm, Rc, Ra, Rb, Mn”. FIG. 6 is a diagram for explaining an instruction “vxfmsuw Mm, Rc, Ra, Rb, Mn”. FIG. 6 is a diagram for explaining an instruction “vhfmsuw Mm, Rc, Ra, Rb, Mn”. FIG. 6 is a diagram for explaining an instruction “vlfmsuw Mm, Rc, Ra, Rb, Mn”.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Processor 10 Instruction control part 10a Instruction cache 10b Address management part 10c-10e Instruction buffer 10f Jump buffer 10g Rotation part 20 Decoding part 30 Register file 30a General-purpose register (R0-R31)
30b Accumulator (MH, ML)
30c Link register (LR)
30d Branch register (TAR)
31 Program status register (PSR)
32 Condition flag register (CFR)
33 Program counter (PC)
34 PC save register (IPC)
35 PSR save register (IPSR)
40 arithmetic units 41 to 43 arithmetic logic / comparison arithmetic unit 41a ALU unit 41b saturation processing unit 41c flag unit 44 product-sum arithmetic unit 44a, 44b multiplier 44c-44e adder 44f selector 44g saturation processing unit 45 barrel shifter 45a, 45b selector 45c Upper barrel shifter 45d Lower barrel shifter 45e Saturation processing section 46 Divider 47 Converter 47a SAT block 47b BSEQ block 47c MSKGEN block 47d VSUMB block 47e BCNT block 47f IL block 50 I / F section 60 Instruction memory section 70 Data memory section 80 Extension register section 90 I / O interface

Claims (14)

A processor that executes SIMD type instructions that operate on a plurality of data with one instruction,
Decoding means for decoding instructions;
An execution means for executing an instruction based on the result of decoding by the decoding means;
The execution means includes an instruction code designating an operation type, a first operand designating a first data group consisting of a sequence of n (≧ 2) data, and a second data group consisting of a sequence of n data. When a SIMD type instruction including a second operand to be specified is decoded by the decoding means, the i-th data and the second data group in the sequence of n data constituting the first data group are Performing an operation specified by the instruction code on each of the n sets of j-th data in an array of n data constituting the data;
The processor is characterized in that i = 1, 2,..., N, and j = constant. N is 2;
The first data group includes first data and second data,
The second data group includes first data and second data,
The execution means performs the calculation on a set of the first data of the first data group and the first data of the second data group, and the second data and second of the first data group. The processor according to claim 1, wherein the calculation is performed on a set of the data group and the first data. N is 2;
The first data group includes first data and second data,
The second data group includes first data and second data,
The execution means performs the calculation on a set of the first data of the first data group and the second data of the second data group, and the second data and the second data of the first data group. The processor according to claim 1, wherein the calculation is performed on a set of the data group and the second data. N is 2;
The first data group includes first data and second data,
The second data group includes first data and second data,
The execution means includes
When the first instruction is decoded by the decoding means, the calculation is performed on a set of the first data of the first data group and the first data of the second data group, and the first data Performing the operation on the set of the second data of the group and the first data of the second data group,
When the second instruction is decoded by the decoding means, the calculation is performed on a set of the first data of the first data group and the second data of the second data group, and the first data The processor according to claim 1, wherein the calculation is performed on a set of second data of the group and second data of the second data group. The type of operation specified by the instruction code is multiplication, sum of products or product difference,
The instruction includes a third operand designating third data for storing a result of the operation,
The said execution means stores the low-order part of each result obtained by performing the said calculation with respect to said two sets in said 3rd data. The one of Claims 2-4 characterized by the above-mentioned. Processor. The type of operation specified by the instruction code is multiplication, sum of products or product difference,
The instruction includes a third operand designating third data for storing a result of the operation,
The said execution means stores the high-order part of each result obtained by performing the said calculation with respect to said two sets in said 3rd data. The one of Claims 2-4 characterized by the above-mentioned. Processor. The type of operation specified by the instruction code is multiplication, sum of products or product difference,
The instruction includes a third operand designating third data for storing a result of the operation,
5. The method according to claim 2, wherein the execution unit stores one of two results obtained by performing the calculation on the two sets in the third data. The processor described. N is 4;
The first data group includes a sequence of first to fourth data,
The second data group consists of a sequence of first to fourth data,
The execution means includes a set of the first data of the first data group and the first data of the second data group, the second data of the first data group and the first data of the second data group, A set of the third data of the first data group and the first data of the second data group, and the fourth data of the first data group and the first data of the second data group, The processor according to claim 1, wherein the calculation is performed on a set of N is 4;
The first data group includes a sequence of first to fourth data,
The second data group consists of a sequence of first to fourth data,
The execution means includes a set of first data of the first data group and second data of the second data group, second data of the first data group, and second data of the second data group, A set of the third data of the first data group and the second data of the second data group, and the fourth data of the first data group and the second data of the second data group, The processor according to claim 1, wherein the calculation is performed on a set of N is 4;
The first data group includes a sequence of first to fourth data,
The second data group consists of a sequence of first to fourth data,
The execution means includes a set of first data of the first data group and third data of the second data group, second data of the first data group, and third data of the second data group, A set of the third data of the first data group and the third data of the second data group, and the fourth data of the first data group and the third data of the second data group, The processor according to claim 1, wherein the calculation is performed on a set of N is 4;
The first data group includes a sequence of first to fourth data,
The second data group consists of a sequence of first to fourth data,
The execution means includes a set of the first data of the first data group and the fourth data of the second data group, the second data of the first data group and the fourth data of the second data group, A set of the third data of the first data group and the fourth data of the second data group, and the fourth data of the first data group and the fourth data of the second data group, The processor according to claim 1, wherein the calculation is performed on a set of The type of operation specified by the instruction code is multiplication, sum of products or product difference,
The instruction includes a third operand designating third data for storing a result of the operation,
The said execution means stores the low-order part of each result obtained by performing the said calculation with respect to the said 4 groups in said 3rd data. The one of Claims 8-11 characterized by the above-mentioned. Processor. The type of operation specified by the instruction code is multiplication, sum of products or product difference,
The instruction includes a third operand designating third data for storing a result of the operation,
The said execution means stores the high-order part of each result obtained by performing the said calculation with respect to the said 4 groups in said 3rd data. The one of Claims 8-11 characterized by the above-mentioned. Processor. The type of operation specified by the instruction code is multiplication, sum of products or product difference,
The instruction includes a third operand designating third data for storing a result of the operation,
The said execution means stores two of the four results obtained by performing the said calculation with respect to the said four groups in said 3rd data. Any one of Claims 8-11 characterized by the above-mentioned. The processor according to item.

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