JP2010135633A - Semiconductor device, and method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which includes an etching stopper film and suppresses an increase of capacitance between wiring, and to provide a method of manufacturing the semiconductor device. <P>SOLUTION: The semiconductor device includes: a semiconductor substrate 11; an interlayer dielectric 29 arranged above a surface of the semiconductor substrate 11; a plurality of via plugs 31 embedded in the interlayer dielectric 29, with upper surfaces that faces the semiconductor substrate 11 arranged in plane with an upper surface of the interlayer dielectric 29, and which are arranged by separating from each other; an interlayer dielectric 39 arranged on a surface upper part of the interlayer dielectric 29 and the via plugs 31; and a plurality of second wirings 33 which are separated by the interlayer dielectric 39, are connected to the via plugs 31, of which upper surfaces facing the via plugs 31 are arranged in plane with an upper surface of the interlayer dielectric 39, and each of which includes, sequentially from a side of the interlayer dielectric 29 on a side surface mutually facing with the interlayer dielectric 39 sandwiched: a side wall insulating film 35 having higher relative permittivity than the interlayer dielectric 39 and having a different etching property from the interlayer dielectric 29; and a side wall insulating film 37 having a different etching property from the side wall insulating film 35. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a small wiring interval and a method for manufacturing the semiconductor device.

  In a semiconductor device such as a memory, an increase in capacity, that is, miniaturization is being promoted. In particular, in a memory cell portion or the like, the pitch between adjacent wirings is narrowed with the miniaturization of wirings. When the pitch of the wiring is reduced, the capacitance between the wirings becomes conspicuous. In order to reduce the capacitance, it is effective to make the wiring layer thin to reduce the facing area between adjacent wirings. In order to secure a current by making the wiring layer thin, it is necessary to reduce the resistance of the wiring layer. For example, Cu wiring is often used.

  On the other hand, it is important to keep the resistance of fine wiring constant. The wiring layer needs to be formed in a groove having a constant dimension in the depth direction along with the width dimension. For example, an interlayer insulating film is formed on the surface of an element region where a plurality of nonvolatile semiconductor memory elements (memory cells) formed on a semiconductor substrate are formed, and a silicon nitride film is formed as a stopper film on the interlayer insulating film And a method of manufacturing a semiconductor device that is a NAND-type nonvolatile memory including a step of forming a bit line wiring groove having the silicon nitride film as a lower surface and embedding a wiring metal in the bit line wiring groove. (For example, refer to Patent Document 1).

Although the disclosed semiconductor device improves the controllability of the groove depth in the bit line wiring groove processing, the capacitance between the wirings when a silicon nitride film exists as a stopper film between the bit line wirings arranged in parallel. No mention is made of leakage current and the like. In other words, if the spacing between interconnects arranged in parallel becomes narrower with miniaturization and a silicon nitride film exists between the interconnects, a silicon nitride film having a higher relative dielectric constant than a silicon oxide-based interlayer insulating film is used. Therefore, there arises a problem that the capacitance between the wirings increases. In addition, when a silicon nitride film is stacked on a silicon oxide film-based interlayer insulating film, there arises a problem that leakage current increases at the interface.
JP 2005-150336 A

  The present invention provides a semiconductor device having an etching stopper film and capable of suppressing an increase in capacitance between wirings, and a method for manufacturing the semiconductor device.

  A semiconductor device according to one embodiment of the present invention is embedded in a semiconductor substrate, a first interlayer insulating film provided over a surface of the semiconductor substrate, and the first interlayer insulating film, and faces the semiconductor substrate. A plurality of first conductors having an upper surface flush with the upper surface of the first interlayer insulating film and spaced apart from each other; the first interlayer insulating film and the first conductor; A second interlayer insulating film disposed on the upper surface is separated from the second interlayer insulating film, connected to the first conductor, and an upper surface facing the first conductor is the second interlayer insulating film. The second interlayer insulating film is disposed on the same plane as the upper surface of the interlayer insulating film, on the side surface facing the second interlayer insulating film, in order from the first interlayer insulating film side. A first sidewall insulating film having a high relative dielectric constant, and a plurality of second conductors having a second sidewall insulating film. And wherein the are.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, wherein an upper surface of a first conductor and a first interlayer insulating film is formed flush with an upper surface of a semiconductor substrate, and the first interlayer is formed on the upper surface. Depositing a stopper insulating film having a relative dielectric constant higher than that of the insulating film, and then depositing a sidewall insulating film having a relative dielectric constant lower than that of the stopper insulating film, and penetrating the sidewall insulating film, and then the stopper insulating film Forming an opening that penetrates through the first conductor and reaching the first conductor; and burying a second conductor connected to the first conductor in the opening to form the sidewall insulating film and the second conductor Forming a top surface of the body flush with the body, anisotropically etching the sidewall insulating film between the second conductors to expose the stopper insulating film, and then anisotropically forming the stopper insulating film Etching to expose the surface of the first interlayer insulating film; Etching the exposed surface of the first interlayer insulating film until it falls to the semiconductor substrate side from the upper surface of the first conductor; and the first conductor, the stopper insulating film, and the sidewall insulation. And a step of depositing a second interlayer insulating film having a film quality similar to that of the first interlayer insulating film so as to embed the second conductor.

  ADVANTAGE OF THE INVENTION According to this invention, it is possible to provide the semiconductor device which has an etching stopper film | membrane, and can suppress the increase in the capacity | capacitance between wiring, and the manufacturing method of a semiconductor device.

  Embodiments of the present invention will be described below with reference to the drawings. In each figure, the same components are denoted by the same reference numerals.

  A semiconductor device that is, for example, a NAND-type nonvolatile memory and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a plan view schematically showing a configuration of a memory cell region of a semiconductor device. 2 is a diagram schematically showing the configuration of the memory cell region of the semiconductor device. FIG. 2A is a cross-sectional view taken along line AA of FIG. 1, and FIG. 2B is BB of FIG. It is sectional drawing along a line. FIG. 3 is a cross-sectional view schematically showing the manufacturing method of the semiconductor device in the order of steps, and corresponds to the region indicated by the alternate long and short dash line in FIG. FIG. 4 is a cross-sectional view schematically showing the method of manufacturing the semiconductor device in the order of steps following FIG. FIG. 5 is a cross-sectional view schematically showing the semiconductor device manufacturing method in the order of steps, following FIG. 4. Note that, in the surface of the semiconductor substrate, the direction away from the semiconductor substrate will be described as upward or upward.

  A semiconductor device which is a NAND type nonvolatile memory includes a memory cell having a memory transistor, a memory cell block including a plurality of memory cells connected in series, and a selection transistor for selecting the memory cell block.

  As shown in FIG. 1, the semiconductor device 1 includes a NAND-structured element region 13 including a series connection of a memory transistor 16 and a selection transistor 18 extending on the surface of a semiconductor substrate 11 in the horizontal direction on the paper surface. Are spaced apart from each other. The element isolation region 15 extends on the surface of the semiconductor substrate 11 in the horizontal direction on the paper surface so as to separate the individual element regions 13 in the vertical direction on the paper surface.

  A data selection line 17 that is a gate electrode of the memory transistor 16 extends in the vertical direction on the paper surface and is spaced apart in the horizontal direction on the paper surface. A block selection line 19 that is a gate electrode of the selection transistor 18 is disposed at an end portion of the memory cell block, extends in the vertical direction on the paper surface, and is spaced apart in the horizontal direction on the paper surface. The memory cells 6 are, for example, regions centering on the region where the element region 13 and the data selection line 17 intersect, and are arranged in a matrix form on the top, bottom, left, and right of the page.

  The second wiring 33 that forms a data transfer line connected to the memory cell block is also referred to as a bit line. For example, the second wiring 33 is counted from the semiconductor substrate 11 side so as to overlap the upper portion of the element region 13 in a plan view. Arranged as wiring. For example, the second wiring 33 is connected to the drain (or source) of the selection transistor 18 on the surface of the semiconductor substrate 11 via a via plug 31 having a circular or elliptical cross section. Although not shown, another selection transistor is provided at the end of the memory cell block opposite to the selection transistor 18, and the source (or drain) of this selection transistor is, for example, on the semiconductor substrate 11 side. To the common source line which is the first wiring.

  The second wiring 33 has a stopper insulating film 35 and a sidewall insulating film 37 on the side surfaces along the extending direction, that is, the upper and lower surfaces of the drawing. An interlayer insulating film 39 is disposed between the adjacent stopper insulating film 35 and sidewall insulating film 37.

  The via plug 31 is shown as being systematically shifted with respect to the second wiring 33. This indicates that the alignment in the photolithography process is shifted within a certain range around the target position. Further, as shown in FIG. 1, the via plugs 31 may be arranged on a single straight line extending in the vertical direction on the paper surface. Alternatively, the via plugs 31 may be arranged in a zigzag shape, that is, every other line shifted in the horizontal direction. It may be arranged.

  As shown in FIG. 2, the semiconductor device 1 is embedded in a semiconductor substrate 11, an interlayer insulating film 29 that is a first interlayer insulating film disposed on the upper surface of the semiconductor substrate 11, and the interlayer insulating film 29. The upper surface facing the semiconductor substrate 11 is flush with the upper surface of the interlayer insulating film 29, and a plurality of via plugs 31 that are first conductors spaced apart from each other, and the interlayer insulating film 29 and the via plugs 31. An interlayer insulating film 39, which is a second interlayer insulating film disposed on the upper surface, is separated by the interlayer insulating film 39 and connected to the via plug 31, and the upper surface facing the via plug 31 is the upper surface of the interlayer insulating film 39. In order from the side of the interlayer insulating film 29 on the side surfaces opposed to each other with the interlayer insulating film 39 interposed therebetween, etching properties differ from the interlayer insulating film 29 and have a higher dielectric constant than the interlayer insulating film 39. 1 side wall insulation And a second wiring 33 which is a plurality of second conductors having a side wall insulating film 37 which is a second side wall insulating film having a different etching property from the side wall insulating film 35. . A characteristic structure of the semiconductor device 1 is shown in the region of the one-dot chain line in FIG. D indicates a shift due to the relative alignment between the via plug 31 and the second wiring 33.

  The semiconductor device 1 has a diffusion region 12 serving as a drain or a source provided on the surface of a semiconductor substrate 11 so as to be spaced apart. The diffusion region 12 is isolated by the element isolation region 15. Although not shown in detail, a channel region is formed between the spaced diffusion regions 12, and a gate insulating film having a width (length) substantially equal to the width of the channel region, a charge storage film, A memory transistor 16 having a control gate electrode and the like, and a selection transistor 18 having a gate insulating film and a control gate electrode are disposed, and each control gate electrode and the like are buried with an interlayer insulating film 21.

  The control gate electrode of the memory transistor 16 extends as a data selection line 17 in a direction perpendicular to the paper surface of FIG. The control gate electrode of the selection transistor 18 extends as a block selection line 19 in a direction perpendicular to the paper surface of FIG.

  The memory transistor 16 and the selection transistor 18 are covered with a barrier insulating film 22. The barrier insulating film 22 is covered with an interlayer insulating film 23 composed of a plurality of layers, for example. For example, a first wiring 27 (via plug) that is formed flush with the upper surface of the interlayer insulating film 23 and forms the same wiring layer as a common source line (not shown) of the selection transistor 18 is disposed. Is connected to the diffusion region 12 forming the drain of the selection transistor 18 through a contact plug 25 penetrating the interlayer insulating film 23 and the barrier insulating film 22.

  The interlayer insulating film 23 and the first wiring 27 are covered with an interlayer insulating film 29. The via plug 31 has an upper surface formed flush with the upper surface of the interlayer insulating film 29, penetrates the interlayer insulating film 29, and is connected to the first wiring 27. A plug connected to the semiconductor substrate 11 is called a contact plug, and a plug connecting the layers is called a via plug.

  The second wiring 33 is connected to the via plug 31, has a width substantially the same as the width or diameter of the via plug 31, and extends in the direction in which the drain and the source of the memory transistor 16 are connected in series. As shown in FIG. 2A, the second wirings 33 are arranged at the same pitch as the arrangement pitch of the memory blocks with their side surfaces facing each other. The second wiring 33 is shifted by a shift D with respect to the via plug 31.

  A stopper insulating film 35 having a substantially uniform width (film thickness) on the lower side close to the semiconductor substrate 11 on the side surfaces facing each other of at least the second wirings 33 arranged at the arrangement pitch of the memory blocks, on the upper side, An inclined side wall insulating film 37 whose width (film thickness) decreases toward the top is provided. The sidewall insulating film 37 may have a film thickness of zero at the upper end of the side surface of the second wiring 33.

  The interlayer insulating film 39 is on the interlayer insulating film 29 and is disposed between the opposing side surfaces of the second wiring 33 so as to separate the stopper insulating film 35 and the sidewall insulating film 37. The upper surface of the interlayer insulating film 39 is flush with the upper surface of the second wiring 33, and the lower surface of the interlayer insulating film 39 is in contact with the upper surface of the interlayer insulating film 29 so that the stopper insulating film 35 does not remain therebetween. Yes.

  Next, a method for manufacturing the semiconductor device 1 will be described. In the description of the manufacturing process, the material and arrangement of the members constituting the semiconductor device 1 are supplemented.

  The semiconductor substrate 11 is, for example, a silicon substrate. After the well-known substrate process is performed on the semiconductor substrate 11 and the wiring process of the first layer is completed, the upper surfaces of the interlayer insulating film 23 and the first wiring 27 are planarized. As shown in FIG. 2, via plugs 31 embedded in the interlayer insulating film 29 and the interlayer insulating film 29 are formed on the upper surfaces of the interlayer insulating film 23 and the first wiring 27, and the upper surfaces are processed to be flush with each other. The interlayer insulating film 29 is a TEOS (Tetraethoxysilane) -based silicon oxide film, and the via plug 31 is W embedded in a barrier metal (not shown) made of Ti or Ti / TiN, for example. Note that the via plug 31 can be configured by, for example, a barrier metal, a seed metal, and Cu.

  As shown in FIG. 3A, a stopper insulating film 35a made of a silicon nitride film is formed on the interlayer insulating film 29 and the via plug 31 by a plasma CVD (Chemical Vapor Deposition) method, and a TEOS-based silicon oxide is formed thereon. An insulating film for forming the second wiring 33 made of a film is deposited. Since the insulating film for forming the wiring remains on the side wall of the second wiring 33, it is referred to as a side wall insulating film 37a.

  As shown in FIG. 3B, a patterned photoresist 41 for forming the second wiring 33 connected to the via plug 31 is formed on the sidewall insulating film 37a by a photolithography process. For miniaturization, for example, the width of the upper surface of the via plug 31 and the width of the second wiring 33 are set to be the minimum dimension of the manufacturing process or a dimension close thereto, and misalignment (deviation D) in the photolithography process. Is almost as it is. The distance (interval) between the second wirings 33 arranged in parallel is also set so as to be the minimum dimension of the manufacturing process or a dimension close thereto.

  As shown in FIG. 3C, the sidewall insulating film 37a made of a silicon oxide film is anisotropically etched by a RIE (Reactive Ion Etching) method using the photoresist 41 as a mask, and a stopper insulation made of a silicon nitride film. An opening 43 reaching the film 35a is formed. Etching of the sidewall insulating film 37a is selectively performed on the stopper insulating film 35a.

  As shown in FIG. 4A, the stopper insulating film 35a is anisotropically etched by the RIE method using the sidewall insulating film 37a as a mask, and the opening 43 reaching the via plug 31 and the interlayer insulating film 29 is transferred. Etching of the stopper insulating film 35 a is selectively performed on the via plug 31 and the interlayer insulating film 29. An opening formed in both films is indicated by reference numeral 43. If necessary, light etching can be performed so that the bottom surface of the opening 43, that is, the top surface of the via plug 31 can be electrically connected. In the above etching, even if the exposed portion 45 where a part of the interlayer insulating film 29 is exposed at the bottom of the opening 43, excessive etching extending downward along the edge of the via plug 31 is suppressed.

  As shown in FIG. 4B, a barrier metal such as Ti (not shown) and a seed film (not shown) made of Cu are formed in the opening 43 by CVD or sputtering, and then electrolytic plating is used. Then, Cu is formed, and the surface is planarized by CMP (Chemical Mechanical Polishing) to expose the silicon oxide film to be the sidewall insulating film 37, Cu to be the second wiring 33, and the like.

  As shown in FIG. 4C, the sidewall insulating film 37a made of a silicon oxide film is anisotropically etched by the RIE method so as to be stopped by the stopper insulating film 35a made of a silicon nitride film, and then the silicon oxide film The stopper insulating film 35a is etched so as to be stopped by the interlayer insulating film 29 made of. This RIE condition is the same as the RIE condition for forming the opening 37. Thereafter, the surface of the interlayer insulating film 29 between the side surfaces of the opposing second wiring 33 is slightly etched.

  As a result, the side wall insulating film 37 whose thickness (width) gradually increases remains on the side surface of the second wiring 33 from the position lowered from the upper surface to the lower stopper insulating film 35, and the second wiring 33. A stopper insulating film 35 having a substantially constant film thickness (width) is left below in contact with the side surface and side wall insulating film 37. The upper surface of the interlayer insulating film 29 is recessed below the bottom surface of the stopper insulating film 35.

  As shown in FIG. 5A, an interlayer insulating film 39 made of a TEOS-based silicon oxide film is formed so as to cover and bury the interlayer insulating film 29, the second wiring 33, the stopper insulating film 35, and the sidewall insulating film 37. To deposit.

  As shown in FIG. 5B, the surface is flattened by the CMP method so that the second wiring 33 has a suitable thickness. For example, the second wiring 33, the sidewall insulating film 37, and the interlayer insulating film 39 are exposed on the planarized upper surface (see FIG. 1). The second wiring 33 is shifted from the via plug 31 by a shift D in the direction along the surface of the semiconductor substrate 11. Note that when the amount of polishing by the CMP method is reduced, the sidewall insulating film 37 may not be exposed on the upper surface.

  Although illustration is omitted, after the planarized upper surface shown in FIG. 5B is formed, the semiconductor device 1 is completed through a known wiring process and the like.

  As described above, in the semiconductor device 1, the second wiring 33 on the interlayer insulating film 29 made of a silicon oxide film is connected to the via plug 31, and the stopper insulating film 35 made of a silicon nitride film and the silicon oxide film are formed on the side surface. The stopper insulating film 35 and the side wall insulating film 37 are formed of a silicon oxide film, and the stopper insulating film 35 and the side wall of the side surface of the adjacent second wiring 33 are interposed therebetween. It faces the insulating film 37. The interlayer insulating film 29 and the stopper insulating film 35 have different etching properties by RIE. The stopper insulating film 35 and the sidewall insulating film 37 are different from each other in etching properties by RIE. The stopper insulating film 35 has a relative dielectric constant higher than that of the interlayer insulating film 39.

  As a result, even if the positions of the via plug 31 and the second wiring 33 are displaced from each other, excessive etching extending downward along the edge of the via plug 31 is suppressed, and the characteristics of the semiconductor device 1 are stable and highly reliable. It becomes possible. In addition, since the stopper insulating film 35 between the side surfaces of the second wiring 33 is divided and replaced with a silicon oxide film having a relative dielectric constant smaller than that of the silicon nitride film, the inter-wiring capacitance between the second wirings 33 is suppressed. The Further, since the interlayer insulating film 29 and the interlayer insulating film 39 made of a silicon oxide film having substantially the same composition are formed between the side surfaces of the second wiring 33, the interface between the silicon nitride film and the silicon oxide film, that is, silicon nitride It becomes possible to suppress the leakage current generated due to the dangling bonds of the film. The miniaturized semiconductor device 1 can reduce the capacitance between wirings and the leakage current between wirings.

  The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.

  For example, in the embodiment, an example is shown in which the second wiring is the second wiring from the semiconductor substrate side, but the second wiring can be the first wiring or the wiring above the third wiring. That is, the second wiring may be a wiring connected to the contact plug, or the second wiring may be a wiring connected to another wiring or another via plug.

  In the embodiment, the sidewall insulating film between the second wirings is a TEOS-based silicon oxide film, but instead of the TEOS-based silicon oxide film, for example, BSG ( Boro-silicate glass), PSG (Phospho-silicate Glass), a silicon oxide film to which F is added, a low-k film such as SiOC, or the like can be used.

  In the embodiment, an example in which the semiconductor device is a NAND-type nonvolatile memory is shown. However, the semiconductor device is, for example, a NOR-type nonvolatile memory, a DRAM or SRAM memory, a logic IC, and an analog It may be an IC or a combination of these.

The present invention can be configured as described in the following supplementary notes.
(Supplementary Note 1) A semiconductor substrate, a first interlayer insulating film disposed on an upper surface of the semiconductor substrate, and an upper surface facing the semiconductor substrate embedded in the first interlayer insulating film A plurality of first conductors disposed flush with the upper surface of the interlayer insulating film and spaced apart from each other, and disposed on the upper surfaces of the first interlayer insulating film and the first conductor. The second interlayer insulating film is separated from the second interlayer insulating film, connected to the first conductor, and the upper surface facing the first conductor is the upper surface of the second interlayer insulating film The second interlayer insulating film has a dielectric constant higher than that of the second interlayer insulating film in order from the side of the first interlayer insulating film on the side surfaces facing each other across the second interlayer insulating film. And a plurality of second conductors having a first sidewall insulating film and a second sidewall insulating film.

(Supplementary note 2) The semiconductor device according to supplementary note 1, wherein the second conductor is a data transfer line connected to a source or a drain formed on the semiconductor substrate.

(Additional remark 3) The said 2nd conductor is a semiconductor device of Additional remark 1 which has the material which has Cu as a main component.

(Additional remark 4) The said 2nd interlayer insulation film is a semiconductor device of Additional remark 1 currently falling to the said semiconductor substrate side from the lower surface of the said 2nd conductor.

1 is a plan view schematically showing a configuration of a memory cell region of a semiconductor device according to an embodiment of the present invention. 2A and 2B are diagrams schematically illustrating a configuration of a memory cell region of a semiconductor device according to an embodiment of the present invention, in which FIG. 2A is a cross-sectional view taken along line AA in FIG. 1, and FIG. Sectional drawing along line BB. Sectional drawing which shows typically the manufacturing method of the semiconductor device which concerns on the Example of this invention in order of a process. Sectional drawing which shows typically the manufacturing method following FIG. 3 of the semiconductor device which concerns on the Example of this invention in process order. Sectional drawing which shows typically the manufacturing method following FIG. 4 of the semiconductor device which concerns on the Example of this invention in process order.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 6 Memory cell 11 Semiconductor substrate 12 Diffusion area 13 Element area 15 Element isolation area 16 Memory transistor 17 Data selection line 18 Selection transistor 19 Block selection line
21, 23, 29, 39 Interlayer insulating film 22 Barrier insulating film 25 Contact plug 27 First wiring 31 Via plug 33 Second wiring 35, 35a Stopper insulating film 37, 37a Side wall insulating film 41 Photoresist 43 Opening 45 Exposed portion D Shift

Claims (5)

A semiconductor substrate;
A first interlayer insulating film disposed on an upper surface of the semiconductor substrate;
A plurality of first conductors embedded in the first interlayer insulating film and having an upper surface facing the semiconductor substrate flush with an upper surface of the first interlayer insulating film and spaced apart from each other When,
A second interlayer insulating film disposed on the surface of the first interlayer insulating film and the first conductor;
Separated by the second interlayer insulating film, connected to the first conductor, and an upper surface facing the first conductor is disposed flush with an upper surface of the second interlayer insulating film, A first sidewall insulating film having a higher relative dielectric constant than the second interlayer insulating film, in order from the side of the first interlayer insulating film, on the side surfaces facing each other across the second interlayer insulating film, and the second A plurality of second conductors having a side wall insulating film;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the first conductor includes one of a contact plug, a via plug, and a wiring.   3. The semiconductor device according to claim 1, wherein the first interlayer insulating film and the second interlayer insulating film are insulating films having the same film quality.   2. The first sidewall insulating film is a silicon nitride film, the second sidewall insulating film, the first interlayer insulating film, and the second interlayer insulating film are silicon oxide films. 4. The semiconductor device according to any one of items 1 to 3. A top surface of the first conductor and the first interlayer insulating film is formed flush with the top surface of the semiconductor substrate, and a stopper insulating film having a higher relative dielectric constant than the first interlayer insulating film is formed on the top surface. And depositing a sidewall insulating film having a relative dielectric constant lower than that of the stopper insulating film;
Forming an opening that penetrates through the sidewall insulating film and then reaches the first conductor through the stopper insulating film;
Burying a second conductor connected to the first conductor in the opening and forming the sidewall insulating film and the upper surface of the second conductor flush with each other;
The sidewall insulating film between the second conductors is anisotropically etched to expose the stopper insulating film, and then the stopper insulating film is anisotropically etched to form the first interlayer insulating film And then etching until the exposed surface of the first interlayer insulating film is lowered from the upper surface of the first conductor toward the semiconductor substrate;
Depositing a second interlayer insulating film having the same film quality as the first interlayer insulating film so as to embed the first conductor, the stopper insulating film, the sidewall insulating film, and the second conductor; ,
A method for manufacturing a semiconductor device, comprising:

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