JP2010134836A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve stable processing of an external device when a power supply voltage falls. <P>SOLUTION: The semiconductor integrated circuit device includes: a power supply terminal 11 which is connected to an external power supply; a voltage detection circuit 12 which detects whether the absolute value of the supply voltage in the power supply terminal 11 is above a predetermined value or not; a register 13 which stores information that the absolute value of the power supply voltage is below a predetermined value; and an output terminal 15 which allows the information stored in the register 13 to be read from the outside. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a function of detecting a power supply voltage.

  In various electronic devices and the like, microcomputers are incorporated to realize various functions. In such an electronic device, particularly a portable electronic device, when the power supply voltage drops, the microcomputer performs various processes in preparation for stopping the power supply, and supplies information on the power supply voltage drop to the outside. It is often equipped with a function to notify

  As a function of notifying the outside of the power supply voltage drop information, the low voltage detection system described in Patent Document 1 includes an interrupt handler that generates an interrupt when the voltage of the power supply pin falls below a predetermined voltage. Provided. The central processing unit (CPU) in the low voltage detection system can notify the outside of the power supply voltage drop information by this interruption.

JP-T-2006-506617

  The following analysis is given in the present invention.

  The low-voltage detection system described in Patent Document 1 notifies the external device of information on a decrease in power supply voltage by performing a power supply voltage decrease interrupt process by the CPU. For this reason, the CPU must execute a program that accompanies the interrupt, and it takes a predetermined time to notify the external device. Therefore, when the external device uses a common power supply with the low voltage detection system, if the power supply voltage decreases rapidly, there is a risk that the processing accompanying the decrease in the power supply voltage on the external device side cannot be performed stably. There is.

  A semiconductor integrated circuit device according to one aspect of the present invention includes an external terminal that can be connected to an external power supply, and a voltage that detects whether or not the absolute value of the power supply voltage at the external terminal is greater than or equal to a predetermined value. A detection circuit, a holding circuit that holds information to that effect when the absolute value of the power supply voltage is less than a predetermined value, and an output terminal that can read information held in the holding circuit from the outside.

  According to the present invention, information on a drop in power supply voltage is immediately and directly notified to the outside without using a CPU. Therefore, the process associated with the decrease in the power supply voltage on the external device side is stabilized.

  The semiconductor integrated circuit device according to the embodiment of the present invention has an external terminal (power supply terminal 11 in FIG. 1) that can be connected to an external power supply, and whether or not the absolute value of the power supply voltage at the external terminal is a predetermined value or more. A voltage detection circuit (12 in FIG. 1), a holding circuit (register 13 in FIG. 1) for holding information to that effect when the absolute value of the power supply voltage is less than a predetermined value, and holding in the holding circuit And an output terminal (15 in FIG. 1) that enables the read information to be read from the outside.

  In a semiconductor integrated circuit device, writing is performed by a central processing unit (CPU 16 in FIG. 1) that is operable when a power source is connected to a power source terminal and the absolute value of the power source voltage is equal to or greater than a predetermined value, and the central processing unit. An output port (output latch circuit 19 in FIG. 1), and a selection circuit (selector 14 in FIG. 1) that selects one of the output of the holding circuit and the output port by the central processing unit and connects to the output terminal; You may make it prepare.

  In the semiconductor integrated circuit device, the voltage detection circuit is preferably capable of variably setting a predetermined value by the central processing unit.

  In the semiconductor integrated circuit device, an interrupt register (interrupt flag register 21 in FIG. 3) capable of notifying the central processing unit of an interrupt, and a port circuit (port control circuit 22 in FIG. 3) communicating with an external device are provided. In addition, the voltage detection circuit notifies the interrupt register to generate an interrupt when the absolute value of the power supply voltage is less than a predetermined value, and the central processing unit triggers the interrupt via the port circuit. The external device may be notified that the absolute value of the power supply voltage is less than a predetermined value.

  The semiconductor integrated circuit device may function as a one-chip microprocessor.

  Hereinafter, it will be described in detail with reference to the drawings in accordance with embodiments.

  FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit device according to a first embodiment of the present invention. In FIG. 1, the semiconductor integrated circuit device 10 includes a power supply terminal 11, a voltage detection circuit 12, registers 13 and 18, a selector 14, an output terminal 15, a CPU 16, a voltage detection circuit operation register 17, and an output latch circuit 19.

  The power supply terminal 11 is connected to an external power supply such as a battery and supplies the power supply voltage Vdd to the semiconductor integrated circuit device 10. The voltage detection circuit 12 detects whether or not the power supply voltage Vdd at the power supply terminal 11 is equal to or higher than a predetermined value when the voltage detection circuit operation register 17 is set by the CPU 16. The register 13 is a holding circuit that holds information (detection flag) that is a detection result of the voltage detection circuit 12. The selector 14 selects the output signal of the register 13 or the output latch circuit 19 according to the contents of the register 18 set by the CPU 16 and outputs it to the output terminal 15. The output latch circuit 19 is an output port that outputs the data written by the CPU 16 to the selector 14. The voltage detection circuit 12 is not limited to directly detecting the voltage at the power supply terminal 11. For example, the semiconductor integrated circuit device 10 includes an external terminal (not shown) that is different from the power supply terminal 11 and is connected to an external power supply equivalent so that the voltage detection circuit 12 detects a voltage at the external terminal. Needless to say, it may be configured.

  The power supply voltage Vdd is supplied to the registers 13 and 18, the selector 14, the output terminal 15, the CPU 16, the voltage detection circuit operation register 17, and the output latch circuit 19 in addition to the voltage detection circuit 12.

  The semiconductor integrated circuit device 10 configured as described above functions as a one-chip microprocessor.

  Next, the operation of the semiconductor integrated circuit device 10 will be described. FIG. 2 is a flowchart showing the operation of the CPU 16. The CPU 16 realizes the following processing by executing a built-in program.

  When started, in step S11, the output terminal 15 is set to the normal output port mode. That is, the register 18 is set so that the selector 14 selects the output signal of the output latch circuit 19 and outputs it to the output terminal 15.

  In step S12, it is determined whether or not to use the voltage detection circuit 12. If not, a series of processing is terminated.

  When using the voltage detection circuit 12 (YES in step S12), in step S13, the voltage detection circuit operation register 17 is set to start the voltage detection operation of the voltage detection circuit 12.

  In step S14, a predetermined time is waited until the voltage detection operation of the voltage detection circuit 12 is stabilized.

  In step S15, it is determined whether or not to output the voltage detection result of the voltage detection circuit 12 to the output terminal 15. If not, a series of processing is terminated.

  When the voltage detection result is output to the output terminal 15 (YES in step S15), the register 18 is set so that the selector 14 selects the voltage detection result of the voltage detection circuit 12 and outputs it to the output terminal 15 in step S16. The series of operations is finished.

  When step S16 is passed, after the operation shown in FIG. 2, when the power supply voltage Vdd becomes less than a predetermined value, the voltage detection circuit 12 writes the fact (detection flag) in the register 13. The register 13 outputs a voltage detection result indicating that the power supply voltage Vdd is less than a predetermined value to the output terminal 15 via the selector 14. These operations are performed regardless of the operation of the CPU 16, and are executed even when the CPU 16 does not function due to a decrease in the power supply voltage Vdd.

  According to the semiconductor integrated circuit device 10 as described above, when the power supply voltage Vdd becomes less than a predetermined value, information indicating that is immediately output directly to the output terminal 15 regardless of the CPU 16. Accordingly, it is possible to notify the outside of the power supply voltage drop at high speed and with high reliability.

  FIG. 3 is a block diagram showing a system configuration according to the second embodiment of the present invention. In FIG. 3, the system includes two semiconductor integrated circuit devices 10 a and 30. In the semiconductor integrated circuit device 10a, the same reference numerals as those in FIG. The semiconductor integrated circuit device 10a further includes a detection voltage setting register 20, an interrupt flag register 21, a port control circuit 22, and an input / output terminal 23 with respect to the semiconductor integrated circuit device 10 shown in FIG.

  The detection voltage setting register 20 is set by the CPU 16a, and can change the detection voltage (predetermined value) of the voltage detection circuit 12a. The interrupt flag register 21 is set when the power supply voltage Vdd becomes less than a predetermined value, and notifies that to the CPU 16a by interruption. The port control circuit 22 enables data transmission / reception between the semiconductor integrated circuit device 30 and the CPU 16a via the input / output terminal 23.

  On the other hand, the semiconductor integrated circuit device 30 includes a CPU 31, an input terminal 32, a selector 33, an interrupt flag register 34, an input port circuit 35, a register 36, an input / output terminal 37, and a port control circuit 38. The semiconductor integrated circuit device 30 is supplied with the same power supply voltage Vdd as that of the semiconductor integrated circuit device 10a.

  The selector 33 distributes data received from the output terminal 15 of the semiconductor integrated circuit device 10 a via the input terminal 32 to the interrupt flag register 34 or the input port circuit 35 based on the contents of the register 36. The interrupt flag register 34 notifies the CPU 31 of the interrupt flag. The input port circuit 35 outputs the received data to the CPU 31. The CPU 31 writes data for determining the selection operation in the selector 33 to the register 36. The port control circuit 38 enables data transmission / reception to / from the semiconductor integrated circuit device 10 a via the input / output terminal 37 and the input / output terminal 23.

  In the system configuration as described above, the CPU 16 a and the CPU 31 transmit and receive data via the port control circuit 22, the input / output terminals 23 and 37, and the port control circuit 38. In addition, transmission / reception of some data can be performed via the output latch circuit 19, the selector 14, the output terminal 15, the input terminal 32, the selector 33, and the input port circuit 35. The detection result information of the voltage detection circuit 12a can be notified to the CPU 31 via the register 13, the selector 14, the output terminal 15, the input terminal 32, the selector 33, and the interrupt flag register 34.

  Next, the operation of the entire system will be described. FIG. 4 is a flowchart showing the operations of the CPU 16a and the CPU 31. The CPU 16a and the CPU 31 each implement the following processing by executing a built-in program.

  First, the operation of the CPU 16a will be described. When started, in step S21, the output terminal 15 is set to the normal output port mode. That is, the register 18 is set so that the selector 14 selects the output signal of the output latch circuit 19 and outputs it to the output terminal 15. It is assumed that the port control circuit 22 is communicable with the outside.

  In step S22, interrupts are prohibited so that unnecessary interrupts do not occur when setting the detection voltage of the voltage detection circuit 12a.

  In step S23, the detection voltage setting register 20 is set so that the detection voltage of the voltage detection circuit 12a becomes the first value. Here, the first value is a value that represents a sign of a decrease in the power supply voltage Vdd. Even if the power supply voltage Vdd is less than the first value, the CPU 16a and the like operate as long as the power supply voltage Vdd is not less than the second value described later.

  In step S24, the voltage detection circuit operation register 17 is set so as to start the detection operation of the voltage detection circuit 12a.

  In step S25, a predetermined time is waited until the voltage detection operation of the voltage detection circuit 12 is stabilized.

  In step S26, the interrupt flag register 34 is cleared and an interrupt is permitted. Further, the contents of the register 13 are cleared.

  In step S27, normal processing in the CPU 16a is performed.

  In step S28, it is monitored whether or not the detected voltage of the voltage detection circuit 12a is less than the first value. If the detected voltage is greater than or equal to the first value, the normal process is continued.

  When the detected voltage is less than the first value, an interrupt is generated (YES in step S28). In step S29, the fact that the detected voltage is less than the first value indicates that the port control circuit 22, the input / output terminal 23 and 37 and the CPU 30 via the port control circuit 38.

  In step S30, interrupts are prohibited so that unnecessary interrupts do not occur when setting the detection voltage of the voltage detection circuit 12a.

  In step S31, the detection voltage setting register 20 is set so that the detection voltage of the voltage detection circuit 12a becomes a second value smaller than the first value.

  In step S32, the register 18 is set so that the selector 14 selects the voltage detection result of the voltage detection circuit 12a and outputs it to the output terminal 15.

  In step S33, a HALT instruction is issued, and the CPU 16a stops operating.

  In step S34, when the power supply voltage Vdd becomes less than the second value, the voltage detection circuit 12a writes the fact (detection flag) in the register 13. The register 13 outputs a voltage detection result indicating that the power supply voltage Vdd is less than the second value to the output terminal 15 via the selector 14. Even if the CPU 16a stops operating, the operation in step S34 as described above is executed.

  Next, the operation of the CPU 31 will be described. When started, in step S41, the input terminal 32 is set to the normal input port mode. That is, the register 36 is set so that the selector 33 selects the signal at the input terminal 32 and outputs it to the input port circuit 35. It is assumed that the port control circuit 38 is communicable with the outside.

  In step S42, normal processing in the CPU 31 is performed.

  In step S43, it is monitored whether or not information indicating that the detection voltage of the voltage detection circuit 12a in the semiconductor integrated circuit device 10a has become less than the first value is received from the port control circuit 38. Continue processing.

  When the information indicating that the detection voltage of the voltage detection circuit 12a has become less than the first value is received (YES in step S43), in step S44, the selector 33 selects the signal at the input terminal 32 and interrupt flag. The register 36 is set to output to the register 34.

  In step S45, for example, processing related to a power supply voltage drop in the semiconductor integrated circuit device 30 such as saving of a cache memory is executed.

  In step S46, a voltage detection result signal indicating that the power supply voltage Vdd is less than the second value appears at the input terminal 32, and it is monitored whether or not the interrupt flag register 34 is set. Continue processing at the time of decline.

  If the interrupt flag register 34 is set (YES in step S46), a HALT instruction is issued in step S47, and the CPU 31 stops its operation.

  According to the semiconductor integrated circuit device 10a as described above, when the power supply voltage Vdd becomes less than the first value, the CPU 31 is notified of a sign of a decrease in the power supply voltage Vdd. Then, the CPU 16a and the CPU 31 perform processing necessary as the power supply voltage Vdd decreases in advance, and immediately stop the operation when the power supply voltage Vdd becomes less than the second value. Therefore, the process accompanying the decrease in the power supply voltage is stabilized.

  It should be noted that the disclosures of the aforementioned patent documents and the like are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

1 is a block diagram showing a configuration of a semiconductor integrated circuit device according to a first exemplary embodiment of the present invention. It is a flowchart showing operation | movement of CPU which concerns on 1st Example of this invention. It is a block diagram which shows the structure of the system which concerns on the 2nd Example of this invention. It is a flowchart showing operation | movement of two CPU which concerns on the 2nd Example of this invention.

Explanation of symbols

10, 10a, 30 Semiconductor integrated circuit device 11 Power supply terminal 12, 12a Voltage detection circuit 13, 18, 36 Register 14, 33 Selector 15 Output terminal 16, 16a, 31 CPU
17 Voltage detection circuit operation register 19 Output latch circuit 20 Detection voltage setting register 21, 34 Interrupt flag register 22, 38 Port control circuit 23, 37 Input / output terminal 32 Input terminal 35 Input port circuit

Claims (7)

An external terminal that can be connected to an external power supply;
A voltage detection circuit for detecting whether or not the absolute value of the power supply voltage at the external terminal is a predetermined value or more;
A holding circuit for holding information to that effect when the absolute value of the power supply voltage is less than a predetermined value;
An output terminal capable of reading the information held in the holding circuit from the outside;
A semiconductor integrated circuit device comprising: A central processing unit connected to the external power supply and operable when the absolute value of the power supply voltage is a predetermined value or more;
An output port for writing by the central processing unit;
A selection circuit that selects one of the output of the holding circuit and the output port and connects to the output terminal by the central processing unit;
The semiconductor integrated circuit device according to claim 1, further comprising:   3. The semiconductor integrated circuit device according to claim 2, wherein the voltage detection circuit can variably set the predetermined value by the central processing unit. An interrupt register capable of notifying the central processing unit of an interrupt;
A port circuit communicating with an external device;
Further comprising
The voltage detection circuit notifies the interrupt register to generate an interrupt when the absolute value of the power supply voltage is less than a predetermined value,
4. The semiconductor integrated circuit according to claim 3, wherein the central processing unit notifies the external device that the absolute value of the power supply voltage is less than a predetermined value via the port circuit in response to the interruption. apparatus.   5. The semiconductor integrated circuit device according to claim 2, which functions as a one-chip microprocessor. A method for the semiconductor integrated circuit device according to any one of claims 2 to 4 to notify an external device,
Setting a predetermined value in the voltage detection circuit to a first value;
Notifying an external device when the absolute value of the power supply voltage is less than a first value;
Selecting an output of the holding circuit and connecting to the output terminal;
Setting a predetermined value in the voltage detection circuit to a second value smaller than the first value;
Making the information readable from the outside;
Holding the information to that effect when the absolute value of the power supply voltage is less than a second value;
A method of notifying the outside of the semiconductor integrated circuit device. A central processing unit in a semiconductor integrated circuit device according to claim 2,
A process of setting a predetermined value in the voltage detection circuit to a first value;
A process of notifying an external device when the absolute value of the power supply voltage is less than a first value;
Processing for selecting the output of the holding circuit and connecting it to the output terminal;
A process of setting a predetermined value in the voltage detection circuit to a second value smaller than the first value;
A process for enabling the information to be read from the outside;
A program that executes

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