JP5053002B2 - Hardware monitoring unit - Google Patents

Description

  The present invention relates to a hardware monitoring unit used in various electronic devices such as an electronic register, a POS terminal, and a personal computer.

  Electronic devices such as an electronic register, a POS terminal, and a personal computer are configured by a plurality of devices such as a control unit and devices connected to the control unit. If a malfunction occurs in the hardware of these devices, such as an operation stop, the user or maintenance personnel cannot immediately determine whether the operation stop is waiting for something or is a lock. That is, it is difficult to identify the cause of a hardware failure, and it takes a long time to recover.

As a system having a function for coping with a hardware failure, a computer system capable of detecting an indication of a hardware failure in its own system is known (for example, Patent Document 1).
JP 2005-115751 A

  In the case of the computer system described above, it is impossible to grasp the current state of the hardware only by detecting in advance signs of hardware failure.

  The present invention takes the above circumstances into consideration, and its purpose is to easily and appropriately grasp the state of the hardware at the present time, thereby easily causing the cause of the hardware malfunction. It is an object of the present invention to provide a hardware monitoring unit that can be specified and can reduce the time required for hardware recovery.

The hardware monitoring unit of the invention according to claim 1 is an electronic device having at least a CPU, a memory, and a VGA as a plurality of devices , and sequentially accesses the CPU, the memory, and the VGA, and reads data from the CPU, the memory, and the VGA . A reading means, a decoding means for decoding the data read by the reading means, and whether the CPU, the memory, or the VGA is operating according to the data reading status by the reading means and the decoding result of the decoding means Determination means for determining whether the operation state is abnormal or abnormal .

  According to the hardware monitoring unit of the present invention, it is possible to easily and appropriately grasp what state the hardware is currently in. As a result, the cause of the hardware failure can be easily identified, and the time required for hardware recovery can be shortened.

An embodiment of the present invention will be described below with reference to the drawings, taking as an example application to electronic devices such as an electronic register, a POS terminal, and a personal computer.
As shown in FIG. 1, an I / O (input / output) controller 2 is connected to a CPU 1 serving as a control unit, and the I / O controller 2 is connected to a super input / output interface 21, a memory 22, USB interfaces 23a, 23b, 23c, a VGA (Video Graphics Array) 24, a LAN (Local Area Network) interface 25, a PCI (Peripheral Components Interconnect) input / output interface 26, and the like.

  The I / O controller 2 includes an LPC (Low Pin Count) bus controller 4, a memory controller 5, a USB bus controller 6, and a PCI bus controller 7 connected to the CPU bus 3. Among these, the super input / output interface 21 is connected to the LPC bus controller 4 via the LPC bus 11, the memory 22 is connected to the memory controller 5 via the memory bus 12, and the USB bus 13 is connected to the USB bus controller 6. The USB interfaces 23a, 23b, and 23c are connected to each other, and the VGA 24, the LAN interface 25, and the PCI input / output interface 26 are connected to the PCI bus controller 7 through the PCI bus 14.

  The hardware monitoring unit 30 is connected to the CPU bus 3 in the I / O controller 2. The hardware monitoring unit 30 monitors the CPU 1 and the hardware such as each device connected to the CPU 1 through the CPU bus 3, and as shown in FIG. 2, the CPU 31, the control program, the address of each device, and the like. It has a memory 32 stored, a decode block 33 for decoding data read from the device to be monitored, and a liquid crystal display 40. In particular, the CPU 31 has the following means (1) to (4) as hardware monitoring functions.

  (1) Reading means for accessing each device including the CPU 1 and reading data from each device. The read data is decoded by the decode block 33.

  (2) Determination means for determining the state of each device according to the data read status by the reading means and the content of the read data (decoding result of the decode block 33).

  (3) Notification means for notifying the determination result of the determination means by character display or image display of the liquid crystal display 40.

  (4) Storage means for storing the access destination address and read data by the reading means in the memory 32 as access history data.

Next, the operation of the hardware monitoring unit 30 will be described with reference to the flowchart of FIG.
The hardware monitoring unit 30 sequentially accesses each device including the CPU 1 based on the address stored in the memory 32, and reads predetermined data from each device (step 101). The read data is decoded by the decode block 33 of the hardware monitoring unit 30.

  Then, the hardware monitoring unit 30 determines the state of each device according to the data read status from each device and the content of the read data (that is, the decoding result of the decode block 33) (step 102).

  For example, when data is read from the CPU 1 during execution of access to the CPU 1, it is determined that the CPU 1 is operating. Also, based on the content of the read data, it is determined what operating state (standby or the like) the CPU 1 is in. However, when data is not read from the CPU 1 despite the access to the CPU 1, it is determined that the CPU 1 is in an operation stopped (so-called locked) state or abnormal. Even if the data is read from the CPU 1 by access, if the read data is not unique to the CPU 1 or contains some trouble, the CPU 1 is determined to be abnormal.

  Further, when data is read from the memory 22 when the access to the memory 22 is executed, it is determined that the memory 22 is operating. Further, based on the content of the read data, it is determined what operating state the memory 22 is in. However, when data is not read from the memory 22 despite the access to the memory 22, it is determined that the memory 22 is in a stopped state or abnormal. Even if data is read from the memory 22 by access, if the read data is not unique to the memory 22 or contains some malfunction, it is determined that the memory 22 is abnormal.

  Furthermore, when data is read from the VGA 24 when executing an access to the VGA 24, it is determined that the VGA 24 is operating. Further, based on the content of the read data, it is determined what operating state the VGA 24 is in. However, if data is not read from the VGA 24 in spite of access to the VGA 24, it is determined that the VGA 24 is in an operation stopped state or abnormal. Even if data is read from the VGA 24 by access, if the read data is not unique to the VGA 24 or contains some malfunction, it is determined that the VGA 24 is abnormal.

  The same applies to the other LPC bus controller 4, memory controller 5, USB bus controller 6, PCI bus controller 7, super input / output interface 21, USB interfaces 23a, 23b, 23c, LAN interface 25, and PCI input / output interface 26. Access and determination are performed.

  Further, the hardware monitoring unit 30 notifies the determination result by character display or image display of the liquid crystal display 40 (step 103), and stores the access destination address and read data in the memory 32 as access history data. (Step 104).

  As described above, each device is accessed in order, data is read from each device, the state of each device is determined according to the data read status and the content of the read data, and the determination result is displayed on the liquid crystal display 40. By notifying, the user and maintenance personnel can easily and appropriately grasp the state of the hardware of each device at the present time. As a result, the cause of the hardware failure can be easily identified, and the time required for hardware recovery can be shortened.

  In addition, it is possible to analyze the hardware state in time series using the access history data stored in the memory 32.

In the above embodiment, the case where the hardware monitoring unit 30 is connected to the CPU bus 3 has been described as an example. However, the hardware monitoring unit 30 is connected to the LPC bus 11 and the PCI bus 14 as shown in FIG. It is good also as a structure to be made. In this case, local devices connected to the LPC bus 11 and the PCI bus 14 are monitored.
In addition, this invention is not limited to each said embodiment, A various deformation | transformation implementation is possible in the range which does not change a summary.

1 is a block diagram showing a control circuit of an embodiment and an electronic device related thereto. The block diagram which shows the specific structure of one Embodiment. The flowchart for demonstrating the effect | action of one Embodiment. The block diagram which shows the modification of the connection destination of one Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... CPU (control part), 2 ... I / O controller, 3 ... CPU bus, 4 ... LPC bus controller, 5 ... Memory controller, 6 ... USB bus controller, 7 ... PCI bus controller, 21 ... Super input / output interface, 22 ... Memory, 23a, 23b, 23c ... USB interface, 24 ... VGA, 25 ... LAN interface, 26 ... PCI input / output interface, 30 ... Hardware monitoring unit, 31 ... CPU, 32 ... Memory, 33 ... Decode block, 40 ... Liquid crystal display

Claims (3)

In an electronic device having at least a CPU, a memory, and a VGA as a plurality of devices,
Reading means for sequentially accessing the CPU, memory and VGA to read data from the CPU, memory and VGA ;
Decoding means for decoding the data read by the reading means;
Determining means for determining whether the CPU, the memory, and the VGA are operating, in an operating state, or abnormal according to a data reading state by the reading means and a decoding result of the decoding means; ,
A hardware monitoring unit comprising:   The hardware monitoring unit according to claim 1, further comprising notification means for notifying a determination result of the determination means.   3. The hardware monitoring unit according to claim 1, further comprising storage means for storing an access destination address and read data by the reading means as access history data.

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