JP2010129991A - Wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board, capable of preventing cracks of a wiring due to deformation caused by heat distortion of a resin filling material, when a chip component is built in the wiring board. <P>SOLUTION: This wiring board 10 includes: a core material 11 placing a semiconductor chip 200 and having a housing hole opened thereon; first and second wiring multilayer portions 12, 13 formed on the top and bottom of the core material 11; a chip capacitor 100 as a chip component housed in the housing hole; and a resin filling material 50 filled in a gap between the housing hole and the side surfaces of the chip capacitor 100. On the upper surface of the core material 11, a filling region of the resin filling material 50 faces a region where the semiconductor chip 200 is placed in a multilayer direction, and on the lower surface side of the core material 11, a wiring is not formed on the region facing the region where the resin-filling material 50 is formed in the multilayer direction, of a conductor layer of a second wiring multilayer portion 13. Accordingly, the disadvantages such as cracks in the wiring portion of the conductor layer of the wiring substrate 10 due to deformation caused by the heat distortion of the resin-filling material 50 can be prevented. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a wiring board in which a chip component is accommodated in an accommodation hole opened in a core material.

Conventionally, a wiring board is used in which a core material is disposed in the center and a wiring laminated portion is formed by alternately laminating conductor layers and insulating layers above and below the core material. When a semiconductor chip is mounted on such a wiring board to form a package, it is necessary to supply a power supply voltage from the external board to the semiconductor chip. In this case, in order to stabilize the power supply voltage supplied to the semiconductor chip, it is desirable to provide a chip capacitor for noise removal on the wiring board. In recent years, a structure in which a chip capacitor is built in a wiring board has been proposed in order to enhance the effect of removing noise by the chip capacitor (see, for example, Patent Document 1). By adopting such a structure, the length of the signal wiring between the semiconductor chip and the chip capacitor can be shortened, noise in the power wiring supplied to the semiconductor chip is surely removed, and the power supply is stabilized. can do.
JP 2007-258541 A

  For example, a wiring board with a built-in chip capacitor has a housing hole opened in the core material, and the chip capacitor is housed in the housing hole, and a resin filler is placed in the gap between the housing hole and the chip capacitor. It can be manufactured by the procedure of filling and fixing the chip capacitor. The structure of such a wiring board is shown in FIG. However, in the wiring board having such a structure, focusing on the resin filler around the chip capacitor, the rigidity is lower and the thermal expansion coefficient is larger than that of the core material and the chip capacitor. Therefore, when thermal strain occurs in the resin filler, the lateral direction is restricted by the core material and the chip capacitor, and thus acts to deform in the upper and lower lamination directions. At this time, since the above-described wiring laminated portions are formed above and below the core material, there is a possibility that stress due to deformation of the resin filler is applied to the conductor layers of the upper and lower wiring laminated portions. As a result, there is a problem that a partial stress is applied to the wiring in the conductor layer facing the resin filler in the stacking direction, thereby causing defects such as a crack in the wiring.

  The present invention has been made to solve these problems. In a wiring board on which a semiconductor chip is placed and a chip component is built in, a chip capacitor is accommodated in an accommodation hole portion of a core material, and a resin is placed in the gap. An object of the present invention is to provide a wiring board that can reliably prevent defects such as cracks in the wiring in the stacking direction due to deformation due to thermal strain of the resin filler when filling the filler.

  In order to solve the above-described problems, a wiring board according to the present invention is a wiring board on which a semiconductor chip is placed and electrically connected between the semiconductor chip and an external board, and the housing penetrates through an upper surface and a lower surface. A core material having a hole, a first wiring laminated portion having a plurality of connection terminals connected to the semiconductor chip, the insulating layer and the conductor layer being alternately laminated on the upper surface side of the core material; and the core Conductive layers and insulating layers are alternately laminated on the lower surface side of the material, a second wiring laminated portion having a plurality of electrode pads for external connection, a chip component housed in the housing hole portion, and the housing hole portion And a resin filler filled in a gap between the chip component and the side surface of the chip component, and the filling region of the resin filler is opposed to the mounting region of the semiconductor chip in the stacking direction on the upper surface side of the core material On the lower surface side of the core material, the second It is characterized in that wiring in a region facing a filling region the stacking direction of the resin filler out of the conductor layers of the line laminated portion is not formed.

  According to the wiring board of the present invention, the chip component is accommodated in the accommodating hole portion of the core material, and fixed with the resin filler filled in the gap between the accommodating hole portion and the side surface of the chip component, and the upper surface side of the core material The first wiring laminated portion and the second wiring laminated portion on the lower surface side are respectively formed. In the filling region filled with the resin filler, the placement region of the semiconductor chip is opposed to the upper portion in the stacking direction, and the region where the wiring of the second wiring stacking portion is not formed is facing the lower portion in the stacking direction. Is done. Therefore, when the resin filler is deformed due to thermal strain, the upper layer wiring is restrained from being deformed by the high-rigidity semiconductor chip disposed immediately above, and no wiring is formed in the lower layer. It can be avoided reliably.

  The wiring board of the present invention includes the core material, the first wiring laminated portion, the second wiring laminated portion, the chip component, and the resin filler. On the upper surface side, the filling region of the resin filler is opposed to the mounting region of the semiconductor chip in the stacking direction, and on the lower surface side of the core material, the filling region of the resin filler in the conductor layer of the second wiring laminate portion The signal wiring is not formed in a region facing each other in the stacking direction. For example, if power supply wiring and ground wiring are formed in the area opposite to the filling area and the entire wiring area is secured, the influence of wiring cracks is minor, while signal wiring is reliably cracked, etc. Can be prevented.

  In the present invention, the chip component is preferably formed using a material having a smaller coefficient of thermal expansion than the resin filler. As the chip component, a chip capacitor configured using a ceramic sintered body can be used. In this case, a plurality of electrodes connected to the conductor layer of the first wiring multilayer portion are formed on the upper surface of the chip capacitor, and the lower surface of the chip capacitor is connected to the conductor layer of the second wiring multilayer portion. A plurality of electrodes may be formed.

  According to the present invention, in the wiring board on which the semiconductor chip is placed, the chip component is accommodated in the accommodating hole portion of the core material, the resin filler is filled in the gap between the accommodating hole portion and the side surface of the chip component, and the filling is performed. A semiconductor chip mounting region is arranged in the upper portion of the region facing in the stacking direction, and no wiring is formed in the lower portion of the filling region facing in the stacking direction. Therefore, when the resin filler is deformed by thermal strain, the upper conductor layer in the stacking direction is prevented from being deformed by the highly rigid semiconductor chip, and no wiring is formed in the lower layer in the stacking direction. Can be prevented. Therefore, the reliability of the wiring connection in the wiring board can be improved with a simple structure. Further, by adopting a structure in which only the signal wiring is not formed in the lower part in the stacking direction, it is possible to improve the connection reliability of the signal wiring while ensuring the degree of freedom of arrangement of the power supply wiring and the ground wiring.

  Hereinafter, a preferred embodiment of a wiring board to which the present invention is applied will be described with reference to the drawings.

  FIG. 1 is a diagram showing a schematic cross-sectional structure of the wiring board of the present embodiment. The wiring board 10 shown in FIG. 1 has a structure including a core material 11, a first wiring laminated portion 12 on the upper surface side of the core material 11, and a second wiring laminated portion 13 on the lower surface side of the core material 11. Yes. The wiring substrate 10 according to the present embodiment has a chip capacitor 100 built therein and a semiconductor chip 200 placed thereon.

  The core material 11 is made of, for example, an epoxy resin containing glass fiber. The core material 11 is formed with a housing hole 11a penetrating the center in a rectangular shape, and the chip capacitor 100 is housed in the housing hole 11a. As shown in FIG. 1, the chip capacitor 100 has a smaller size in the plane direction than the semiconductor chip 200. The internal structure of the chip capacitor 100 will be described later. A resin filler 50 is filled in the gap between the accommodation hole 11 a and the side surface of the chip capacitor 100. As shown in FIG. 1, the resin filler 50 is filled in the range of the width W1 in the surface direction. The resin filler 50 is made of, for example, a thermosetting resin and has a role of fixing the chip capacitor 100. Further, the resin filler 50 acts to absorb when the chip capacitor 100 and the core material 11 are deformed.

  A conductor layer 21 is formed on the upper surface of the core material 11, and a conductor layer 22 is formed on the lower surface of the core material 11. The core material 11 is formed with a plurality of through-hole conductors 30 penetrating a predetermined portion in the stacking direction. The interior of the through-hole conductor 30 is filled with a resin 31 made of, for example, glass epoxy. The through-hole conductor 30 can connect and conduct any wiring pattern in the upper and lower conductor layers 21 and 22 of the core material 11 in the stacking direction.

  The first wiring laminated portion 12 is formed on the resin insulating layers 14 and 16 formed on the upper surface side of the core material 11, the conductor layer 23 formed on the upper surface of the resin insulating layer 14, and the upper surface of the resin insulating layer 16. The plurality of terminal pads 25 and a solder resist layer 18 covering the top surface of the resin insulating layer 16 are provided. A plurality of via conductors 32 are provided at predetermined positions on the resin insulating layer 14 to connect and conduct the conductor layers 21 and 23 in the laminating direction. The conductor layers 23 and the terminal pads 25 are provided at predetermined positions on the resin insulating layer 16. A plurality of via conductors 34 that are conductively connected in the stacking direction are provided. The solder resist layer 18 is opened at a plurality of locations to expose a plurality of terminal pads 25, and a plurality of solder bumps 40 are formed there. Each solder bump 40 is connected to each pad 201 of the semiconductor chip 200 placed on the wiring substrate 10.

  The second wiring laminated portion 13 is formed on the lower surface of the resin insulating layer 17, the resin insulating layers 15 and 17 formed on the lower surface side of the core material 11, the conductor layer 24 formed on the lower surface of the resin insulating layer 15. The plurality of BGA pads 26 and a solder resist layer 19 covering the lower surface of the resin insulating layer 17 are provided. A plurality of via conductors 33 are provided at predetermined positions of the resin insulating layer 15 to connect and conduct the conductor layers 22 and 24 in the laminating direction. At predetermined positions of the resin insulating layer 17, the conductor layer 24 and the BGA pad 26 are provided. A plurality of via conductors 35 are provided which are connected in the laminating direction. The solder resist layer 19 is opened at a plurality of locations to expose a plurality of BGA pads 26 to which a plurality of solder balls 41 are connected. When the wiring board 10 is used as a BGA package, an external board (not shown) and each part of the wiring board 10 can be electrically connected via a plurality of solder balls 41.

  The internal structure of the chip capacitor 100 of FIG. 1 will be described with reference to FIGS. The chip capacitor 100 according to the present embodiment is a so-called via array type capacitor, and has a structure in which a plurality of ceramic dielectric layers 102 are laminated using a ceramic sintered body 101. The ceramic sintered body 101 is made of a high dielectric constant ceramic such as barium titanate. Between the ceramic dielectric layers 102, the first internal electrode layers 110a and the second internal electrode layers 110b are alternately arranged. The first internal electrode layer 110a functions as an electrode for power supply, the second internal electrode layer 110b functions as an electrode for ground, and both electrodes are disposed to face each other with each ceramic dielectric layer 102 being an insulator interposed therebetween. Thus, a predetermined capacity is formed.

  A plurality of first terminal electrodes 107a and second terminal electrodes 107b are formed on the upper surface of the ceramic sintered body 101, and a plurality of first terminal electrodes 108a and second terminals are formed on the lower surface of the ceramic sintered body 101. An electrode 108b is formed. Further, the ceramic sintered body 101 is formed with a plurality of first via conductors 109 a and a plurality of second via conductors 109 b in which a large number of via holes penetrating all the ceramic dielectric layers 102 are embedded. Each first via conductor 109a connects and connects the upper first terminal electrode 107a and the lower first terminal electrode 108a in the stacking direction. In addition, each second via conductor 109b connects and connects the upper second terminal electrode 107b and the lower second terminal electrode 108b in the stacking direction.

  As shown in the top view of the chip capacitor 100 in FIG. 3, the first and second terminal electrodes 107a and 107b (108a and 108b) and the first and second via conductors 109a and 109b are all arranged in an array. Has been. In FIG. 1, the power supply pad 201 in the semiconductor chip 200 passes through the solder bump 40, the terminal pad 25, the via conductor 34, the conductor layer 23, the via conductor 32, the first terminal electrode 107a, and the first via conductor 109a. In addition to being connected to the first internal electrode layer 110a, it is further connected to the power supply solder ball 41 via the first terminal electrode 108a, the via conductor 33, the conductor layer 24, the via conductor 35, and the BGA pad 26. Is done. The ground pad 201 in the semiconductor chip 200 is connected to the second terminal electrode 107b, the second via conductor 109b, and the second internal electrode layer 110b through the above-described path, and is connected to the ground solder ball 41. Connected to.

  Next, the wiring structure in the wiring board 10 of this embodiment will be described with reference to FIG. FIG. 4 shows the positional relationship in the planar direction of each of the semiconductor chip 200, the chip capacitor 100, and the filling region R1 filled with the resin filler 50 with respect to the entire wiring substrate 10. The filling region R1 is a region having a width W1 sandwiched between an inner side rectangle that matches the side surface of the chip capacitor 100 and an outer side rectangle that matches the side surface of the receiving hole 11a, and the entire region is a semiconductor chip. It is in the relationship which opposes 200 mounting area | regions in a lamination direction. For convenience, FIG. 4 shows a case where the four sides of the filling region R1 have a uniform width W1, but the width may be different depending on the position of the filling region R1.

  The wiring structure of the wiring board 10 according to the present embodiment is characterized in that no wiring is formed in the region of the second wiring laminated portion 13 that faces the filling region R1. In general, the thermal expansion coefficient of the resin filler 50 is about several tens of ppm / ° C., which is much larger than the core material 11 and the chip capacitor 100. Therefore, when heat is applied to the wiring board 10, the resin filler 50 is deformed due to thermal strain. In this case, since the planar direction of the resin filler 50 is surrounded by the highly rigid core material 11 and the chip capacitor 100, the resin filler 50 is deformed in the stacking direction. Since the highly rigid semiconductor chip 200 exists above the first wiring laminated portion 12 above the resin region R1, even if stress is applied to the first wiring laminated portion 12 from below, the high rigidity of the semiconductor chip 200 is high. Therefore, deformation is suppressed.

  However, since it is necessary for the resin filler 50 and the semiconductor chip 200 to face each other at a sufficiently close distance, it is desirable that the thickness of the first wiring laminated portion 12 is about several tens of μm in total. In addition, if the number of the plurality of pads 201 interposed between the semiconductor chip 200 and the first wiring laminated portion 12 is small, the effect of suppressing the deformation of the first wiring laminated portion 12 is reduced. It is desirable that they are arranged in a density.

  On the other hand, in the second wiring laminated portion 13 below the filling region R1, there is no highly rigid member like the semiconductor chip 200. Therefore, when the resin filler 50 is deformed by thermal strain, the wiring below the second wiring laminated portion 13 is not provided. Stress is applied to the surface, which causes cracks and the like. Therefore, in the present embodiment, since no wiring is formed in a region facing at least the filling region R1 in the stacking direction in at least the second wiring stacked portion 13, it is possible to prevent the above-described defects such as cracks. In the second wiring stacked portion 13, since stress is applied not only in the region facing the filling region R1, but also in the vicinity thereof, it is desirable not to form the wiring in a region having a width somewhat larger than the width W1.

  Next, the manufacturing method of the wiring board 10 of this embodiment is demonstrated with reference to FIGS. First, as shown in FIG. 5, the core material 11 having the accommodation hole 11a is prepared and prepared. In producing the core material 11, for example, a copper-clad laminate in which copper foil is pasted on both sides of a base having a square shape of 400 mm on a side and a thickness of 0.80 mm is prepared. Drilling is performed using a drill to form a through hole at the position of the through hole conductor 30. Moreover, a copper-clad laminated board is drilled using a router, and the through-hole used as the accommodation hole part 11a is previously formed in the predetermined position. In addition, the accommodation hole part 11a is formed in 14.0 mm on one side, for example. On the other hand, the electroless copper plating and the electrolytic copper plating are applied to the through hole to be the through-hole conductor 30, and then a paste made of an epoxy resin is printed and cured to form the resin 31. Furthermore, the copper foils on both sides of the copper-clad laminate are etched, and the conductor layers 21 and 22 are formed on the upper and lower sides by using, for example, a subtractive method. Specifically, after electroless copper plating is performed and electrolytic copper plating is performed using that portion as a common electrode. A dry film having a predetermined pattern is formed by laminating the dry film and performing exposure and development. In this state, unnecessary electrolytic copper plating layers, electroless copper plating layers, and copper foils are removed by etching, and then the dry film is peeled off to obtain the core material 11 shown in FIG. 5 shows a state in which the upper surface of the core material 11 in FIG. 1 is directed downward.

  On the other hand, the chip capacitor 100 having the structure of FIG. 2 is prepared and prepared. When manufacturing the chip capacitor 100, a nickel paste is screen-printed on a ceramic green sheet and dried to form the first internal electrode layer 110a / second internal electrode layer 110b. And the green sheet in which the 1st internal electrode layer 110a was formed, and the green sheet in which the 2nd internal electrode layer 110b were formed are laminated alternately, giving a pressing force in the lamination direction, and integrating each green sheet, A laminate is formed. Subsequently, a plurality of via holes are formed through the stacked body using a laser processing machine, and each via hole is filled with nickel paste to form the first via conductor 109a and the second via conductor 109b. Then, a paste is printed on the upper surface of the stacked body to form a metallized layer of the first terminal electrode 107a and the second terminal electrode 107b. Further, a paste is printed on the lower surface of the stacked body to form a metallized layer of the first terminal electrode 108a and the second terminal electrode 108b. Next, the laminate is dried and degreased, and the laminate is fired at a predetermined temperature for a predetermined time. As a result, barium titanate and nickel in the paste are simultaneously sintered, and a ceramic sintered body 101 is obtained. The first terminal electrodes 107a and 108a and the second terminal electrodes 107b and 108b of the ceramic sintered body 101 are subjected to, for example, electrolytic copper plating with a thickness of about 10 μm to form a copper plating layer. Complete.

  Next, as shown in FIG. 6, a peelable adhesive tape 60 is placed in close contact with the bottom of the accommodation hole 11 a. The adhesive tape 60 is supported by a support base 61. Then, using the mounting device, the chip capacitor 100 is accommodated in the accommodation hole 11 a, and the chip capacitor 100 is pasted and temporarily fixed with the adhesive tape 60. In addition, the chip capacitor 100 fixed to the adhesive tape 60 is in a state where the upper surface is directed downward like the core material 11. Next, as shown in FIG. 7, a resin filler 50 made of a thermosetting resin is filled into the gap between the accommodation hole 11 a and the side surface of the chip capacitor 100 using a dispenser device. The resin filler 50 is cured by heat treatment, and the chip capacitor 100 is fixed inside the accommodation hole 11a. At this time, each of the conductor layer 21 of the core material 11 and the first terminal electrode 107a and the second terminal electrode 107b of the chip capacitor 100 is in contact with the adhesive tape 60, so that it is formed on a flat surface whose position is aligned in the stacking direction. Is done.

  Next, as shown in FIG. 8, after the chip capacitor 100 is fixed, the adhesive tape 60 is peeled off. Thereafter, the adhesive material remaining on the peeled adhesive tape 60 is removed by subjecting the upper surface of the core material 11 and the upper surface of the chip capacitor 100 to solvent cleaning by acid degreasing and polishing. Subsequently, the surface of the copper plating layer above the first terminal electrode 107 a and the second terminal electrode 107 b is roughened, and the surface of the conductor layer 21 above the core material 11 is roughened. After finishing the roughening, the core material 11 and the chip capacitor 100 are washed.

  Next, film-like insulating resin materials mainly composed of epoxy resin are laminated on the upper and lower surfaces of the core material 11 and the chip capacitor 100, respectively. Then, the insulating resin material is cured by pressurizing and heating under vacuum to form an upper surface side resin insulating layer 14 and a lower surface side resin insulating layer 15 as shown in FIG. Subsequently, as shown in FIG. 10, a plurality of via conductors 32 are formed in the resin insulating layer 14, and a plurality of via conductors 33 are formed in the resin insulating layer 15. At this time, a plurality of via holes are formed in the resin insulating layers 14 and 15 by laser processing, and after desmear processing for removing smears therein, via conductors 32 and 33 are formed in the via holes.

  Thereafter, as shown in FIG. 1, the surfaces of the resin insulating layers 14 and 15 are patterned to form conductor layers 23 and 24, respectively. Next, a photosensitive epoxy resin is applied to the upper surface of the resin insulating layer 14 and the lower surface of the resin insulating layer 15, respectively, and exposed and developed to form the resin insulating layers 16 and 17. Then, via conductors 34 and 35 are formed inside blind holes previously formed in the resin insulating layers 16 and 17. Subsequently, a plurality of terminal pads 25 are formed on the top of the resin insulating layer 16, and a plurality of BGA pads 26 are formed on the bottom of the resin insulating layer 17. Next, solder resist layers 18 and 19 are formed by applying and curing a photosensitive epoxy resin on the upper surface of the resin insulating layer 16 and the lower surface of the resin insulating layer 17, respectively. Thereafter, openings are patterned in the solder resist layer 18 to form a plurality of solder bumps 40 connected to the plurality of terminal pads 25. Also, openings are patterned in the solder resist layer 19 to form a plurality of solder balls 41 connected to the plurality of BGA pads 26. The wiring board 10 of this embodiment is completed by the above procedure.

  The contents of the present invention have been specifically described above based on the present embodiment, but the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention. FIG. 11 shows a schematic cross-sectional structure of the wiring board 10 when the arrangement of the wirings in the second wiring laminated portion 13 is changed as a modification of the present embodiment. The wiring board 10 shown in FIG. 11 is different from the wiring pattern of the conductor layer 24 in the second wiring laminated portion 13 in FIG. That is, the ground wiring 24a is formed in the conductor layer 24 of the second wiring stacked portion 13 in a region facing the filling region R1 in the stacking direction. In FIG. 11, the signal wiring of the conductor layer 24 is the same as that of FIG. 1, but a solid ground wiring 24a is formed in a region where the signal wiring is not formed. In the wiring substrate 10 of FIG. 11, the structure other than the ground wiring 24a is the same as that of FIG.

  In the modification shown in FIG. 11, the portion of the ground wiring 24 a immediately below the filling region R <b> 1 is a part of the ground wiring 24 a having a large area even if a crack or the like is generated due to partial stress from the resin filler 50. However, the overall connection reliability of the wiring board 10 is not deteriorated. As described above, in the wiring substrate 10 of the present embodiment, a structure in which at least the signal wiring is not formed in the region facing the filling region R1 on the lower surface side of the core material 11 in the stacking direction can be adopted. It is possible to improve reliability by preventing cracks in the wiring. In this case, in a region facing the filling region R1, as shown in FIG. 11, in addition to the formation of the ground wiring 24a, a power supply wiring for supplying a predetermined power supply voltage may be formed.

  FIG. 12 shows a schematic cross-sectional structure of the wiring board 10 when the method for forming the through-hole conductor 30 and the resin 31 in FIG. 1 is changed as another modification of the present embodiment. The wiring board 10 shown in FIG. 12 is different from the through-hole conductor 30 and the resin 31 shown in FIG. 1 in that the through-hole conductor 30a and the resin 31a that extend in the stacking direction and penetrate the upper and lower resin insulating layers 14 and 15 are formed. Is different. Therefore, when manufacturing the wiring substrate 10, it is necessary to form the through-hole conductor 30 a and the resin 31 a after forming the resin insulating layers 14 and 15 on and under the core material 11. In the wiring substrate 10 of FIG. 12, the structure other than the through-hole conductor 30a and the resin 31a is the same as that of FIG.

It is a figure which shows the general | schematic cross-section of the wiring board of this embodiment. It is sectional drawing of the chip capacitor of FIG. It is a top view of the chip capacitor of FIG. It is a figure explaining the wiring structure in the wiring board of this embodiment. It is a 1st figure explaining the manufacturing method of the wiring board of this embodiment. It is a 2nd figure explaining the manufacturing method of the wiring board of this embodiment. It is a 3rd figure explaining the manufacturing method of the wiring board of this embodiment. It is a 4th figure explaining the manufacturing method of the wiring board of this embodiment. It is a 5th figure explaining the manufacturing method of the wiring board of this embodiment. It is a 6th figure explaining the manufacturing method of the wiring board of this embodiment. As a modified example of the present embodiment, it is a diagram showing a schematic cross-sectional structure of a wiring board when the arrangement of wirings in a second wiring laminated portion is changed. It is a figure which shows the general | schematic cross-section of a wiring board at the time of changing the formation method of a through-hole conductor and resin as another modification of this embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Wiring board 11 ... Core material 11a ... Accommodating hole part 12 ... 1st wiring laminated part 13 ... 2nd wiring laminated part 14, 15, 16, 17 ... Resin insulation layers 18, 19 ... Solder resist layers 21, 22, 23 , 24 ... conductor layer 25 ... terminal pad 26 ... BGA pad 30 ... through-hole conductor 31 ... resin 32, 33, 34, 35 ... via conductor 40 ... solder bump 41 ... solder ball 50 ... resin filler 100 ... chip capacitor 200 ... Semiconductor chip 201 ... Pad R1 ... Filling area

Claims (5)

A wiring substrate on which a semiconductor chip is placed and electrically connected between the semiconductor chip and an external substrate,
A core material having an accommodation hole that penetrates the upper and lower surfaces; and
Insulating layers and conductor layers are alternately laminated on the upper surface side of the core material, and a first wiring laminated portion having a plurality of connection terminals connected to the semiconductor chip;
A second wiring laminated portion having a plurality of electrode pads for external connection, wherein conductor layers and insulating layers are alternately laminated on the lower surface side of the core material;
A chip component housed in the housing hole;
A resin filler filled in a gap between the accommodation hole and the side surface of the chip component;
A filling region of the resin filler is opposed to the mounting region of the semiconductor chip in the stacking direction on the upper surface side of the core material, and of the conductor layer of the second wiring stacked portion on the lower surface side of the core material A wiring board, wherein no wiring is formed in a region facing the filling region of the resin filler in the stacking direction. A wiring substrate on which a semiconductor chip is placed and electrically connected between the semiconductor chip and an external substrate,
A core material having an opening that penetrates the upper surface and the lower surface;
Insulating layers and conductor layers are alternately laminated on the upper surface side of the core material, and a first wiring laminated portion having a plurality of connection terminals connected to the semiconductor chip;
A second wiring laminated portion having a plurality of electrode pads for external connection, wherein conductor layers and insulating layers are alternately laminated on the lower surface side of the core material;
A chip component housed in the housing hole;
A resin filler filled in a gap between the accommodation hole and the side surface of the chip component;
A filling region of the resin filler is opposed to the mounting region of the semiconductor chip in the stacking direction on the upper surface side of the core material, and of the conductor layer of the second wiring stacked portion on the lower surface side of the core material A wiring board, wherein a signal wiring is not formed in a region facing the filling region of the resin filler in the stacking direction.   The wiring board according to claim 1, wherein the chip component is formed using a material having a smaller thermal expansion coefficient than the resin filler.   The wiring board according to claim 3, wherein the chip component is a chip capacitor configured using a ceramic sintered body. A plurality of electrodes connected to the conductor layer of the first wiring multilayer portion are formed on the upper surface of the chip capacitor, and a plurality of electrodes connected to the conductor layer of the second wiring multilayer portion are formed on the lower surface of the chip capacitor. The wiring board according to claim 4, wherein the wiring board is formed.

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