JP2010124046A - Level shift circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a level shift circuit capable of transiting to a standby state of the next signal in a limited time by preventing malfunction caused by dispersion of discharge time of capacitors. <P>SOLUTION: The level shift circuit converts a first voltage level to a second one different from the first voltage level. The level shift circuit includes: a set level circuit 20 for transmitting set signals for setting a logical voltage state of the second voltage level via a first capacitor C1; a reset level circuit 20 for transmitting reset signals for resetting a logical voltage state of the second voltage level via a second capacitor C2; and a charge/discharge circuit 20 that discharges or charges voltage at one end of the first capacitor when the reset level circuit resets the logical voltage state of the second voltage level, and charges or discharges voltage at one end of the second capacitor after the completion of the discharge or charge. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a level shift circuit for providing a level shift required in a switch of a half bridge or full bridge configuration.

  As a conventional level shift circuit, for example, a level shift circuit described in Patent Document 1 is known.

  In this level shift circuit, the high-side ground potential at the midpoint between the high-side switch and the low-side switch in the half-bridge configuration is synchronized with the on / off operation of the high-side switch and the low-side switch with respect to the ground potential, for example. The voltage level changes greatly from zero volts to a maximum of 400V. Therefore, a high side driver that applies a potential higher than the high side ground potential is used for the gate of the high side switch.

  In addition, a first capacitor and a second capacitor are provided as two passive devices, the rising edge of the pulse signal is input to the first capacitor via the first driver, and the rising edge of the pulse signal falls via the inverter. An edge is input to the second capacitor. The first capacitor and the second capacitor function to generate a required current by a rising edge and a falling edge.

  In other words, a temporary current is generated in the first capacitor and the second capacitor, and the proper current required to properly drive a half-bridge driver or a similar type circuit using the temporary current. At some point, the latch is set or reset. The high side driver turns on or off the high side switch by a set signal or a reset signal from the latch.

In the above configuration, when the charging voltage of the first capacitor and the second capacitor changes due to an external factor regardless of the set signal and the reset signal, a temporary current flows through the first capacitor and the second capacitor.
JP 2005-512444 A

  In the above configuration, an inductance load such as a transformer or a reactor may be connected to the midpoint between the high-side switch and the low-side switch having a half bridge configuration. Here, vibration is generated by the inductance component of the inductance load due to voltage fluctuation and current fluctuation due to switching operation by the high side switch and the low side switch.

  Since the midpoint between the high-side switch and the low-side switch is the high-side ground potential of the high-side driver, this vibration causes the entire high-side potential of the high-side driver to vibrate. Due to this factor, when the charging voltage of the first capacitor and the second capacitor is changed by the vibration regardless of the set signal and the reset signal, a temporary current flows through the first capacitor and the second capacitor. For this reason, the latch circuit malfunctions and a signal transmission failure to the high side switch occurs.

  In the conventional level shift circuit, as shown in FIG. 10, when the high-side ground potential VS is significantly lowered after the reset signal Reset is input at a high level, the high level of the first capacitor C1 and the second capacitor C2 is increased. The side potential is at a high level. In addition, it is necessary to provide a certain discharge period for the first and second capacitors C1 and C2 from the reception of the reset signal Reset until the set signal Set can be received.

  However, since the high-side potentials of the first capacitor C1 and the second capacitor C2 gradually decrease with respect to the decrease in the high-side ground potential VS, the discharge times of the first and second capacitors C1 and C2 vary. May cause malfunction.

  An object of the present invention is to provide a level shift circuit capable of preventing a malfunction due to variations in capacitor discharge time and shifting to a standby state for the next signal in a short time.

  In order to solve the above-mentioned problem, the invention of claim 1 is a level shift circuit for converting a first voltage level to a second voltage level different from the first voltage level, wherein the logic voltage state of the second voltage level is A set level circuit for transmitting a set signal for setting the first voltage via a first capacitor, a reset level circuit for transmitting a reset signal for resetting the logic voltage state of the second voltage level via a second capacitor, and the reset level When the logic voltage state of the second voltage level is reset by the circuit, the voltage at one end of the first capacitor is discharged or charged, and after the discharge or charging is completed, the voltage at one end of the second capacitor is discharged or charged. And a charge / discharge circuit to be charged.

  According to a second aspect of the present invention, in the level shift circuit according to the first aspect, one end of each of the capacitors is clamped or opened by a logic voltage state of the second voltage level.

  The invention according to claim 3 is a level shift circuit for converting the first voltage level to a second voltage level different from the first voltage level, wherein the logic voltage state of the second voltage level is set via the first capacitor. A set level circuit for transmitting a set signal to be transmitted; a reset level circuit for transmitting a reset signal for resetting a logic voltage state of the second voltage level through a second capacitor; the set signal at the second voltage level; and A reference level circuit for setting a reference value for detecting a reset signal via a third capacitor, and a voltage at one end of the first capacitor when the logical voltage state of the second voltage level is reset by the reset level circuit Is discharged or charged, and after this discharge or charging is completed, the voltage at one end of the second capacitor is discharged or charged. Characterized in that it comprises an electric circuit.

  According to a fourth aspect of the present invention, in the level shift circuit according to the third aspect, the charge / discharge circuit has a voltage at one end of the first capacitor when the logic voltage state at the second voltage level is reset by the reset level circuit. At the same time as charging or discharging, the reference level circuit is reset, and after the discharging or charging is completed, the voltage at one end of the second capacitor is discharged or charged.

  According to a fifth aspect of the present invention, in the level shift circuit according to the third aspect, the set level circuit detects a potential difference between the set signal and a reference value signal set by the reference level circuit, and the potential difference is predetermined. When the voltage level is greater than or equal to a value, a logic voltage state is set, and the reset level circuit detects a potential difference between the reset signal and the reference value signal, and when the potential difference is greater than or equal to the predetermined value, the logic voltage state is set. It is characterized by resetting.

  A sixth aspect of the present invention is the level shift circuit according to any one of the third to fifth aspects, wherein one end of each capacitor is clamped or opened by a logic voltage state of the second voltage level. Features.

  According to the present invention, the charge / discharge circuit discharges or charges the voltage at one end of the first capacitor when the logic voltage state of the second voltage level is reset by the reset level circuit, and after the discharge or charge is completed, Since the voltage at one end of the second capacitor is discharged or charged, the high-side potential of each capacitor is instantaneously reduced in accordance with the reduction of the high-side ground potential, and malfunction due to variations in the capacitor discharge time can be prevented and reduced. Transition to the standby state for the next signal in time.

  Hereinafter, a level shift circuit according to an embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a circuit configuration diagram showing a level shift circuit according to a first embodiment of the present invention. The level shift circuit shown in FIG. 1 includes a low side circuit 1a, a high side circuit 2a, a low side circuit 1a, and first and second capacitors C1 and C2 that connect the high side circuit 2a.

  The low-side circuit 1 a includes a buffer 11, a buffer 12, and first and second clamp circuits 13 and 14. The buffer 11 drives the first capacitor C1 in synchronization with the set signal input from the set input terminal. The buffer 12 drives the second capacitor C2 in synchronization with the reset signal input from the reset input terminal.

  The first clamp circuit 13 has an input side connected to the output of the buffer 11 and an output side connected to one end of the first capacitor C1, and clamps the low-side terminal voltage to a voltage within a certain range. The second clamp circuit 14 has an input side connected to the output of the buffer 12 and an output side connected to one end of the second capacitor C2, and clamps the low-side terminal voltage to a voltage within a certain range.

  The high side circuit 2a includes a signal detection circuit 20. The signal detection circuit 20 is connected to the other end of the first capacitor C1 and the other end of the second capacitor C2. The signal detection circuit 20 corresponds to the set level circuit and the reset level circuit of the present invention, detects the voltage at the other end of the first capacitor C1, receives the set signal, and detects the voltage at the other end of the second capacitor C2. Then, the reset signal is received.

  A latch (not shown) generates an output signal based on the detection signal from the signal detection circuit 20. The first and second capacitors C1 and C2 are used for transmitting and receiving a set signal and a reset signal between the high side circuit 2a and the low side circuit 1a, respectively.

  FIG. 2 is a circuit configuration diagram showing a low side circuit in the level shift circuit according to the first embodiment of the present invention.

  In the buffer 11 shown in FIG. 2, current sources I <b> 10 and I <b> 11 are connected to the buffer 11. In the first clamp circuit 13 shown in FIG. 2, the NPN transistor Q10, the PNP transistor Q11, and the current source I12 constitute a first plus clamp circuit. The first plus clamp circuit prevents the low-side potential of the first capacitor C1 from exceeding the Vreg potential. The base and collector of the transistor Q10 are connected to the power supply Vreg, the emitter of the transistor Q10 is connected to one end of the current source I12 and the base of the transistor Q11, and the other end of the current source I12 is grounded. The emitter of the transistor Q11 is connected to the first capacitor C1 and the output of the buffer 11.

  The NPN transistor Q12, the NPN transistor Q13, and the current source I13 form a first minus clamp circuit. The first minus clamp circuit prevents the low-side potential of the first capacitor C1 from becoming lower than the ground potential. A series circuit of a current source I13 and a transistor Q12 is connected between the power supply Vreg and the ground. The collector and base of the transistor Q12 are commonly connected. The base of the NPN transistor Q13 is connected to the connection point between the current source I13 and the collector and base of the transistor Q12. The collector of the transistor Q13 is connected to the power supply Vreg, and the emitter of the transistor Q13 is connected to the first capacitor C1 and the output of the buffer 11.

  In the buffer 12 shown in FIG. 2, current sources I20 and I21 are connected to the buffer 12. In the second clamp circuit 14 shown in FIG. 2, the NPN transistor Q20, the PNP transistor Q21, and the current source I22 form a second plus clamp circuit. The second plus clamp circuit prevents the low-side potential of the second capacitor C2 from exceeding the Vreg potential.

  The base and collector of the transistor Q20 are connected to the power supply Vreg, the emitter of the transistor Q20 is connected to one end of the current source I22 and the base of the transistor Q21, and the other end of the current source I22 is grounded. The emitter of the transistor Q21 is connected to the second capacitor C2 and the output of the buffer 12.

  The NPN transistor Q22, the NPN transistor Q23, and the current source I23 constitute a second minus clamp circuit. The second minus clamp circuit prevents the low-side potential of the second capacitor C2 from becoming lower than the ground potential. A series circuit of a current source I23 and a transistor Q22 is connected between the power supply Vreg and the ground. The collector and base of the transistor Q22 are commonly connected. The base of the NPN transistor Q23 is connected to the connection point between the current source I23 and the collector and base of the transistor Q22. The collector of the transistor Q23 is connected to the power supply Vreg, and the emitter of the transistor Q23 is connected to the second capacitor C2 and the output of the buffer 12.

  Further, the buffers 11 and 12 change the potential of one end of the first and second capacitors C1 and C2 according to the input signal. At this time, since the voltage across the first and second capacitors C1, C2 does not change, the voltage at the other end of the first and second capacitors C1, C2 also changes in the same manner.

  Further, when the voltage at the other end of the first and second capacitors C1 and C2 increases or decreases, the voltage at one end of the first and second capacitors C1 and C2 also increases or decreases.

  The terminals of the first and second capacitors C1 and C2 are respectively connected to the low side circuit 1a, and the voltage of each connection terminal is within the range from the power supply voltage Vreg to the ground voltage by each plus clamp circuit and each minus clamp circuit. Limited. For this reason, no overvoltage or reverse voltage is applied to the low-side circuit 1a, and malfunctions and element damage can be prevented.

  The output of the buffer 11 is limited by the current sources I10 and I11, and the output of the buffer 12 is limited by the current sources I20 and I21. That is, by limiting the output capability of the buffers 11 and 12 by the current sources I10, I11, I20, and I21, it is possible to reduce stress due to excessive current due to charging and discharging of the first and second capacitors C1 and C2.

  FIG. 3 is a circuit configuration diagram showing a high side circuit in the level shift circuit according to the first embodiment of the present invention.

  The signal detection circuit 20 shown in FIG. 3 includes a signal detection circuit 21a, a signal detection circuit 22, and a latch 23.

  The signal detection circuit 21a includes a current source I50, diodes D50 and D55, a comparator COMP2, an N-type MOS-FET Q50, a resistor R50, a P-type MOS-FET Q55, an AND circuit AND1, and an OR circuit OR1. The N-type MOS-FET Q50, the resistor R50, the P-type MOS-FET Q55, the AND circuit AND1, and the OR circuit OR1 constitute a charge / discharge circuit.

  The current source I50 is connected between the other end of the first capacitor C1 and the high side ground VS. The high side ground VS is a potential at a connection point between the high side switch and the low side switch. The diode D50 is connected in parallel with the current source I50. The diode D55 is connected between the other end of the first capacitor C1 and the high side power supply VB.

  In the comparator COMP2, the reference power supply vref50 is connected to the inverting input terminal, and the other end of the first capacitor C1 is input to the non-inverting input terminal. The comparator COMP2 constitutes a comparison circuit, and when the voltage difference between the non-inverting input terminal voltage and the inverting input terminal voltage exceeds a certain level, the output changes from L level to H level.

  A series circuit of the N-type MOS-FET Q50 and the resistor R50 is connected between both ends of the diode D50, and the P-type MOS-FET Q55 is connected between both ends of the diode D55. The gate of the P-type MOS-FET Q55 is connected to the inverting output terminal Qb of the latch 23 and one input terminal of the AND circuit AND1.

  The other input terminal of the AND circuit AND1 is connected to the output terminal of the comparator COMP2 and one input terminal of the AND circuit AND2. The output terminal of the AND circuit AND1 is connected to one input terminal of the OR circuit OR1, and the other input terminal of the OR circuit OR1 is connected to the output terminal of the AND circuit AND2. The output terminal of the OR circuit OR1 is connected to the gate of the N-type MOS-FET Q50.

  The signal detection circuit 22 shown in FIG. 3 includes a current source I51, diodes D51 and D56, a comparator COMP1, an N-type MOS-FET Q51, a resistor R51, and an AND circuit AND2. The N-type MOS-FET Q51, resistor R51, and AND circuit AND2 constitute a discharge circuit.

  The current source I51 is connected between the other end of the second capacitor C2 and the high side ground VS. The diode D51 is connected in parallel to the current source I51. The diode D56 is connected between the other end of the second capacitor C2 and the high side power supply VB.

  In the comparator COMP1, the reference power supply Vref51 is connected to the inverting input terminal, and the other end of the second capacitor C2 is input to the non-inverting input terminal. The comparator COMP1 forms a comparison circuit, and when the voltage difference between the non-inverting input terminal voltage and the inverting input terminal voltage exceeds a certain level, the output changes from L level to H level.

  In the latch 23, the output of the comparator COMP2 is input to the set terminal S, and the output of the comparator COMP1 is input to the reset terminal R.

  A series circuit of an N-type MOS-FET Q51 and a resistor R51 is connected between both ends of the diode D51.

  One input terminal of the AND circuit AND2 is connected to the output terminal of the comparator COMP2, and the other input terminal of the AND circuit AND2 is connected to the output terminal of the comparator COMP1. The output terminal of the AND circuit AND2 is connected to the gate of the N-type MOS-FET Q51 and the other input terminal of the OR circuit OR1.

  FIG. 4 is an operation waveform diagram of each part in the level shift circuit according to the first embodiment of the present invention. The operation of the high side circuit shown in FIG. 3 will be described with reference to FIG.

  First, when the set signal Set is input at time t1, the voltage at the other end of the first capacitor C1 rises, and the latch 23 composed of a flip-flop circuit is set. When the latch 23 is set, the MOS-FET Q55 is turned on, and the potential of the other end of the first capacitor C1 is fixed to the high side power supply VB.

  Next, when the reset signal Reset is input at time t4, the potential at the other end of the second capacitor C2 rises, and the latch 23 is reset by the comparator COMP1. Then, the inversion output terminal Qb of the latch 23 is inverted to a high level. At this time, since the output of the comparator COMP2 remains at a high level, the AND circuit AND1 changes from a low level to a high level output, and the MOS-FET Q50 is changed. Turn it on.

  When the MOS-FET Q50 is turned on, the charge of the first capacitor C1 is discharged to the high side ground VS, and when the potential of the first capacitor C1 is lowered, the output of the comparator COMP2 changes to a low level. Then, the AND circuit AND2 outputs a high level, the MOS-FET Q51 is turned on, and the second capacitor C2 is discharged. For this reason, the output of the comparator COMP1 changes to the low level, and the high side circuit 2 enters a state of waiting for the set signal.

  When the high-side ground potential VS is significantly lowered at the timing when the high-side output is stopped by the reset signal Reset, the potentials at the other ends of the first and second capacitors C1 and C2 are clamped to the high-side power supply VB. In this state, a high level signal is input to the latch 23 for both set and reset. Here, by setting the logic configuration of the latch 23 to the reset signal priority, the reset of the latch 23 is prevented.

  When the high side ground VS decreases to the ground level (time t6), the potential at the other end of the first capacitor C1 is discharged by the MOS-FET 50, and the output of the comparator COMP2 changes to the low level. Then, the AND circuit AND2 outputs a high level, the MOS-FET Q51 is turned on, and the second capacitor C2 is discharged. For this reason, the output of the comparator COMP1 changes to the low level, and the high side circuit 2 enters a state of waiting for the set signal.

  Therefore, as shown in FIG. 4, the high-side terminal voltages of the first and second capacitors C1 and C2 do not change with a delay with respect to the change of the high-side ground voltage VS.

  That is, the period from when the reset signal is transmitted by the second capacitor C2 to when the set signal can be received again is the sum of the delay time of the comparators COMP1 and COMP2, and the delay time of the latch 23 and the logic gate. The time is shorter than the time that is reset by natural discharge by the discharge current sources I50 and I51.

  Thus, according to the level shift circuit of the first embodiment, the charge / discharge circuit discharges or charges the voltage at one end of the first capacitor C1 when the reset signal is input, and after the discharge or charge is completed, Since the voltage at one end of the two capacitors C2 is discharged or charged, the high-side potentials of the capacitors C1 and C2 are instantaneously lowered according to the drop in the high-side ground potential VS, and the first and second capacitors C1 and C2 Therefore, it is possible to prevent malfunction due to variations in the discharge time, and shift to a standby state for the next signal in a minimum time.

  FIG. 5 is a circuit diagram showing a level shift circuit according to the second embodiment of the present invention. The level shift circuit according to the second embodiment illustrated in FIG. 5 includes a low side circuit 1 in which a third clamp circuit 15 is further provided in the configuration of the low side circuit 1a illustrated in FIG. 1, and a high side having signal detection circuits 21b and 22b and a latch 23. The circuit 2 includes a third capacitor C3 connected to the output terminal of the third clamp circuit 15 and the input terminals of the signal detection circuits 21b and 22b.

  A series circuit of a low-side switch Q1 made of a MOS-FET and a high-side switch Q2 made of a MOS-FET is connected between the power source Vin and the ground. The low side switch Q1 and the high side switch Q2 constitute a half bridge circuit. The high side switch Q2 is driven by the drive circuit 24.

  A full bridge circuit may be used instead of the half bridge circuit.

  The signal detection circuit 21b corresponds to the set level circuit of the present invention, detects the voltage difference between the voltage of the first capacitor C1 and the voltage of the third capacitor C3 (corresponding to the reference value signal of the present invention), and the voltage difference Is equal to or greater than a predetermined value, a set signal is received from the first clamp circuit 13 and the logic voltage state is set in the latch 23. The signal detection circuit 22b corresponds to the reset level circuit of the present invention, detects the voltage difference between the voltage of the second capacitor C2 and the voltage of the third capacitor C3, and the second clamp when the voltage difference is greater than or equal to a predetermined value. Receiving the reset signal from the circuit 14, the logic voltage state is reset in the latch 23.

  FIG. 6 is a circuit diagram showing a low side circuit in the level shift circuit according to the second embodiment of the present invention. Since the first and second clamp circuits 13 and 14 have been described with reference to FIG. 2, the configuration of the third clamp circuit 15 will be described here.

  In the third clamp circuit 15 shown in FIG. 6, the NPN transistor Q30, the PNP transistor Q31, and the current source I31 constitute a third plus clamp circuit. The third plus clamp circuit prevents the low-side potential of the third capacitor C3 from becoming equal to or higher than the Vreg potential. The third capacitor C3 is grounded via the current source I30.

  The base and collector of the transistor Q30 are connected to the power supply Vreg, the emitter of the transistor Q30 is connected to one end of the current source I31 and the base of the transistor Q31, and the other end of the current source I31 is grounded. The emitter of the transistor Q31 is connected to the third capacitor C3 and the current source I30.

  The NPN transistor Q32, the NPN transistor Q33, and the current source I33 form a third minus clamp circuit. The third minus clamp circuit prevents the low-side potential of the third capacitor C3 from becoming lower than the ground potential. A series circuit of a current source I33 and a transistor Q32 is connected between the power supply Vreg and the ground. Transistor Q32 has a collector and a base commonly connected. The base of the NPN transistor Q33 is connected to the connection point between the current source I33 and the collector and base of the transistor Q32. The collector of the transistor Q33 is connected to the power supply Vreg, and the emitter of the transistor Q33 is connected to the third capacitor C3 and the current source I30.

  According to the above configuration, the first and second clamp circuits 13 and 14 of the first embodiment shown in FIG. 2 operate in the same manner, and similar effects can be obtained.

  FIG. 7 is a circuit configuration diagram showing a high side circuit in the level shift circuit according to the second embodiment of the present invention.

  In FIG. 7, the signal detection circuit 21b is different in the comparator COMP2a from the configuration of the signal detection circuit 21a shown in FIG.

  The signal detection circuit 22b further includes a current source I52, an N-type MOS-FET Q52, a resistor R52, diodes D52 and D57, and a comparator COMP1a in addition to the signal detection circuit 22 shown in FIG. The N-type MOS-FET Q52 and the resistor R52 constitute a discharge circuit.

  A series circuit of an N-type MOS-FET Q52 and a resistor R52 is connected between both ends of the diode D52. One input terminal of the AND circuit AND2 is connected to the output terminal of the comparator COMP2a, and the other input terminal of the AND circuit AND2 is connected to the output terminal of the comparator COMP1a and the gate of the N-type MOS-FET Q52.

  In the comparator COMP2a, the other end of the third capacitor C3 is connected to the inverting input terminal, and the other end of the first capacitor C1 is input to the non-inverting input terminal. The comparator COMP2a constitutes a comparison circuit, and when the voltage difference between the non-inverting input terminal voltage and the inverting input terminal voltage exceeds a certain level, the output changes from L level to H level. In the comparator COMP1a, the other end of the third capacitor C3 is connected to the inverting input terminal, and the other end of the second capacitor C2 is input to the non-inverting input terminal. The comparator COMP1a constitutes a comparison circuit, and when the voltage difference between the non-inverting input terminal voltage and the inverting input terminal voltage exceeds a certain level, the output changes from L level to H level.

  As soon as the output of the comparator COMP1a becomes H level, the N-type MOS-FET Q52 is turned on. When the N-type MOS-FET Q52 is turned on, the charge of the third capacitor C3 is discharged, and the reference voltage becomes the high side ground VS potential. However, since the non-inverting input terminal voltages of the comparators COMP2a and COMP1a are at the high level at this time, the output does not change. At the same time, the R terminal of the latch 23 is set, the inverting output terminal Qb of the latch 23 is set to the high level, the P-type MOS-FET Q55 is turned off, and one input of the AND circuit AND1 is set to the high level. The output of the AND1 is changed to a high level to turn on the N-type MOS-FET Q50 via the OR circuit OR1, thereby discharging the charge of the first capacitor C1.

  Here, both the inverting input terminal voltage and the non-inverting input terminal voltage of the comparator COMP2a are at the low level, but as will be described later, the output of the comparator COMP2a changes from the high level to the low level. When the output of the comparator COMP2a becomes low level, the S terminal of the latch 23 is changed to low level, and at the same time, a low level signal is inputted to one input terminal of the AND circuit AND2 and the output of the AND circuit AND2 is changed to high level. To output. Then, the output of the AND circuit AND2 changes to a high level, whereby the MOS-FET Q51 is turned on and the second capacitor C2 is discharged.

  FIG. 8 is a circuit configuration diagram showing an example of a comparator in the high side circuit shown in FIG. In the comparators COMP1a and COMP2a shown in FIG. 8, a series circuit including a current source I80, a resistor R80, a P-type MOS-FET Q80, and an N-type MOS-FET Q83 is connected between the high-side power supply VB and the high-side ground VS. Has been. A series circuit composed of a current source I80, a resistor R81, a P-type MOS-FET Q81, and an N-type MOS-FET Q84 is connected between the high-side power supply VB and the high-side ground VS.

  The P-type MOS-FETs Q80 and 81 constitute a differential pair, and the gate terminals of the P-type MOS-FETs Q80 and Q81 are an inverting input terminal and a non-inverting input terminal, respectively. A current source I82 is connected between the connection point of the drain of the P-type MOS-FET Q81 and the drain of the N-type MOS-FET Q84 and the high side ground VS, and a series circuit of the N-type MOS-FET Q82 and the current source I81 is connected. Has been.

  A series circuit composed of a P-type MOS-FET Q87 and an N-type MOS-FET Q85 is connected between the high-side power supply VB and the high-side ground VS. A series circuit composed of a P-type MOS-FET Q88 and an N-type MOS-FET Q86 is connected between the high-side power supply VB and the high-side ground VS.

  N-type MOS-FETs Q84 and Q85 constitute a first current mirror circuit, N-type MOS-FETs Q83 and Q86 constitute a second current mirror circuit, and P-type MOS-FETs Q87 and Q88 constitute a third current mirror circuit. ing.

  An input terminal of the Schmitt inverter S-INV80 is connected to a connection point between the P-type MOS-FET Q88 and the N-type MOS-FET Q86, and the Schmitt inverter S-INV80 outputs an output signal OUT through the inverter INV80.

  According to the above configuration, when the voltage input to the inverting input terminals of the comparators COMP1a and COMP2a is the same as the voltage input to the non-inverting input terminal, the drains of the P-type MOS-FETs Q80 and Q81 are connected. The flowing current is the same. At this time, the current flowing in the drain of the P-type MOS-FET Q80 is output to the drain of the N-type MOS-FET Q86 via the second current mirror circuit.

  On the other hand, the current flowing in the drain of the P-type MOS-FET Q81 is subtracted by the current sources I81 and I82 and then output to the drain of the P-type MOS-FET Q88 via the first and third current mirror circuits.

  Since the drains of the N-type MOS-FET Q86 and the P-type MOS-FET Q88 are connected, a comparison between the current flowing in the N-type MOS-FET Q86 and the current flowing in the P-type MOS-FET Q88 shows that the N-type MOS-FET Q86 and P The drain terminal voltage of the type MOS-FET Q88 is determined.

  When there is no voltage difference between the inverting input terminal and the non-inverting input terminal, the current of the current sources I81 and I82 is subtracted from the current flowing through the drain of the P-type MOS-FET Q81, so that the N-type MOS- Since the current output to the FET Q86 is larger than the current output to the P-type MOS-FET Q88, the drain terminal voltage of the N-type MOS-FET Q86 is at a low level. This low level is inverted by the Schmitt inverter S-INV80, and further inverted by the inverter INV80 to output a low level.

  On the other hand, when the non-inverting input terminal voltage becomes larger than the inverting input terminal voltage, the current flowing through the P-type MOS-FET Q80 becomes smaller than the current flowing through the P-type MOS-FET Q81. When the difference between the current flowing through the P-type MOS-FET Q80 and the current flowing through the P-type MOS-FET Q81 becomes larger than the sum of the current of the current source I81 and the current of the current source I82, the current is output to the N-type MOS-FET Q86. The current is smaller than the current output to the P-type MOS-FET Q88. For this reason, the drain terminal voltage of the N-type MOS-FET Q86 is at a high level. This high level is inverted by the Schmitt inverter S-INV80 and further inverted by the inverter INV80 to output a high level.

  Note that the charging voltages of the first to third capacitors C1 to C3 are limited between the high-side power supply VB and the high-side ground VS by the diodes D50, D51, D52, D55, D56, and D57. When external noise or a sudden change in the high side ground VS occurs, the voltages at the other ends of the first to third capacitors C1 to C3 do not follow the change in the high side ground VS. For this reason, if the signal levels of the first capacitor C1 and the second capacitor C2 are detected with reference to the high-side ground VS, erroneous signal detection occurs.

  In the level shift circuit of the second embodiment, in order to prevent erroneous detection of a signal, a third capacitor C3 that does not transmit a signal is separately provided, and the voltage at the other end of the first capacitor C1 for signal transmission by the signal detection circuit 21b. And the voltage at the other end of the third capacitor C3 are detected. When the voltage difference is equal to or greater than a predetermined value, the set signal is received and the logic voltage state is set in the latch 23. The signal detection circuit 22b detects a voltage difference between the voltage at the other end of the second capacitor C2 for signal transmission and the voltage at the other end of the third capacitor C3. If the voltage difference is equal to or greater than a predetermined value, the reset signal , The logic voltage state is reset to the latch 23, and a signal is transmitted to the latch 23.

  That is, by detecting the voltage difference signal between the voltage of the first capacitor C1 and the voltage of the third capacitor C3, and the voltage difference signal between the voltage of the second capacitor C2 and the voltage of the third capacitor C3, the high side ground VS can be detected. Stable signal transmission can be realized without being affected by an applied noise component.

  FIG. 9 shows an operation waveform diagram of each part in the level shift circuit according to the second embodiment. The waveforms of the first and second capacitors C1 and C2 shown in FIG. 9 are the same as the waveforms of the first and second capacitors C1 and C2 shown in FIG. 4, and the waveform of the third capacitor C3 is added.

It is a circuit block diagram which shows the level shift circuit of Example 1 of this invention. It is a circuit block diagram which shows the low side circuit in the level shift circuit of Example 1 of this invention. It is a circuit block diagram which shows the high side circuit in the level shift circuit of Example 1 of this invention. It is an operation waveform diagram of each part in the level shift circuit of Example 1 of the present invention. It is a circuit block diagram which shows the level shift circuit of Example 2 of this invention. It is a circuit block diagram which shows the low side circuit in the level shift circuit of Example 2 of this invention. It is a circuit block diagram which shows the high side circuit in the level shift circuit of Example 2 of this invention. It is a circuit block diagram which shows an example of the comparator in the high side circuit shown in FIG. It is an operation | movement waveform diagram of each part in the level shift circuit of Example 2 of this invention. It is an operation | movement waveform diagram of each part in the conventional level shift circuit.

Explanation of symbols

1, 1a Low side circuit 2, 2a High side circuit 11, 12 Buffer 13 First clamp circuit 14 Second clamp circuit 15 Third clamp circuit 20, 21a, 21b, 22, 22b Signal detection circuit 23 Latch 24 Drive circuit Q1 Low side switch Q2 High-side switch C1 First capacitor C2 Second capacitor C3 Third capacitors I10 to I13, I20 to I23, I30 to I33, I50 to I52, I80 to I82 Current sources Q10 to Q13, Q20 to Q23, Q30 to Q33 Transistor D50 D52, D55 to D57 Diodes COMP1, COMP1a, COMP2, COMP2a Comparators Q50, Q51, Q55, Q80 to Q88 MOS-FET
AND1, AND2 AND circuit OR1 OR circuit S-INV80 Schmitt inverter INV80 Inverter

Claims (6)

A level shift circuit for converting a first voltage level to a second voltage level different from the first voltage level,
A set level circuit for transmitting a set signal for setting a logic voltage state of the second voltage level through a first capacitor;
A reset level circuit for transmitting a reset signal for resetting a logic voltage state of the second voltage level through a second capacitor;
When the logic level of the second voltage level is reset by the reset level circuit, the voltage at one end of the first capacitor is discharged or charged, and after this discharge or charging is completed, the voltage at one end of the second capacitor is A charge / discharge circuit for discharging or charging
A level shift circuit comprising:   2. The level shift circuit according to claim 1, wherein one end of each capacitor is clamped or opened according to a logic voltage state of the second voltage level. A level shift circuit for converting a first voltage level to a second voltage level different from the first voltage level,
A set level circuit for transmitting a set signal for setting a logic voltage state of the second voltage level through a first capacitor;
A reset level circuit for transmitting a reset signal for resetting a logic voltage state of the second voltage level through a second capacitor;
A reference level circuit for setting a reference value for detecting the set signal and the reset signal at the second voltage level via a third capacitor;
When the logic level of the second voltage level is reset by the reset level circuit, the voltage at one end of the first capacitor is discharged or charged, and after this discharge or charging is completed, the voltage at one end of the second capacitor is A charge / discharge circuit for discharging or charging
A level shift circuit comprising:   The charge / discharge circuit resets the reference level circuit at the same time as charging or discharging the voltage at one end of the first capacitor when the logic voltage state of the second voltage level is reset by the reset level circuit. 4. The level shift circuit according to claim 3, wherein the voltage at one end of the second capacitor is discharged or charged after discharging or charging is completed.   The set level circuit detects a potential difference between the set signal and a reference value signal set by the reference level circuit, sets a logical voltage state when the potential difference is equal to or greater than a predetermined value, and the reset level circuit 4. The level shift circuit according to claim 3, wherein a potential difference between the reset signal and the reference value signal is detected, and a logic voltage state is reset when the potential difference is equal to or greater than the predetermined value.   6. The level shift circuit according to claim 3, wherein one end of each capacitor is clamped or opened according to a logic voltage state of the second voltage level.

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