JP2010122549A - Plasma display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the following problem: in a large screen plasma display, since wiring distances of a drive waveform transmitted from a sustain circuit to scan ICs differ from one another, brightness differences occur in the adjacent part of scan ICs. <P>SOLUTION: In the plasma display device, at least more than one output wire is replaced in adjacent scan ICs. In this condition, output wire is taken out one by one. Accordingly, four or more cells of output wires different in luminance difference on the connection block boundary of an FPC4 are used, so that they are alternately connected to a scanning electrode, like bright (a1), dark (b1), bright (a1), dark (b1), and step differences in brightness are dispersed. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a plasma display device used for a thin display device or the like.

  Generally, a plasma display device (hereinafter referred to as a PDP device) can be roughly divided into two main parts: a drive unit and a display unit. In the glass panel of the display unit, a large number of discharge cells are formed between a front plate and a back plate arranged to face each other. The front plate is formed by forming a plurality of pairs of display electrodes consisting of a pair of scan electrodes (Y) and sustain electrodes (X) on the front glass substrate in parallel with each other, and covering the display electrode pairs with a dielectric layer and a protective layer. A layer is formed. The back plate is formed with a plurality of parallel address electrodes on the back glass substrate and a dielectric layer so as to cover them, and a plurality of barrier ribs formed in parallel with the address electrodes on the back surface glass substrate. A phosphor layer is formed on the side surface of the partition wall. The front plate and the back plate are arranged opposite to each other so that the display electrode pair and the address electrode are three-dimensionally crossed and sealed, and the internal discharge space has one of Xe, Ne, He, Ar or a mixture thereof. Noble gas is enclosed. Here, a discharge cell is formed in a portion where the display electrode pair and the address electrode face each other. The panel is divided into an image display area for displaying an image and a non-display area other than that, and each electrode is formed by pulling each electrode out of the image display area on the front plate or the back plate, that is, to the non-display region. The PDP device is driven by providing an extraction unit and applying a drive voltage to the extraction unit.

A plurality of scan ICs are mounted on the Y-side relay board (hereinafter referred to as SDR board), and data is sent to each scan IC from the control circuit, and a scan pulse is generated by each IC. The output terminal of each scan IC is electrically connected to the scan electrode of the panel by a flexible wiring board (hereinafter referred to as FPC), and a scan pulse is applied to the scan electrode of the panel. In addition, in a Y (scanning) drive circuit (hereinafter referred to as a YSUS substrate), a drive waveform for initialization and sustain discharge is generated and applied to a scan electrode of the panel via a scan IC and FPC. (See Patent Document 1)
JP 2003-195777 A

  In such a PDP device, a difference in current path length from the YSUS substrate to the scan IC connected to each scan electrode causes a difference in luminance between adjacent scan ICs. For example, since the current path length from the YSUS substrate to the scan IC for generating the scan pulse is different for each scan IC, the voltage of the drive waveform of the sustain discharge applied to the scan electrode due to the difference in electrical resistance value Different. For this reason, there is a problem in that a luminance difference occurs in an adjacent portion in units of scan ICs, and the luminance unevenness appears. The present invention has been made in view of such problems, and aims to alleviate luminance unevenness.

  In order to achieve the above object, in the plasma display device of the present invention, at least one output wiring to the panel electrode of the scan IC is replaced in the adjacent scan IC.

  By replacing the output wiring of the scan ICs with each other, the brightness difference is dispersed and less noticeable, and by replacing drive waveforms with different voltage values, adjacent drive waveforms interfere with each other and the voltage difference is reduced. The difference itself can be reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  The structure of the panel body of the present invention will be described with reference to FIG. As shown in FIG. 2, on a transparent front substrate 8 such as a glass substrate, a plurality of stripe-shaped display electrodes that form pairs of scan electrodes 6 and sustain electrodes 7 are formed. Further, a first dielectric layer 9 is formed so as to cover the electrode group, and a protective film 10 such as MgO is formed on the first dielectric layer 9. The protective film 10 has a role of protecting the first dielectric layer 9, and further has a function of emitting many secondary electrons by ion bombardment of discharge.

  In addition, a plurality of layers covered with the second dielectric layer 12 are formed on the rear substrate 11 facing the front substrate 8 so as to intersect the display electrodes of the scan electrodes 6 and the sustain electrodes 7. A stripe-shaped address electrode 15 is formed. On the second dielectric layer 12 between the address electrodes (A) 15, a plurality of partition walls 13 are arranged in parallel with the address electrodes (A) 15, and the side surfaces between the partition walls 13 and the second dielectric layer A phosphor layer 14 is provided on the surface of 12.

  These substrates 8 and 11 are arranged opposite to each other with a minute discharge space so that the display electrodes of the scan electrodes 6 and the sustain electrodes 7 and the address electrodes 15 are almost orthogonal, and the periphery is sealed. The In the discharge space, one or a mixed gas of helium, neon, argon, and xenon is sealed as a discharge gas. Further, the discharge space is divided into a plurality of sections by the partition walls 13, so that a plurality of discharge cells located at the intersections of the display electrodes of the scan electrodes 6 and the sustain electrodes 7 and the address electrodes 15 are provided. The phosphor layers 14 are sequentially arranged one by one so as to emit red, green and blue light.

  FIG. 3 shows an electrode arrangement of the PDP main body. As shown in FIG. 3, the AC panel 5 includes scan electrodes 6, sustain electrodes 7, and address electrodes 15, and is configured in a matrix of M rows × N columns. M rows of scan electrodes 6 SCN1 to SCNM and sustain electrodes 7 SUS1 to SUSM are arranged in the column direction, and N columns of address electrodes 15A1 to AN are arranged in the row direction.

  In the PDP body having such an electrode configuration, by applying a voltage pulse for performing the address discharge 15 between the address electrode 15 and the scan electrode 6, the address discharge is performed between the address electrode 15 and the scan electrode 6, and the discharge is performed. Select a cell. Thereafter, by applying a periodic sustain pulse that is alternately inverted between the scan electrode 6 and the sustain electrode 7, a sustain discharge is performed between the scan electrode 6 and the sustain electrode 7, and a predetermined display is performed. Is.

  Next, the overall configuration of the PDP device (PDP module) 22 according to the present embodiment will be described with reference to FIG. The present PDP device 22 is mainly configured to include an AC type panel 5 and a circuit unit for driving and controlling the same. In the PDP module 22, a panel 5 is attached to one surface of a chassis portion (not shown) and held, and a circuit portion is held on the other surface. Further, the panel 5 and the circuit unit are electrically connected.

  The sustain electrode 7 of the panel 5 is connected to the XSUS substrate 16 via the FPC 17, and the address electrode 15 is connected to the address substrate 19 via the FPC 18. The scan electrode 6 is connected to the YSUS substrate 23 via the FPC 4 and the SDR substrate 1, and a corresponding drive waveform is applied.

  Each drive circuit (1, 16, 23) is connected to the control circuit 20 and controlled by a control signal. The control circuit 20 controls the entire PDP device 22, and generates a drive waveform on the XSUS substrate 16, the YSUS substrate 23, and the SDR substrate 1 based on input display data (video signal). Drive 5

Next, the relationship between the YSUS substrate 23 and the SDR substrate 1 will be described with reference to FIG.
A plurality of scan ICs 2 for generating a scan pulse waveform are mounted on the SDR substrate 1, and the scan IC 2 performs scanning by switching operation so that negative scan pulses are sequentially applied to all the scan electrodes 5. .

  The drive waveform other than the scan pulse is a pattern wiring that is connected sequentially from top to bottom with the scan IC 2 (A), (B, (C) via the connector (or FFC) 24 from the YSUS board 23. The scan pulse waveform generated by the scan IC 2 is taken out one by one as the output of the scan IC 2, and connected to the scan electrode 6 one by one via the connector 3 and the FFC 4. Generally, the FFC 4 and the scan electrode 6 are They are connected by thermocompression bonding, and one scan IC output wiring is assigned to each scan electrode, so that the drive waveform generated on the YSUS substrate 23 is also passed through each scan IC. This is applied to the scan electrode 6 via the FFC 4. Next, the main part of the present embodiment is shown in Fig. 1. Fig. 1 is a wiring diagram of the SDR substrate 1.

  As shown in FIG. 1, a plurality of scan ICs 2 for generating a scan pulse waveform are mounted on the SDR substrate 1. From the YSUS substrate 23 to the scan ICs 2 (A), (B), (C) and above. The pattern wiring is sequentially connected downward. Also, focusing on the scan ICs (A) and (B) among the scan ICs adjacent to each other, the last output wiring of the scan IC (A) and the first output wiring of the scan IC (B) On the substrate, at least one or more output wirings are replaced using the surface layer surface and the interior surface. In this state, one by one is taken out and connected to the scan electrode 6. However, in FIG. 1, the display line to which the output wiring of the scan IC (A) is connected is a1, the display line to which the output wiring of the scan IC (B) is connected is b1, and so on.

  In the conventional method, the drive waveform from the YSUS substrate 23 to the scan IC 2 mounted on the SDR substrate 1 in a plurality of patterns is connected to the scan IC 2 (A), (B), (C) sequentially from top to bottom. It was. Further, the output wiring of the scan IC 2 (A) was straight as it was and connected to the scan electrode via the connector 3 and the FPC 4. Therefore, since the wiring distance of the drive waveform sent from the YSUS substrate 23 differs for each scan IC, the longer the wiring distance, the larger the voltage drop due to the wiring resistance. Therefore, the output wiring of the scan IC (A) with the shortest wiring distance of the scan IC is the least affected by the voltage drop, so the corresponding display line is the brightest, and the scan IC (B) with the next shortest wiring distance scans. Since the voltage drop is larger than that of IC (A), the corresponding display line is lit darker than the display line corresponding to the output of scan IC (A).

  Therefore, when the display line corresponding to the output of the scan IC (A) is compared with the display line corresponding to the output of the scan IC (B), a difference in luminance of the display line occurs. Similarly, when the scan ICs (B) and (C) were compared, a difference in brightness of the display line was observed.

  For this reason, in the present invention, in the scan ICs adjacent to each other, focusing on the scan ICs (A) and (B), if there are a total of n output wirings of the scan IC (A), the nth output wiring is replaced. Target. Next, the first output wiring b1 of the output wiring of the scan IC (B) is to be replaced, and the nth scanning IC (A) and the first scanning IC (B) are the surface layers of the SDR board 1, respectively. Then, the inner layer surface is used to make a replacement, and then the scan electrode 6 is connected. As a result, 4 lines or more of output wirings having different luminances at the connection block boundary of the FPC4 can be used to be dispersed with light (a1) dark (b1) light (a1) dark (b1). Hereinafter, the scan ICs (B) and (C), (C) and (D), and (D) and (E) are interchanged in the same manner.

  Further, by replacing the output wirings of the scan ICs adjacent to each other on the SDR, the bright output and the dark output are wired close to each other in the FPC 4. Therefore, because different voltage drops are wired at close distances, they affect each other and shift to an intermediate potential between the voltage values, thereby reducing the luminance difference itself. .

  As shown in FIG. 6, a plurality of scan ICs 2 for generating scan pulses are mounted on the SDR substrate 1, and the drive waveforms from the YSUS substrate 23 to the scan ICs 2 (A), (B), (C) The pattern wiring is sequentially connected from top to bottom.

  Also, when paying attention to the adjacent scan ICs (A) and (B), the second output wiring from the end of the output wiring of the scan IC (A) and the output wiring of the scan IC (B), The second output wirings counted from the beginning are switched using the surface layer surface and the inner layer surface of the SDR substrate 1 and then connected to the scan electrode 6. However, in FIG. 6, the display line to which the output wiring of the scan IC (A) is connected is a1, the display line to which the output wiring of the scan IC (B) is connected is b1, and so on.

  As with the conventional method, the pattern wiring is connected from the YSUS substrate 23 to the scan ICs (A), (B), and (C) in order from top to bottom, so that bright display lines and dark display lines are displayed. It appears as a brightness step. Therefore, in this embodiment, the output step of the adjacent scan IC 2 is replaced as follows to make it difficult to see the luminance step.

  Focusing on the adjacent scan ICs (A) and (B) as shown in FIG. 6, if there are a total of n output wires of the scan IC (A), the second (n-1 The output wiring corresponding to) is to be replaced. Next, the output wiring corresponding to the second b2 counted from the beginning of the output wiring of the scan IC (B) is to be replaced, and the (n-1) th line and the second (b2) line are respectively displayed on the surface of the SDR board 1. After the layer surface and the inner layer surface are used for replacement, the scan electrode 6 is connected.

  By switching the wiring in this way, display lines with different brightness differences at the connection block boundary of FPC4 can be displayed in a wider range of light (a1) dark (b1) light (a1) dark (b1) light (a1) dark (b1). Can be dispersed. Hereinafter, the scan ICs (B) and (C), (C) and (D), and (D) and (E) are interchanged in the same manner.

  Further, by replacing the output wirings of the scan ICs adjacent to each other on the SDR, the bright output and the dark output are wired close to each other in the FPC 4. Therefore, because different voltage drops are wired at close distances, they affect each other and shift to an intermediate potential between the voltage values, thereby reducing the luminance difference itself. .

  Next, the main part of this embodiment is shown in FIG. FIG. 7 is a wiring diagram of the SDR substrate 1. As shown in FIG. 7, a plurality of scan ICs 2 for generating a scan pulse waveform are mounted on the SDR substrate 1, and the drive waveforms from the YSUS substrate 23 to the scan ICs 2 (A), (B), (C) The pattern wiring is connected sequentially from top to bottom. In addition, the FPC26 that connects the scan IC output wiring and the scan electrode can pass through the output wiring of two scan ICs, and between the adjacent scan IC2 corresponding to the break of the connection block of the FPC26 The configuration is such that the output wirings can be interchanged. However, in FIG. 7, the display line to which the output wiring of the scan IC (A) is connected is a1, the display line to which the output wiring of the scan IC (B) is connected is b1, and so on.

  As with the conventional method, the pattern wiring is connected from the YSUS substrate 23 to the scan ICs (A), (B), and (C) in order from top to bottom, so that bright display lines and dark display lines are displayed. It appears as a brightness step. Therefore, in this embodiment, the output step of the scan IC 2 corresponding to the break of the FPC 26 is replaced as follows to make the luminance step difficult to see.

  First, attention is paid between the scan ICs (B) and (C) corresponding to the breaks of the FPC 26 as shown in FIG. If there are n output wires of the scan IC (B), the nth output wire is to be replaced. Next, the first output wiring c1 among the output wirings of the scan IC (C) is to be replaced, and the n-th scanning IC (B) and the first scanning IC (C) are the surface layers of the SDR substrate 1, respectively. Then, the inner layer surface is used to make a replacement, and then the scan electrode 6 is connected. As a result, the output wirings having different luminance differences at the connection block boundaries of the FPC 26 can be dispersed in light (b1) dark (c1) light (b1) dark (c1).

  In addition, it is possible to receive a voltage drop in FPC26 without changing the output wiring between adjacent scan ICs (A) and (B), between (C) and (D), and between (E) and (F). Since different objects are wired at close distances, it is difficult for the brightness difference to occur at the point where the FPC26 is connected, and it is possible to improve the brightness difference without replacing each other's output wiring. It is not necessary to replace it.

  The present invention relates to a plasma display device, and as described above, it is industrially useful because an effect of improving image quality can be obtained.

The wiring pattern in Example 1 is shown Shows the structure of the panel body of the PDP device Shows the electrode layout of the panel of the PDP device 1 shows an overall configuration of a PDP apparatus according to an embodiment of the present invention. A circuit configuration diagram for applying to the sustain electrode of the PDP device is shown. The wiring pattern in Example 2 is shown. The wiring pattern in Example 3 is shown.

Explanation of symbols

1… SDR board
2… Scan IC
3… Connector for scan electrode connection
4 ... Flexible wiring board (FPC) for connecting scan electrodes
5… AC type PDP
6 ... Scanning electrode
7… sustain electrode
8… Front substrate
9… first dielectric layer
10 ... Protective layer
11 ... Back substrate
12 ... Second dielectric layer
13 ... Bulkhead
14 ... phosphor
15… Address electrode
16 ... Maintenance circuit (XSUS circuit)
17… Flexible wiring board (FPC) for connecting sustain electrodes
18… Flexible wiring board (FPC) for address electrode connection
19 ... Address circuit
20 ... Control circuit
21 ... Power circuit
22 ... PDP device (PDP module)
23 ... Scanning circuit (YSUS circuit)
24… Connector for connecting YSUS circuit and SDR circuit
25… Two flexible connectors
26… 2 sheets flexible wiring board

Claims (6)

A plasma display panel that repeatedly discharges between scan electrodes and sustain electrodes;
A plurality of scan ICs connected to the scan electrodes;
A drive circuit connected to the scan IC and generating a drive waveform to be applied to the scan electrode;
A plasma display device comprising:
A plasma display device, wherein the outputs of the scan ICs are switched between different scan ICs connected to the adjacent scan electrodes and connected to the scan electrodes.   A flexible wiring board for connecting the output wirings of a plurality of scan ICs to the scanning electrodes, and connecting the scanning ICs to the scanning electrodes by switching the output wirings of the scanning ICs connected to the adjacent scanning electrodes and different flexible wiring boards. The plasma display device according to claim 1, wherein A substrate on which the scan IC is mounted;
The plasma display apparatus according to claim 2, wherein the output wiring of the scan IC is switched by passing through a surface layer surface and an inner layer surface of the substrate. A plasma display panel that repeatedly discharges between scan electrodes and sustain electrodes;
A plurality of scan ICs connected to the scan electrodes;
A drive circuit connected to the scan IC and generating a drive waveform to be applied to the scan electrode;
A plasma display device comprising:
Corresponding to the first scan IC, a first scan electrode group composed of a plurality of the scan electrodes is arranged on the plasma display panel, and the second scan IC is arranged below the first scan IC. Correspondingly, in the structure in which the second scan electrode group composed of a plurality of the scan electrodes is disposed below the first scan electrode group, a part of the output of the first scan IC is the first scan IC. 2. A plasma display device, wherein the plasma display device is connected to two scan electrode groups, and a part of the output of the second scan IC is connected to the first scan electrode group.   The plasma display apparatus according to claim 4, wherein a part of the output of the first scan IC is an output of a part closest to the second scan IC.   5. The plasma display device according to claim 4, wherein a part of the output of the first scan IC is an output of a part second closest to the second scan IC. 6.

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