JP2010122097A - Semiconductor integrated circuit device and probe card - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device capable of reducing an influence of a capacitance generated in a coaxial wire on the semiconductor integrated circuit device side outputting an analog signal, when using the coaxial wire as a connection signal wire. <P>SOLUTION: The semiconductor integrated circuit chip 1 includes a buffer amplifier 3 for outputting to a second output terminal 4, a signal acquired by buffering in the same phase, an output signal (analog signal) V<SB>O</SB>transmitted to a first output terminal 2. As for a core of the coaxial wire 5, one end is connected to another chip/measuring device 6, and the other end is connected to the first output terminal 2. As for a shield wire of the coaxial wire 5, one end on the chip/measuring device 6 side is in the open state, and the other end is connected to the second output terminal 4. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device and a probe card.

  When an analog signal generated by a signal generation circuit in a semiconductor integrated circuit chip is measured by another chip or measuring instrument, the parasitic capacitance corresponding to the wiring length generated in the connection signal line hinders accurate signal transmission. It becomes a factor.

  As a measure for reducing the influence of the parasitic capacitance generated in the connection signal line and enabling accurate signal transmission, for example, a semiconductor parameter analyzer is configured as follows using a method disclosed in Non-Patent Document 1. Yes.

  That is, in the semiconductor parameter analyzer, the signal voltage input from the coaxial cable core line is buffered in the same phase at the connection end of the coaxial cable connecting the measurement target in the chip to the shielded line. A configuration is adopted in which the potential of the shielded wire on the semiconductor parameter analyzer side is maintained at the same potential as that of the core wire by providing a buffer amplifier with an applied voltage gain = 1. According to this configuration, since the potential difference between the core wire and the shield wire becomes 0 V, accurate measurement can be performed without being affected by the capacitance between the core wire and the shield wire.

  However, in this configuration, the input capacity of the buffer amplifier is added to the core wire. In addition, since a protection element against electrostatic breakdown is required at the input portion of the buffer amplifier, the capacitance value added to the core wire increases, and the load capacitance on the signal generation circuit side in the semiconductor integrated circuit chip increases. There is.

“Design of OP amplifier circuit by Sadamoto” written by Ikuo Okamura, pages 199-200 (Fig. 7-10), CQ Publishing Co., Ltd., issued July 1, 2006 (22nd edition)

  The present invention has been made in view of the above, and when a coaxial line is used as a connection signal line, it is possible to reduce the influence of capacitance generated on the coaxial line on the semiconductor integrated circuit device side that outputs an analog signal. An object of the present invention is to provide a semiconductor integrated circuit device.

  Another object of the present invention is to provide a probe card suitable for measurement of the semiconductor integrated circuit device according to the above invention.

  According to one aspect of the present invention, in order to achieve the above-described object, a semiconductor integrated circuit device according to the present invention includes a first output terminal to which one end of a core wire of a coaxial line is connected, and a shield wire of the coaxial line. And a buffer amplifier that outputs a signal obtained by buffering an analog signal transmitted to the first output terminal in the same phase to the second output terminal. To do.

  According to the present invention, when a coaxial line is used as the connection signal line, an effect of reducing the influence of the electrostatic capacitance generated in the coaxial line on the semiconductor integrated circuit device side that outputs an analog signal can be achieved.

  Exemplary embodiments of a semiconductor integrated circuit device and a probe card according to the present invention will be explained below in detail with reference to the accompanying drawings.

(First embodiment)
FIG. 1 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to a first embodiment of the present invention. In FIG. 1, a semiconductor integrated circuit chip 1 sends an analog signal (hereinafter referred to as “output signal”) Vo generated by an internal signal generation circuit to a path for sending it to a first output terminal 2. A buffer amplifier 3 for buffering and outputting in phase is provided. The output terminal of the buffer amplifier 3 is connected to the second output terminal 4.

  The other chip in the other chip / measuring instrument 6 is not on the substrate on which the semiconductor integrated circuit chip 1 is mounted, and is not mounted on another substrate in a package that accommodates the substrate. Mounted on another board at a distant place, or mounted on the same board or in the same package, but the distance from the chip 1 is, for example, several cm or more, and the parasitic capacitance of the wiring between the chips Is at a distance that affects function. Further, the measuring instrument in the other chip / measuring instrument 6 is a semiconductor parameter analyzer or the like, which is also located at a place on the order of meters from the substrate on which the semiconductor integrated circuit chip 1 is mounted.

  In the first embodiment, in such a situation, the semiconductor integrated circuit chip 1 is connected to another chip / measuring instrument 6 through the coaxial line 5. In this case, in the connection between the semiconductor integrated circuit chip 1 and the coaxial line 5, the core wire of the coaxial line 5 is connected to the first output terminal 2, and the shield line of the coaxial line 5 is connected to the second output terminal 4. . The shield wire of the coaxial wire 5 on the other chip or the measuring instrument 6 side is in an open state.

  In this way, a signal obtained by buffering the output signal Vo in phase with the buffer amplifier 3 is applied to the shield line of the coaxial line 5, so that the potential difference between the core line of the coaxial line 5 and the shield line is If the voltage gain of the amplifier 3 is 1, it is kept at 0V. Therefore, the capacitance between the core wire and the shield wire does not affect the output signal Vo propagating through the core wire. That is, the other chip / measuring instrument 6 can accurately capture the output signal Vo of the semiconductor integrated circuit chip 1 from the core wire of the coaxial line 5.

  The probe of the probe card used in a measuring instrument such as a semiconductor parameter analyzer is brought into contact with the first output terminal 2 and the second output terminal 4, so that the first output terminal 2 and the second output terminal 2 are in contact with each other. The output terminals 4 are desirably arranged adjacent to each other.

  As described above, according to the first embodiment, a buffer amplifier that buffers an analog signal output to the outside in the same phase is provided in the semiconductor integrated circuit chip, and an internal signal generation circuit is generated outside. The analog signal and the buffered signal in the same phase can be output, reducing the influence of the capacitance generated on the coaxial line when using a coaxial line for connection to an external measuring instrument or chip. It is possible to transmit an accurate signal to an external measuring instrument or chip.

  In this case, the signal generation circuit in the semiconductor integrated circuit chip does not need to be designed to increase the driving capability in consideration of the influence of the capacitance of the coaxial line or to secure a large margin. An increase can be avoided.

  Further, since the buffer amplifier is disposed in the same chip as the signal generation circuit, it is not necessary to insert a protection element against electrostatic breakdown on the input terminal side of the buffer amplifier. In addition, the signal generation circuit and the input terminal of the buffer amplifier 3 can be connected by a short wiring, and the parasitic capacitance of this wiring portion can be reduced.

(Second Embodiment)
FIG. 2 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to the second embodiment of the present invention.

  In the second embodiment, the other chip as the connection partner is arranged on the same substrate on which the semiconductor integrated circuit chip 1 is mounted, or is contained in the same package. In this case, it is not necessary to use a coaxial line for connection between the other chip as the connection partner and the semiconductor integrated circuit chip 1. On the other hand, when the connection partner is a measuring instrument, it is necessary to use a coaxial line.

  Therefore, FIG. 2 shows a case where the measuring instrument 8 is connected to the semiconductor integrated circuit chip 1 via the coaxial line 5. That is, as shown in FIG. 2, a switch 7 that opens and closes by the test mode signal TM is provided in the input path of the output signal Vo to the buffer amplifier 3.

  When the measuring instrument 8 is connected to the semiconductor integrated circuit chip 1 at the time of the test, the switch 7 is closed and the output from the second output terminal 4 to the shielded wire of the coaxial line 5 as described with reference to FIG. A signal obtained by buffering the signal Vo with the buffer amplifier 3 in phase is applied.

  In this case, the current flowing into the input capacitance of the buffer amplifier 3 can be limited by increasing the resistance value in the closed state of the switch 7 within a range where the output signal Vo and the buffered signal can be kept at the same potential. Therefore, the influence of the input capacitance of the buffer amplifier 3 on the output signal Vo directed to the first output terminal 2 can be reduced. This measure is effective when the input capacity of the buffer amplifier 3 is large and the output signal Vo is relatively low speed.

  At times other than the test, the switch 7 is opened, and the output signal Vo is sent from the first output terminal 2 to another chip via a connection line (not shown). Since the buffer amplifier 3 is excluded, it is possible to prevent the input capacitance of the buffer amplifier 3 from affecting the output signal Vo directed to the first output terminal 2.

  As described above, according to the second embodiment, since a buffer amplifier is used during a test, accurate measurement by a measuring instrument that requires long-distance wiring can be appropriately performed. In addition, since the buffer amplifier is excluded except during the test, accurate signal transmission with other chips arranged close to each other can be performed.

(Third embodiment)
FIGS. 3 and 4 are circuit diagrams showing specific configuration examples of the semiconductor integrated circuit device shown in FIGS. 1 and 2 as a third embodiment of the present invention.

  In FIG. 3, the output signal Vo is input to the non-inverting input terminal (+) of the operational amplifier 10. The output terminal of the operational amplifier 10 is connected directly to the inverting input terminal (−) and to the second output terminal 4. The operational amplifier 10 connected in this way constitutes a voltage follower having a voltage gain of 1, and since the output has the same amplitude as the input, it can be used as the buffer amplifier 3 shown in FIG.

  As in FIG. 2, when it is necessary to transmit a buffered signal only at the time of testing through a long distance wiring, as shown in FIG. 4, a switch is made to the input path of the output signal Vo to the voltage follower (operational amplifier 10). 7 can be inserted.

  However, in the configuration shown in FIG. 4, since the non-inverting input terminal (+) of the operational amplifier 10 is in a floating state except during the test, the operation is not stopped and an unnecessary signal is sent to the output terminal. An undesirable thing happens. Therefore, except during the test, the non-inverting input terminal (+) of the operational amplifier 10 is clamped to a fixed potential (for example, a power supply potential or a ground potential), or measures such as disabling the operational amplifier 10 are taken. It is better to stop the operation.

  FIG. 5 is a diagram illustrating a circuit example in which the voltage follower illustrated in FIG. 4 is completely stopped when there is no input. As a method of disabling the operational amplifier 10, there are methods shown in FIGS. 5 (a), 5 (b), and 5 (c). In FIG. 5A, power switches 11 and 12 that are opened / closed by a test mode signal TM are provided between the operational amplifier 10 and the upper power supply VCC and lower power supply VEE. Disconnect from the side power supply VCC and the lower power supply VEE. In FIG. 5B, a power switch 12 that is opened and closed by a test mode signal TM is provided between the operational amplifier 10 and the lower power supply VEE, and the operational amplifier 10 is disconnected from the lower power supply VEE except during a test. In FIG. 5C, a power switch 11 that is opened and closed by a test mode signal TM is provided between the operational amplifier 10 and the upper power supply VCC, and the operational amplifier 10 is disconnected from the upper power supply VCC except during a test.

(Fourth embodiment)
FIGS. 6 and 7 are circuit diagrams showing other specific configuration examples of the semiconductor integrated circuit device shown in FIGS. 1 and 2 as the fourth embodiment of the present invention.

  In FIG. 6, the drain terminal of the N-type transistor MN1 is connected to the power supply, and the source terminal is connected to the circuit ground via the resistance element RL. The output signal Vo is input to the gate terminal of the N-type transistor MN1. A connection terminal between the source terminal of the N-type transistor MN1 and the resistance element RL is connected to the second output terminal 4 as an output terminal.

  The N-type transistor MN1 and the resistance element RL that are connected in this way constitute a source follower. Although the source follower outputs a signal whose input is buffered in phase with a voltage gain smaller than 1, it can be used as the buffer amplifier 3 shown in FIG. 1 for the following reason.

  That is, in the source follower, since the output does not have the same amplitude as the input, the capacitance between the core line of the coaxial line 5 and the shield line cannot be completely eliminated. However, for example, if the voltage gain of the source follower is 0.5, the electrostatic capacitance between the core wire and the shield line is ½ that when the potential of the shield line is fixed to a certain potential. Therefore, compared with a case where the potential of the shield line is fixed to a certain potential, the influence of the capacitance can be reduced.

  When a source follower is used as the buffer amplifier 3 shown in FIG. 1, the circuit can be simplified as compared with the voltage follower using the operational amplifier 10, so that the circuit area as the buffer amplifier 3 can be reduced.

  As in FIG. 2, when it is necessary to transmit a buffered signal only at the time of testing through a long distance wiring, N-type transistors MN2 and MN3 are added as shown in FIG. The N-type transistor MN2 is inserted in a path through which the output signal Vo is input to the gate terminal of the N-type transistor MN1. The N-type transistor MN3 is inserted between the resistance element RL and the circuit ground. The on / off operation is performed in synchronization with each other in accordance with the test mode signal TM input to the gate terminal.

  The N-type transistor MN2 corresponds to the switch 7 shown in FIG. The N-type transistor MN2 is turned on during the test to introduce the output signal Vo into the gate terminal of the N-type transistor MN1 to operate the source follower, and is turned off to exclude the source follower except during the test. To do. The resistance value during the ON operation of the N-type transistor MN2 during the test is made sufficiently large so that the input capacitance of the source follower does not affect the output signal Vo.

  The N-type transistor MN3 corresponds to the power switch 12 shown in FIG. This allows the source follower to be disconnected from the power source and disabled at times other than during testing.

(Fifth embodiment)
FIG. 8 is a conceptual diagram showing the main configuration of a probe card according to the fifth embodiment of the present invention. When testing the semiconductor integrated circuit chip 1 shown in the first to fourth embodiments in a wafer state, for example, a probe card 15a as shown in FIG. 8 may be used.

  In FIG. 8, the probe card 15a is provided with a coaxial line 16 and two probes 17a and 17b connected thereto for each measurement terminal. The measurement terminals are the first and second output terminals 2 and 4 that are pads formed on the semiconductor integrated circuit chip 1 shown in FIG.

  One end of the core wire of the coaxial line 16 is connected to the measuring instrument 8, and the other end is connected to one end of the probe 17a. One end of the coaxial line 16 on the measuring instrument 8 side is in an open state, and the other end is connected to one end of the probe 17b.

  In the test, the other end of the probe 17a is brought into contact with the first output terminal 2 shown in FIG. 1 and the like, and the other end of the probe 17b is brought into contact with the second output terminal 4 shown in FIG. To be implemented. In this measurement, since the influence of the parasitic capacitance at the probes 17a and 17b cannot be excluded, it is preferable to shorten the lengths of the probes 17a and 17b as much as possible. In this sense, it is preferable that the first and second output terminals 2 and 4 used in the semiconductor integrated circuit chip 1 are also arranged close to each other.

  As described above, by using the probe card according to the fifth embodiment, accurate measurement can be performed without being affected by the capacitance between the coaxial core wire and the shield wire.

(Sixth embodiment)
FIG. 9 is a conceptual diagram showing the main configuration of a probe card according to the sixth embodiment of the present invention. As shown in FIG. 8, when the shield line is driven by a signal buffered in the semiconductor integrated circuit chip 1, the semiconductor integrated circuit chip 1 is affected by external noise on the coaxial line 16.

  Therefore, in the probe card 15b according to the sixth embodiment, as shown in FIG. 9, instead of the coaxial line 16 shown in FIG. 8, a double coaxial line in which a shield line is further provided on the outer periphery of the shield line. 18 and three probes 17a, 17c, and 17c are used.

  One end of the core wire of the double coaxial line 18 is connected to the measuring instrument 8, and the other end is connected to one end of the probe 17a. The shielded wire inside the double coaxial line 18 has one end on the measuring instrument 8 side in an open state and the other end connected to one end of the probe 17b. The shield wire outside the double coaxial line 18 has one end on the measuring instrument 8 side in an open state and the other end connected to one end of the probe 17c.

  In the test, the other end of the probe 17a is brought into contact with the first output terminal 2 shown in FIG. 1 and the like, and the other end of the probe 17b is brought into contact with the second output terminal 4 shown in FIG. Although implemented, the other end of the probe 17c is brought into contact with a terminal (pad) connected to a fixed potential (for example, ground potential) on the semiconductor integrated circuit chip 1.

  As described above, by using the probe card according to the sixth embodiment, the test can be performed while avoiding the influence of the external noise on the semiconductor integrated circuit chip.

(Seventh embodiment)
FIG. 10 is a conceptual diagram showing a main configuration of a probe card according to the seventh embodiment of the present invention. In the seventh embodiment, another example of the problem solving method in FIG. 9 (sixth embodiment) is shown.

  As shown in FIG. 10, in the probe card 15c according to the seventh embodiment, the double coaxial line 18 is used as in FIG. 9 (sixth embodiment), but the probe 17c is deleted. Similarly to FIG. 8 (fifth embodiment), two probes 17a and 17b are used.

  The shielded wire outside the double coaxial line 18 used in the probe card 15c according to the seventh embodiment has one end on the measuring instrument 8 side connected to a fixed potential such as a ground potential in the measuring instrument 8, and a semiconductor integrated circuit The other end on the chip 1 side is in an open state. The connection relationship between the core wire of the double coaxial wire 18 and the inner shield wire is the same as that in FIG. 9 (sixth embodiment).

  Also with the probe card 15c according to the seventh embodiment, as in the sixth embodiment, the semiconductor integrated circuit chip can be avoided from being affected by external noise, and the test can be performed.

  In this case, in the seventh embodiment, the number of probes can be reduced to two as compared with the sixth embodiment, and the number of terminals (pads) prepared at the measurement points of the semiconductor integrated circuit chip. Can be reduced to two.

1 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to a first embodiment of the present invention. It is a circuit diagram which shows the structure of the semiconductor integrated circuit device concerning the 2nd Embodiment of this invention. FIG. 6 is a circuit diagram showing a specific configuration example of the semiconductor integrated circuit device shown in FIG. 1 as a third embodiment of the present invention. FIG. 4 is a circuit diagram showing a specific configuration example of the semiconductor integrated circuit device shown in FIG. 2 as a third embodiment of the present invention. FIG. 5 is a diagram illustrating a circuit example for completely stopping the operation of the voltage follower illustrated in FIG. 4 when there is no input. FIG. 10 is a circuit diagram showing another specific configuration example of the semiconductor integrated circuit device shown in FIG. 1 as a fourth embodiment of the present invention. FIG. 10 is a circuit diagram showing another specific configuration example of the semiconductor integrated circuit device shown in FIG. 2 as a fourth embodiment of the present invention. It is a conceptual diagram which shows the principal part structure of the probe card concerning the 5th Embodiment of this invention. It is a conceptual diagram which shows the principal part structure of the probe card concerning the 6th Embodiment of this invention. It is a conceptual diagram which shows the principal part structure of the probe card concerning the 7th Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit chip 2 1st output terminal 3 Buffer amplifier 4 2nd output terminal 5 Coaxial line 6 Other chip | tip / measuring instrument 7 Switch 8 Measuring instrument 10 Operational amplifier 11 which comprises a voltage follower 11, 12 Power switch 15a, 15b, 15c Probe card 16 Coaxial line 17a, 17b, 17c Probe 18 Double coaxial line MN1 N-type transistor that is a component of the source follower RL Resistance element that is a component of the source follower MN2 N-type transistor that constitutes a switch MN3 N-type transistor constituting power switch

Claims (5)

A first output terminal to which one end of a coaxial wire is connected;
A second output terminal to which one end of the shield wire of the coaxial line is connected;
A buffer amplifier that outputs, to the second output terminal, a signal obtained by buffering an analog signal sent to the first output terminal in the same phase;
A semiconductor integrated circuit device comprising: A first output terminal and a second output terminal;
A buffer amplifier that outputs, to the second output terminal, a signal obtained by buffering an analog signal sent to the first output terminal in the same phase;
A switch for opening and closing the input path of the analog signal to the buffer amplifier;
With
The switch is controlled to be closed when one end of a coaxial cable core wire is connected to the first output terminal and one end of the coaxial cable shield wire is connected to the second output terminal. A semiconductor integrated circuit device.   The semiconductor integrated circuit device according to claim 1, wherein the buffer amplifier is a voltage follower.   The semiconductor integrated circuit device according to claim 1, wherein the buffer amplifier is a source follower. In a probe card in which a plurality of probes that contact the tip with each of a plurality of measurement terminals provided in a semiconductor integrated circuit device are arranged,
Each of the plurality of measurement terminals includes two of the first output terminal and the second output terminal in the semiconductor integrated circuit device according to claim 1 or 2,
In each of the plurality of adjacent probes, the plurality of probes are connected to one end of a coaxial wire, and the other end of the second probe is brought into contact with one of the first output terminals. The proximal end of the probe that is brought into contact with the output terminal is connected to one end of the shield wire of the coaxial line,
A probe card characterized by that.

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