JP2010118901A - Clock circuit, and video processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clock circuit capable of achieving a timing adjustment process based on time information and a clock generation process based on a clock adjustment value by using a single clock generation circuit. <P>SOLUTION: This clock circuit 2 includes a clock generation circuit 5 for generating a clock S4 with frequency adjusted based on PCR included in a transport packet, and a timing adjustment circuit 4 for adjusting timing at which the transport packet is input to the clock generation circuit 5. The timing adjustment circuit 4 includes a counter 26 for executing counting operation based on the clock S4. The timing adjustment circuit 4 executes an adjustment process of the timing at which the transport packet is input to the clock generation circuit 5 based on a counter value (signal S26) output from the counter 26 and a time stamp value (signal S24B) attached to the transport packet. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a clock circuit and a video processing apparatus including the clock circuit.

  In a communication protocol using MPEG (Moving Picture Experts Group) 2-TS (Transport Stream), an encoder on the transmission side adds a PCR (Program Clock Reference) for each transport packet at a predetermined interval. The decoder on the receiving side detects the PCR included in the transport packet and regenerates the encoder clock based on the detected PCR. In MPEG2-TS, meaningless transport packets (null packets) are included in the transport stream in order to adjust the communication speed. In the encoder, PCR is added to the transport stream including a null packet.

  In communication via an IP (Internet Protocol) network, such as IP broadcast or VOD (Video On Demand) service, it is desirable to transmit a transport stream after deleting null packets in order to reduce the amount of communication data. . In this case, the position of the transport packet including the PCR differs before and after the null packet is deleted. Therefore, also in the transport stream received by the decoder, the position of the transport packet including the PCR is different from the original position (position in the transport stream before the null packet is deleted). Therefore, the decoder cannot accurately reproduce the encoder clock only by the detected PCR.

  Patent Documents 1 and 2 below disclose techniques for converting MPEG2-TS into MPEG2-TTS (Time-stamped Transport Stream) by adding a time stamp to each MPEG2-TS transport packet. Even when the null packet is deleted in the encoder, the decoder can restore the original position of the transport packet including the PCR based on the time stamp. Therefore, the decoder can regenerate the encoder clock based on the PCR included in the transport packet restored to the original position.

  FIG. 14 is a block diagram showing a part of the configuration of a decoder that handles MPEG2-TTS. The TTS decoder 330 operates based on the reference clock generated by the clock generation unit 334, reads the TTS packet from the TTS packet buffer 332 according to the time stamp added to each TTS packet, and sends it to the MPEG decoder 340 as a TS packet. input.

  The TTS decoder 330 has a function of adjusting the frequency of the reference clock as follows. The TTS packet buffer 332 stores TTS packets that are about half of their capacity (that is, the occupation amount is about 1/2). The TTS decoder 330 monitors the occupation amount of the TTS packet buffer 332, and raises the frequency of the reference clock when the occupation amount exceeds the specified range. This speeds up the pace at which TTS packets are read from the TTS packet buffer 332. On the other hand, when the occupation amount falls below the specified range, the frequency of the reference clock is lowered. This slows down the pace at which TTS packets are read from the TTS packet buffer 332.

JP 2008-35197 A JP 2008-35198 A

  According to the decoder shown in FIG. 14, it is necessary to provide a clock generation unit 334 separately from the clock generation circuit included in the MPEG decoder 340. That is, it is necessary to provide a clock generation circuit for TTS processing separately from a clock generation circuit for clock recovery based on PCR. As a result, the circuit configuration becomes complicated, leading to an increase in the size of the device and an increase in manufacturing costs.

  The present invention has been made in view of such circumstances, and a timing adjustment process based on time information (time stamp) added to a transport packet, and a clock adjustment value (PCR) included in the transport packet. The clock generation processing based on (1) is realized by using a single clock generation circuit, and a clock circuit and a video processing apparatus including the clock circuit are provided.

  A clock circuit according to a first aspect of the present invention generates a clock having a frequency adjusted based on a clock adjustment value included in a transport packet, and inputs the transport packet to the clock generation unit. Timing adjustment means for adjusting the timing to perform, the timing adjustment means has a counter that performs a counting operation based on the clock, the timing adjustment means, the counter value output from the counter, Based on the time information value added to the transport packet, a timing adjustment process for inputting the transport packet to the clock generating means is executed.

  According to the clock circuit according to the first aspect, the timing adjustment means has a counter that performs a counting operation based on the clock generated by the clock generation means. Then, the timing adjustment means executes timing adjustment processing for inputting the transport packet to the clock generation means based on the counter value output from the counter and the value of the time information added to the transport packet. To do. Therefore, the timing adjustment means does not need to have a clock generation circuit. As a result, the timing adjustment process based on the time information and the clock generation process based on the clock adjustment value can be realized using one clock generation circuit in the clock generation means.

  The clock circuit according to a second aspect of the present invention is the clock circuit according to the first aspect, in particular, the timing adjustment means includes a storage means for temporarily storing a plurality of transport packets, and a storage means in the storage means. Detecting means for detecting a storage amount of the plurality of transport packets, the clock generation means based on the clock adjustment value and a detection result of the storage amount by the detection means. It is characterized by adjusting.

  According to the clock circuit of the second aspect, the detection means detects the storage amount of a plurality of transport packets in the storage means. Then, the clock generation means adjusts the clock frequency based not only on the clock adjustment value but also on the detection result of the storage amount by the detection means. When the storage amount of the storage means is increasing, the clock frequency is increased, and when the storage amount of the storage means is decreasing, the clock frequency of the reception side decoder is decreased by decreasing the clock frequency. The frequency of the encoder clock can be approached. As a result, the clock generation means can reliably adjust the clock frequency using the clock adjustment value.

  The clock circuit according to a third aspect of the present invention is the clock circuit according to the second aspect, particularly, wherein the clock generation means weights at least one of the clock adjustment value and the detection result of the storage amount. It is characterized by this.

  According to the clock circuit of the third aspect, by weighting at least one of the clock adjustment value and the storage amount detection result, the influence of the clock adjustment value and the storage amount detection result on the adjustment of the clock frequency is affected. The degree can be adjusted as desired.

  The clock circuit according to a fourth aspect of the present invention is the clock circuit according to any one of the first to third aspects, and in particular, the timing adjusting means is added to the counter value and the transport packet. When the difference from the value of the time information is not included in the predetermined range, the transport packet is transmitted at the timing when a predetermined time has elapsed from the timing when the previous transport packet is input to the clock generation unit. It is characterized by being inputted to the clock generation means.

  According to the clock circuit of the fourth aspect, the timing adjustment means, when the difference between the counter value and the value of the time information added to the transport packet is not included in the predetermined range, The port packet is input to the clock generation unit at a timing when a predetermined time has elapsed from the timing at which the previous transport packet was input to the clock generation unit. Therefore, when the time information added to the transport packet indicates an abnormal value for some reason, the transport packet can be input to the clock generation means after a predetermined time has elapsed. As a result, it is possible to avoid a situation where the operation of the clock circuit stops due to abnormal time information.

  The clock circuit according to a fifth aspect of the present invention is the clock circuit according to any one of the first to fourth aspects, and in particular, the timing adjusting means includes a part of a plurality of transport packets. For a packet, a timing adjustment process for inputting the transport packet to the clock generation unit is executed, and a transport packet for which the adjustment process is not executed is input to the clock generation unit in succession to the previous transport packet. It is characterized by that.

  According to the clock circuit according to the fifth aspect, the timing adjustment means executes the input timing adjustment processing for a part of the plurality of transport packets. Therefore, it is possible to reduce the processing load as compared with the case where adjustment processing is performed for all transport packets.

  The clock circuit according to a sixth aspect of the present invention is the clock circuit according to the fifth aspect, in particular, the timing adjustment means, for a transport packet including a clock adjustment value, transfers the transport packet to the clock generation means. The process of adjusting the timing to input to is executed.

  According to the clock circuit of the sixth aspect, the timing adjustment unit performs the input timing adjustment process for the transport packet including the clock adjustment value. Therefore, the transport packet including the clock adjustment value can be input to the clock generation means at an appropriate input timing at which the adjustment process is executed. As a result, it is possible to avoid a situation in which the accuracy of adjustment of the clock frequency by the clock generation means decreases.

  A video processing device according to a seventh aspect of the present invention executes a transport packet decoding process based on a clock circuit according to any one of the first to sixth aspects and a clock generated by the clock circuit. And a decoding circuit.

  According to the video processing device of the seventh aspect, in the clock circuit, the timing adjustment process based on the time information and the clock generation process based on the clock adjustment value use one clock generation circuit in the clock generation means. Has been realized. This reduces the size of the clock circuit. Accordingly, by providing the video processing device with a miniaturized clock circuit, the overall size of the video processing device can be reduced.

  According to the present invention, one clock generation circuit is used for timing adjustment processing based on time information added to a transport packet and clock generation processing based on a clock adjustment value included in the transport packet. Can be realized.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the element which attached | subjected the same code | symbol in different drawing shall show the same or corresponding element.

  FIG. 1 is a block diagram showing a simplified configuration of a video processing apparatus 1 according to an embodiment of the present invention. The video processing device 1 is, for example, a receiving device (set) for receiving a video signal transmitted from an encoder on the transmission side in communication via an IP network (IP broadcasting, streaming type or download type VOD service, etc.). Top box). Referring to FIG. 1, the video processing apparatus 1 includes a clock circuit 2 and a decode circuit 3. The clock circuit 2 includes a timing adjustment circuit 4 and a clock generation circuit 5.

  FIG. 2 is a block diagram showing a configuration of the timing adjustment circuit 4. FIG. 3 is a block diagram showing the configuration of the clock generation circuit 5. As shown in the connection relationship of FIG. 2, the timing adjustment circuit 4 includes a buffer 21 (storage unit), a detection unit 22, a gate 23, an extraction unit 24, a calculation unit 25, and a counter 26. 3, the clock generation circuit 5 includes a PCR detector 31, an STC (System Time Clock) counter 32, a subtractor 33, DACs (Digital to Analog Converter) 34, 38, LPF (Low Pass Filters) 35 and 39, an adder 36, and a VCO (Voltage Control Oscillator) 37 as a clock generation circuit.

  FIG. 4 is a diagram showing a part of the transport stream S1 received by the video processing device 1. The transport stream S1 includes a plurality of transport packets TP. In FIG. 4, only eight transport packets TP <b> 1 to TP <b> 8 that are consecutive in this order are shown for simplicity of explanation.

  5 and 6 are diagrams illustrating the structure of the transport packet TP. The transport packet TP has a header part PH and a payload part PP, and the total data length of these is 188 bytes. A time stamp (time information) 50 having a data length of 4 bytes is added to the transport packet TP. Further, a PCR (clock adjustment value) 51 is included in the header portion PH for each transport packet TP at a predetermined interval. FIG. 5 shows a transport packet TP including the PCR 51, and FIG. 6 shows a transport packet TP not including the PCR 51. Both the time stamp 50 and the PCR 51 are counter values, and are generated by a counting operation using a common clock of 27 MHz in the encoder 6, but usually both values are different from each other.

  Hereinafter, the operation of the video processing apparatus 1 will be described. First, the operation of the timing adjustment circuit 4 will be described. The video processing apparatus 1 receives the MPEG2-TTS transport stream S1 transmitted from the encoder 6 via the IP network. Then, the received transport stream S1 is temporarily stored in the buffer 21. Referring to FIG. 2, transport stream S <b> 1 is read from buffer 21 and input to gate 23.

  FIG. 7 is a timing chart showing the relationship between the transport stream S1 input to the gate 23 and the transport stream S2 output from the gate 23. Regarding the transport stream S1, transport packets TP1 to TP8 are successively read from the buffer 21 in this order and input to the gate 23.

  Referring to FIG. 2, extraction unit 24 extracts the value of time stamp 50 added to the first transport packet TP1 (hereinafter referred to as “time stamp value ST (1)”). Then, the time stamp value ST (1) is input to the counter 26 as the signal S24A. Thereby, the initial value of the counter 26 is set to the time stamp value ST (1) given by the signal S24A.

  The counter 26 receives the clock S4 output from the VCO 37 (see FIG. 3). The counter 26 performs a counting operation using the time stamp value ST (1) as an initial value, and increments the counter value of the counter 26 by “1” every time the clock S4 is input. The counter value output from the counter 26 is input to the calculation unit 25 as a signal S26.

  The time stamp value ST (1) extracted from the transport packet TP1 by the extraction unit 24 is input to the calculation unit 25 as a signal S24B. The arithmetic unit 25 subtracts the counter value given by the signal S26 from the time stamp value ST (1) given by the signal S24B, and at the same time the control value S25 for opening the gate 23 is obtained. Input to the gate 23. Regarding the transport packet TP1, since the time stamp value ST (1) given by the signal S24B is equal to the initial value of the counter 26, the gate 23 is immediately opened. By opening the gate 23, input of the transport packet TP1 to the clock generation circuit 5 is started at time T1. When the transport packet TP1 completes passing through the gate 23, the gate 23 is closed again. When passing through the gate 23, the time stamp 50 added to the transport packet TP1 is deleted, whereby conversion from MPEG2-TTS to MPEG2-TS is performed.

  Next, the extraction unit 24 extracts the value of the time stamp 50 (hereinafter referred to as “time stamp value ST (2)”) added to the transport packet TP2 following the transport packet TP1. Then, the time stamp value ST (2) is input to the calculation unit 25 as the signal S24B. Further, the counter 26 continues the counting operation based on the clock S4.

  The arithmetic unit 25 subtracts the counter value given by the signal S26 from the time stamp value ST (2) given by the signal S24B, and at the same time the control value S25 for opening the gate 23 is obtained. Input to the gate 23. By opening the gate 23, input of the transport packet TP2 to the clock generation circuit 5 is started at time T2. When the transport packet TP2 completes passing through the gate 23, the gate 23 is closed again. Similarly to the above, when passing through the gate 23, the time stamp 50 added to the transport packet TP2 is deleted.

  The same operation as described above is repeated for the transport packets TP3 and subsequent, and the transport stream S2 is input from the timing adjustment circuit 4 to the clock generation circuit 5.

  Referring to FIG. 7, for transport stream S2, for example, transport packet TP2 is input to clock generation circuit 5 in succession to transport packet TP1. This is because the encoder 6 does not have a null packet between the transport packet TP1 and the transport packet TP2. Strictly speaking, an interval of 4 bytes corresponding to the time stamp 50 deleted in the gate 23 exists between the end of the transport packet TP1 and the head of the transport packet TP2. In FIG. 7, the interval is ignored.

  For example, the transport packet TP3 is input to the clock generation circuit 5 with a delay from the transport packet TP2. The delay amount is a time WT1 corresponding to two transport packets TP in comparison between the heads. This is because the encoder 6 has deleted one null packet that existed between the transport packet TP2 and the transport packet TP3.

  For example, the transport packet TP6 is input to the clock generation circuit 5 with a delay from the transport packet TP5. The delay amount is a time WT2 corresponding to three transport packets TP in comparison between the heads. This is because the encoder 6 has deleted two null packets that existed between the transport packet TP5 and the transport packet TP6.

  As described above, the timing adjustment circuit 4 determines the transport packet TP based on the counter value (signal S26) output from the counter 26 and the time stamp value (signal S24B) added to the transport packet TP. Is input to the clock generation circuit 5.

  Next, the operation of the clock generation circuit 5 will be described. Among the plurality of transport packets TP1 to TP8 input from the timing adjustment circuit 4 to the clock generation circuit 5, some transport packets TP include the PCR 51 in the header portion PH (see FIG. 5). ). Here, as an example, it is assumed that PCR 51 is included in transport packets TP1 and TP7.

  Referring to FIG. 3, the PCR detecting unit 31 firstly refers to the value of the PCR 51 included in the transport packet TP1 that is the first transport packet TP including the PCR 51 (hereinafter referred to as “PCR value PCR (1)”). ) And the PCR value PCR (1) is set in the STC counter 32. The clock S4 output from the VCO 37 is input to the STC counter 32. The STC counter 32 increments the counter value of the STC counter 32 by “1” every time the clock S4 is input. When it is necessary to reset the STC counter 32 due to an error or the like, the PCR detection unit 31 extracts the PCR value of the first transport packet TP after restart including the PCR 51, and uses the value as a result. The STC counter 32 is set.

  Next, the PCR detection unit 31 detects the value of the PCR 51 (PCR value PCR (7)) included in the transport packet TP7, and inputs the PCR value PCR (7) to the subtracter 33 as a signal S31. . At this time, the current counter value of the STC counter 32 is input to the subtracter 33 as the signal S32. The subtracter 33 subtracts the value of the signal S32 from the value of the signal S31 and outputs the subtraction value as the signal S33. The DAC 34 converts the signal S33, which is a digital signal, into a signal S34, which is an analog signal, and outputs the signal S34. When the value of the signal S33 is zero, the DAC 34 outputs, for example, a 1V signal S34. When the value of the signal S33 is a positive value, the DAC 34 outputs a signal S34 having a voltage exceeding 1V according to the value. When the value of the signal S33 is a negative value, the DAC 34 outputs a signal S34 having a voltage of less than 1V according to the value. The LPF 35 outputs a signal S35 by performing a low pass filter process on the signal S34. Thereby, the fluctuation | variation of the voltage value in minute time is averaged. The signal S35 is input to the adder 36.

  With reference to FIG. 2, the detection unit 22 detects the total data amount of a plurality of transport packets TP currently stored in the buffer 21. A predetermined reference value (for example, ½ of the storage capacity of the buffer 21) is set in advance as the total data amount. The detection unit 22 outputs a signal S3 corresponding to the difference between the reference value and the current total data amount (difference obtained by subtracting the reference value from the total data amount; the same applies hereinafter). Referring to FIG. 3, DAC 38 converts signal S3, which is a digital signal, into signal S38, which is an analog signal, and outputs the signal S38. When the difference between the reference value and the total data amount is zero, the DAC 38 outputs a signal S38 of 1 V, for example. When the difference is a positive value, the DAC 38 outputs a signal S38 exceeding 1 V in accordance with the value. When the difference is a negative value, the DAC 38 outputs a signal S38 of less than 1 V according to the value. The LPF 39 outputs a signal S39 by performing a low-pass filter process on the signal S38. Thereby, the fluctuation | variation of the voltage value in minute time is averaged. The signal S39 is input to the adder 36.

  The adder 36 adds the signal S35 and the signal S39, and outputs the added value as the signal S36. The VCO 37 generates and outputs a clock S4 whose frequency is adjusted based on the analog voltage value indicated by the signal S36. For example, when the value of the signal S36 is 2V, the VCO 37 outputs a clock S4 of 27 MHz, and when the value of the signal S36 is more than 2V, the VCO 37 outputs a clock S4 of more than 27 MHz according to the value. When the value of S36 is less than 2V, the clock S4 of less than 27 MHz is output according to the value. The clock S4 is input to the STC counter 32 and the counter 26 (see FIG. 2). Referring to FIG. 1, clock S4 is input to decoding circuit 3.

  With reference to FIG. 1, a transport stream S <b> 2 and a clock S <b> 4 are input to the decode circuit 3 from the clock generation circuit 5. The decoding circuit 3 operates based on the clock S4, and outputs a video signal S5 by executing a decoding process on the transport stream S2. The video signal S5 is input to the display device 7 connected to the video processing device 1.

  As described above, according to the clock circuit 2 according to the present embodiment, the timing adjustment circuit 4 includes the counter 26 that performs the counting operation based on the clock S4 generated by the clock generation circuit 5. The timing adjustment circuit 4 clocks the transport packet TP based on the counter value (signal S26) output from the counter 26 and the time stamp value (signal S24B) added to the transport packet TP. Adjustment processing of timing input to the generation circuit 5 is executed. Therefore, the timing adjustment circuit 4 does not need to have a clock generation circuit (VCO). As a result, the timing adjustment process based on the time stamp and the clock generation process based on the PCR can be realized by using one VCO 37 in the clock generation circuit 5. As a result, the clock circuit 2 can be reduced in size, and the video processing apparatus 1 can be reduced in size as a whole by providing the reduced-size clock circuit 2 in the video processing apparatus 1. It becomes possible.

  Further, according to the clock circuit 2 according to the present embodiment, the detection unit 22 detects the storage amount of the plurality of transport packets TP in the buffer 21. Then, the clock generation circuit 5 adjusts the frequency of the clock S4 based not only on the PCR but also on the detection result (signal S3) of the storage amount by the detection unit 22. When the storage amount of the buffer 21 tends to increase, the frequency of the clock S4 is increased, and when the storage amount of the buffer 21 tends to decrease, the frequency of the clock S4 is decreased to reduce the frequency of the clock on the receiving side decoder. It is possible to approach the frequency of the transmitting encoder clock. As a result, the clock generation circuit 5 can reliably adjust the frequency of the clock S4 using PCR.

  Note that the initial value of the counter 26 set based on the signal S24A may be updated regularly or irregularly. For example, the time stamp value extracted from the transport packet TP is compared with the current counter value of the counter 26, and when the difference exceeds a predetermined threshold value, a new initial value is set in the counter 26. As a result, it is possible to avoid a situation in which the timing at which the transport packet TP is input to the clock generation circuit 5 due to an incorrect counter value occurs. In this case, in order to avoid erroneous update processing due to sudden noise, the initial value of the counter 26 is set based on a plurality of time stamp values, and a plurality of time stamp values are also used in the update processing. It is desirable to set a new initial value based on

<First Modification>
FIG. 8 is a block diagram showing a configuration of the timing adjustment circuit 4 according to the first modification. A determination unit 40 is added to the configuration shown in FIG. Other configurations are the same as those in FIG.

  The calculation unit 25 subtracts the counter value given by the signal S26 from the time stamp value given by the signal S24B, and inputs the subtraction value to the determination unit 40 as the signal S25. A predetermined allowable range (maximum value and minimum value) regarding the value of the signal S25 is taught in advance to the determination unit 40, and the determination unit 40 includes the subtraction value given by the signal S25 within the allowable range. It is determined whether or not.

  When the subtraction value given by the signal S25 is included in the allowable range, the determination unit 40 sets the control signal S40 for opening the gate 23 to the gate 23 at the same time as the subtraction value becomes zero. input.

  On the other hand, when the subtraction value given by the signal S25 is not included in the allowable range, the determination unit 41 is set in advance after the input of the previous transport packet TP to the clock generation circuit 5 is started. After the predetermined time WT0 has elapsed, a control signal S40 for opening the gate 23 is input to the gate 23. As a result, the input of the current transport packet TP to the clock generation circuit 5 is started after a predetermined time WT0 has elapsed since the previous input of the transport packet TP to the clock generation circuit 5 was started.

  FIG. 9 is a timing chart showing the relationship between the transport stream S1 input to the gate 23 and the transport stream S2 output from the gate 23. Here, in the example shown in FIG. 7, an example is shown in which the value obtained by subtracting the counter value of the counter 26 from the time stamp value ST (3) related to the transport packet TP3 is not included in the allowable range. . In the example of FIG. 9, the predetermined time WT0 is set to a time corresponding to the data length (188 bytes) of the transport packet TP.

  The determination unit 40 inputs a control signal S40 for opening the gate 23 to the gate 23 at time T4 when the predetermined time WT0 has elapsed from time T2. As a result, the transport packet TP3 is input to the clock generation circuit 5 in succession to the transport packet TP2.

  The predetermined time WT0 is not limited to the time corresponding to the data length (188 bytes) of the transport packet TP, and may be other time.

  According to the clock circuit 2 according to the first modification, when the time stamp value added to the transport packet TP indicates an abnormal value for some reason, the transport packet TP is passed after a predetermined time WT0 has elapsed. Can be input to the clock generation circuit 5. As a result, it is possible to avoid a situation where the operation of the clock circuit 2 stops due to abnormal time information.

<Second Modification>
FIG. 10 is a block diagram showing a configuration of the timing adjustment circuit 4 according to the second modification. A detection unit 41 is added to the configuration shown in FIG. Other configurations are the same as those in FIG. The detection unit 41 detects the transport packet TP input from the buffer 21 to the gate 23 and counts the number thereof.

  In the above embodiment, the passage of the gate 23 is controlled for each transport packet TP. On the other hand, in the second modification, the passage of the gate 23 is controlled for each of a plurality (four in the following example) of transport packets TP.

  FIG. 11 is a timing chart showing the transport stream S2 output from the gate 23. Similar to the above embodiment, the transport packets TP1 to TP8 are successively read from the buffer 21 in this order and input to the gate 23.

  When the detection unit 41 detects the transport packet TP1, the extraction unit 24 and the calculation unit 25 perform the same operation as the operation described in the above embodiment based on the control signal S41 input from the detection unit 41. On the other hand, even if the detection unit 41 subsequently detects the transport packets TP2 to TP4, the control signal S41 is not input from the detection unit 41 to the extraction unit 24 and the calculation unit 25, and the extraction unit 24 and the calculation unit 25 The operation described in the embodiment is not executed. In this case, the gate 23 is opened at the timing when the value obtained by subtracting the counter value given by the signal S26 from the time stamp value ST (1) given by the signal S24B becomes zero, so that the clock generation circuit 5 Continuous input of the transport packets TP1 to TP4 is started. When the transport packet TP4 completes passing through the gate 23, the gate 23 is closed again based on the control signal S41 input from the detection unit 41 to the gate 23. As described above, when passing through the gate 23, the time stamp 50 added to each transport packet TP1 to TP4 is deleted.

  Next, when the detection unit 41 detects the transport packet TP5, the extraction unit 24 and the calculation unit 25 perform the same operation as the operation described in the above embodiment based on the control signal S41 input from the detection unit 41. Execute. On the other hand, even if the detection unit 41 subsequently detects the transport packets TP6 to TP8, the control signal S41 is not input from the detection unit 41 to the extraction unit 24 and the calculation unit 25, and the extraction unit 24 and the calculation unit 25 The operation described in the embodiment is not executed. In this case, the gate 23 opens at the timing when the value obtained by subtracting the counter value given by the signal S26 from the time stamp value ST (5) given by the signal S24B becomes zero, so that the clock generation circuit 5 Continuous input of the transport packets TP5 to TP8 is started. When the transport packet TP8 completes passing through the gate 23, the gate 23 is closed again based on the control signal S41 input from the detection unit 41 to the gate 23. Similarly to the above, when passing through the gate 23, the time stamp 50 added to each of the transport packets TP5 to TP8 is deleted.

  Referring to FIG. 11, transport packet TP5 is input to clock generation circuit 5 with a delay from transport packet TP4. The amount of delay is a time WT3 corresponding to six transport packets TP in comparison between the heads of the transport packets TP1 and TP5. This is because the encoder 6 has deleted two null packets that existed between the transport packet TP1 and the transport packet TP5.

  According to the clock circuit 2 according to the second modified example, the timing adjustment circuit 4 executes input timing adjustment processing for some transport packets TP1 among the plurality of transport packets TP1 to TP4. Therefore, it is possible to reduce the processing load as compared with the case where adjustment processing is performed for all transport packets TP1 to TP4. Similarly, the timing adjustment circuit 4 executes input timing adjustment processing for some transport packets TP5 among the plurality of transport packets TP5 to TP8. Therefore, it is possible to reduce the processing load as compared with the case where adjustment processing is performed for all the transport packets TP5 to TP8.

<Third Modification>
The configuration of the timing adjustment circuit 4 according to the third modification is the same as the configuration illustrated in FIG. In the second modified example, as shown in FIG. 11, the transport packets TP2 to TP4 are input to the clock generation circuit 5 following the transport packet TP1. In the third modification, a case will be described in which a transport packet TP including the PCR 51 exists in the transport packets TP2 to TP4. In the following description, it is assumed that the PCR 51 is included in the transport packet TP3.

  FIG. 12 is a timing chart showing the transport stream S2 output from the gate 23. Similar to the second modified example, the transport packets TP1 to TP10 are successively read from the buffer 21 in this order and input to the gate 23.

  When the detection unit 41 detects the transport packet TP1, the extraction unit 24 and the calculation unit 25 perform the same operation as the operation described in the above embodiment based on the control signal S41 input from the detection unit 41. On the other hand, even if the detection unit 41 subsequently detects the transport packet TP2, the control signal S41 is not input from the detection unit 41 to the extraction unit 24 and the calculation unit 25, and the extraction unit 24 and the calculation unit 25 The operation described in the form is not executed. In this case, the gate 23 is opened at the timing when the value obtained by subtracting the counter value given by the signal S26 from the time stamp value ST (1) given by the signal S24B becomes zero, so that the clock generation circuit 5 Continuous input of the transport packets TP1 and TP2 is started. Similarly to the above, when passing through the gate 23, the time stamp 50 added to each transport packet TP1, TP2 is deleted.

  Next, when the detection unit 41 detects the transport packet TP3 including the PCR 51, the extraction unit 24 and the calculation unit 25 perform the operations described in the above embodiment based on the control signal S41 input from the detection unit 41. A similar operation is performed. On the other hand, even if the detection unit 41 subsequently detects the transport packets TP4 to TP6, the control signal S41 is not input from the detection unit 41 to the extraction unit 24 and the calculation unit 25, and the extraction unit 24 and the calculation unit 25 The operation described in the embodiment is not executed. In this case, the gate 23 opens at the timing when the value obtained by subtracting the counter value given by the signal S26 from the time stamp value ST (3) given by the signal S24B becomes zero, so that the clock generation circuit 5 Continuous input of the transport packets TP3 to TP6 is started. As described above, when passing through the gate 23, the time stamp 50 added to each of the transport packets TP3 to TP6 is deleted.

  Next, when the detection unit 41 detects the transport packet TP7, the extraction unit 24 and the calculation unit 25 perform the same operation as the operation described in the above embodiment based on the control signal S41 input from the detection unit 41. Execute. On the other hand, even if the detection unit 41 subsequently detects the transport packets TP8 to TP10, the control signal S41 is not input from the detection unit 41 to the extraction unit 24 and the calculation unit 25, and the extraction unit 24 and the calculation unit 25 The operation described in the embodiment is not executed. In this case, the gate 23 opens at the timing when the value obtained by subtracting the counter value given by the signal S26 from the time stamp value ST (7) given by the signal S24B becomes zero, so that the clock generation circuit 5 Continuous input of the transport packets TP7 to TP10 is started. Similarly to the above, when passing through the gate 23, the time stamp 50 added to each transport packet TP7 to TP10 is deleted.

  Referring to FIG. 12, transport packet TP3 is input to clock generation circuit 5 with a delay from transport packet TP2. The delay amount is a time WT4 corresponding to two transport packets TP in comparison between the heads of the transport packets TP1 and TP3. This is because the encoder 6 has deleted one null packet that existed between the transport packet TP1 and the transport packet TP3.

  The transport packet TP7 is input to the clock generation circuit 5 with a delay from the transport packet TP6. The amount of delay is a time WT5 corresponding to five transport packets TP in comparison between the heads of the transport packets TP3 and TP7. This is because the encoder 6 has deleted one null packet that existed between the transport packet TP3 and the transport packet TP7.

  According to the clock circuit 2 according to the third modification, the timing adjustment circuit 4 executes the input timing adjustment process for the transport packet TP3 including the PCR 51. Therefore, the transport packet TP3 including the PCR 51 can be input to the clock generation circuit 5 at an appropriate input timing at which the adjustment process is executed. As a result, it is possible to avoid a situation in which the frequency adjustment accuracy of the clock S5 by the clock generation circuit 5 is lowered.

<Fourth Modification>
FIG. 13 is a block diagram showing a configuration of the clock generation circuit 5 according to the fourth modification. Multipliers 80 and 81 are added to the configuration shown in FIG. The multiplier 80 multiplies the signal S34 input from the DAC 34 by a desired weighting coefficient Y to output a signal S80. The signal S80 is input to the LPF 35. The multiplier 81 multiplies the signal S38 input from the DAC 38 by a desired weighting coefficient Z, and outputs a signal S81. The signal S81 is input to the LPF 39. One of the multipliers 80 and 81 may be omitted.

  According to the clock circuit 2 according to the fourth modified example, by weighting at least one of the signal S34 related to the PCR value and the signal S38 related to the detection result of the storage amount of the buffer 21, the PCR value and It is possible to adjust the degree of influence of the detection result of the storage amount of the buffer 21 on the adjustment of the frequency of the clock S4 as desired.

  In addition, embodiment mentioned above and the 1st-4th modification can be applied in arbitrary combinations.

  In addition, it should be considered that the embodiment disclosed this time is illustrative and not restrictive in all respects. The scope of the present invention is defined not by the above-mentioned meaning but by the scope of claims for patent, and is intended to include all modifications within the scope and meaning equivalent to the scope of claims for patent.

It is a block diagram which simplifies and shows the structure of the video processing apparatus which concerns on embodiment of this invention. It is a block diagram which shows the structure of a timing adjustment circuit. It is a block diagram which shows the structure of a clock generation circuit. It is a figure which extracts and shows a part of transport stream which a video processing apparatus receives. It is a figure which shows the structure of a transport packet. It is a figure which shows the structure of a transport packet. It is a timing chart which shows the relationship between the transport stream input into a gate, and the transport stream output from a gate. It is a block diagram which shows the structure of the timing adjustment circuit which concerns on a 1st modification. It is a timing chart which shows the relationship between the transport stream input into a gate, and the transport stream output from a gate. It is a block diagram which shows the structure of the timing adjustment circuit which concerns on a 2nd modification. It is a timing chart which shows the transport stream output from a gate. It is a timing chart which shows the transport stream output from a gate. It is a block diagram which shows the structure of the clock generation circuit which concerns on a 4th modification. It is a block diagram which extracts and shows a part of structure of a decoder.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Video processing device 2 Clock circuit 3 Decoding circuit 4 Timing adjustment circuit 5 Clock generation circuit 21 Buffer 22,41 Detection part 23 Gate 24 Extraction part 25 Operation part 26 Counter 31 PCR detection part 32 STC counter 37 VCO
40 determination unit 80, 81 multiplier

Claims (7)

Clock generating means for generating a clock whose frequency is adjusted based on a clock adjustment value included in the transport packet;
Timing adjustment means for adjusting the timing of inputting the transport packet to the clock generation means,
The timing adjustment means includes a counter that performs a counting operation based on the clock,
The timing adjustment unit performs a timing adjustment process for inputting the transport packet to the clock generation unit based on the counter value output from the counter and the value of time information added to the transport packet. A clock circuit to execute. The timing adjusting means includes
Storage means for temporarily storing a plurality of transport packets;
Detecting means for detecting a storage amount of the plurality of transport packets in the storage means;
The clock circuit according to claim 1, wherein the clock generation unit adjusts a frequency of the clock based on the clock adjustment value and a detection result of the storage amount by the detection unit.   The clock circuit according to claim 2, wherein the clock generation unit weights at least one of the clock adjustment value and the storage amount detection result.   When the difference between the counter value and the value of the time information added to the transport packet is not included in the predetermined range, the timing adjustment unit replaces the transport packet with the previous transport packet. The clock circuit according to claim 1, wherein the clock circuit is input to the clock generation unit at a timing when a predetermined time has elapsed from the timing input to the clock generation unit. The timing adjustment unit performs a timing adjustment process of inputting the transport packet to the clock generation unit with respect to a part of the transport packets of the plurality of transport packets,
The clock circuit according to any one of claims 1 to 4, wherein a transport packet that is not subjected to the adjustment processing is input to the clock generation unit in succession to the previous transport packet.   The clock circuit according to claim 5, wherein the timing adjustment unit executes a timing adjustment process for inputting a transport packet to the clock generation unit for a transport packet including a clock adjustment value. A clock circuit according to any one of claims 1 to 6;
A video processing apparatus comprising: a decoding circuit that performs a decoding process of a transport packet based on a clock generated by the clock circuit.

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