JP2010118674A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which enables manufacturing without troubles even if an FZ wafer of a low price is used in a wafer process and can achieve both a low cost and high performance while providing a steep incline to impurity concentration at a boundary side to a drift layer of low impurity concentration in a high impurity concentration layer at a rear uppermost surface side. <P>SOLUTION: In the manufacturing method, an element active region and an anode electrode 8 are formed in a surface side of an FZ wafer and a rear side of the FZ wafer is cut off to a prescribed thickness. Thereafter, an n<SP>+</SP>cathode layer 1b is formed by casting light or laser on the FZ wafer backside while cooling the FZ wafer by carrying out particle beam irradiation of phosphor or arsenic ion from the FZ wafer backside. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to power semiconductor devices such as diodes and MOSFETs (field effect insulated gate transistors) used in power conversion devices, and more particularly to a semiconductor device suitable for adopting an FZ (floating zone) wafer and a manufacturing method thereof. .

The epi-type diode shown in FIG. 4 is manufactured using an epi-wafer formed by growing a low-concentration n-type epitaxial layer functioning as the n ⁻ drift layer 3 on a high-concentration n-type silicon substrate on which the n ⁺ cathode layer 1 is formed. Is done. In the n ⁻ drift layer 3, a drift current flows in the on state, and in the blocking mode (off state), the depletion layer extends from the pn junction with the p ⁺ anode layer 4 to the n ⁺ cathode layer 1 to secure a withstand voltage. To help. The n ⁺ cathode layer 1 has a function of preventing the depletion layer from reaching the cathode electrode 9 and obtaining a good ohmic contact with the cathode electrode 9 in the blocking mode. The epi-type diode using this epi-wafer has a high-concentration n-type silicon substrate and an n ^- drift layer 3 epitaxially grown thereon, so that the doping concentration shown in FIG. As shown in the graph, since the impurity concentration has a steep gradient on the boundary side of the n ⁺ cathode layer 1 with the n ⁻ drift layer 3, the trade-off between the forward voltage and the breakdown voltage is good. However, since an epi-wafer is expensive, an epi-type diode has a drawback of high manufacturing cost.

On the other hand, the DW-type diode shown in FIG. 5 is formed by diffusing high-concentration phosphorus from the back surface of a low-concentration n-type silicon substrate (FZ wafer) functioning as the n ⁻ drift layer 3 to form an n ⁺ cathode layer 1a. Manufactured using DW wafers. Since this DW wafer is less expensive than the epitaxial wafer because it does not require an epitaxial growth process, the manufacturing cost of the DW diode can be reduced, but the vertical dependence of the doping concentration shown in FIG. As shown in the graph, since the impurity concentration has a gentle gradient on the boundary side of the n ⁺ cathode layer 1a with the n ⁻ drift layer 3, the trade-off between the forward voltage and the breakdown voltage is deteriorated.

In recent years, power semiconductor devices such as diodes and MOSFETs have been required to further reduce costs while realizing high characteristics. In order to reduce the cost, it is more advantageous to employ a low-cost FZ wafer in the wafer process. In order to obtain high characteristics, the surface active region such as the p ⁺ anode layer 4 and the back side of the FZ wafer on which the anode electrode 8 is formed are shaved to a predetermined thickness, and then a particle beam such as phosphorus or arsenic ions is formed from the back side. It is conceivable to form an n ⁺ cathode layer by irradiating (implanting) and activating impurities by annealing. Since the maximum concentration point can be set in the deep part by the ion implantation method, the impurity concentration becomes steep on the boundary side of the n ⁺ cathode layer with the n ⁻ drift layer, so that high characteristics similar to those of the epi type diode can be expected.

  However, in fact, in order to sufficiently activate phosphorus or arsenic atoms in the silicon wafer, it is necessary to set the annealing temperature to 1000 ° C. or higher. Therefore, an aluminum anode electrode having a low melting point (about 700 ° C.) on the wafer surface. The above annealing process must be completed before depositing 8. However, even if the annealing process is performed before the deposition of the anode electrode 8, if the thin wafer after cutting is annealed at a high temperature of 1000 ° C. or higher, the wafer shape is greatly warped, so that the anode electrode 8 is a subsequent process. Photolithography for the formation of is no longer possible. For this reason, it was impossible to use a low-cost FZ wafer in the wafer process. Such a problem is not limited to the cathode layer of the vertical diode as described above, but the ohmic on the backmost surface side, such as the drain layer of the vertical MOSFET and the collector layer of a non-punch-through IGBT (conductivity modulation MOSFET). This is also a problem that can be said in the general formation of a contact layer (high impurity concentration layer).

  Therefore, in view of the above problems, an object of the present invention is to manufacture a low-cost FZ wafer without any problem even if it is used for a wafer process. It is an object of the present invention to provide a semiconductor device having a steep slope of impurity concentration on the boundary side of the substrate and capable of achieving both low cost and high performance, and a method for manufacturing the same.

  In order to solve the above-described problems, the present invention is characterized in that a high impurity concentration layer on the back surface (second main surface) on the outermost surface can be formed by a low temperature process.

  The first means of the present invention uses a first conductivity type low impurity concentration substrate forming a first conductivity type low impurity concentration drift layer, an element active region formed on the first main surface side of the substrate, and In a semiconductor device comprising the first electrode, a high impurity concentration layer formed on the outermost surface of the second main surface of the substrate, and the second electrode, the high impurity concentration layer is configured as an n-type defect layer. It is characterized by. The n-type defect layer is a single crystal lattice defect layer, but substantially functions as a high-concentration n-type semiconductor layer.

  Such a method of manufacturing a semiconductor device using the n-type defect layer on the outermost side of the second main surface as a high-concentration n-type semiconductor layer such as a contact layer has an element active region and a first active region on the first main surface side of the substrate. After forming the electrode and scraping off the second main surface side of the substrate to a predetermined thickness, proton irradiation is performed from the second main surface and annealing is performed to form an n-type defect layer. Since the annealing temperature for activating the n-type defect layer is sufficient to be lower than the melting point of the first electrode layer such as aluminum (700 degrees or less), the first electrode on the first main surface side is deposited. The n-type defect layer on the second main surface side can be formed without hindrance after the process. Since a low-priced n-type low impurity concentration FZ wafer can be used, the cost of the semiconductor device can be reduced. In addition, since the proton ion implantation method is used, the range is long, the maximum concentration point can be set deep, and impurities are present on the boundary side with the n-type low impurity concentration drift layer in the n-type defect layer which is a high impurity concentration layer. Since the concentration becomes steep, high characteristics similar to those of a semiconductor device using an epi-wafer can be obtained.

  The annealing temperature is preferably 300 ° C. or more and 500 ° C. or less. The irradiation energy of proton irradiation may be 1 MeV or less.

  According to a second means of the present invention, a first conductivity type low impurity concentration substrate forming a first conductivity type low impurity concentration drift layer is used, and an element active region formed on the first main surface side of the substrate, and In the semiconductor device including the first electrode, the high impurity concentration layer formed on the outermost surface of the second main surface of the substrate, and the second electrode, the high impurity concentration layer is an oxygen donor doped layer. Features. When the high impurity concentration layer is an oxygen donor-doped layer, the annealing process temperature can be set lower than the melting point of the first electrode such as aluminum, so that the second main surface can be easily obtained after the first electrode layer deposition step. A high impurity concentration layer on the side can be formed.

  In such a method for manufacturing a semiconductor device, an element active region and a first electrode are formed on a first main surface side of a substrate, and after the second main surface side of the substrate is scraped down to a predetermined thickness, a high impurity concentration layer is formed. It is formed by performing oxygen ion irradiation from the second main surface and annealing. Since a low-priced n-type low impurity concentration FZ wafer can be used, the cost of the semiconductor device can be reduced. In addition, since the ion implantation method of oxygen ions is used, the range is long, the maximum concentration point can be set deep, and the impurity concentration on the boundary side with the n-type low impurity concentration drift layer in the oxygen donor doped layer that is a high impurity concentration layer As a result, the characteristics as high as those of a semiconductor device using an epi-wafer can be obtained. The annealing temperature is preferably 300 ° C. or more and 500 ° C. or less.

  A third means of the present invention uses a first conductivity type low impurity concentration substrate forming a first conductivity type low impurity concentration drift layer, an element active region formed on the first main surface side of the substrate, and In the method of manufacturing a semiconductor device including the first electrode, the high impurity concentration layer formed on the outermost surface of the second main surface of the substrate, and the second electrode, the first electrode on the first main surface side of the substrate After forming the element active region and the first electrode layer and scraping off the second main surface side of the substrate to a predetermined thickness, the high impurity concentration layer is irradiated with the particle beam of impurity ions from the second main surface. And performing irradiation with light or laser on the second main surface while cooling the first main surface.

  As described above, as the annealing process for forming the high impurity concentration layer on the second main surface side, the second main surface side is cooled (cooling gas sprayed or heat sink) while cooling the first main surface side having the first electrode. Since the surface is subjected to lamp annealing or laser annealing, the annealing temperature on the second main surface side is set to a temperature higher than the melting point of aluminum (700 ° C. or higher) while ensuring a temperature gradient in the substrate thickness direction. Thus, even an introduced impurity with a short range can be sufficiently activated, and for example, phosphorus or arsenic can be used as a donor impurity. Since a low-cost low-impurity concentration FZ wafer can be used, the cost of the semiconductor device can be reduced. In addition, since the ion implantation method is used, the maximum concentration point can be set deep, and the impurity concentration on the boundary side with the drift layer of the high impurity concentration layer becomes steep, so that high characteristics similar to those of semiconductor devices using epiwafers can be obtained. It is done.

The irradiation energy of phosphorus or arsenic ions may be 1 MeV or less. The dose amount of phosphorus or arsenic is preferably 1 × 10 ¹³ cm ⁻² or more and 1 × 10 ¹⁶ cm ⁻² or less.

The present invention is not limited to diodes and MOSFETs, and can be applied to general vertical semiconductor devices including an n ⁻ drift layer and an n-type high impurity concentration layer (such as an ohmic contact layer) on the outermost side of the second main surface. Further, the third means of the present invention is not limited to the particle beam irradiation of the donor impurity, but may be the particle beam irradiation of the acceptor impurity (for example, boron), and the p-type high layer on the outermost side of the p ⁻ drift layer and the second main surface. The present invention is generally applicable to a vertical semiconductor device having an impurity concentration layer (such as an ohmic contact layer). Like the collector layer of a non-punch-through type IGBT (conductivity modulation type MOSFET), it can be applied to the ohmic contact layer (high impurity concentration layer regardless of the conductivity type) on the rearmost surface.

  As described above, the present invention is a high impurity on the outermost surface of the second main surface that functions as an ohmic contact layer such as a cathode layer of a vertical diode, a drain layer of a vertical MOSFET, a collector layer of a non-punch through IGBT. Since the concentration layer can be formed by a low-temperature process, the following effects can be obtained.

  In a semiconductor device using an n-type defect layer as a high-concentration n-type semiconductor layer, after forming an element active region and a first electrode on the first main surface side, proton irradiation is performed from the second main surface and annealing is performed. Since the n-type defect layer can be formed, the annealing temperature for activating the n-type defect layer is sufficient to be lower than the melting point of the first electrode. The n-type defect layer on the second main surface side can be formed without hindrance. For this reason, a low-cost n-type low impurity concentration FZ wafer can be used for the wafer process, and the cost reduction of the semiconductor device can be realized. In addition, since the impurity concentration is steep on the boundary side of the n-type defect layer, which is a high impurity concentration layer, with the drift layer having the n-type low impurity concentration, high characteristics similar to those of a semiconductor device using an epi-wafer can be obtained.

  In a semiconductor device that uses an oxygen donor doped layer as a high-concentration n-type semiconductor layer, after forming an element active region and a first electrode on the first main surface side, oxygen ion irradiation is performed from the second main surface and annealing is performed. Thus, an oxygen donor doped layer can be formed. For this reason, since a low-priced n-type low impurity concentration FZ wafer can be used, cost reduction of the semiconductor device can be realized. In addition, since the impurity concentration becomes steep on the boundary side of the oxygen donor doped layer with the drift layer having an n-type low impurity concentration, high characteristics similar to those of a semiconductor device using an epi-wafer can be obtained.

  After forming the element active region and the first electrode on the first main surface side, the ion beam is irradiated with impurity ions from the second main surface, and light or laser is applied to the second main surface while cooling the first main surface. When a manufacturing method in which a high impurity concentration layer is formed by an irradiation annealing method, the annealing temperature on the second main surface side can be set to a temperature higher than the melting point of aluminum while ensuring a temperature gradient in the substrate thickness direction. It is possible to sufficiently activate even an introduced impurity with a short range, and for example, phosphorus or arsenic can be used as a donor impurity, and boron or the like can be used as an acceptor impurity. Since a low-cost low-impurity concentration FZ wafer can be used, the cost of the semiconductor device can be reduced. In addition, since the impurity concentration is steep on the boundary side with the drift layer in the high impurity concentration layer, high characteristics similar to those of a semiconductor device using an epi-wafer can be obtained.

It is a partial cross section figure which shows the cross-section of the vertical diode which concerns on Embodiment 1 of this invention. It is a partial cross section figure which shows the cross-section of the vertical MOSFET which concerns on Embodiment 2 of this invention. It is a partial cross section figure which shows the cross-section of the vertical MOSFET which concerns on Embodiment 3 of this invention. It is a partial cross section figure which shows the cross-section of the conventional epi-type diode. It is a partial cross section figure which shows the cross-section of the conventional DW type diode.

Next, embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a partial cross-sectional view showing a cross-sectional structure of a vertical diode according to Embodiment 1 of the present invention. The vertical diode of this embodiment is a 1200V withstand voltage diode, and is manufactured using an n-type low impurity concentration FZ wafer forming the n ⁻ drift layer 3b. An element active region and an aluminum anode electrode 8 are formed on the surface side of the FZ wafer. Here, the element active region (core portion) of the diode means a pn junction between the p ⁺ anode layer 4 and the n ⁻ drift layer 3 b. An n ⁺ cathode layer 1b is formed on the rearmost surface side of the FZ wafer, and an aluminum cathode electrode 9 is deposited on the n ⁺ cathode layer 1b.

Thus, in the vertical diode using the n-type low impurity concentration FZ wafer, the element active region and the anode electrode 8 are formed on the front side of the FZ wafer, and the back side of the FZ wafer is scraped down to a predetermined thickness. After that, a particle beam irradiation of impurity ions described later is performed from the back surface, a predetermined annealing process is performed to form the n ⁺ cathode layer 1b, and then the cathode electrode 9 is deposited and manufactured.

In the structure of the vertical diode of Example 1, the n ⁺ cathode layer 1b is composed of an n-type defect layer. The n-type defect layer is a single crystal lattice defect layer, but substantially functions as a high-concentration n-type semiconductor layer. As described above, the manufacturing method of the diode using the n-type defect layer on the backmost surface side as the n ⁺ cathode layer 1b has the element active region (p ⁺ anode layer 4) and anode on the front side of the FZ wafer. After forming the electrode 8 and scraping off the back side of the FZ wafer to a predetermined thickness, proton irradiation is performed from the back side of the FZ wafer, and annealing treatment (eg, 300 ° C. to 500 ° C.) is performed to form an n-type defect layer To do. The irradiation energy of proton irradiation may be 1 MeV or less because the range is long. An annealing temperature for activating the n-type defect layer is sufficient if it is lower than the melting point of the aluminum anode electrode 8 (700 ° C. or less), and therefore, the n ⁺ cathode layer without any trouble after the deposition process of the anode electrode 8 An n-type defect layer as 1b can be formed. Of course, since a low-priced n-type low impurity concentration FZ wafer is used, the cost of the diode can be reduced. Moreover, since the proton ion implantation method is used in forming the n ⁺ cathode layer 1b, the range is long, the maximum concentration point can be set in the deep portion, and as shown in the graph of the longitudinal dependency of the doping concentration attached to FIG. In addition, since the impurity concentration is steep on the boundary side with the n ⁻ drift layer 3b in the n-type defect layer as the n ⁺ cathode layer 1b, high characteristics similar to those of a diode using an epi wafer can be obtained.

In the structure of the vertical diode of Example 2, the n ⁺ cathode layer 1b is composed of an oxygen donor doped layer. When the n ⁺ cathode layer 1b is an oxygen donor doped layer, the annealing temperature can be set to a temperature lower than the melting point of the aluminum anode electrode 8, so that the n ⁺ cathode layer 1b can be used without any problem after the deposition process of the anode electrode 8. Can be formed.

As described above, the diode manufacturing method using such an oxygen donor doped layer on the backmost surface side as the n ⁺ cathode layer 1b forms the element active region and the anode electrode 8 on the front side of the FZ wafer. After the back surface side of the substrate is scraped down to a predetermined thickness, oxygen ion irradiation is performed from the back surface side of the FZ wafer, and an annealing process (for example, 300 ° C. to 500 ° C.) is performed to form an oxygen donor dope layer. Since the irradiation energy of oxygen ion irradiation is long, it may be 1 MeV or less. An annealing temperature for activating the oxygen donor doped layer is also sufficient if the temperature is lower than the melting point of the aluminum anode electrode 8 (700 ° C. or lower), so that the n ⁺ cathode layer 1b can be used without any trouble after the anode electrode 8 deposition process. An oxygen donor doped layer can be formed. Further, since a low-priced n-type low impurity concentration FZ wafer is used, the cost of the diode can be reduced. In addition, since the ion implantation method of oxygen ions is used for forming the n ⁺ cathode layer 1b, the range is long, the maximum concentration point can be set in a deep portion, and the longitudinal concentration dependence graph of doping concentration shown in FIG. Similarly, since the impurity concentration becomes steep on the boundary side with the n ⁻ drift layer 3b in the n-type defect layer as the n ⁺ cathode layer 1b, high characteristics similar to those of a diode using an epi-wafer can be obtained.

The vertical diode of Example 3 is characterized by an annealing method. That is, in the manufacturing method of this example, the element active region and the anode electrode 8 are formed on the front surface side of the FZ wafer, and the back surface side of the FZ wafer is scraped down to a predetermined thickness, and then the n ⁺ cathode layer 1b is removed from the FZ wafer. It is formed by irradiating phosphor or arsenic ion particles from the back of the wafer and irradiating the back of the FZ wafer with light or laser while cooling the FZ wafer. The irradiation energy of phosphorus or arsenic ions may be 1 MeV or less. The dose of phosphorus or arsenic may be 1 × 10 ¹³ cm ⁻² to 1 × 10 ¹⁶ cm ⁻² . The cooling method on the FZ wafer surface side is spraying of a cooling gas or a heat sink.

Since the annealing method is short-time lamp annealing or laser annealing on the back surface while cooling the FZ wafer surface, the annealing temperature on the back surface is set to aluminum while ensuring a temperature gradient in the thickness direction of the FZ wafer during this annealing. It is possible to set the temperature higher than the melting point (700 ° C. or higher), and it is possible to sufficiently activate even an introduced impurity with a short range, and for example, phosphorus or arsenic can be used as a donor impurity. Of course, since a low-cost, low-impurity concentration FZ wafer can be used, the cost of the diode can be reduced. In addition, since an ion implantation method, it can set the maximum density point deep, as shown in the vertical direction dependency graph of the doping concentrations appended to Figure 1, n of the n ⁺ cathode layer 1b ^- the drift layer 3b Since the impurity concentration is steep on the boundary side, high characteristics similar to a diode using an epi-wafer can be obtained.

  Next, FIG. 2 is a partial cross-sectional view showing a cross-sectional structure of a vertical MOSFET according to Embodiment 2 of the present invention.

The vertical MOSFET of this embodiment is a 600V breakdown voltage MOSFET, and is manufactured using an n-type low impurity concentration FZ wafer forming the n ⁻ drift layer 13b. An element active region (core portion) and an aluminum source electrode 18 are formed on the surface side of the FZ wafer. Here, the element active region of the MOSFET includes a well-shaped p ⁺ base region 14 formed on the surface side of the n ⁻ drift layer 13 b, and an n ⁺ source region 15 formed on the surface side of the p ⁺ base region 14. A gate electrode 17 made of polycrystalline silicon or the like formed through the gate oxide film 16, and a source electrode 18 formed through the interlayer insulating film. An n ⁺ drain layer 11b is formed on the outermost surface of the back surface of the FZ wafer, and an aluminum drain electrode 19 is deposited on the n ⁺ drain layer 11b.

Thus, in the vertical MOSFET using the n-type low impurity concentration FZ wafer, the element active region and the source electrode 18 are formed on the front side of the FZ wafer, and the back side of the FZ wafer is scraped down to a predetermined thickness. After that, a particle beam irradiation of impurity ions to be described later is performed from the back surface, a predetermined annealing process is performed to form the n ⁺ drain layer 11b, and then the drain electrode 19 is deposited and manufactured.

In the vertical MOSFET structure of the fourth embodiment, the n ⁺ drain layer 11b is formed of an n-type defect layer. The n-type defect layer is a single crystal lattice defect layer, but substantially functions as a high-concentration n-type semiconductor layer. As described above, the MOSFET manufacturing method using the n-type defect layer on the backmost surface side as the n ⁺ drain layer 1b forms the element active region and the source electrode 18 on the front surface side of the FZ wafer, and the FZ After scraping off the back side of the wafer to a predetermined thickness, proton irradiation is performed from the back side of the FZ wafer, and an annealing process (for example, 300 ° C. to 500 ° C.) is performed to form an n-type defect layer. The irradiation energy of proton irradiation may be 1 MeV or less because the range is long. Since the annealing temperature for activating the n-type defect layer is sufficient to be lower than the melting point of the aluminum source electrode 18 (700 ° C. or less), the n ⁺ drain layer can be safely used after the deposition process of the source electrode 18. An n-type defect layer as 11b can be formed. Of course, since a low-priced n-type low impurity concentration FZ wafer is used, the cost of the MOSFET can be reduced. Moreover, since the proton ion implantation method is used for forming the n ⁺ drain layer 1b, the range is long, the maximum concentration point can be set in the deep part, and as shown in the vertical dependence graph of the doping concentration attached to FIG. Moreover, since the impurity concentration is steep on the boundary side with the n ⁻ drift layer 13b in the n-type defect layer serving as the n ⁺ drain layer 11b, high characteristics similar to those of a MOSFET using an epi wafer can be obtained.

In the structure of the vertical MOSFET of the fifth embodiment, the n ⁺ drain layer 11b is composed of an oxygen donor doped layer. When the n ⁺ drain layer 11b is an oxygen donor doped layer, the annealing temperature can be set lower than the melting point of the aluminum source electrode 18. Therefore, the n ⁺ drain layer 1b can be used without difficulty after the deposition process of the source electrode 18. Can be formed.

As described above, the MOSFET manufacturing method using such an oxygen donor doped layer on the backmost surface side as the n ⁺ drain layer 11b forms the element active region and the source electrode 18 on the front surface side of the FZ wafer, and the FZ wafer. After the back surface side of the substrate is scraped down to a predetermined thickness, oxygen ion irradiation is performed from the back surface side of the FZ wafer, and an annealing process (for example, 300 ° C. to 500 ° C.) is performed to form an oxygen donor dope layer. Since the irradiation energy of oxygen ion irradiation is long, it may be 1 MeV or less. Annealing temperature for the activation of the oxygen donor-doped layer also because at a temperature lower than the melting point of the aluminum of the source electrode 18 (700 ° C. or less) is sufficient, trouble after deposition step of the source electrode 18 without the n ⁺ drain layer 11b An oxygen donor doped layer can be formed. Further, since a low-priced n-type low impurity concentration FZ wafer is used, the cost of the MOSFET can be reduced. In addition, since the ion implantation method of oxygen ions is used to form the n ⁺ drain layer 11b, the range is long, the maximum concentration point can be set in a deep portion, and the longitudinal concentration dependence graph of the doping concentration attached to FIG. Similarly, since the impurity concentration becomes steep on the boundary side with the n ⁻ drift layer 13b in the n-type defect layer serving as the n ⁺ drain layer 11b, high characteristics similar to those of the MOSFET using the epi-wafer can be obtained.

The vertical MOSFET of Example 6 is characterized by an annealing method in the manufacturing method. That is, in the manufacturing method of this example, the element active region and the source electrode 18 are formed on the front surface side of the FZ wafer, the back surface side of the FZ wafer is scraped down to a predetermined thickness, and then the n ⁺ drain layer 11b is removed from the FZ wafer. It is formed by irradiating phosphor or arsenic ion particles from the back of the wafer and irradiating the back of the FZ wafer with light or laser while cooling the FZ wafer. The irradiation energy of phosphorus or arsenic ions may be 1 MeV or less. The dose of phosphorus or arsenic may be 1 × 10 ¹³ cm ⁻² to 1 × 10 ¹⁶ cm ⁻² . The cooling method on the FZ wafer surface side is spraying of a cooling gas or a heat sink.

Since the annealing method is a short-time lamp annealing or laser annealing on the back surface while cooling the FZ wafer surface, the annealing temperature on the back surface is set higher than the melting point of aluminum while ensuring a temperature gradient in the thickness direction of the FZ wafer. A high temperature (700 ° C. or higher) can be set, and even an introduced impurity with a short range can be sufficiently activated. For example, phosphorus or arsenic can be used as a donor impurity. Of course, a low-cost low-impurity concentration FZ wafer can be used, so that the cost of the MOSFET can be reduced. In addition, since an ion implantation method, can set the maximum density point deep, as shown in the vertical direction dependency graph of the doping concentrations appended in FIG. 2, n of the n ⁺ drain layer 11b ^- the drift layer 3b Since the impurity concentration is steep on the boundary side, high characteristics similar to MOSFETs using an epi wafer can be obtained.

  FIG. 3 is a partial sectional view showing a sectional structure of a vertical MOSFET having a trench gate structure according to a third embodiment of the present invention.

The vertical MOSFET having the trench gate structure according to this embodiment is also manufactured using an n-type low impurity concentration FZ wafer forming the n ⁻ drift layer 13b. The difference from the vertical MOSFET according to the second embodiment is in the element active region (core portion). The element active region has a trench gate structure, and includes a p ⁺ base region 24 formed on the surface side of the n ⁻ drift layer 13b, and an n ⁺ source region 25 formed on the surface side of the p ⁺ base region 24. , A gate electrode 27 such as polycrystalline silicon embedded in a trench dug beyond the depth of the p ⁺ base region 24 via a gate oxide film 26, and a source electrode 28 formed via an interlayer insulating film Etc. An n ⁺ drain layer 11b is formed on the outermost surface of the back surface of the FZ wafer, and an aluminum drain electrode 19 is deposited on the n ⁺ drain layer 11b.

  Such a vertical MOSFET having a trench gate structure also employs the same manufacturing method as in the first or second embodiment and exhibits the same effect. However, the trench MOSFET structure has a trench gate structure in the element active region. It is possible to further reduce the on-resistance.

1a, 1b ... n ⁺ cathode layers 3, 3b, 13b ... n ^- drift layer 4 ... p ⁺ anode layer 8 ... anode electrode 9 ... cathode electrode 11b ... n ⁺ drain layers 14, 24 ... p ⁺ base regions 15, 25 ... n ⁺ source regions 16, 26 ... gate oxide films 17, 27 ... gate electrodes 18, 28 ... source electrodes 19, 29 ... drain electrodes

Claims (4)

Using a first conductivity type low impurity concentration substrate forming a first conductivity type low impurity concentration drift layer, an element active region and its first electrode formed on the first main surface side of the substrate, In a method for manufacturing a semiconductor device including a high impurity concentration layer formed on the outermost surface of the second main surface and the second electrode thereof,
The device active region and the first electrode are formed on the first main surface side of the substrate, and the second main surface side of the substrate is scraped down to a predetermined thickness, and then impurity ions are formed from the second main surface. A method of manufacturing a semiconductor device, wherein the high impurity concentration layer is formed by irradiating the second main surface with light or laser while cooling the first main surface. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the impurity ions are phosphorus or arsenic ions. 3. The method for manufacturing a semiconductor device according to claim 2, wherein the irradiation energy of the phosphorus or arsenic ions is 1 MeV or less. 4. The method for manufacturing a semiconductor device according to claim 2, wherein a dose amount of the phosphorus or arsenic is 1 × 10 ¹³ cm ⁻² or more and 1 × 10 ¹⁶ cm ⁻² or less.

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