JP2010118572A - Method of manufacturing semiconductor light-emitting device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a new method of manufacturing a semiconductor light-emitting device having improved light extraction efficiency. <P>SOLUTION: The method of manufacturing the semiconductor light-emitting device includes: a process for preparing members to be treated including semiconductor light-emitting element structures; a process for forming photoresists on the members to be treated; a process for exposing the photoresists; a process for developing the photoresists to form resist patterns; and a process for etching the members to be treated from the top of the resist patterns. The exposure process includes a process for exposing the photoresists via masks where a plurality of light transmission sections are disposed in a lattice shape beyond light-shielding sections, and diffracting light that has transmitted through the light transmission sections so that the distribution of light intensity on the photoresist has a first peak under the light transmission sections and a second one also under the light-shielding sections. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor light emitting device, and more particularly, to a method for manufacturing a semiconductor light emitting device with improved light extraction efficiency.

  In order to improve the light extraction efficiency of a semiconductor light emitting element, a technique for forming a concavo-convex structure in the light emitting element is known (see, for example, Japanese Patent Application Laid-Open Nos. 2005-150261 and 2007-0336240). The uneven structure is formed, for example, on the back surface of the growth substrate, on the grown semiconductor layer, or on the transparent conductive film.

  A large number of light emitting elements are simultaneously formed on the growth substrate, and then individually divided, and each light emitting element is mounted on a support substrate. When the light emitting element is divided or mounted on the support substrate, defects such as cracks are likely to occur due to the uneven structure.

  6A and 6B are schematic cross-sectional views showing a state in which the light emitting element is mounted on the support with a collet.

  FIG. 6A shows a case where the concavo-convex structure 102 has a serrated cross section and has a trough 102A sharpened in a V shape. The light emitting element is sucked and lifted by the suction hole 101A of the collet 101, and the light emitting element is moved onto the support. When mounted on the support, the tip of the collet 101 presses the light emitting element against the support, and pressure is applied to the concavo-convex structure 102. Stress tends to concentrate on the sharp bottom of the valley 102A, and cracks are particularly likely to occur. In the figure, arrows on the concavo-convex structure indicate the direction of force.

  FIG. 6B shows a case where the concavo-convex structure 103 has a gentle wavy cross section and a U-shaped valley 103A. Compared to the sharp valley 102A as shown in FIG. 6A, when mounting with the collet 101, stress is less likely to concentrate on the bottom of the valley 103A, and the generation of cracks is suppressed.

  In particular, when a blue light emitting diode using a GaN-based material is taken as an example, a heterogeneous substrate such as sapphire, SiC, or Si may be used as a growth substrate. When a heterogeneous substrate is used, stress is generated in the direction in which the epi-wafer warps due to the difference in thermal expansion coefficient and lattice constant between the substrate material and the GaN-based material to be grown.

  FIG. 6C is a schematic cross-sectional view showing an epi wafer in which a GaN-based semiconductor layer 112 is formed on a sapphire substrate 111. A shrinkage stress 113 is generated in the GaN-based semiconductor layer 112, and the epi-wafer is warped in a shape in which the back surface 114 of the sapphire substrate 111 is convex. When the collet is brought into contact with the warped epiwafer from the back side of the sapphire substrate 111 and the pressure 115 is applied, cracks and cracks are likely to occur in the concentration region 116 of the shrinkage stress 113 and the pressure 115.

  Here, in the example shown in FIG. 6C, the growth substrate is thinned by grinding and polishing to a thickness of 70 μm to 90 μm so that it can be easily divided after element growth and before element division. Usually, the growth substrate has a thickness of 400 μm to 500 μm, and immediately after the growth, the wafer is almost flat or slightly warped in the opposite direction to FIG. 6C.

  In recent years, semiconductor light emitting devices having a chip size as large as 1 mm × 1 mm have been increasing in order to achieve higher output. Even in such an element having a large size, the structure of the semiconductor layer is almost the same as that in the prior art, so the thickness of the element is almost the same as that in the prior art, and the displacement due to warpage is likely to increase, and cracks and cracks are likely to occur.

JP 2005-150261 A Japanese Patent Laid-Open No. 2007-036240

  An object of the present invention is to provide a novel method for manufacturing a semiconductor light emitting device in which light extraction efficiency is improved.

  Another object of the present invention is to provide a method for manufacturing a semiconductor light emitting device in which light extraction efficiency is improved and generation of cracks and the like is suppressed.

  According to one aspect of the present invention, (a) a step of preparing a processing target member including a semiconductor light emitting element structure, (b) a step of forming a photoresist on the processing target member, and (c) the photoresist (D) developing the photoresist to form a resist pattern; and (e) etching the member to be processed from above the resist pattern. (C) exposing the photoresist through a mask in which a plurality of light-transmitting portions are arranged in a grid pattern with a light-shielding portion interposed therebetween, and the light intensity distribution on the photoresist is exposed under the light-transmitting portions. There is provided a method for manufacturing a semiconductor light emitting device including a step of diffracting light transmitted through a light transmitting part so as to have a peak of 1 and also have a second peak under a light shielding part.

  By performing exposure such that diffracted light travels under the light-shielding portion of the mask and a peak of the light intensity distribution is generated also under the light-shielding portion, in the resist pattern, for example, a depression Can be made. The light extraction efficiency can be improved by transferring the concavo-convex shape formed in the resist pattern to the member to be processed.

  A method for manufacturing a semiconductor light emitting device according to an embodiment of the present invention will be described with reference to FIGS. 1A to 1I are schematic cross-sectional views of a semiconductor light emitting device of an example. A large number of light emitting elements are simultaneously formed on a single substrate, and are divided into individual light emitting elements by a chip forming process. 1A to 1G show a process before dividing an element, but only one element is shown.

First, a semiconductor light emitting element will be described with reference to FIG. 1A. On the C + face (Ga face) of the GaN substrate 1, a semiconductor layer 5 composed of a stack of an n-type semiconductor layer 2, an active layer 3, and a p-type semiconductor layer 4 is formed. The n-type semiconductor layer 2, the active layer 3, and the p-type semiconductor layer 4 are nitrides represented by Al _x In _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1), respectively. A semiconductor, for example, grown by metal organic chemical vapor deposition (MOCVD). The n-type semiconductor layer 2 is doped with an n-type dopant such as Si, and the p-type semiconductor layer 4 is doped with a p-type dopant such as Mg. The composition of the semiconductor layer 5 of the example is selected so that the emission wavelength is blue.

  The configuration of the semiconductor layer 5 is not limited to this. For example, in order to improve the light emission efficiency, a current diffusion layer, a clad layer, a contact layer, or the like can be inserted as necessary. Furthermore, the structure which makes the active layer 3 a multilayer film (multiple quantum well structure) is also considered.

  After the semiconductor layer 5 is formed on the GaN substrate 1, the semiconductor layer 5 is etched to a depth at which the n-type semiconductor layer 2 is exposed by wet etching or dry etching. An n-side ohmic electrode 6 is formed on the exposed n-type semiconductor layer 2. The n-side ohmic electrode 6 is formed of, for example, any one of TiAl, AlRh, Pt, and Au, and is formed through a photolithography process and a vapor deposition process.

  Next, the p-side ohmic electrode 7 is formed on the p-type semiconductor layer 4. For example, the p-side ohmic electrode 7 includes, in order from the semiconductor layer side, an indium tin oxide (ITO) layer for ohmic contact, a NiAg layer for light reflection, and an AuSn layer for bonding to a support. It is a laminated multilayer electrode, which is formed through a photolithography process and a vapor deposition process.

  Next, as shown in FIG. 1B, the light emitting element is fixed to the sample holder 11. The p-side ohmic electrode 7 side is fixed to the sample holder 11 by the fixing wax 12, and the C-plane (N plane) which is the back surface of the GaN substrate 1 is exposed.

  Next, the GaN substrate 1 is ground and polished from the back surface, and is preferably thinned to a thickness of 260 μm or less. As the polished surface becomes a mirror surface, the yield in the subsequent chip forming process is improved. After polishing, the fixing wax 12 is removed. The fixing wax 12 can be easily wiped off by heating and an organic solvent.

  Next, as shown in FIG. 1C, a photoresist agent 21 is applied on the back surface of the GaN substrate 1. The photoresist agent 21 is, for example, AZ6130 (62 cp) manufactured by AZ Electronic Materials. The photoresist agent 21 is spin-coated at 3000 rpm, for example, and uniformly applied on the GaN substrate 1 and then dried at 90 ° C. for 1 minute, for example. The resist film thickness at this time is, for example, 3 μm.

  The resist film thickness is preferably adjusted to a range of about 2 μm to 6 μm. If the thickness is less than this range, sufficient resist does not remain after development, and a desired curved surface shape cannot be obtained in the subsequent uneven processing, or a sufficient height difference of the uneven shape cannot be obtained. On the other hand, if it is thicker than this range, a resist pool is generated at the edge of the substrate, and the resist remains after the subsequent uneven processing step.

  Next, as shown in FIG. 1D, the photoresist agent 21 is exposed through the mask 22 in which the openings 23 are formed. The photoresist agent 21 is exposed with the light intensity distribution generated by the mask 22. After the exposure, for example, the reaction of the resist in the exposed portion is promoted by heating at 110 ° C. for 1 minute on a hot plate (post-exposure baking).

  Next, as shown in FIG. 1E, the photoresist agent 21 is developed. The development is performed by immersing in a developer, for example, AZ600MIF manufactured by AZ Electronic Materials, for 60 seconds, for example. After development, for example, the resist shape is fixed by heating at 115 ° C. for 2 minutes on a hot plate (post-development baking). In this way, a resist pattern 26 having a concavo-convex structure corresponding to the exposure intensity distribution is formed.

  Here, the exposure process will be described in detail.

  FIG. 2 is a photograph showing the mask of the example. Openings are arranged on lattice points of a regular triangular lattice (openings are arranged in a close-packed structure). The openings have a circular shape with a diameter of 3 μm, and the center distance between adjacent openings (referred to as an opening pitch) is 5 μm.

  FIG. 3A is a schematic sectional view of the photoresist agent 21 and the mask 22. The cross section of the mask 22 is shown along the direction in which the openings 23 are arranged at the opening pitch. The lower surface of the mask 22 and the upper surface of the photoresist agent 21 are arranged in parallel with an exposure gap L therebetween. The exposure light 25 having a substantially uniform light intensity distribution enters the mask 22.

  The diameter of the opening 23 is a, and the opening pitch is b. The distance from the center 27 of the light shielding part 24 between the adjacent openings 23 (hereinafter also referred to as the center 27 between adjacent openings) to the center of the opening 23 in the direction in which the openings 23 are arranged at the opening pitch. Becomes b / 2.

  The exposure intensity on the surface of the photoresist agent 21 with respect to the light transmitted through one opening 23 will be described. When the diameter a of the opening 23 is sufficiently small and an appropriate exposure gap L is ensured, the exposure intensity distribution D1 below the opening 23 gradually decreases from the center toward the bottom due to the diffraction phenomenon. It becomes a bell shape. Further, the light intensity distribution D2 of the diffracted light having the same bell shape appears in the direction of the diffraction angle θ according to the following equation (1).

θ = 1.83 (λ / a) (1)
Here, a is the diameter of the opening 23 and λ is the exposure wavelength.

When the peak position of the light intensity distribution D2 of the diffracted light diffracted at the opening 23 is represented by a distance x from the center of the opening 23, the diffraction position x is expressed by the exposure gap L and the diffraction angle θ.
x = Ltanθ (2)
It is expressed. Therefore, the diffraction position x on the photoresist agent 21 can be adjusted by the exposure gap L.

The diffraction position x is arranged below the center 27 between adjacent openings, that is, n is an odd number.
x = n × (b / 2) (n = 1, 3, 5, 7,...) (3)
The exposure gap L can be adjusted so that

  In the embodiment, n = 3 (x = 3/2 × b), and the diffraction position x is arranged below the center 27 between the adjacent openings of the light shielding part 24 adjacent to the opening 23.

Summarizing the exposure conditions of the example, a mask in which openings having a diameter a = 3 μm are arranged in a close-packed structure with an opening pitch b = 5 μm, an exposure wavelength λ = 230 nm, n = 3, and an exposure gap L = about The exposure amount on the mask was 58 mJ / cm ² .

  FIG. 4 is a schematic plan view of the photoresist agent 21 and the mask 22. The light intensity distribution obtained by superimposing the diffracted lights of the openings 23 will be described. With respect to a certain center 27a between adjacent openings, two openings satisfying the relationship of n = 3 are the opening 23a1 and the opening 23a2 disposed on the opposite side of the opening 23a1 with respect to the center 27a. A circle having a radius of 3/2 × b centered on the center of these openings is indicated by a broken line. On these circles, the peaks of the diffracted light by the openings 23a1 and 23a2 are located. At the center 27a between adjacent openings, the peaks of the diffracted light are superimposed.

  Three openings 23 close to each other define a unit cell 29 of an equilateral triangle having one side b. A unit cell center 28 that is the center of the unit cell 29 is defined. The center 27a between adjacent openings is located at the center of one side of a certain unit cell 29a. The distance from the unit cell center 28a of the unit cell 29a to the centers of the openings 23a1 and 23a2 is approximated by 3/2 × b. Therefore, it can be considered that the peak of the diffracted light from the openings 23a1 and 23a2 overlaps even at the unit cell center 28a. Note that this approximation becomes more accurate as n in equation (3) increases.

  At the center 27b between the adjacent openings located at the center of one of the other two sides of the unit cell 29a, the peak of the diffracted light from the openings 23b1 and 23b2 overlaps and is positioned at the other center of the other two sides of the unit cell 29a. At the center 27c between adjacent openings, the peaks of diffracted light from the openings 23c1 and 23c2 overlap. The distances from the unit cell center 28a to the centers of the openings 23b1, 23b2, 23c1, and 23c2 are also approximated by 3/2 × b, respectively.

  From the above, at the unit cell center 28a, it can be considered that the peaks of the six diffracted lights from the openings 23a1, 23a2, 23b1, 23b2, 23c1, and 23c2 overlap (this is illustrated in FIG. 4 with these six openings as the center. This corresponds to the fact that the six circumferences of radius 3/2 × b indicated by broken lines almost overlap at the unit cell center 28a). Note that the number 6 of diffracted lights overlapping at the unit grating center 28a is derived by multiplying the number 2 of diffracted lights overlapping at the center 27 between adjacent openings by the three-fold symmetry 3 of the triangular lattice arrangement. it can.

  FIG. 3B is a graph schematically showing the exposure intensity distribution D3 on the surface of the photoresist agent 21. The light intensity distribution D31 near the center of the opening 23 and the vicinity of the unit cell center 28 (each diffracted light overlaps). The combined light intensity distribution D32 is shown one-dimensionally. Both distributions D31 and D32 have a gentle shape.

  In the embodiment, as a result of development, the photoresist agent 21 is removed at a position where the light intensity is higher, and a resist pattern is formed with a concavo-convex shape D4 in which peaks and valleys of the light intensity distribution D3 are inverted.

  As described above, at the unit cell center 28 (below the light shielding portion 24), the peaks of the diffracted light from the six openings 23 are superimposed. The peak intensity of the diffracted light distribution D32 superimposed under the light shielding part 24 is approximately the same as the peak intensity of the distribution D31 under the opening (translucent part) 23 (range of 0.8 to 1.2 times). It is particularly preferable (see also FIG. 5A, FIG. 5B, and FIG. 5C described later and the description thereof).

  Under the exposure conditions of the examples, the peak intensity under the light shielding part and the peak intensity under the opening part are considered to be approximately the same (see FIG. 5A described later). Therefore, it is estimated that the peak intensity of each diffracted light superimposed under the light-shielding part is about 1/6 of the peak intensity of the opening. The ratio between the peak intensity of the opening and the peak intensity of each diffracted light can be experimentally adjusted by appropriately adjusting the opening diameter a, the exposure gap L, the exposure wavelength λ, and the like.

  FIG. 5A is a scanning probe microscope (SPM) image showing the concavo-convex structure of the resist pattern obtained under such conditions.

  A recess is formed below the opening of the mask, and a recess having the same size and depth as the recess of the opening is formed below the light-shielding portion (in the center of the unit cell). Corresponding to the fact that one opening of the mask is surrounded by six unit cells, six recesses below the light shielding part are arranged adjacent to one recess below the opening. Corresponding to the gently changing exposure intensity distribution, the uneven shape on the resist pattern is also a gently curved surface.

  By performing post-development baking, the slope of the slope connecting the concave portion and the convex portion is distributed at an angle of 52 ° to 64 ° with respect to the back surface of the substrate. If the post-development baking temperature is 90 ° C. to 120 ° C., an angle range of 52 ° to 64 ° is obtained, and the processing time is not significantly affected. The higher the post-development baking temperature, the smaller the slope of the slope connecting the concave and convex portions (close to the horizontal). This angle range is known as the angle at which light from the active layer is most efficiently emitted outside the device when the light emitting device is sealed with resin. By performing post-exposure baking, the angle reproducibility of the slope connecting the concave and convex portions on the resist pattern formed by post-development baking is improved.

Returning to FIG. 1F, the description will be continued. Next, a concavo-convex processing step for transferring the concavo-convex structure on the resist pattern 26 to the underlying GaN substrate 1 by anisotropic etching is performed. For example, dry etching such as reactive ion etching (RIE) is used. Etching is performed by the RIE apparatus 31 under the process conditions of, for example, a degree of vacuum of 1 Pa, an etching gas Cl ₂ flow rate of 20 sccm, and an applied voltage of 50 W to 100 W.

  By etching from above the resist pattern 26 until the GaN substrate 1 is exposed on the entire surface, the concavo-convex structure of the resist pattern 26 is transferred to the back surface of the GaN substrate 1. In order to smooth the surface of the concavo-convex structure formed on the GaN substrate 1, Si may be contained in the plasma atmosphere in dry etching. This is due to the effect that the etching surface becomes smooth because Si in the plasma atmosphere adheres to the object to be etched and the etching rate decreases.

In the concavo-convex structure formed on the GaN substrate 1, it is preferable that the base of the convex part is about 1 μm to 6 μm (interval between adjacent concave parts), and the height of the convex part with respect to the bottom of the concave part is 0. It is preferable that it is about 6 micrometers-5.6 micrometers. As a reactive gas for dry etching, a known reactive gas such as BCl ₃ containing chlorine can be used in addition to Cl ₂ .

  FIG. 1G shows a light emitting device in which a concavo-convex structure is formed on the GaN substrate 1.

  Next, as shown in FIG. 1H, a chip forming process is performed in which the light-emitting element having a concavo-convex structure formed on the GaN substrate 1 is divided into individual light-emitting elements. The element can be divided by a known method such as scribing and breaking.

  Next, as shown in FIG. 1I, the light emitting element is formed by the collet 43 of the eutectic bonder device so that the n-side ohmic electrode 6 and the p-side ohmic electrode 7 are arranged on the corresponding junction electrodes 42. Flip chip bonding is performed on the support substrate 41.

  In order to reduce defects after bonding, the bonding pressure (load) is adjusted so that the bonding strength by die shear measurement is 50N. The bonding pressure is preferably 300 mN to 500 mN / chip. If the bonding pressure is too high, the eutectic member protrudes from the installation portion, and problems such as leakage or short circuit occur. In this manner, the semiconductor light emitting device of the example is manufactured.

  As described above, in the method for manufacturing the semiconductor light emitting device of the embodiment, a resist pattern having a gentle curved concavo-convex shape can be easily formed by exposure using diffraction.

  Etching is performed using such a resist pattern as a mask, and the concavo-convex structure of the resist pattern can be transferred to the surface of the light emitting element. The light extraction efficiency can be improved by the uneven structure on the surface of the light emitting element.

  When the light emitting element is bonded to the support substrate, the contact surface with the collet has a gently curved uneven structure, so that, for example, the bonding pressure is dispersed and cracks are reduced compared to a serrated uneven structure. Generation etc. are suppressed. The junction yield can be improved.

  In the examples, the resist pattern and the concavo-convex structure were formed on the back surface of the substrate on which the light-emitting element was formed. However, if the photoresist is coated and etched, the resist pattern is formed in another place, A structure can be formed. For example, the uppermost surface of the semiconductor layer grown on the substrate, the surface of the transparent electrode, and the like. Thereby, the freedom degree of design of a semiconductor light-emitting device improves.

  Exposure is performed by diffracting the light transmitted through the opening so that the peak of the light intensity distribution also occurs under the light shielding portion of the mask. As a result, a concavo-convex structure can be formed under the light-shielding portion, so that it is not necessary to make the opening structure of the mask fine, and exposure is facilitated. It becomes easy to form the uneven structure densely, and the light extraction efficiency is improved.

  In the example, n = 3 was selected in the formula (3). Hereinafter, the reason why n = 3 is selected in the embodiment will be described.

  When n = 1, the exposure gap between the mask and the photoresist agent is narrower than when n = 3. If the exposure gap is too narrow, only the opening is exposed almost uniformly, and the light-shielding portion is close to non-exposure. Since the light intensity changes sharply at the boundary between the exposed area and the non-exposed area, the height of the resist pattern changes sharply at the boundary between the concave and convex portions, the number of flat portions increases, and the surface has a gentle curved surface. It becomes difficult to obtain a structure. When the flat portion increases in the resist pattern, the total reflection component increases, which is not preferable from the viewpoint of improving the light extraction efficiency.

  Further, when only the opening is exposed, the uneven structure is not densely formed. Furthermore, when n is small, the above-mentioned approximation accuracy is not good.

  On the other hand, when n = 5 (or more), the exposure gap is wider than when n = 3. If the exposure gap is too wide, the peak intensity of the diffracted light becomes small and broad. As a result, even if the diffraction peaks are overlapped, it is difficult to make the peak intensity under the light shielding portion comparable to the peak intensity under the opening, and the (for example) concave portion under the light shielding portion becomes shallow.

  In the example, n = 3 was an appropriate exposure gap. The exposure gap may not strictly satisfy n = 3 (in FIG. 3A, the diffraction position x is arranged below the center of the light shielding portion adjacent to the opening portion two times).

  5B and 5C are SPM images showing the concavo-convex structure of the resist pattern of the modified example in which the exposure gap is shifted from about 50 μm of the above embodiment to be 30 μm and 70 μm, respectively. In the case of FIG. 5B and FIG. 5C as well, the diffracted light is irradiated under the light-shielding portion to form a recess. However, compared to the case of FIG. 5A in which the exposure gap is 50 μm, the intensity of diffracted light under the light-shielding portion is weak, the uniformity of the concave shape of the opening and the light-shielding portion is lowered, and the smoothness of the uneven shape is lowered. ing.

  Note that the resist pattern of FIG. 5A, which has a more uniform recess shape of the opening and the light-shielding portion, has a larger contact area with the collet during die bonding than the resist pattern of FIGS. 5B and 5C. It is particularly preferable for improving the yield.

From Expressions (1) to (3), the exposure gap L is defined as λ is the exposure wavelength, a is the diameter of the opening, and b is the pitch between adjacent openings.
L = [n × b / 2] / [tan (1.83λ / a)] (4)
It is expressed. Under the conditions of the above embodiment (a = 3 μm, b = 5 μm, λ = 230 nm), the exposure gaps L of n = 2, 3, and 4 are 35 μm, 53 μm, and 71 μm, respectively. 5B and 5C generally correspond to n = 2 and n = 4, and 2 <n <4 is a preferable condition for exposure.

  In general, 2 <n <4 can be regarded as a condition in which the peak of the light intensity distribution of the diffracted light is arranged in the light shielding portion adjacent to the opening in FIG. 3A. Note that it is more preferable that n <3, for example, 2.5 <n <3.5.

  In the above embodiment, the openings of the mask are arranged in a regular triangular lattice (closest-packed structure), but the arrangement of the openings is not limited to this. For example, a mask in which openings are periodically arranged in a lattice shape such as a square lattice can be used. The opening shape is not limited to a circle, and may be a polygon, for example.

  Considering the same consideration as FIG. 4, in the case of a square lattice, a square defined by four adjacent openings is a unit lattice. Since the square lattice is four-fold symmetric, the peaks of the diffracted light from the eight openings are superimposed at the center of the unit lattice. For light transmitted through one opening, the peak intensity of diffracted light at the center between adjacent openings is preferably about 1/8 of the peak intensity immediately below the opening (see FIG. 3A). .

  Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

1A and 1B are schematic cross-sectional views showing a manufacturing process of a semiconductor light emitting device according to an embodiment of the present invention. 1C to 1E are schematic cross-sectional views illustrating manufacturing steps of the semiconductor light emitting device of the example, following FIGS. 1A and 1B. 1F and FIG. 1G are schematic cross-sectional views illustrating manufacturing steps of the semiconductor light emitting device of the example, following FIGS. 1C to 1E. 1H and FIG. 1I are schematic cross-sectional views showing manufacturing steps of the semiconductor light emitting device of the example, following FIG. 1F and FIG. 1G. FIG. 2 is a photograph showing the mask of the example. 3A and 3B are schematic cross-sectional views of a mask and a photoresist agent for explaining the exposure conditions of the embodiment. FIG. 4 is a schematic plan view of a mask and a photoresist agent for explaining the exposure conditions of the embodiment. FIG. 5A to FIG. 5C are SPM images of resist patterns according to examples and modifications thereof. 6A and 6B are schematic cross-sectional views showing the concavo-convex structure of the light-emitting element adsorbed on the collet, and FIG. 6C is a schematic cross-sectional view showing an epi-wafer in which a GaN-based semiconductor layer is formed on a sapphire substrate.

Explanation of symbols

1 substrate 2 n-type semiconductor layer 3 active layer 4 p-type semiconductor layer 5 semiconductor layer 6 n-side ohmic electrode 7 p-side ohmic electrode 21 photoresist agent 22 mask 23 opening 24 light-shielding portion 25 exposure light 26 resist pattern 41 support substrate 42 Joining electrode 43 Collet

Claims (6)

(A) preparing a processing target member including a semiconductor light emitting element structure;
(B) forming a photoresist on the workpiece;
(C) exposing the photoresist;
(D) developing the photoresist to form a resist pattern;
(E) etching the member to be processed from above the resist pattern,
In the step (c), the photoresist is exposed through a mask in which a plurality of light-transmitting portions are arranged in a grid pattern with a light-shielding portion interposed therebetween, and the light intensity distribution on the photoresist is below the light-transmitting portions. A method of manufacturing a semiconductor light emitting device, comprising: diffracting light transmitted through the light transmitting portion so as to have a first peak and a second peak below the light shielding portion.   2. The method of manufacturing a semiconductor light emitting device according to claim 1, wherein in the step (c), the intensity of the second peak is in a range of 0.8 to 1.2 times the intensity of the first peak. Method. In the step (c), an exposure gap L between the mask and the photoresist, λ is an exposure wavelength, a is a diameter of the light transmitting portion, and b is a pitch between centers of adjacent light transmitting portions,
L = [n × b / 2] / [tan (1.83λ / a)]
The method for manufacturing a semiconductor light emitting device according to claim 1, wherein n is selected so that 2 <n <4.   In the step (c), the diameter of the light transmitting part is arranged such that the diffraction position of the diffracted light of the light transmitting part on the photoresist is arranged below the center of the light shielding part between the adjacent light transmitting parts. And a method for manufacturing a semiconductor light emitting device according to claim 1, wherein an exposure gap between the mask and the photoresist is defined.   5. The method of manufacturing a semiconductor light emitting device according to claim 1, wherein in the step (c), the light transmitting portions of the mask are arranged in a regular triangular lattice shape.   The said process (b) forms the said photoresist on the back surface on the opposite side to this light emitting element structure of the board | substrate with which the semiconductor light emitting element structure is formed of the said process target member. 2. A method for manufacturing a semiconductor light emitting device according to item 1.