JP2010114710A - Electronic circuit, electronic device equipped with the same, and pulse detection method of electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a simple and highly stable square detection circuit. <P>SOLUTION: An electronic circuit 1 includes a signal output part 120 containing a first field effect transistor 103 in which one end of the balanced signal is connected to a gate terminal with a source terminal being grounded, a second field effect transistor 104 in which the other end of the balanced signal is connected to a gate terminal with a source terminal being grounded, a third field effect transistor 113 in which a source terminal is connected to a drain terminal of the first field effect transistor 103 with a gate terminal being biased to a first potential, a fourth field effect transistor 114 in which a source terminal is connected to a drain terminal of the second field effect transistor 104 with a gate terminal being biased to the first potential, and an output line for outputting an output signal by connecting the drain terminal of the third field effect transistor 113 to the drain terminal of the fourth field effect transistor 114. It also includes a signal addition part 121 which is connected to an output line 115 of the signal output part 120. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an electronic circuit, an electronic device including the electronic circuit, and more particularly to an electronic device that receives a UWB (Ultra Wide Band) signal and a pulse detection method for the electronic device.

  A circuit for detecting an envelope of a received signal and demodulating a baseband signal has been used for a long time, and various circuits have been devised. The envelope is obtained by connecting the peak values of the signal, and is obtained by smoothing the absolute value of the AC component. A method of squaring and smoothing a signal and replacing it with envelope detection has also been called “square detection”. For example, Patent Document 1 describes a square detection circuit for obtaining a square value of a signal and an amplitude detection method using the square detection circuit.

  In addition, there is a receiver using envelope detection in UWB signal, particularly UWB communication (hereinafter referred to as “UWB-IR” communication) using IR (Impulse Radio) that does not use a carrier wave, for example, Patent Document 2 or Patent Document 3 Describes its effectiveness. In these Patent Documents 2 and 3, a rectifier circuit and an integrating circuit are used, which obtains an envelope by smoothing the absolute value of the AC component of the signal. Hereinafter, the operation of detecting the envelope of a modulated carrier wave (a high-frequency signal whose amplitude changes with time) will be referred to as “envelope detection”. In addition, there is no example using the square wave detection in the UWB-IR receiver.

JP-A-4-170807 JP 2004-320083 A JP 2005-252740 A

  However, the conventional square detection circuit of Patent Document 1 uses bipolar transistors and does not use MOS transistors suitable for large-scale integration. Further, the square characteristic can be obtained approximately only when a small signal whose signal current change is sufficiently small compared to the collector current is input, and there is a problem that an error occurs with a large signal. When trying to handle a large signal, the power consumption inevitably increases. Furthermore, the operation speed of the circuit is not so fast, and it is not suitable for handling a signal having a frequency as high as the performance limit of an element such as a UWB-IR signal. In addition, when there is no function for obtaining the sum of squares of a plurality of signals and demodulation is performed down to baseband by frequency conversion, highly accurate phase synchronization is required.

As is well known, the drain current of a field effect transistor is proportional to the square of the difference between the gate voltage and the threshold voltage when the operating region is in the saturation region. In other words, the relationship between the drain current Id and the gate voltage Vg is as follows.
Id = (1/2) β (Vg−Vt) ² (Formula 1)
It becomes.

Therefore, it is possible to obtain the square value of the signal using the relationship of (Equation 1) of the field effect transistor. That is, if the input signal vi is biased with Vb and adjusted so that Vb = Vt,
Id = (1/2) β (Vb + vi−Vt) ² = (1/2) vi ² (Equation 2)
Thus, the square value of the input signal can be obtained.

However, in this case, it is difficult to stably bias so that Vb = Vt. If Vb ≠ Vt,
Id = (1/2) vi ² + vi (Vb−Vt) + (1/2) (Vb−Vt) ² (Equation 3)
Thus, vi (Vb−Vt) and (½) (Vb−Vt) ² in (Equation 3) are errors. Since (1/2) (Vb−Vt) ² is a direct current component, it can be easily eliminated by a capacitor, but vi (Vb−Vt) is difficult to remove.

  In addition, Vt is difficult to know an accurate value due to the presence of a minute current that does not follow (Equation 1) called tailing or the like, and also changes with changes in temperature and power supply voltage. Further, at the bias point where Vb = Vt, if Id is an extremely small operation region and the input signal is very small, the operation becomes extremely unstable.

  As in the electronic circuit 13 shown in FIG. 13, there is a conventional technique for removing the error by using two field effect transistors 1303 and 1304. That is, the input signal vi input to the terminal 1301 is converted into two signals ± vi having the same absolute value and opposite polarity by a balun (BALUN: Balance-Unbalance converter) 1302, and the field effect transistors 1303 and 1304. Apply to the gate.

At this time, if the drain current of the field effect transistor 1303 is Id1, and the drain current of the field effect transistor 1304 is Id2,
Id1 = (1/2) β (Vb + vi−Vt) ² (Formula 4)
Id2 = (1/2) β (Vb−vi−Vt) ² (Formula 5)
Holds. Here, Vb is a value of a bias voltage applied from the power source 1309 to the gates of the field effect transistors 1303 and 1304 through the resistors 1307 and 1308.

Therefore, the current I0 flowing through the resistor 1310 is
I0 = Id1 + Id2 = β {vi ² + (Vb−Vt) ² } (Formula 6)
It becomes.

(Vb−Vt) ^{2 on} the right side of (Expression 6) is a DC component, and the square value of the input signal vi can be extracted by extracting only the change. In the conventional technique according to (Expression 1), vi (Vb−Vt) remains as an error in addition to the DC component, but the conventional electronic circuit 13 according to (Expression 6) includes such an error that cannot be excluded. Absent. Therefore, the bias voltage Vb does not need to be exactly equal to the threshold voltage Vt as in the conventional example.

However, the above (Equation 1) or (Equation 4) and (Equation 5) are first-order approximation equations, and do not actually exhibit constant current characteristics due to a phenomenon called channel length modulation of a field effect transistor. Changes. That is, (Equation 1) must be rewritten as (Equation 7) in consideration of this effect.
Id = (1/2) β (Vg−Vt) ² (1 + λVd) (Expression 7)

  In (Expression 7), Vd is a drain voltage viewed from the source of the field effect transistor, and λ is a constant called a channel modulation coefficient. This λ appears to have a resistance (drain resistance) connected in parallel between the source and drain of the field effect transistor. Part of Id1 in (Equation 6) flows into the drain resistance of the field effect transistor 1304, and part of Id2 flows into the drain resistance of the field effect transistor 1303, so that a signal component flowing out to the resistor 1310 is generated. It will be reduced. In particular, with the recent miniaturization of integrated circuit elements, the value of λ tends to increase, and this problem is serious.

  Neither Patent Document 2 nor Patent Document 3 discloses a fundamental proposal for UWB-IR communication, and various problems and solutions that are unavoidable to overcome in actual implementation. Is not disclosed at all.

  The problem with the prior art is that an envelope detection circuit that functions effectively for high-frequency signals (steep and instantaneous pulses) as applied to UWB-IR communication cannot be realized.

  Patent Document 2 exemplifies a circuit example using an envelope detection circuit including an operational amplifier circuit and a PN junction diode. However, it is difficult for a circuit using a PN junction diode to be on-chip by a CMOS semiconductor process frequently used in one-chip UWB analog front ends. It is almost impossible to detect the envelope by rectification.

  In UWB, high frequency that reaches the limit of device performance is used, whereas the maximum operable speed of the operational amplifier circuit is a fraction of the limit frequency of device performance, and the operation speed is absolutely insufficient. is there. Furthermore, this type of conventional full-wave rectifier circuit does not operate well unless the input signal is sufficiently large compared to the signal level received by the receiver. It is almost impossible to detect a signal with a peak value of about several mV obtained by amplifying a received signal obtained from an antenna with a pre-low noise amplifier circuit, and measures such as increasing the amplification factor of pre-amplification are available. Although necessary, this also involves difficulties such as high frequency, system complexity, and increased power consumption.

  The present invention has been made to solve the above-described problems, and can be realized as the following forms or application examples.

[Application Example 1]
A first field effect transistor having one of the balanced signals connected to the gate terminal and the source terminal grounded, and a second electric field having the other one connected to the gate terminal grounded and the source terminal grounded An effect transistor; a third field effect transistor having a source terminal connected to a drain terminal of the first field effect transistor and a gate terminal biased to a first potential; and the second field effect transistor. A fourth field effect transistor having a source terminal connected to the drain terminal of the transistor and a gate terminal biased to the first potential; the drain terminal of the third field effect transistor; and the fourth field effect. And n (n is an integer equal to or greater than 1) signal output units configured to include an output line for connecting the drain terminal of the transistor and outputting an output signal; A signal adder connected to each of the output lines of the n signal output units and outputting a signal proportional to the sum of the output signals output from the output lines of the n signal output units; The electronic circuit characterized by including.

  According to this configuration, a signal proportional to the square of the signal input to the gate can be taken out by the square characteristic of the field effect transistor. The electronic circuit is composed of a field effect transistor and does not use a PN junction, and can be on-chip by a normal CMOS semiconductor process. The third and fourth field effect transistors can also prevent the above-described problem that the drain currents of the first and second field effect transistors flow into each other's drain resistance. The circuit configuration is extremely simple, and furthermore, high-frequency and high-speed operation of the limit frequency of the MOS transistor is possible, and application to a system that requires high-speed operation such as IR communication becomes possible. In addition, a square circuit that can be easily integrated can be realized.

[Application Example 2]
The electronic circuit according to the above, wherein the signal adding unit includes a field effect transistor whose gate terminal is biased to the second potential.

  According to this configuration, a small change in current can be obtained as a large voltage signal with a small voltage drop by the high small signal channel resistance characteristic of the field effect transistor biased to a second potential different from the first potential. .

[Application Example 3]
A first field effect transistor having a gate terminal biased to a first potential and a source terminal connected to one of the balanced signals; a gate terminal biased to the first potential; and a source terminal receiving the balanced signal A second field effect transistor to which the other one is connected; and a third field effect in which a source terminal is connected to a drain terminal of the first field effect transistor and a gate terminal is biased to a second potential. A fourth field effect transistor having a source terminal connected to the drain terminal of the second field effect transistor and a gate terminal biased to the second potential, and the third field effect transistor. An output line for connecting the drain terminal of the transistor and the drain terminal of the fourth field effect transistor to output an output signal. (N is an integer of 1 or more) signal output units and the output lines connected to the output lines of the n signal output units and output from the output lines of the n signal output units An electronic circuit comprising: a signal adding unit that outputs a signal proportional to the sum of the signals.

  According to this configuration, a signal proportional to the square of the signal input to the source can be extracted by the square characteristic of the grounded gate circuit using the field effect transistor. The grounded gate circuit can constitute an amplifier circuit having a good frequency characteristic with a low input impedance and a high output impedance. The third and fourth field effect transistors can also prevent the above-described problem that the drain currents of the first and second field effect transistors flow into each other's drain resistance. The electronic circuit is composed of a field effect transistor and does not use a PN junction, and thus can be formed on-chip by a normal CMOS semiconductor process. The circuit configuration is extremely simple, and furthermore, high-frequency and high-speed operation of the limit frequency of the MOS transistor is possible, and application to a system that requires high-speed operation such as UWB-IR communication becomes possible. In addition, a square circuit that can be easily integrated can be realized.

[Application Example 4]
The electronic circuit according to the above, wherein the signal addition unit includes a field effect transistor whose gate terminal is biased to a third potential.

  According to this configuration, a small change in current can be obtained as a large voltage signal with a small voltage drop by the high small signal channel resistance characteristic of the field effect transistor biased to a second potential different from the first potential. .

[Application Example 5]
An electronic device comprising the electronic circuit described above.

  According to this configuration, the square value of the signal can be easily detected by the electronic circuit. In addition, a simple and low-power electronic device such as a receiving device using square detection can be realized.

[Application Example 6]
In the electronic device described above, the electronic device includes a signal processing unit that detects a pulse carried by a supplied UWB signal.

  According to this configuration, the square value of the signal can be easily detected by the electronic circuit. In particular, a simple and low-power electronic device can be realized by a receiving device that detects a pulse carried by a UWB signal.

[Application Example 7]
In the electronic device described above, the electronic device has a template signal generation unit that generates first and second signals orthogonal to each other, and a first multiplication signal obtained by multiplying the first signal and the reception signal. A first multiplier that outputs, a second multiplier that outputs a second multiplied signal obtained by multiplying the second signal and the received signal, and a high-frequency component is removed from the first multiplied signal. A first low-frequency extraction circuit that outputs one low-frequency signal; and a second low-frequency extraction circuit that outputs a second low-frequency signal by removing a high-frequency component from the second multiplication signal. An electronic device characterized by being configured.

  According to this configuration, by multiplying two orthogonal template signals (the first signal and the second signal) and the received signal, and removing the high frequency component and blocking the high frequency, the correlation between each template and the received signal is obtained. A value is obtained. Since the sum of the squares of these correlation values is the square of the absolute value of the received signal, the absolute value of the received signal can be known. In this case, exact synchronization with the carrier of the received signal is not necessary. Since the sum of the squares of the correlation values can be easily obtained by the electronic circuit described above, the amplitude of the signal can be obtained without accurate synchronization with the carrier wave, and a square detection receiver can be simply configured.

[Application Example 8]
A template signal generator for generating first and second signals orthogonal to each other; a first multiplier for outputting a first multiplied signal obtained by multiplying the first signal and the received signal; and the second multiplier A second multiplier that outputs a second multiplication signal obtained by multiplying the signal and the received signal, and a first low-frequency signal that outputs a first low-frequency signal by removing a high-frequency component from the first multiplication signal A pulse detection method for an electronic device, comprising: an extraction circuit; a second low-frequency extraction circuit that outputs a second low-frequency signal by removing a high-frequency component from the second multiplication signal; and the electronic circuit described above A pulse detection method for an electronic device, characterized in that the first low-frequency signal and the second low-frequency signal are square sum output by the electronic circuit to detect a pulse.

  According to this configuration, by multiplying two orthogonal template signals (the first signal and the second signal) and the received signal, and removing the high frequency component and blocking the high frequency, the correlation between each template and the received signal is obtained. A value is obtained. Since the sum of the squares of these correlation values is the square of the absolute value of the received signal, the absolute value of the received signal can be known. In this case, exact synchronization with the carrier of the received signal is not necessary. Since the sum of the squares of the correlation values can be easily obtained by the electronic circuit, the amplitude of the signal can be obtained without accurate synchronization with the carrier wave, and pulse detection can be performed.

[Application Example 9]
The pulse detection method for an electronic device according to the above, wherein the pulse carried by the supplied UWB signal is detected.

  According to this configuration, since the occupied frequency band of the signal is extremely wide in UWB-IR, the frequency accuracy of the template signal may not be high. In addition, neither accurate phase synchronization nor frequency synchronization of the carrier wave is required, and UWB-IR pulse detection can be easily performed.

  Hereinafter, embodiments of an electronic circuit will be described with reference to the drawings.

(First embodiment)
<Configuration of electronic circuit>
First, the configuration of the electronic circuit according to the first embodiment will be described with reference to FIG. FIG. 1 is a circuit diagram showing a configuration of an electronic circuit according to the first embodiment.

  As shown in FIG. 1, the electronic circuit 1 includes an n = 1 signal output unit 120, a current-voltage conversion unit 121 as a signal addition unit, a balun (Balance-Unbalance transformer, BALUN: Balance-Unbalance transformer). ) 102, capacitors 105 and 106, resistors 107 and 108, a bias power source 109, and a bias power source 116 that biases the gate potentials of the NMOS transistors 113 and 114 to the first potential.

  The signal output unit 120 includes an NMOS transistor 103 that is a first field effect transistor, an NMOS transistor 104 that is a second field effect transistor, an NMOS transistor 113 that is a third field effect transistor, and a fourth transistor. And an NMOS transistor 114 which is a field effect transistor.

  The unbalanced signal input to the input terminal 101 is input to the balun 102, separated into two balanced signals b1 and b2, and output. One balanced signal b1 is applied to the gate terminal of the NMOS transistor 103 via the capacitor 105, and the other balanced signal b2 is applied to the gate terminal of the NMOS transistor 104 via the capacitor 106. The gate terminal of the NMOS transistor 103 is connected to the bias power source 109 via the resistor 107, and the gate terminal of the NMOS transistor 104 is connected to the bias power source 109 via the resistor 108. The source terminals of the NMOS transistors 103 and 104 are grounded.

  The source terminal of the NMOS transistor 113 is connected to the drain terminal of the NMOS transistor 103. The source terminal of the NMOS transistor 114 is connected to the drain terminal of the NMOS transistor 104. The gate terminals of the NMOS transistors 113 and 114 are connected to the bias power supply 116. The drain terminals of the NMOS transistors 113 and 114 are connected to the output line 115, connected to the current / voltage converter 121, and connected to the output terminal 112. The NMOS transistors 103, 104, 113, and 114 may be configured by PMOS transistors with the polarities of the power supply voltage line 111 and the bias power supplies 109 and 116 reversed.

  The current-voltage conversion unit 121 includes a resistor 110 connected between the output line 115 and the power supply voltage line 111. The current-voltage conversion unit 121 converts the sum of drain currents of the NMOS transistors 113 and 114, which are output signals output from the output line 115 generated by the signal output unit 120, into a voltage by flowing through the resistor 110, and outputs the voltage to the output terminal. 112 to output. A power supply voltage VDD is applied to the power supply voltage line 111. The current-voltage conversion unit 121 can convert the current addition value of the plurality (n) of signal output units 120 into a voltage and output the voltage.

Here, channel width W, channel length L, carrier mobility μ, gate capacitance C per unit area, source-drain applied voltage Vd, source-gate applied voltage Vg, threshold voltage of NMOS transistors 103 and 104 Assuming Vt, the drain current Id flowing through the NMOS transistors 103 and 104 is as follows when Vd ≧ Vg−Vt:
Id = (1/2) μC (W / L) (Vg−Vt) ² (Equation 8)
It becomes. On the other hand, when Vd ≦ Vg−Vt, (Expression 7) described above is used as a better approximation of the drain current Id. Β in (Expression 7) is a constant, and β = μC (W / L).

  Since the carrier mobility is different between the PMOS transistor and the NMOS transistor, the drain current that can be flowed with respect to the same applied voltage is usually larger in the NMOS transistor in the transistors of the same size. By adjusting W / L, it is possible to balance the PMOS transistor and the NMOS transistor. The ability of the drain current that can flow with respect to the applied voltage is determined by β = μC (W / L).

  The bias voltage of the bias power supply 109 is Vb1, the unbalanced signal input to the input terminal 101 is converted by the balun 102, the voltage applied to the gate terminal of the NMOS transistor 103 via the capacitor 105 is + vi, and the NMOS is connected via the capacitor 106. The voltage applied to the gate terminal of the transistor 104 is −vi. The NMOS transistors 103 and 104 can be operated at Vd ≧ Vg−Vt if the power supply voltage VDD is set sufficiently high with respect to the bias voltage Vb, and the above-described (Equation 7) can be applied. Hereinafter, a case where the power supply voltage VDD, the bias voltage Vb1 of the bias power supply 109, and the bias voltage Vb2 of the bias power supply 116 are set so that the NMOS transistors 103, 104, 113, and 114 operate within the applicable range of (Equation 7). explain.

Assuming that the drain current of the NMOS transistor 103 is Id1, the drain current of the NMOS transistor 104 is Id2, the drain voltage of the NMOS transistor 103 is Vd1, and the drain voltage of the NMOS transistor 104 is Vd2.
Id1 = (1/2) β (Vb1 + vi−Vt) ² (1 + λVd1) (Equation 9)
Id2 = (1/2) β (Vb1−vi−Vt) ² (1 + λVd2) (Equation 10)
Holds.

  In the conventional example in FIG. 13, when a current is to flow through the NMOS transistors 1303 and 1304, the voltage Vd of the output line 1313 is lowered by the resistor 1310. It can be seen from (Equation 7) that the sensitivity of the electronic circuit 13 is reduced because the current flowing through the NMOS transistors 1303 and 1304 decreases. In the electronic circuit 13, the drain resistances of the NMOS transistors 1303 and 1304 and the resistance 1310 are connected, and the current flowing through the channels of the NMOS transistors 1303 and 1304 is shunted by the drain resistance of the NMOS transistors 1303 and 1304 and the resistance 1310 of the load. Looks like. That is, the voltage drop due to the resistor 1310 is directly reflected, and the voltage Vd changes greatly, which causes a decrease in the gain of the electronic circuit 13.

  On the other hand, in the example of the first embodiment, there are NMOS transistors 113 and 114 between the resistor 110 and the NMOS transistors 103 and 104 so that the voltage drop due to the resistor 110 cannot be seen from the NMOS transistors 103 and 104. I have to. By connecting in this way, λ in (Equation 9) and (Equation 10) can be made smaller.

Accordingly, λ in (Equation 9) and (Equation 10) can be approximately λ≈0, and the current I0 flowing through the resistor 110 is
I0≈Id1 + Id1 = β {vi ² + (Vb1−Vt) ² } (Formula 11)
It becomes.

  The NMOS transistors 113 and 114 separate the NMOS transistors 103 and 104 so that their drain resistances are not visible to each other. As a result, the influence of the effect of the channel modulation shown in (Expression 7) can be reduced, and a current closer to (Expression 6) can be passed from the output line 115. In addition, since the NMOS transistors 113 and 114 also block the output line 115 and the gate of the NMOS transistor 103 or the NMOS transistor 104, it is possible to prevent a decrease in input impedance due to the Miller effect. As a result, good frequency characteristics can be obtained.

(Vb1−Vt) ^{2 on} the right side of (Equation 11) is a DC component, and the square value of the input signal vi can be extracted by extracting only the change. In the conventional technique according to (Equation 1) described above, vi (Vb−Vt) remains as an error in addition to the DC component, but the electronic circuit 1 according to (Equation 8) does not include such an error. Therefore, it is not necessary for the bias voltage Vb1 to exactly match the threshold voltage Vt as in the conventional example. The DC component of (Vb1-Vt) ² can be easily eliminated by the capacitor. Regardless of how the bias voltage Vb1 is selected, only a DC component that can be easily eliminated remains as an error term, so that the NMOS transistors 103 and 104 can be set in a stable operating region. In particular, when noise characteristics are concerned, noise depending on the drain current such as shot noise can be reduced by adjusting the bias voltage Vb1. Further, by the action of the NMOS transistors 113 and 114, it is possible to prevent the current flowing through the NMOS transistors 103 and 104 from being shunted by the drain resistance of the NMOS transistors 113 and 114, to prevent the sensitivity from being lowered, and to be insulated from the output line 115. Therefore, the frequency characteristics are also improved.

  According to the present embodiment described above, the following effects can be obtained.

  The electronic circuit 1 for obtaining the square value of the input signal according to the present embodiment can be configured by field effect transistors (NMOS transistors 103, 104, 113, 114), and therefore can be on-chip by a semiconductor process. . In particular, since high-frequency and high-speed operation about the limit frequency of a field effect transistor is possible, application to a system that requires high-speed operation such as UWB-IR communication becomes possible. Thereby, a demodulator circuit and a pulse detection circuit of a receiver that can be easily integrated can be realized.

  In addition, although the balun 102 is used in this embodiment in order to obtain input signals having the same amplitude and opposite polarities, the present invention is not limited to this. The signal obtained from the balanced antenna and the output signal obtained from the differential amplifier satisfy the above conditions, so that the balun 102 can be omitted. Further, when the output signal is biased by an appropriate DC value depending on the operation level of the differential amplifier output, the capacitors 105 and 106, the resistors 107 and 108, and the bias power source 109 can be omitted.

(Second Embodiment)
Next, the configuration of the electronic circuit according to the second embodiment will be described with reference to FIG. FIG. 2 is a circuit diagram showing a configuration of an electronic circuit according to the second embodiment.

  As shown in FIG. 2, the electronic circuit 2 includes a signal output unit 120 and a current / voltage conversion unit 221. The current-voltage conversion unit 221 is a PMOS transistor whose gate terminal is biased to a second potential that is not necessarily the same as the first potential by the bias power source 202 instead of the resistor 110 of the current-voltage conversion unit 121 in the first embodiment. 201. The input signal input from the input terminal 211 becomes two balanced signals b1 and b2 having the same absolute value by the balun 102, and the square value of the balanced signal b1 or the balanced signal b2 is output from the output terminal 212. Note that description of the signal output unit 120 and the like that are the same as those in the first embodiment is omitted.

  If the bias value applied by the bias power source 202 is set so that the PMOS transistor 201 operates in the saturation region, the PMOS transistor 201 operates in the constant current region, and its output impedance becomes very high, and the output line 115 Can be taken out as a large voltage change. Although the same effect can be obtained by increasing the resistance 110 in the first embodiment, the voltage drop due to the resistance 110 is large, and the power supply voltage VDD applied to the power supply voltage line 111 needs to be very high.

  In the electronic circuit 2, even a weak signal can be amplified by the high resistance dynamic impedance of the PMOS transistor 201, and the square value of the signal can be extracted as a signal having a large amplitude. Furthermore, all the elements used can be made on-chip by a semiconductor process, and high-speed and high-speed operation at the limit frequency of the element is also possible, so that it can be applied to systems that require high-speed operation such as UWB-IR communication. It becomes possible. As a result, a pulse detection circuit that can be easily integrated can be realized.

  When the signal output unit 120 is configured with a PMOS transistor by the method described above, the PMOS transistor 201 used in the current-voltage conversion unit 221 is an NMOS transistor. In addition, the current-voltage conversion unit 221 can also convert the added value of the currents of the plurality (n) of signal output units 120 into a voltage and output the voltage.

(Third embodiment)
Next, the configuration of the electronic circuit according to the third embodiment will be described with reference to FIG. FIG. 3 is a circuit diagram showing a configuration of an electronic circuit according to the third embodiment.

  As shown in FIG. 3, the electronic circuit 3 includes an n = 1 signal output unit 320, a current-voltage conversion unit 321, a balun 302, capacitors 305 and 306, resistors 307 and 308, and a first potential. And a bias power source 316 for biasing the second potential. The signal output unit 320 includes an NMOS transistor 303 that is a first field effect transistor, an NMOS transistor 304 that is a second field effect transistor, an NMOS transistor 313 that is a third field effect transistor, and a fourth transistor. NMOS transistor 314 which is a field effect transistor.

  The unbalanced signal input to the input terminal 301 is input to the balun 302, and is separated into two balanced signals b1 and b2 having the same amplitude and opposite polarities. One balanced signal b1 is applied to the source terminal of the NMOS transistor 303 via the capacitor 305, and the other balanced signal b2 is applied to the source terminal of the NMOS transistor 304 via the capacitor 306. A bias power supply 309 is connected to the gate terminal of the NMOS transistor 303 and the gate terminal of the NMOS transistor 304, and a bias voltage Vb1 that is a first potential is applied. The source terminal of the NMOS transistor 303 is grounded via a resistor 307, and the source terminal of the NMOS transistor 304 is grounded via a resistor 308.

  The source terminal of the NMOS transistor 313 is connected to the drain terminal of the NMOS transistor 303. The source terminal of the NMOS transistor 314 is connected to the drain terminal of the NMOS transistor 304. A bias power supply 316 is connected to the gate terminals of the NMOS transistors 313 and 314, and a bias voltage Vb2 as a second potential is applied. The drain terminals of the NMOS transistors 313 and 314 are connected to the output line 315, connected to the current-voltage converter 321, and connected to the output terminal 312. The NMOS transistors 303, 304, 313, and 314 may be configured by PMOS transistors with the polarities of the power supply voltage line 311 and the bias power supplies 309 and 316 reversed.

  The current-voltage conversion unit 321 includes a resistor 310 connected between the output line 315 and the power supply voltage line 311. The current-voltage converter 321 converts the sum of drain currents of the NMOS transistors 313 and 314, which are output signals output from the output line 315 generated by the signal output unit 320, into a voltage by flowing the resistance 310, and outputs the voltage to the output terminal. 312 is output. A power supply voltage VDD is applied to the power supply voltage line 311. The current-voltage conversion unit 321 can convert the added value of the currents of the plurality (n) of signal output units 320 into a voltage and output the voltage.

  The voltage converted by the balun 302 and applied to the source terminal of the NMOS transistor 303 via the capacitor 305 is + vi, and the voltage applied to the source terminal of the NMOS transistor 304 via the capacitor 306 is −vi. If the bias voltages Vb1 and Vb2 and the power supply voltage VDD are set to appropriate voltage values, the NMOS transistors 303, 304, 313, and 314 can be operated in the saturation region, and the above-described (Equation 7) can be applied. Hereinafter, a case where the power supply voltage VDD and the bias voltages Vb1 and Vb2 are set so that the NMOS transistors 303, 304, 313, and 314 operate within the applicable range of (Expression 7) will be described.

Assuming that the drain current of the NMOS transistor 303 is Id1, the drain current of the NMOS transistor 304 is Id2, the drain voltage of the NMOS transistor 303 is Vd1, and the drain voltage of the NMOS transistor 304 is Vd2, Id1 = (1/2) β (Vb1-vi −Vt) ² (1 + λVd1) (Equation 12)
Id2 = (1/2) β (Vb1 + vi−Vt) ² (1 + λVd2) (Equation 13)
Holds.

  There are NMOS transistors 313 and 314 between the resistor 310 and the NMOS transistors 303 and 304 so that the voltage drop due to the resistor 310 is not visible to the NMOS transistors 303 and 304. By connecting in this way, λ in (Expression 12) and (Expression 13) can be made smaller.

  Accordingly, λ in (Expression 12) and (Expression 13) can be approximately set to λ≈0, and the current I0 flowing through the resistor 310 is expressed by (Expression 11) described above.

  NMOS transistors 313 and 314 isolate NMOS transistors 303 and 304 so that their drain resistances are not visible to each other. As a result, the influence of the effect of channel modulation or the like shown in (Expression 7) can be reduced, and a current closer to (Expression 6) can be supplied from the output line 315. In addition, since the NMOS transistors 313 and 314 also block the output line 315 and the gate of the NMOS transistor 303 or the NMOS transistor 304, it is possible to prevent a decrease in input impedance due to the Miller effect. As a result, good frequency characteristics can be obtained.

(Equation 11) (Vb1−Vt) ^{2 on the} right side is a DC component, and the square value of the input signal vi can be extracted by extracting only the change. In the conventional technique according to (Equation 1), vi (Vb1-Vt) remains as an error in addition to the DC component, but in the case of the third embodiment according to (Equation 11), such an error is not included. Therefore, it is not necessary for the bias voltage Vb1 to exactly match the threshold voltage Vt as in the conventional example. The DC component of (Vb1-Vt) ² can be easily eliminated by the capacitor. Regardless of how the bias voltage Vb1 is selected, only a DC component that can be easily eliminated remains as an error term, so that the NMOS transistors 303 and 304 can be set in a stable operating region. In particular, when noise characteristics are concerned, noise depending on the drain current, such as shot noise, can be reduced by adjusting the bias voltage Vb1.

  The electronic circuit 3 of the third embodiment can be regarded as a wired-or-connected cascode-connected grounded-gate amplifier circuit. The low input impedance characteristic that is a feature of the common-gate amplifier circuit facilitates matching design of the input circuit.

  According to the present embodiment described above, the following effects can be obtained.

  Since the electronic circuit 3 for obtaining the square value of the signal according to the third embodiment can be composed of field effect transistors (NMOS transistors 303, 304, 313, and 314), it can be made on-chip by a semiconductor process. is there. In particular, since high-frequency and high-speed operation about the limit frequency of a field effect transistor is possible, application to a system that requires high-speed operation such as UWB-IR communication becomes possible. As a result, a demodulator circuit and a pulse detection circuit of a receiver that can be easily integrated can be realized.

  In order to obtain input signals having the same amplitude and opposite polarities, the balun 302 is used in the third embodiment, but the present invention is not limited to this. The signal obtained from the balanced antenna and the output signal obtained from the differential amplifier satisfy the above conditions, so that the balun 302 can be omitted. Further, when a DC component is not included as in the output signal of the balanced antenna, the capacitors 305 and 306 and the resistors 307 and 308 can be omitted.

(Fourth embodiment)
Next, the configuration of the electronic circuit according to the fourth embodiment will be described with reference to FIG. FIG. 4 is a circuit diagram showing a configuration of an electronic circuit according to the fourth embodiment.

  As shown in FIG. 4, the electronic circuit 4 includes a signal output unit 320 and a current / voltage conversion unit 421. Instead of the resistor 310 of the current-voltage conversion unit 321 in the third embodiment, the current-voltage conversion unit 421 is biased to a third potential whose gate terminal is not necessarily the same as the first potential and the second potential by the bias power source 402. The PMOS transistor 401 is configured. The input signal input from the input terminal 411 becomes two balanced signals b1 and b2 by the balun 302, and the square value of the balanced signals b1 and b2 is output from the output terminal 412. Note that the description of the same signal output unit 320 and the like as in the third embodiment is omitted.

  When the bias value applied by the bias power source 402 is set so that the PMOS transistor 401 operates in the saturation region, the PMOS transistor 401 operates in the constant current region, and its output impedance becomes very high, and the output line 315 Can be taken out as a large voltage change. Even if the resistor 310 is increased in the third embodiment, the same effect can be obtained, but the voltage drop due to the resistor 310 is large, and the power supply voltage VDD applied to the power supply voltage line 311 needs to be very high.

  In the electronic circuit 4, even a weak signal can be amplified by the high resistance dynamic impedance of the PMOS transistor 401, and the square value of the signal can be extracted as a signal having a large amplitude. Furthermore, all the elements used can be made on-chip by a semiconductor process, and high-speed and high-speed operation at the limit frequency of the element is also possible, so that it can be applied to systems that require high-speed operation such as UWB-IR communication. It becomes possible. As a result, a pulse detection circuit that can be easily integrated can be realized.

  When the signal output unit 320 is configured by a PMOS transistor by the method described above, the PMOS transistor 401 used in the current-voltage conversion unit 421 is an NMOS transistor. In addition, the current-voltage conversion unit 421 can connect each output line 315 in parallel using a plurality (n) of signal output units 320, convert the added value of these currents into a voltage, and output the voltage.

(Fifth embodiment)
Next, the configuration of the electronic circuit according to the fifth embodiment will be described with reference to FIG. FIG. 5 is a circuit diagram showing a configuration of an electronic circuit according to the fifth embodiment. In the fifth embodiment, a case of a square sum circuit in which n = 2 signal output units 120 in FIG. 1 are connected in parallel to a current-voltage conversion unit 521 is shown.

  As shown in FIG. 5, the electronic circuit 5 includes signal output units 522 and 523 that are the signal output unit 120 of FIG. 1, a current-voltage conversion unit 521, an input terminal 524, a balun 102, capacitors 105 and 106, and , Resistors 107 and 108, bias power source 109, input terminal 525, balun 152, capacitors 155 and 156, resistors 157 and 158, and bias power source 159. The output line 513 of the signal output unit 522 and the output line 514 of the signal output unit 523 are connected in parallel to the current-voltage conversion unit 521 and the output terminal 515. The current-voltage conversion unit 521 includes a resistor 510 connected between the output lines 513, 514 and the power supply voltage line 511. The drain current generated by the signal output units 522, 523 is added, and a voltage is generated by the resistor 510. The signal is converted into a signal and output from the output terminal 515.

  Both of the bias power sources of the signal output units 522 and 523 may be individually provided or shared by the signal output units 522 and 523 like the bias power sources 109 and 159 illustrated in FIG. In the former case, different bias values can be set for the signal output units 522 and 523. It is also possible to correct the variation in constants for each signal output unit, or to operate by deviating the operating point intentionally. In the latter case, the number of bias power supplies can be reduced and the circuit can be simplified.

The resistance value of the resistor 510 may be half the resistance value in the case of an individual circuit, assuming that the two signal output units 522 and 523 are connected in parallel, or the same value as the resistance value in the case of an individual circuit You may take When the latter same resistance value is set, the voltage drop due to the DC term β (Vb1-Vt) ² in (Equation 11) is doubled. In the former case, there is no increase in the voltage drop, but if the intended βvi ² term is converted into a voltage and taken out, the amplitude value is halved. Taking both into consideration, it is possible to set the value of the resistor 510 to a different appropriate value. In addition, an inductance can be used instead of the resistor 510 in order to extract only the change in current. When the inductance is used, the voltage drop due to the DC term β (Vb−Vt) ² can be eliminated.

When the signal input to the input terminal 524 is vi1, the signal input to the input terminal 525 is vi2, and the loss of amplitude due to the baluns 102 and 152 is ignored, the current I0 flowing through the resistor 510 is the current of the signal output unit 522. Since I01 is the sum of the current I02 of the signal output unit 523, referring to (Equation 11), I0 = I01 + I02 = β {vi1 ² + (Vb−Vt) ² } + β {vi2 ² + (Vb−Vt) ² } = β (vi1 ² + vi2 ² ) + 2β (Vb−Vt) ² (Equation 14)
It becomes.

The first term on the right side of (Expression 14) is the sum of vi1 ² and vi2 ² , and this is the target output. The second term on the right side of (Equation 14) is a direct current component and can be easily cut off by a capacitor. In the fifth embodiment, the case where n = 2 signal output units 522 and 523 is illustrated, but n may be an integer larger than that. The n output lines from each signal output unit are connected in parallel, the current sum is converted by the current-voltage conversion unit, converted into a voltage signal by the resistor 510, and output from the output terminal 515. In this case, the sum of squares of n signals can be obtained as an output signal.

  Regardless of how the bias voltage Vb1 is selected, only a DC component that can be easily eliminated remains as an error term, so that the NMOS transistors 103 and 104 can be set in a stable operating region. In particular, when noise characteristics are concerned, noise depending on the drain current such as shot noise can be reduced by adjusting the bias voltage Vb.

  As described in the first embodiment, the signal output units 522 and 523 prevent the drain currents of the NMOS transistors 103 and 104 from being desensitized by the shunting of the mutual drain resistances by the functions of the NMOS transistors 113 and 114, and Improve frequency characteristics.

  The electronic circuit 5 of the fifth embodiment is a wired-OR connection of the common-source electronic circuit 1 of the first embodiment.

  Since the electronic circuit 5 for obtaining the square value of the signal according to the fifth embodiment can be constituted by a field effect transistor, it can be formed on-chip by a semiconductor process, and in particular, a high-frequency high speed about the limit frequency of the field effect transistor. Since it can operate, it can be applied to a system that requires high-speed operation such as UWB-IR communication. Thereby, a demodulator circuit and a pulse detection circuit of a receiver that can be easily integrated can be realized.

(Sixth embodiment)
Next, the configuration of the electronic circuit according to the sixth embodiment will be described with reference to FIG. FIG. 6 is a circuit diagram showing a configuration of an electronic circuit according to the sixth embodiment. In the sixth embodiment, a case of a square sum circuit in which n = 2 signal output units 120 of FIG. 1 are connected in parallel to a current-voltage conversion unit 621 is shown. Since the signal output unit 120 and the like are the same as those in the first embodiment, the same numbers are given and the description is omitted.

  As shown in FIG. 6, the electronic circuit 6 includes a signal output unit 622, 623, a current-voltage conversion unit 621, an input terminal 624, a balun 102, capacitors 105, 106, which are the signal output unit 120 of FIG. , Resistors 107 and 108, bias power source 109, input terminal 625, balun 152, capacitors 155 and 156, resistors 157 and 158, and bias power source 159. The output line 613 of the signal output unit 622 and the output line 614 of the signal output unit 623 are connected in parallel to the current-voltage conversion unit 621 and the output terminal 615. In the current-voltage converter 621, a PMOS transistor 601 whose gate terminal is biased by a bias power source 602 is connected between the output lines 613 and 614 and the power source voltage line 611. The current / voltage conversion unit 621 adds the drain currents generated by the signal output units 622 and 623, converts the current into a voltage signal by the current / voltage conversion unit 621, and outputs the voltage signal from the output terminal 615.

  The PMOS transistor 601 of the current-voltage converter 621 is biased at a predetermined potential by the bias power source 602. When the PMOS transistor 601 is biased to operate in the saturation region, the channel impedance can be increased. With this high resistance dynamic impedance, even a weak signal can be amplified and the square value of the signal can be extracted as a signal having a large amplitude. Furthermore, all the elements used can be made on-chip by a semiconductor process, and high-speed and high-speed operation at the limit frequency of the element is also possible, so that it can be applied to systems that require high-speed operation such as UWB-IR communication. It becomes possible. As a result, a pulse detection circuit that can be easily integrated can be realized.

  When the signal output units 622 and 623 are configured with PMOS transistors by the method described above, the PMOS transistor 601 used in the current-voltage conversion unit 621 is an NMOS transistor.

  Since the electronic circuit 6 for obtaining the square value of the signal according to the sixth embodiment can be constituted by a field effect transistor, it can be formed on-chip by a semiconductor process, and in particular, the limit frequency of the field effect transistor. Since high frequency high-speed operation is possible, it can be applied to a system that requires high-speed operation such as UWB-IR communication. Thereby, a demodulator circuit and a pulse detection circuit of a receiver that can be easily integrated can be realized.

(Seventh embodiment)
Next, the configuration of the electronic circuit according to the seventh embodiment will be described with reference to FIG. FIG. 7 is a circuit diagram showing a configuration of an electronic circuit according to the seventh embodiment. In the seventh embodiment, a case of a square sum circuit in which n = 2 signal output units 320 of FIG. 3 are connected in parallel and the output currents of the signal output units are added and then connected to a current-voltage conversion unit 721 is shown.

  As shown in FIG. 7, the electronic circuit 7 connects the output lines 713 and 714 of the signal output units 722 and 723 that are the signal output unit 320 of FIG. Input to the conversion unit 721. The output currents of the signal output units 722 and 723 are added, converted into a voltage signal here, and output from the output terminal 715.

  The operation of the electronic circuit 7 is omitted because the signal output units 522 and 523 of the fifth embodiment are simply replaced with the signal output unit 320 of FIG. 3. Furthermore, as in the sixth embodiment, the current-voltage conversion unit 721 can be replaced with a PMOS transistor for calibration. In this case, as already described, high sensitivity can be detected with a small voltage drop by the high output resistance in the saturation region of the PMOS transistor.

(Eighth embodiment)
Next, the configuration of a receiving device that is an electronic device including the electronic circuit according to the eighth embodiment will be described with reference to FIGS. 8 and 9. FIG. 8 is a circuit diagram showing a configuration of a receiving apparatus according to the eighth embodiment. FIG. 9 is a timing chart showing the operation of the receiving apparatus according to the eighth embodiment.

  In the eighth embodiment, a case will be described as an example in which a waveform as shown in the received signal a in FIG. 9 obtained by multiplying a rectangular pulse as a UWB-IR pulse signal by a sine wave of the carrier frequency fc is used. It is not limited to. Gaussian monopulse, Hermite pulse, or their n-th order differential waveform (n is a natural number) frequently used as an IR signal, and a pulse whose spectrum is moved on the frequency axis by multiplying it by a sine wave of the carrier frequency fc, etc. A pulse may be used. In particular, a pulse obtained by multiplying a sine wave having a carrier frequency fc is frequently used because it does not contain a direct current component and the spectrum is symmetrical about fc. In the eighth embodiment, a UWB-IR receiving apparatus (electronic apparatus) that uses a pulse (a in FIG. 9) obtained by multiplying the simplest rectangular pulse by a sine wave as an IR signal will be described as an example.

  As shown in FIG. 8, the receiving device 8 includes an antenna 801, a low noise amplifier (LNA) 802, a square circuit 803 (FIGS. 1 to 4), a low-pass filter (LPF: Low). -Pass Filter) 804 and a discrimination circuit 805 as a signal processing unit.

  A received signal a (FIG. 9) received by the antenna 801 is amplified by the LNA 802. When the LNA 802 having a balanced output is configured as an amplifier circuit, the baluns 102 and 302 shown in FIGS. 1 to 4 can be omitted. The square circuit 803 squares the received signal a and outputs a square signal b (FIG. 9). The LPF 804 removes the high frequency component of the square signal b and outputs an LPF signal c (FIG. 9). The LPF 804 may use an integration circuit. The determination circuit 805 performs binarization processing on the LPF signal c, outputs a binarization signal d (FIG. 9), and can detect the presence or absence of a pulse.

  In UWB-IR, if “send pulse” or “do not send pulse” is controlled according to bit 1 or 0 of information to be transmitted, a modulation method called OOK (On-Off-Keying) Become. Further, if the pulse position is controlled according to the transmission bit information, a modulation method called PPM (Pulse Position Modulation) is obtained. In the configuration of the receiving device 8, since the presence or position of the transmitted pulse can be detected, UWB-IR can be demodulated. When the timing of the next pulse signal to be received can be predicted by the pulse detected by the determination circuit 805, the operation of the circuit for the previous period is stopped by the signal 807, and the power consumption of the receiving device 8 can be reduced. is there.

  If the squaring circuit 803 is used as in the eighth embodiment, the UWB-IR receiver 8 can be easily configured. Any circuit used in the receiving device 8 can be integrated with a semiconductor integrated circuit or the like using CMOS, and a highly reliable and low-cost receiving device can be realized.

  The configuration of the receiving device 8 according to the eighth embodiment can also be used for a signal receiving device using amplitude modulation. In that case, the determination circuit 805 is unnecessary, and the envelope of the received signal is output to the LPF 804. That is, the envelope can be detected from the amplitude modulation signal, which is nothing but demodulation of the amplitude modulation signal.

(Ninth embodiment)
Next, the configuration of a receiving device that is an electronic device including the electronic circuit according to the ninth embodiment will be described with reference to FIGS. 10 and 11. FIG. 10 is a circuit diagram showing a configuration of a receiving apparatus according to the ninth embodiment. FIG. 11 is a timing chart showing the operation of the receiving apparatus according to the ninth embodiment.

  As shown in FIG. 10, the receiving apparatus 10 includes an antenna 1001, an LNA 1002, mixers 1003 and 1004, LPFs 1005 and 1006, a square sum circuit 1007 (FIGS. 5 to 7), a template generation circuit 1008, and a discrimination circuit. 1009 and an AD conversion circuit 1011.

  Similarly to the eighth embodiment, the ninth embodiment uses a waveform as shown in the received signal a of FIG. 11 obtained by multiplying a rectangular pulse as a UWB-IR pulse signal by a sine wave of the carrier frequency fc. This is explained in the example, but it is not limited to this. A Gaussian monopulse, Hermitian pulse, or an n-th order differential waveform frequently used as an IR signal, a pulse obtained by multiplying them by a sine wave of the carrier frequency fc, and moving the spectrum on the frequency axis may be used. In particular, a pulse obtained by multiplying a sine wave having a carrier frequency fc does not include a direct current component, and the spectrum is symmetric about fc, and is frequently used because it is easy to generate. In the ninth embodiment, a UWB-IR receiver 10 that uses a pulse (a in FIG. 11) obtained by multiplying the simplest rectangular pulse by a sine wave as an IR signal will be described as an example.

  There is a method called synchronous detection as a demodulation method when configuring the receiving apparatus 10. In this method, a correlation between a template prepared on the receiver side and a received signal is calculated, and information transmitted from the correlation value is extracted. The correlation value is obtained by multiplying the template and the received signal and further integrating the result. Integration has the same effect as LPF removal of high frequencies, and integration is often substituted by LPF.

  The ninth embodiment is a UWB-IR receiver for synchronous detection using a square sum circuit (FIGS. 5 to 7).

A reception signal a (FIG. 11) that is a UWB-IR signal received by the antenna 1001 is amplified by the differential LNA 1002 and input to the mixers 1003 and 1004. Each of the mixers 1003 and 1004 is multiplied by two orthogonal template signals generated by the template generation circuit 1008, and outputs multiplication waveforms b and c (FIG. 11). In these multiplication waveforms b and c, LPF signals d and e (FIG. 11) from which high-frequency components have been removed by LPFs 1005 and 1006 are input to a square sum circuit 1007, and the sum of squares of the respective LPF signals d and e is a sum of squares. It is output as a signal f (FIG. 11). This square sum signal f (that is, the sum of the square of the signal d and the square of the signal e, d ² + e ² ) is equal to the square value of the envelope of the received signal a. The LPFs 1005 and 1006 can use an integration circuit. By discriminating the presence or absence of a pulse from the square sum signal f by the discrimination circuit 1009, information transmitted from the received signal can be taken out and restored, and output from the output terminal 1010 as a restoration signal g (FIG. 11). .

  If the signals of the LNA 1002, the mixers 1003 and 1004, and the template generation circuit 1008 are constituted by a balanced circuit that can handle a balanced signal (differential signal), the signal input to the square sum circuit 1007 is balanced. Thus, the baluns 102, 302, 152, and 352 in FIGS.

  The determination circuit 1009 also controls the operation of the entire receiving apparatus. That is, if the next timing when the received signal a arrives can be predicted based on the information of the restored signal g, the circuit operation is stopped by the control signals h1, h2, and h3 until that time and the power consumption is saved. Can do. The template signal generated by the template generation circuit 1008 may be generated intermittently for a time during which the signal will be received, or may be generated continuously when it cannot be predicted.

  In the following, the fact that the amplitude (square value) of a signal can be detected without accurate frequency and phase synchronization with the above-described configuration will be described using equations as a supplement to the above description.

  First, as a UWB-IR signal, assuming that a signal obtained by multiplying the above-described rectangular pulse (with pulse width Tp) by the carrier frequency fc is transmitted every time interval Tb, the received UWB-IR signal S The period of nTb ≦ t ≦ nTb + Tp is represented by S = cos (2πfct), and the period of nTb + Tp <t <(n + 1) Tb can be represented by S = 0. Here, t is time and n is an integer. The received signal a in FIG. 11 has this waveform.

  If two orthogonal template signals generated in the template generation circuit 1008 are PI and PQ, they can be expressed as PI = cos {(ωc + Δω) t + φ} and PQ = sin {(ωc + Δω) t + φ}. Here, ωc = 2πfc and Δω = 2πΔfc, and Δfc is an error from the carrier frequency fc of the template signal. Φ is a phase difference indicating that the phases do not match.

Since the outputs IFI and IRQ of the mixers 1003 and 1004 are multiplications of S, PI, and PQ, respectively, the period of nTb ≦ t ≦ nTb + Tp is
IFI = SPI = cos (ωct) cos {(ωc + Δω) t + φ} = (1/2) {cos ((2ωc + Δω) t + φ) + cos (Δωt + φ)} (Equation 15)
IFQ = SPQ = cos (ωct) sin {(ωc + Δω) t + φ} = (1/2) {sin ((2ωc + Δω) t + φ) + sin (Δωt + φ)} (Expression 16)
In the period of nTb + Tp <t <(n + 1) Tb, IFI = IFQ = 0. The multiplication waveforms b and c in FIG. 11 are this waveform.

The LPFs 1005 and 1006 remove the first term from the high frequency component from this signal, that is, from the right side of (Expression 15) and (Expression 16). Therefore, if the IFI and IRQ signals that have passed through the LPFs 1005 and 1006 are IFI ′ and IQ ′, the period of nTb ≦ t ≦ nTb + Tp is:
IFI ′ = (1/2) cos (Δωt + φ) (Expression 17)
IFQ ′ = (1/2) sin (Δωt + φ) (Equation 18)
Thus, IFI ′ = IFQ ′ = 0 during the period of nTb + Tp <t <(n + 1). Here, the signal delay due to the LPF was ignored. The LPF signals d and e in FIG. 11 have this waveform. Therefore, if the output of the square sum circuit 1007 is B, the period of nTb ≦ t ≦ nTb + Tp is
B = IFI ′ ² + IFQ ′ ² = (1/4) {cos ² (Δωt + φ) + sin ² (Δωt + φ)} = 1/4 (Equation 19)
In the period of nTb + Tp <t <(n + 1), B = 0, and a pulse having an amplitude of 1/4 is output when the UWB-IR signal is received regardless of the error Δfc and the phase shift φ of the carrier frequency fc. The

Also, even when the carrier phase is modulated like BPM,
Φ = tan ⁻¹ (IFI ′ / IFQ ′) (Equation 20)
It is easy to know by calculating In the calculation of (Equation 20), the value of (IFI ′ / IFQ ′) is sufficient if it has a resolution of 1 to 2 bits, and can be easily known by the AD conversion circuit 1011 using a simple comparator. The AD conversion circuit 1011 is an AD conversion circuit 1011 for BPM. The AD conversion circuit 1011 AD-converts the output values of the LPFs 1005 and 1006, and the discrimination circuit 1009 represents the square sum circuit 1007 representing the square of the absolute value of the UWB-IR signal S. Together with the output, phase information is extracted and demodulated by the output of the AD conversion circuit 1011. In the case of OOK or PPM, the AD conversion circuit 1011 can be omitted.

  As described above, when the sum of squares circuit 1007 is used, synchronous detection can be performed without accurate phase and frequency synchronization. Thereby, the structure of the receiving apparatus 10 can be remarkably simplified.

(10th Embodiment)
Next, the configuration of a receiving device that is an electronic device including the electronic circuit according to the tenth embodiment will be described with reference to FIG. FIG. 12 is a circuit diagram showing a configuration of a receiving apparatus according to the tenth embodiment.

  In the ninth embodiment, the case where two orthogonal template signals are used has been described. The ninth embodiment can be extended when two or more orthogonal templates are used.

  In addition to UWB-IR communication, in general, a signal can be regarded as a position vector representing one point on an n-dimensional (n is an integer or infinity) space, and analysis and processing thereof can be performed. The description of the tenth embodiment will be made using this method. Such techniques are obvious to those skilled in the art, but for confirmation, the following outlines how this technique would look when looking at the prior art.

A vector consisting of a number of numbers enclosed in parentheses is called a vector, and can represent a quantity with direction and size. When sampling is performed at a predetermined interval in, for example, one symbol section of the signal waveform, n sampling values s1, s2,... Sn are obtained. This sampling value is arranged in order and enclosed in parentheses (s1, s2,... Sn) is a vector. Since n numbers are arranged, it is an n-dimensional vector and can represent coordinates in an n-dimensional space. If this is now expressed as s →, then s → = (s1, s2,... Sn). Since the vector s → can represent a signal or a position as a position vector, it may be simply referred to as “signal s ^{→” or “point s →} ”.

In n-dimensional space, a set of n linearly independent vectors can be chosen, and any vector in this space can be represented as a linear combination thereof. In particular, a set of n vectors that are orthogonal to each other with an absolute value of 1 is called an orthonormal basis. If this is e1 ^{→, e2 →} , ... en, then an arbitrary vector x ^{→
x → = (x →, e1 →) e1 →} + (x ^{→, e2 →} ) e2 ^{→ + ... + (x →, en →) en →} ... (formula 21)
It can be expressed as Here, (x ^{→, y →)} represents the inner product of the ^{vectors x → and y →} . This equation, e1 ^→ coordinate axes on the n-dimensional ^{space, e2 →,} when taking · · · en ^→, the position coordinates representing a point ^{X ((x →, e1 →} ), (x →, e2 →) ,... (X ^→ , en ^→ )). A discrete Fourier series expansion uses a set of trigonometric functions of an integer i of a period T as e1 ^{→, e2 →} ,... en ^→ . Here, i is an integer of 1 ≦ i ≦ n.

Now, considering the case where an arbitrary m terms on the right side of (Equation 21) are omitted and approximation is performed using only k = n−m terms, x ′ ^→ = (x ^→ , e1 ^→ ) e1 ^→ + (x ^{→ , E2 →} ) e2 ^→ + ... + (x ^→ , ek ^→ ) ek ^→ ... (formula 22)
It becomes.

When x ^→ is approximated by x ′ ^→ , the error x ^→ −x ′ ^→ when the coefficient of ei ^→ (where i is an integer of 1 ≦ i ≦ k) is set to (x ^→ , ei ^→ ) as described above. It is known that the square of the absolute value of (the error in energy) is minimized.

For the magnitude of the vector x ^→ , it is convenient to calculate the square value of its absolute value. It can be easily known by calculating the inner product (x ^→ , x ^→ ) with itself. Further, from (Expression 21), (x ^→ , x ^→ ) = Σ (x ^→ , ei ^→ ) ² (Expression 23)
(Σ is the sum of i = 1 to n).

In the conventional correlation detection, the correlation between the received signal r ^→ and the templates p0 ^→ , p1 ^→ , that is, the inner product is calculated to know and demodulate the “similarity” between r ^→ , p0 ^→ , and p1 ^→ . Here, p0 ^→ and p1 ^→ are templates representing that the transmitted information is bit 0 and bit 1, respectively. When the template and r ^→ coincide with each other, the value becomes the largest, so that both can be compared and the transmitted information can be known with higher accuracy. However, in the conventional synchronous detection, it is necessary to completely match the timings of r ^→ , p0 ^→ , and p1 ^→ . The vector r ^→ in the n-dimensional space needs to be in (or very close to) the two-dimensional subspace spanned by p0 ^→ and p1 ^→ . In general, when the number of templates k is increased on the transmitting side, the amount of information that can be transmitted per symbol can be increased, but k may be increased only by the receiving device. In this case, since the range in which the existence of r ^→ is allowed is expanded to the k-dimensional subspace in the n-dimensional space, the degree of freedom such as the synchronization accuracy and the method of selecting the template signal is further increased.

The phase information of r ^→ can be obtained as follows. That is, {(x ^→ , ei ^→ ) | i is an integer of 1 ≦ i ≦ k} represents a position coordinate in a k-dimensional subspace, and a direction cosine of r ^→ with respect to {ei} is obtained by normalization. In many cases, the vector of signal symbols is arranged so that the distance between the symbols is as large as possible, and is arranged so as to be symmetric about the origin in the n-dimensional space. In the case of k = 2 in the ninth embodiment, it is obtained by (Equation 20), but this is merely a ratio of the direction cosine to the PI and PQ of the UWB-IR signal S. In the case of BPM, since signal symbols are taken at two symmetrical positions around the origin, IFI 'and IFQ' are demodulated if their signs (correlation value is positive or negative) are known by 1-bit AD conversion. Was possible. That is, if it is known in which quadrant in the k-dimensional subspace the received signal exists, it can be demodulated. When the signal-to-noise ratio is poor, or when the accuracy of the template, the carrier frequency, or the phase shift is large, high-precision AD conversion is necessary when k = 2. It is possible to accurately determine (that is, just know whether the sign is positive or negative).

In the above description, r ^→ and {pi ^→ } are described as n-dimensional vectors obtained by n samplings, that is, discrete (time) functions. However, it should be noted that the above description can also be applied to continuous functions such as general signals by well-known linear algebra techniques. In that case, the limit (infinite dimension) where the sampling number n is infinite is considered. As the inner product, the sum of products is used in the case of a discrete quantity, but the integral is used as the limit in the case of a continuous quantity.

  As illustrated in FIG. 12, the reception device 12 includes an antenna 1201, an LNA 1202, k correlation circuits 1208, 1209,... 1210, a square sum circuit 1206, an AD conversion circuit 1207, and a determination circuit 1211. , Is composed of. The sum of squares circuit 1206 is obtained by connecting n = 2 signal output units in parallel in the fifth to seventh embodiments, but connecting n = k in parallel.

The reception signal received by the antenna 1201 is amplified by the LNA 1202 and sent to k correlation circuits 1208, 1209,. Let the output signal vector of the LNA 1202 be r ^→ .

Since the configuration of the k correlation circuits 1208, 1209,... 1210 is the same, the configuration of the correlation circuit 1208 will be described in detail. The correlation circuit 1208 includes a template generation circuit 1205, a multiplication circuit 1203, and an integration circuit (or LPF) 1204. The template generation circuit 1205 generates a template p1 ^→ , is multiplied by r ^→ in the multiplication circuit 1203, and is integrated in the integration circuit 1204 to obtain a correlation value ρ1. The correlation value ρ1 is a scalar quantity. Similarly, the correlation circuit 1209 outputs the correlation value ρ2 of the received signal r ^→ and the template p2 ^→ , and the correlation circuit 1210 outputs the correlation value ρk of the received signal r ^→ and the template pk ^→ . These correlation values ρ1, ρ2,... Ρk are input to the square sum circuit 1206 and the AD conversion circuit 1207.

The sum of squares circuit 1206 outputs the absolute value of r ^→ based on (Equation 23). In this case, the square sum circuit 1206 is a k-input square sum circuit in which k pieces of electronic circuits (square circuits) 1 to 4 in FIGS. (The case where k = 2 is illustrated in FIGS. 5 to 7. The required number of signal output units may be connected in parallel also when k> 2.) In the determination circuit 1211, the square sum circuit 1206 and the AD conversion circuit 1207 are connected. Information transmitted from the output value is estimated and demodulated.

The discriminating circuit 1211 also takes control of the entire receiving device 12, estimates the timing when the next signal reception can be expected from the timing obtained from the received signal, activates the template, or turns off the power of the device when there is no received signal. To save power consumption. It also captures signals at the beginning of the communication link. Further, when the carrier frequency is shifted in transmission / reception, the shift from the template is shifted at every reception, and this phase shift is also corrected. That is, since the signal position to be received next can be estimated from the position of r ^→ (in the k-dimensional space) previously received by the AD conversion circuit 1207, correction is performed based on these positions.

  In the tenth embodiment, since the number of templates can be increased in the configuration of the receiving device 12, there is no accurate carrier frequency and phase synchronization, and a simple low-resolution AD converter circuit 1207 is used. The accuracy during demodulation can be further increased. As described above, the structure of the receiver can be remarkably simplified by the sum of squares circuit 1206.

1 is a circuit diagram showing a configuration of an electronic circuit according to a first embodiment. The circuit diagram which shows the structure of the electronic circuit which concerns on 2nd Embodiment. The circuit diagram which shows the structure of the electronic circuit which concerns on 3rd Embodiment. The circuit diagram which shows the structure of the electronic circuit which concerns on 4th Embodiment. The circuit diagram which shows the structure of the electronic circuit which concerns on 5th Embodiment. The circuit diagram which shows the structure of the electronic circuit which concerns on 6th Embodiment. The circuit diagram which shows the structure of the electronic circuit which concerns on 7th Embodiment. The circuit diagram which shows the structure of the receiver which concerns on 8th Embodiment. The timing diagram which shows operation | movement of the receiver which concerns on 8th Embodiment. The circuit diagram which shows the structure of the receiver which concerns on 9th Embodiment. The timing diagram which shows operation | movement of the receiver which concerns on 9th Embodiment. The circuit diagram which shows the structure of the receiver which concerns on 10th Embodiment. The circuit diagram which shows the structure of the conventional electronic circuit.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1-7 ... Electronic circuit 8, 10, 12 ... Receiver, 101 ... Input terminal, 102 ... Balun, 103, 104, 113, 114 ... NMOS transistor, 105, 106 ... Capacitor, 107, 108 ... Resistance, 109, DESCRIPTION OF SYMBOLS 116 ... Bias power supply, 110 ... Resistance, 111 ... Power supply voltage line, 112 ... Output terminal, 120 ... Signal output part, 121 ... Current-voltage conversion part, 201 ... PMOS transistor, 202 ... Bias power supply, 211 ... Input terminal, 212 ... Output terminal 301... Input terminal 302. Balun 303, 304, 313, 314 NMOS transistor 305 306 Capacitor 307 308 Resistor 309 316 Bias power supply 310 Resistor 311 Power supply voltage Line 312 ... Output terminal 315 ... Output line 320 ... Signal output unit 321 ... Current and current Conversion unit 401 ... PMOS transistor 402 ... Bias power supply 411 ... Input terminal 412 ... Output terminal 510 ... Resistance 511 ... Power supply voltage line 515 ... Output terminal 521 ... Current voltage conversion unit 522, 523 ... Signal Output unit, 524, 525 ... input terminal, 601 ... PMOS transistor, 611 ... power supply voltage line, 615 ... output terminal, 621 ... current-voltage converter, 622, 623 ... signal output unit, 624, 625 ... input terminal, 710 ... Resistor, 714 ... Output terminal, 722, 723 ... Signal output unit, 724, 725 ... Input terminal, 801 ... Antenna, 802 ... LNA, 803 ... Square circuit, 804 ... LPF, 805 ... Discrimination circuit, 1001 ... Antenna, 1002 ... LNA, 1003, 1004 ... mixer, 1005, 1006 ... LPF, 1007 ... square sum circuit, 10 DESCRIPTION OF SYMBOLS 8 ... Template generation circuit, 1009 ... Discrimination circuit, 1010 ... Output terminal, 1011 ... AD conversion circuit, 1201 ... Antenna, 1202 ... LNA, 1203 ... Multiplication circuit, 1204 ... Integration circuit, 1205 ... Template generation circuit, 1206 ... Sum of squares Circuit, 1207 ... AD conversion circuit, 1208, 1209, 1210 ... Correlation circuit, 1211 ... Discrimination circuit.

Claims (9)

A first field effect transistor having one of the balanced signals connected to the gate terminal and the source terminal grounded;
A second field effect transistor having the other one of the balanced signals connected to the gate terminal and the source terminal grounded;
A third field effect transistor having a source terminal connected to a drain terminal of the first field effect transistor and a gate terminal biased to a first potential;
A fourth field effect transistor having a source terminal connected to the drain terminal of the second field effect transistor and a gate terminal biased to the first potential;
An output line for connecting the drain terminal of the third field effect transistor and the drain terminal of the fourth field effect transistor to output an output signal;
N (n is an integer greater than or equal to 1) signal output units configured to include:
A signal adder that is connected to each of the output lines of the n signal output units and outputs a signal that is proportional to the sum of the output signals output from the output lines of the n signal output units; ,
An electronic circuit comprising:   2. The electronic circuit according to claim 1, wherein the signal adding unit includes a field effect transistor having a gate terminal biased to a second potential. A first field effect transistor having a gate terminal biased to a first potential and a source terminal connected to one of the balanced signals;
A second field effect transistor having a gate terminal biased to the first potential and a source terminal connected to the other one of the balanced signals;
A third field effect transistor having a source terminal connected to a drain terminal of the first field effect transistor and a gate terminal biased to a second potential;
A fourth field effect transistor having a source terminal connected to a drain terminal of the second field effect transistor and a gate terminal biased to the second potential;
An output line for connecting the drain terminal of the third field effect transistor and the drain terminal of the fourth field effect transistor to output an output signal;
N (n is an integer greater than or equal to 1) signal output units configured to include:
A signal adder connected to each of the output lines of the n signal output units and outputting a signal proportional to the sum of the output signals output from the output lines of the n signal output units; ,
An electronic circuit comprising:   4. The electronic circuit according to claim 3, wherein the signal adding unit includes a field effect transistor having a gate terminal biased to a third potential.   An electronic device comprising the electronic circuit according to claim 1.   The electronic apparatus according to claim 5, wherein the electronic apparatus includes a signal processing unit that detects a pulse carried by a supplied UWB signal. The electronic device according to claim 5 or 6,
The electronic device is
A template signal generator for generating first and second signals orthogonal to each other;
A first multiplier that outputs a first multiplied signal obtained by multiplying the first signal and the received signal;
A second multiplier that outputs a second multiplied signal obtained by multiplying the second signal and the received signal;
A first low-frequency extraction circuit for removing a high-frequency component from the first multiplication signal and outputting a first low-frequency signal;
A second low-frequency extraction circuit that removes high-frequency components from the second multiplication signal and outputs a second low-frequency signal;
An electronic device comprising: A template signal generator for generating first and second signals orthogonal to each other;
A first multiplier that outputs a first multiplied signal obtained by multiplying the first signal and the received signal;
A second multiplier that outputs a second multiplied signal obtained by multiplying the second signal and the received signal;
A first low-frequency extraction circuit for removing a high-frequency component from the first multiplication signal and outputting a first low-frequency signal;
A second low-frequency extraction circuit that removes high-frequency components from the second multiplication signal and outputs a second low-frequency signal;
An electronic circuit according to any one of claims 1 to 4,
A method for detecting a pulse of an electronic device comprising:
The first low-frequency signal and the second low-frequency signal are square sum output by the electronic circuit to detect a pulse,
A method for detecting a pulse of an electronic device.   9. The pulse detection method for an electronic device according to claim 8, wherein a pulse carried by the supplied UWB signal is detected.

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