US6617889B1 - Signal amplitude comparator - Google Patents
Signal amplitude comparator Download PDFInfo
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- US6617889B1 US6617889B1 US10/156,963 US15696302A US6617889B1 US 6617889 B1 US6617889 B1 US 6617889B1 US 15696302 A US15696302 A US 15696302A US 6617889 B1 US6617889 B1 US 6617889B1
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- transistor
- comparator
- signal amplitude
- differential input
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
Definitions
- the present invention generally relates to methods and devices for detecting the presence or absence of high frequency signals in a system, and more specifically relates to a signal amplitude comparator.
- Dual differencing amplifiers have been applied to signal processing and comparison tasks with good success. However, at high frequencies, it is difficult to get good performance.
- a general object of an embodiment of the present invention is to provide a signal amplitude comparator which is configured to generate an output that accurately determines presence of a signal with a repeatable amount of amplitude.
- Another object of an embodiment of the present invention is to provide a differential input circuit that is configured to generate an output current that is a non-linear function of an input voltage, and is configured to produce even order harmonic distortion over an input voltage range of interest.
- an embodiment of the present invention provides a signal amplitude comparator which includes a first differential input circuit that is biased, is configured to receive an input voltage and is configured to generate a first output current that is a non-linear function of the input voltage, a second differential input circuit which is biased similarly to the first differential input circuit, is configured to receive a reference input voltage and is configured to generate a second output current that generally tracks process, temperature and supply variation, and a comparator which is connected to the first differential input circuit and the second differential input circuit and is configured to receive the first output current from the first differential input circuit and the second output current from the second differential input circuit.
- the comparator is configured to compare the first and second output currents and generate an output which indicates whether the input voltage exceeds a pre-determined threshold value.
- FIG. 1 is a schematic drawing of a signal amplitude comparator which is in accordance with an embodiment of the present invention
- FIG. 2 is a block diagram of a full-wave poly-phase signal amplitude comparator which is in accordance with an embodiment of the present invention.
- FIG. 3 is a block diagram of a poly-phase signal amplitude comparator which is in accordance with an embodiment of the present invention.
- FIG. 1 illustrates a signal amplitude comparator 10 which is in accordance with an embodiment of the present invention. Many aspects of what is shown in FIG. 1 would be readily understood by one having ordinary skill in the art while reviewing FIG. 1 . Those aspects of FIG. 1 which directly relate to the present invention are described hereinbelow.
- the signal amplitude comparator 10 is configured to generate an output 12 that accurately determines presence of a signal with a repeatable amount of amplitude.
- the signal amplitude comparator 10 includes a first differential input circuit 14 and a second differential input circuit 16 which is effectively a replica of the first differential input circuit 14 .
- Each differential input circuit consists of a pair of input circuits.
- the first differential input circuit 14 is configured to receive an input voltage 20 , and consists of two asymmetrical differential transistor pairs, a first pair which consists of transistor 22 and 24 , wherein transistor 24 is biased so that it is in saturation for all signal levels where an accurate comparison is required.
- Transistors 26 and 28 form an opposing, second coupled transistor pair which is biased in an identical matter.
- the drains of transistors 22 and 28 are connected together and form the output 30 of the first differential input circuit 14 . All input and reference devices are built from multiple legs of width W/L; best practices for device matching should be followed.
- the first differential input circuit 14 is configured to generate an output current that is a non-linear function of the input voltage.
- the width ratio of 24 to 22 set by the ratio of the number of legs, determines the non-linearity of the transfer function; if 24 is much, much wider than 22 , the transfer function will approach the natural transfer function of the device, which in the case of a FET, will be square-law. For smaller width ratios, a more linear transfer function is given. It is expected that, for most cases, a ratio of 8:1 will work well. While higher ratios will generally provide better performance, higher ratios also generally require greater power levels. Smaller ratios tend to be more linear, and this reduces the output signal level.
- the second differential input circuit 16 is configured to receive a reference input voltage 32 which may be a direct current voltage source or an alternating current voltage source. Like the first differential input circuit 14 , the second differential input circuit 16 consists of two asymmetrical differential transistor pairs. A first pair consists of transistors 34 and 36 , wherein transistor 36 is biased so that it is in saturation for all signal levels expected. Transistors 38 and 40 form an opposing, second coupled transistor pair which is biased in an identical matter. The drains of transistors 34 and 40 are connected together and form the output 50 of the second differential input circuit 16 . The output 50 is a current that generally tracks process, temperature and supply variation.
- the signal amplitude comparator 10 includes a comparator or comparison circuit 52 which is connected to the first differential input circuit 14 and second differential input circuit 16 .
- the comparator 52 is configured to receive the outputs 30 , 50 from the first differential input circuit 14 and second differential input circuit 16 and compare the signals to determine whether the input voltage 20 exceeds a pre-determined threshold value.
- the comparator 52 may consist of a plurality of transistors 54 , 56 , 58 , 60 , 62 and 64 .
- the signal amplitude comparator 10 also preferably includes a filter or filtering circuit 66 which consists of a transistor 68 .
- the signal amplitude comparator 10 can be configured such that the first differential input circuit 14 generates an output current 30 that is a non-linear function of the input voltage 20 and produces even order harmonic distortion over the input voltage range of interest.
- Input capacitance is primarily related to the size of transistors 22 and 28 .
- the other transistors in the differential input circuit 14 i.e., transistors 24 and 26 , act primarily as source followers and do not contribute, relative to their size, to the input capacitance. Offset performance is a function of the size of the smaller device as well. Each process has a different sensitivity to offsets, so the devices must be scaled accordingly.
- the signal amplitude comparator 10 can use an alternating current voltage as well as a direct current voltage for a reference 32 . If the reference and measured signal voltages have similar waveshapes, the accuracy with respect to the reference signal will be very good. If, as in the case for the actual application, the waveforms do not match, it can only be determined that the input has met the threshold based on the waveshape which are expected.
- transistor 22 is connected common-source to transistor 24 .
- the common source connection tends to track the VINM input ( 70 ) but offset by a Vt.
- transistor 22 IS Much smaller than transistor 24 , the current in transistor 22 can vary considerably without upsetting the operation of transistor 24 .
- transistor 22 operates primarily as a square law device generating an output current that varies with VINP ( 72 ) minus VINM ( 74 ) squared up to the point where transistor 22 gets cut-off. This does not generally affect the circuit operation.
- a suitable threshold voltage such as a direct current voltage
- oppositely connected signal path input differential pairs be used, so at the time one side gets cut-off, the other side is generating a strong squared signal.
- the reference differential pair 16 is configured to generate an output current that tracks the process, temperature and supply variation. So, for example, if k-prime drops due to a higher on-chip temperature, the output 50 from the reference 16 drops also moving the actual reference back to the same relative place it was.
- the two currents 30 and 50 are compared in the output stage and filtered by filter 66 .
- the output voltage difference VOP ( 78 ) minus VOM ( 80 ) goes positive indicating that the signal has crossed the threshold.
- FIG. 2 illustrates a poly-phase signal amplitude comparator 10 a which is similar to that which is shown in FIG. 1, and is in accordance with an embodiment of the present invention.
- the poly-phase signal amplitude comparator 10 a includes an input circuit 14 , a reference circuit or scaled reference circuit 16 , a comparison circuit 52 and a filter 66 much like the signal amplitude comparator 10 shown in FIG. 1 .
- the poly-phase signal amplitude comparator 10 a includes an additional input circuit 14 a (or two additional input circuits 14 a and 14 b (shown in phantom) if a three-phase detector is desired) and an additional reference circuit 16 a. Additional input circuits and reference circuits or reference scaling can be added for higher order poly-phase operation.
- input circuit 14 a receives input 20 a and outputs output 30 a (and input circuit 14 b, if provided, receives input 20 b and outputs output 30 b ).
- input circuits 14 , 14 a (and 14 b if provided) are “full wave”.
- both the input circuits and the reference circuit can be provided as being “half wave”, and may be provided as shown in FIG. 3 .
- the second differential input circuit 14 a receives input 20 a and produces a second output 30 a that is summed with output 30 (and with output 30 b, if input circuit 14 b is provided).
- the composite output 30 + 30 a (or 30 + 30 a + 30 b, if input circuit 14 b is provided) is compared with the reference current 50 in the comparator 52 and is filtered by filter 66 .
- the inputs 20 and 20 a (and 20 b if input circuit 14 b is provided) are sinusoidal and have a relationship in phase such that 20 and 20 a (and 20 b, if reference circuit 14 b is provided) are 90 degrees apart, the identity sin squared plus cosine squared equals one can be applied.
- the reference will now represent the peak of the poly-phase source 20 , 20 a (or 20 , 20 a and 20 b , if input circuit 14 b is provided) without scaling.
- This configuration or the logical extension of it represents a poly-phase signal amplitude comparator.
- the second reference circuit 16 a provides reference output 50 a from input 32 a .
- the reference 50 + 50 a and signal 30 + 30 a will be compared in a single comparison circuit 52 and will be filtered by 66 .
- the third input circuit 14 b and reference 16 b both of which are shown in phantom in FIG. 2) can be added, and a three-phase detector is the result. If the reference is a direct current voltage, the multiple reference circuits can be combined in the poly-phase case to give a single appropriately scaled reference circuit.
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Manipulation Of Pulses (AREA)
Abstract
Description
Claims (20)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/156,963 US6617889B1 (en) | 2002-05-29 | 2002-05-29 | Signal amplitude comparator |
US10/207,943 US6664816B1 (en) | 2002-05-29 | 2002-07-30 | Signal amplitude comparator |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/156,963 US6617889B1 (en) | 2002-05-29 | 2002-05-29 | Signal amplitude comparator |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US10/207,943 Continuation-In-Part US6664816B1 (en) | 2002-05-29 | 2002-07-30 | Signal amplitude comparator |
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US6617889B1 true US6617889B1 (en) | 2003-09-09 |
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US10/156,963 Expired - Lifetime US6617889B1 (en) | 2002-05-29 | 2002-05-29 | Signal amplitude comparator |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080061842A1 (en) * | 2006-09-07 | 2008-03-13 | Micron Technology, Inc. | Circuit and method for detecting timed amplitude reduction of a signal relative to a threshold voltage |
US20080084956A1 (en) * | 2006-09-18 | 2008-04-10 | Milam Paraschou | Absolute value peak differential voltage detector circuit and method |
CN114337709A (en) * | 2021-12-31 | 2022-04-12 | 湖南国科微电子股份有限公司 | Differential signal receiver |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4931797A (en) * | 1987-11-11 | 1990-06-05 | Matsushita Electric Industrial Co., Ltd. | Folding circuit and serial-type A/D converter |
US6064240A (en) * | 1997-02-28 | 2000-05-16 | Siemens Aktiengesellschaft | Comparator circuit with low current consumption |
US6229350B1 (en) * | 1997-12-30 | 2001-05-08 | Texas Instruments Incorporated | Accurate, fast, and user programmable hysteretic comparator |
US6448821B1 (en) * | 2000-02-25 | 2002-09-10 | National Semiconductor Corporation | Comparator circuit for comparing differential input signal with reference signal and method |
-
2002
- 2002-05-29 US US10/156,963 patent/US6617889B1/en not_active Expired - Lifetime
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4931797A (en) * | 1987-11-11 | 1990-06-05 | Matsushita Electric Industrial Co., Ltd. | Folding circuit and serial-type A/D converter |
US6064240A (en) * | 1997-02-28 | 2000-05-16 | Siemens Aktiengesellschaft | Comparator circuit with low current consumption |
US6229350B1 (en) * | 1997-12-30 | 2001-05-08 | Texas Instruments Incorporated | Accurate, fast, and user programmable hysteretic comparator |
US6448821B1 (en) * | 2000-02-25 | 2002-09-10 | National Semiconductor Corporation | Comparator circuit for comparing differential input signal with reference signal and method |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080061842A1 (en) * | 2006-09-07 | 2008-03-13 | Micron Technology, Inc. | Circuit and method for detecting timed amplitude reduction of a signal relative to a threshold voltage |
US20080084956A1 (en) * | 2006-09-18 | 2008-04-10 | Milam Paraschou | Absolute value peak differential voltage detector circuit and method |
US7560959B2 (en) | 2006-09-18 | 2009-07-14 | Micron Technology, Inc. | Absolute value peak differential voltage detector circuit and method |
CN114337709A (en) * | 2021-12-31 | 2022-04-12 | 湖南国科微电子股份有限公司 | Differential signal receiver |
CN114337709B (en) * | 2021-12-31 | 2023-07-14 | 湖南国科微电子股份有限公司 | Differential signal receiver |
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