JP2009272913A - Electronic circuit, electronic device having electronic circuit, and pulse detection method of electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a square detection circuit whose circuit is simple and whose stability is high. <P>SOLUTION: This electronic circuit 1 includes: a current output part 120 including an input terminal 101, a balance-unbalance converter 102 which outputs a balance signal and an unbalance signal from a signal input from the input terminal 101, a first field effect transistor 103 whose gate terminal is connected to the balance signal, and whose source terminal is grounded, a second field effect transistor 104 whose gate terminal is connected to the unbalance signal, and whose source terminal is grounded, and an output terminal 112 which mutually connects a drain terminal of the first field effect transistor 103 and a drain terminal of the second field effect transistor 104 to output drain current; and a current addition part 121 which is connected to an output line 113 of the power output part 120 to output added current obtained by adding the drain current to be output from the current output part 120. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an electronic circuit, an electronic device including the electronic circuit, and more particularly to an electronic device that receives a UWB (Ultra Wide Band) signal and a pulse detection method for the electronic device.

  A circuit for detecting an envelope of a received signal and demodulating a baseband signal has been used for a long time, and various circuits have been devised. The envelope is obtained by connecting peak values and smoothing the absolute value of the AC component. Also, a method of squaring and smoothing a signal and replacing it with envelope detection has been known for a long time, and is called “square detection” or the like. For example, Patent Document 1 describes a square detection circuit for obtaining a square value of a signal and an amplitude detection method using the square detection circuit.

  In addition, there is a receiver using envelope detection in UWB signal, particularly UWB communication (hereinafter referred to as “UWB-IR” communication) using IR (Impulse Radio) that does not use a carrier wave, for example, Patent Document 2 or Patent Document 3 Describes its effectiveness. In these Patent Documents 2 and 3, a rectifier circuit and an integrating circuit are used, which obtains an envelope by smoothing the absolute value of the AC component of the signal. Hereinafter, the operation of detecting the envelope of a modulated carrier wave (a high-frequency signal whose amplitude changes with time) will be referred to as “envelope detection”. In addition, there is no example using the square wave detection in the UWB-IR receiver.

JP-A-4-170807 JP 2004-320083 A JP 2005-252740 A

  However, the conventional square detection circuit of Patent Document 1 uses bipolar transistors and does not use MOS transistors suitable for large-scale integration. Further, the square characteristic can be obtained approximately only when a small signal whose signal current change is sufficiently small compared to the collector current is input, and there is a problem that an error occurs with a large signal. When trying to handle a large signal, the power consumption inevitably increases. Furthermore, the operation speed of the circuit is not so fast, and it is not suitable for handling a signal having a frequency as high as the performance limit of an element such as a UWB-IR signal. In addition, when there is no function for obtaining the sum of squares of a plurality of signals and demodulation is performed down to baseband by frequency conversion, highly accurate phase synchronization is required.

As is well known, the drain current of a field effect transistor is proportional to the square of the difference between the gate voltage and the threshold voltage when the operating region is in the saturation region. In other words, the relationship between the drain current Id and the gate voltage Vg is as follows.
Id = (1/2) β (Vg−Vt) ² (Formula 1)
It becomes.

Therefore, it is possible to obtain the square value of the signal using the relationship of (Equation 1) of the field effect transistor. That is, if the input signal vi is biased with Vb and adjusted so that Vb = Vt,
Id = (1/2) β (Vb + vi−Vt) ² = (1/2) vi ² (Equation 2)
Thus, the square value of the input signal can be obtained.

However, in this case, it is difficult to stably bias so that Vb = Vt. If Vb ≠ Vt,
Id = (1/2) vi ² + vi (Vb−Vt) + (1/2) (Vb−Vt) ² (Equation 3)
Thus, vi (Vb−Vt) and (½) (Vb−Vt) ² in (Equation 3) are errors. Since (1/2) (Vb−Vt) ² is a direct current component, it can be easily eliminated by a capacitor, but vi (Vb−Vt) is difficult to remove.

  Further, Vt also changes with respect to fluctuations in temperature and power supply voltage due to the presence of a minute current that does not follow (Equation 1) called tailing or the like. Further, at the bias point where Vb = Vt, if Id is an extremely small operation region and the input signal is very small, the operation becomes extremely unstable.

  In addition, both Patent Document 2 and Patent Document 3 disclose only a fundamental proposal for UWB-IR communication, and various problems that cannot be overcome in actual implementation, and their solutions. No measures are disclosed.

  The problem with the prior art is that an envelope detection circuit that functions effectively for high-frequency signals (steep and instantaneous pulses) as applied to UWB-IR communication cannot be realized.

  Patent Document 2 exemplifies a circuit example using an envelope detection circuit including an operational amplifier circuit and a PN junction diode. However, it is difficult for a circuit using a PN junction diode to be on-chip by a CMOS semiconductor process frequently used in one-chip UWB analog front ends. It is almost impossible to detect the envelope by rectification.

  In UWB, high frequency that reaches the limit of device performance is used, whereas the maximum operable speed of the operational amplifier circuit is a fraction of the limit frequency of device performance, and the operation speed is absolutely insufficient. is there. Furthermore, this type of conventional full-wave rectifier circuit does not operate well unless the input signal is sufficiently large compared to the signal level received by the receiver. It is almost impossible to detect a signal with a peak value of about several mV obtained by amplifying a received signal obtained from an antenna with a pre-low noise amplifier circuit, and measures such as increasing the amplification factor of pre-amplification are available. Although necessary, this also involves difficulties such as high frequency, system complexity, and increased power consumption.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

[Application Example 1]
A first field effect transistor having one of the balanced signals connected to the gate terminal and the source terminal grounded, and a second electric field having the other one connected to the gate terminal grounded and the source terminal grounded An n-type transistor including an effect transistor, and an output terminal for connecting a drain terminal of the first field effect transistor and a drain terminal of the second field effect transistor to output a drain current. (N is an integer greater than or equal to 1) current output units and n output terminals of the n current output units are connected to the sum of the drain currents output from the n current output units. And an electric current adder that outputs a proportional signal.

  According to this configuration, a signal proportional to the square of the signal input to the gate can be taken out by the square characteristic of the field effect transistor. The electronic circuit is composed of a field effect transistor and does not use a PN junction, and can be formed on-chip by a normal CMOS semiconductor process. The circuit configuration is extremely simple, and furthermore, high-frequency and high-speed operation of the limit frequency of the MOS transistor is possible, and application to a system that requires high-speed operation such as IR communication becomes possible. In addition, a square circuit that can be easily integrated can be realized.

[Application Example 2]
In the electronic circuit described above, the electronic circuit is connected between the output terminal of the n current output units and the current adding unit, and a gate terminal is grounded through a first bias voltage. An electronic circuit including m (m is an integer of 1 to n) third field effect transistors.

  According to this configuration, since the cascode stage that amplifies the output value by the third field effect transistor is included, the output impedance can be increased, and a high gain circuit with a large load impedance can be realized. Further, the output side and the input side can be shielded by the cascode stage to reduce the mirror effect, and operation at a higher frequency is possible.

[Application Example 3]
One of the balanced signals is connected to the source terminal, the first field effect transistor whose gate terminal is grounded via the second bias voltage, and the other one of the unbalanced signals is connected to the source terminal, and the gate A second field effect transistor having a terminal grounded via the second bias voltage, a drain terminal of the first field effect transistor, and a drain terminal of the second field effect transistor are mutually connected. An output terminal connected to output drain current, and connected to n (n is an integer of 1 or more) current output units, and n output terminals of the n current output units. And an electric current adder that outputs a signal proportional to the sum of the drain currents output from the n current output units.

  According to this configuration, a signal proportional to the square of the signal input to the source can be extracted by the square characteristic of the grounded gate circuit using the field effect transistor. The grounded gate circuit can constitute an amplifier circuit having a good frequency characteristic with a low input impedance and a high output impedance. The electronic circuit is composed of a field effect transistor and does not use a PN junction, and thus can be formed on-chip by a normal CMOS semiconductor process. The circuit configuration is extremely simple, and furthermore, high-frequency and high-speed operation of the limit frequency of the MOS transistor is possible, and application to a system that requires high-speed operation such as IR communication becomes possible. In addition, a square circuit that can be easily integrated can be realized.

[Application Example 4]
In the electronic circuit described above, the electronic circuit is connected between the output terminal of the n current output units and the current adding unit, and a gate terminal is grounded through a first bias voltage. An electronic circuit including m (m is an integer of 1 to n) third field effect transistors.

  According to this configuration, since the cascode stage that amplifies the output value by the third field effect transistor is included, the output impedance can be increased, and a high gain circuit with a large load impedance can be realized.

[Application Example 5]
An electronic device comprising the electronic circuit described above.

  According to this configuration, the square value of the signal can be easily detected by the electronic circuit. In addition, a simple and low-power electronic device such as a receiving device using square detection can be realized.

[Application Example 6]
In the electronic device described above, the electronic device includes a signal processing unit that detects a pulse carried by a supplied UWB signal.

  According to this configuration, the square value of the signal can be easily detected by the electronic circuit. In particular, a simple and low-power electronic device can be realized by a receiving device that detects a pulse carried by a UWB signal.

[Application Example 7]
In the electronic device described above, the electronic device includes a template signal generator that generates a first signal and a second signal orthogonal to each other, and a first multiplication obtained by multiplying the first signal and the received signal. A first multiplier that outputs a signal; a second multiplier that outputs a second multiplied signal obtained by multiplying the second signal by the received signal; and a high-frequency component is removed from the first multiplied signal. A first low-pass filter that outputs the first low-pass filtered signal, and a second low-pass filter that outputs a second low-pass filtered signal obtained by removing high-frequency components from the second multiplied signal. An electronic device comprising: a pass filter.

  According to this configuration, by multiplying two orthogonal template signals (the first signal and the second signal) and the received signal, and removing the high frequency component and blocking the high frequency, the correlation between each template and the received signal is obtained. A value is obtained. Since the sum of the squares of these correlation values is the square of the absolute value of the received signal, the absolute value of the received signal can be known. In this case, exact synchronization with the carrier of the received signal is not necessary. Since the sum of the squares of the correlation values can be easily obtained by the electronic circuit described above, the amplitude of the signal can be obtained without accurate synchronization with the carrier wave, and a square detection receiver can be simply configured.

[Application Example 8]
A template signal generator for generating a first signal and a second signal orthogonal to each other; a first multiplier for outputting a first multiplied signal obtained by multiplying the first signal by a received signal; A second multiplier that outputs a second multiplied signal obtained by multiplying the received signal by the second signal, and a first low-pass filtered signal obtained by removing high-frequency components from the first multiplied signal. 1 low-pass filter, a second low-pass filter that outputs a second low-pass filtered signal obtained by removing high-frequency components from the second multiplication signal, and the electronic circuit described above, A method for detecting a pulse of an electronic device comprising: the first low-pass filtered signal and the second low-pass filtered signal are square sum output by the electronic circuit to detect a pulse. A method for detecting a pulse of an electronic device.

  According to this configuration, by multiplying two orthogonal template signals (the first signal and the second signal) and the received signal, and removing the high frequency component and blocking the high frequency, the correlation between each template and the received signal is obtained. A value is obtained. Since the sum of the squares of these correlation values is the square of the absolute value of the received signal, the absolute value of the received signal can be known. In this case, exact synchronization with the carrier of the received signal is not necessary. Since the sum of the squares of the correlation values can be easily obtained by the electronic circuit, the amplitude of the signal can be obtained without accurate synchronization with the carrier wave, and pulse detection can be performed.

[Application Example 9]
The pulse detection method for an electronic device according to the above, wherein the pulse carried by the supplied UWB signal is detected.

  According to this configuration, since the occupied frequency band of the signal is extremely wide in UWB-IR, the frequency accuracy of the template signal may not be high. In addition, neither accurate phase synchronization nor frequency synchronization of the carrier wave is required, and UWB-IR pulse detection can be easily performed.

  Hereinafter, embodiments of an electronic circuit will be described with reference to the drawings.

(First embodiment)
<Configuration of electronic circuit>
First, the configuration of the electronic circuit according to the first embodiment will be described with reference to FIG. FIG. 1 is a circuit diagram showing a configuration of an electronic circuit according to the first embodiment.

  As shown in FIG. 1, the electronic circuit 1 includes n = 1 current output units 120 and a current addition unit 121. The current output unit 120 includes a balance-unbalance transformer (BALUN) 102, an NMOS transistor 103 that is a first field effect transistor, and an NMOS transistor that is a second field effect transistor. 104, capacitors 105 and 106, resistors 107 and 108, and a bias power source 109.

  The unbalanced signal input to the input terminal 101 is input to the balun 102, separated into two balanced signals, and output. One of the balanced signals is applied to the gate terminal of the NMOS transistor 103 via the capacitor 105, and the other one of the balanced signals is applied to the gate terminal of the NMOS transistor 104 via the capacitor 106. The gate terminal of the NMOS transistor 103 is connected to the bias power source 109 via the resistor 107, and the gate terminal of the NMOS transistor 104 is connected to the bias power source 109 via the resistor 108. The source terminals of the NMOS transistors 103 and 104 are grounded, and the drain terminals are connected to the output line 113. The NMOS transistors 103 and 104 may be constituted by PMOS transistors with the polarities of the power supply and bias power supply reversed.

  The current adding unit 121 includes a resistor 110 connected between the output line 113 and the power supply voltage line 111, and the drain current flowing through the output line 113 generated by the current output unit 120 flows through the resistor 110 to generate a voltage. And output from the output terminal 112. The power supply voltage applied to the power supply voltage line 111 is set to VDD. The current adding unit 121 can convert the added value of the currents of the plurality (n) of current output units 120 into a voltage and output the voltage. As an example, the case where n = 2 will be described in detail in the fifth embodiment.

The NMOS transistors 103 and 104 have channel width W, channel length L, transistor carrier mobility μ, gate capacitance C per unit area, source-drain applied voltage Vd, source-gate applied voltage Vg, and threshold voltage Vt. The drain current Id flowing through the transistors 103 and 104 is Vd ≧ Vg−Vt,
Id = (1/2) μC (W / L) (Vg−Vt) ² (Formula 4)
When Vd ≦ Vg−Vt,
Id = (1/2) μC (W / L) Vd {2 (Vg−Vt) −Vd} (Formula 5)
It becomes.

  Since the carrier mobility is different between the PMOS transistor and the NMOS transistor, the drain current that can be flowed with respect to the same applied voltage is usually larger in the NMOS transistor in the transistors of the same size. By adjusting W / L, it is possible to balance the PMOS transistor and the NMOS transistor. The ability of the drain current that can flow with respect to the applied voltage is determined by β = μC (W / L).

  The bias voltage of the bias power supply 109 is set to Vb, converted by the balun 102, passed through the capacitor 105, applied to the gate terminal of the NMOS transistor 103, + vi, passed through the capacitor 106, and applied to the gate terminal of the NMOS transistor 104. Let the voltage be -vi. If the power supply voltage VDD is set sufficiently higher than the bias voltage Vb, the NMOS transistors 103 and 104 can be operated at Vd ≧ Vg−Vt, and (Equation 4) can be applied. Hereinafter, it is assumed that the power supply voltage VDD and the bias voltage Vb are set so that the NMOS transistors 103 and 104 operate within the applicable range of (Equation 4).

When the drain current of the NMOS transistor 103 is Id1, and the drain current of the NMOS transistor 104 is Id2,
Id1 = (1/2) β (Vb + vi−Vt) ² (Formula 6)
Id2 = (1/2) β (Vb−vi−Vt) ² (Expression 7)
Holds.

Therefore, the current I0 flowing through the resistor 110 is
I0 = Id1 + Id2 = β {vi ² + (Vb−Vt) ² } (Equation 8)
It becomes.

(Expression 8) (Vb−Vt) ^{2 on the} right side is a DC component, and if only the change is extracted, the square value of the input signal vi can be extracted. In the conventional technique according to (Equation 1), vi (Vb−Vt) remains as an error in addition to the DC component, but the electronic circuit 1 according to (Equation 8) does not include such an error that cannot be excluded. Therefore, the bias voltage Vb does not need to be exactly equal to the threshold voltage Vt as in the conventional example. The DC component of (Vb−Vt) ² can be easily eliminated by the capacitor. Regardless of how the bias voltage Vb is selected, only a DC component that can be easily eliminated remains as an error term, so that the NMOS transistors 103 and 104 can be set in a stable operating region. In particular, when noise characteristics are concerned, noise depending on the drain current such as shot noise can be reduced by adjusting the bias voltage Vb.

  According to the present embodiment described above, the following effects can be obtained.

  The electronic circuit 1 for obtaining the square value of the input signal according to the present embodiment has a feature that it can be formed on-chip by a semiconductor process because it can be configured by a field effect transistor, and in particular, the limit frequency of the field effect transistor. Therefore, it can be applied to a system that requires high-speed operation such as IR communication. Thereby, a demodulator circuit and a pulse detection circuit of a receiver that can be easily integrated can be realized.

  In order to obtain input signals having the same amplitude and opposite polarities, the balun 102 is used in this embodiment, but the present invention is not limited to this. The signal obtained from the balanced antenna and the output signal obtained from the differential amplifier satisfy the above conditions, so that the balun 102 can be omitted. Further, when the output signal is shifted by an appropriate DC value depending on the operation level of the differential amplifier output, the capacitors 105 and 106, the resistors 107 and 108, and the bias power supply 109 can be omitted.

(Second Embodiment)
Next, the configuration of the electronic circuit according to the second embodiment will be described with reference to FIG. FIG. 2 is a circuit diagram showing a configuration of an electronic circuit according to the second embodiment.

  As shown in FIG. 2, in the electronic circuit 2, m = 1 in which the gate terminal is grounded via the bias power source 202 that supplies the first bias voltage between the output line 113 of the current output unit 120 and the resistor 110. It is configured by connecting a common-gate amplification section 122 composed of an NMOS transistor 201 which is a third field effect transistor.

Due to the action of the NMOS transistor 201, the sum of the drain currents of the NMOS transistors 103 and 104 subtracts the shunt due to the drain output resistance of the NMOS transistors 103 and 104, thereby boosting the gain. The output impedance becomes higher, and the sum of the drain currents of the NMOS transistors 103 and 104 can be taken out more accurately even when the resistance 110 and the load fluctuation increase.
In this electronic circuit 2, by making cascade connection with the NMOS transistor 201, it is possible to detect the square value of the signal while amplifying even a weak signal. Furthermore, any element used can be made on-chip by a semiconductor process, and high-frequency and high-speed operation at the limit frequency of the element is possible, so that it can be applied to systems that require high-speed operation such as IR communication. Become. As a result, a pulse detection circuit that can be easily integrated can be realized.

(Third embodiment)
Next, the configuration of the electronic circuit according to the third embodiment will be described with reference to FIG. FIG. 3 is a circuit diagram showing a configuration of an electronic circuit according to the third embodiment.

  As shown in FIG. 3, the electronic circuit 3 includes n = 1 current output units 320 and current addition units 321. The current output unit 320 includes a balun 302, NMOS transistors 303 and 304, capacitors 305 and 306, resistors 307 and 308, and a bias power supply 309.

  The unbalanced signal input to the input terminal 301 is input to the balun 302, separated into two balanced signals, and output. One of the balanced signals is applied to the source terminal of the NMOS transistor 303 via the capacitor 305, and the other one of the balanced signals is applied to the source terminal of the NMOS transistor 304 via the capacitor 306. A bias power supply 309 is connected to the gate terminal of the NMOS transistor 303 and the gate terminal of the NMOS transistor 304. The source terminal of the NMOS transistor 303 is grounded via a resistor 307, and the source terminal of the NMOS transistor 304 is grounded via a resistor 308. The drain terminals of the NMOS transistors 303 and 304 are connected to the output line 313. The NMOS transistors 303 and 304 may be configured by PMOS transistors with the polarities of the power supply and bias power supply reversed.

  The current adding unit 321 is configured by a resistor 310 connected between the output line 313 and the power supply voltage line 311, and the drain current flowing through the output line 313 generated by the current output unit 320 is caused to flow through the resistor 310. And output from the output terminal 312. The power supply voltage applied to the power supply voltage line 311 is assumed to be VDD. The current adding unit 321 can convert the added value of the currents of the plurality (n) of current output units 320 into a voltage and output the voltage. For example, the case of n = 2 will be described in detail in the sixth embodiment.

  The bias voltage of the bias power supply 309 is assumed to be Vb. Further, the voltage converted by the balun 302 and passing through the capacitor 305 and applied to the source terminal of the NMOS transistor 303 is + vi, and the voltage passing through the capacitor 306 and applied to the source terminal of the NMOS transistor 304 is −vi. If the power supply voltage VDD is set sufficiently higher than the bias voltage Vb, the NMOS transistors 303 and 304 can be operated at Vd ≧ Vg−Vt, and (Equation 4) can be applied. Hereinafter, it is assumed that the power supply voltage VDD and the bias voltage Vb are set so that the NMOS transistors 303 and 304 operate within the applicable range of (Equation 4).

When the drain current of the NMOS transistor 303 is Id1, and the drain current of the NMOS transistor 304 is Id2, Id1 = (1/2) β (Vb−vi−Vt) ² (Equation 9)
Id2 = (1/2) β (Vb + vi−Vt) ² (Equation 10)
Holds.

Therefore, the current I0 flowing through the resistor 310 is
I0 = Id1 + Id2 = β {vi ² + (Vb−Vt) ² } (Formula 11)
It becomes.

(Equation 11) (Vb−Vt) ^{2 on the} right side is a DC component, and the square value of the input signal vi can be extracted by extracting only the change. In the conventional technique according to (Expression 1), vi (Vb−Vt) remains as an error in addition to the DC component, but in the case of the third embodiment according to (Expression 11), such an error that cannot be excluded is included. Absent. Therefore, the bias voltage Vb does not need to be exactly equal to the threshold voltage Vt as in the conventional example. The DC component of (Vb−Vt) ² can be easily eliminated by the capacitor. Regardless of how the bias voltage Vb is selected, only a direct current component that can be easily eliminated remains as an error term, so that the NMOS transistors 303 and 304 can be set in a stable operating region. In particular, when noise characteristics are concerned, noise depending on the drain current such as shot noise can be reduced by adjusting the bias voltage Vb.

  The electronic circuit 3 of the third embodiment can be regarded as a wired-or connection of a grounded-gate amplifier circuit. The low input impedance characteristic that is a feature of the common-gate amplifier circuit facilitates matching design of the input circuit.

  The electronic circuit 3 for obtaining the square value of the signal according to the third embodiment has a feature that it can be formed on-chip by a semiconductor process because it can be constituted by a field effect transistor, and in particular, the limit frequency of the field effect transistor. Therefore, it can be applied to a system that requires high-speed operation such as IR communication. As a result, a demodulator circuit and a pulse detection circuit of a receiver that can be easily integrated can be realized.

  In order to obtain input signals having the same amplitude and opposite polarities, the balun 302 is used in the third embodiment, but the present invention is not limited to this. The signal obtained from the balanced antenna and the output signal obtained from the differential amplifier satisfy the above conditions, so that the balun 302 can be omitted. Further, when a DC component is not included as in the output signal of the balanced antenna, the capacitors 305 and 306 and the resistors 307 and 308 can be omitted.

(Fourth embodiment)
Next, the configuration of the electronic circuit according to the fourth embodiment will be described with reference to FIG. FIG. 4 is a circuit diagram showing a configuration of an electronic circuit according to the fourth embodiment.

  As shown in FIG. 4, in the electronic circuit 4, m = 1 in which the gate terminal is grounded via the bias power source 402 that supplies the second bias voltage between the output line 313 of the current output unit 320 and the resistor 310. It is configured by connecting a common gate amplifying unit 322 composed of an NMOS transistor 401 which is a third field effect transistor.

  The sum of the drain currents of the NMOS transistors 303 and 304 is boosted by reducing the shunting caused by the drain output resistance of the NMOS transistors 303 and 304 by the action of the NMOS transistor 401. The output impedance becomes higher, and the sum of the drain currents of the NMOS transistors 303 and 304 can be taken out more accurately even when the resistance 310 and the load fluctuation increase.

  In this electronic circuit 4, the cascade value of the NMOS transistor 401 allows the detection of the square value of the signal while amplifying even a weak signal. Furthermore, any element used can be made on-chip by a semiconductor process, and high-frequency and high-speed operation at the limit frequency of the element is possible, so that it can be applied to systems that require high-speed operation such as IR communication. Become. As a result, a pulse detection circuit that can be easily integrated can be realized.

(Fifth embodiment)
Next, the configuration of the electronic circuit according to the fifth embodiment will be described with reference to FIG. FIG. 5 is a circuit diagram showing a configuration of an electronic circuit according to the fifth embodiment. The fifth embodiment shows a case of a square sum circuit in which n = 2 current output units 120 in FIG. 1 are connected in parallel to a current adder unit 121.

  As shown in FIG. 5, the electronic circuit 5 includes current output units 522 and 523 that are the current output unit 120 of FIG. 1, and a current addition unit 521. The current output units 522 and 523 have input terminals 524 and 525, respectively, and the output lines 513 and 514 are connected in parallel. The current adder 521 includes a resistor 510 connected between the output line 513 and the power supply voltage line 511, and adds a drain current flowing in the output lines 513 and 514 generated by the current output units 522 and 523 to add a resistor. A voltage signal is converted by 510 and output from an output terminal 515.

The resistance value of the resistor 510 may be half the resistance value in the case of an individual circuit, assuming that the two current output units 522 and 523 are connected in parallel, or the same value as the resistance value in the case of an individual circuit You may take When the same resistance value is set, the voltage drop due to the DC term β (Vb−Vt) ² in (Equation 11) is doubled. In the former case, there is no increase in the voltage drop, but if the intended βvi ² term is converted into a voltage and taken out, the amplitude value is halved. Taking both into consideration, it is possible to set the value of the resistor 510 to a third appropriate value. In addition, an inductance can be used instead of a resistor in order to extract only the change in current. When the inductance is used, the voltage drop due to the DC term β (Vb−Vt) ² can be eliminated.

If the signal input to the input terminal 524 is vi1, the signal input to the input terminal 525 is vi2, and the amplitude loss due to the balun 102 is ignored, the current I0 flowing through the resistor 510 is the current I01 of the current output unit 522 and the current Since it is the sum of the current I02 from the output unit 523, see (Equation 11),
I0 = I01 + I02 = β {vi1 ² + (Vb−Vt) ² } + β {vi2 ² + (Vb−Vt) ² } = β (vi1 ² + vi2 ² ) + 2β (Vb−Vt) ² (Equation 12)
It becomes.

The first term on the right side of (Equation 12) is the sum of vi1 ² and vi2 ² , and this is the target output. The second term on the right side of (Equation 12) is a direct current component and can be easily cut off by a capacitor.
In the present embodiment, the case where n = 2 current output units are illustrated, but n may be an integer larger than that. The n output lines from each current output unit are connected in parallel, the current adder 521 takes the current and converts it into a voltage signal by the resistor 510 and outputs it from the output terminal 515. In this case, the sum of squares of n signals can be obtained as an output signal.

  Regardless of how the bias voltage Vb is selected, only a direct current component that can be easily eliminated remains as an error term, so that the NMOS transistors 103 and 104 can be set in a stable operating region. In particular, when noise characteristics are concerned, noise depending on the drain current such as shot noise can be reduced by adjusting the bias voltage Vb.

  The electronic circuit 5 of the fifth embodiment is a wired-OR connection of the common-source electronic circuit 1 of the first embodiment.

  Since the electronic circuit 5 for obtaining the square value of the signal according to the fifth embodiment can be constituted by a field effect transistor, it can be formed on-chip by a semiconductor process, and in particular, a high-frequency high speed about the limit frequency of the field effect transistor. Since it can operate, it can be applied to a system that requires high-speed operation such as IR communication. Thereby, a demodulator circuit and a pulse detection circuit of a receiver that can be easily integrated can be realized.

(Sixth embodiment)
Next, the configuration of the electronic circuit according to the sixth embodiment will be described with reference to FIG. FIG. 6 is a circuit diagram showing a configuration of an electronic circuit according to the sixth embodiment. In the sixth embodiment, a case of a square sum circuit in which n = 2 current output units 320 of FIG. 3 are connected in parallel to a current adder 321 is shown.

  As shown in FIG. 6, the electronic circuit 6 includes current output units 622 and 623 that are the current output unit 320 of FIG. 3, and a current addition unit 621. The current output units 622 and 623 have input terminals 624 and 625, respectively, and the output lines 613 and 614 are connected in parallel. The current adder 621 includes a resistor 610 connected between the output line 613 and the power supply voltage line 611, and adds a drain current flowing through the output lines 613 and 614 generated by the current output units 622 and 623 to add a resistor. A voltage signal is converted by 610 and output from an output terminal 615.

The resistance value of the resistor 610 may be half the resistance value in the case of an individual circuit, assuming that the two current output units 622 and 623 are connected in parallel, or the same value as the resistance value in the case of an individual circuit. You may take When the same resistance value is set for the latter, the voltage drop due to the DC term β (Vb−Vt) ² in (Equation 11) is doubled. In the former case, there is no increase in the voltage drop, but if the intended βvi ² term is converted into a voltage and taken out, the amplitude value is halved. Taking both into consideration, it is also possible to set the value of the resistor 610 to a third appropriate value. In addition, an inductance can be used instead of a resistor in order to extract only the change in current. When the inductance is used, the voltage drop due to the DC term β (Vb−Vt) ² can be eliminated.

If the signal input to the input terminal 624 is vi1, the signal input to the input terminal 625 is vi2, and the amplitude loss due to the balun 302 is ignored, the current I0 flowing through the resistor 610 is the current I01 of the current output unit 622 and the current Since it is the sum of the current I02 from the output unit 623, see (Equation 11),
I0 = I01 + I02 = β {vi1 ² + (Vb−Vt) ² } + β {vi2 ² + (Vb−Vt) ² } = β (vi1 ² + vi2 ² ) + 2β (Vb−Vt) ² (Equation 13)
It becomes.

The first term on the right side of (Equation 13) is the sum of vi1 ² and vi2 ² , and this is the target output. The second term on the right side of (Equation 13) is a direct current component and can be easily cut off by a capacitor.
In the present embodiment, the case where n = 2 current output units are illustrated, but n may be an integer larger than that. The n output lines from each current output unit are connected in parallel, the current adding unit 621 takes the current and converts it into a voltage signal by the resistor 610 and outputs it from the output terminal 615. In this case, the sum of squares of n signals can be obtained as an output signal.

  Regardless of how the bias voltage Vb is selected, only a direct current component that can be easily eliminated remains as an error term, so that the NMOS transistors 303 and 304 can be set in a stable operating region. In particular, when noise characteristics are concerned, noise depending on the drain current such as shot noise can be reduced by adjusting the bias voltage Vb.

  The electronic circuit 6 according to the sixth embodiment is obtained by wire-or-connecting the electronic circuit 3 according to the third embodiment of the common source type. Similar to the third embodiment, the low input impedance characteristic that is a feature of the common-source amplifier circuit facilitates matching design of the input circuit.

  Since the electronic circuit 6 for obtaining the square value of the signal according to the sixth embodiment can be constituted by a field effect transistor, it can be formed on-chip by a semiconductor process, and in particular, the limit frequency of the field effect transistor. Since high frequency high speed operation is possible, it can be applied to a system that requires high speed operation such as IR communication. Thereby, a demodulator circuit and a pulse detection circuit of a receiver that can be easily integrated can be realized.

(Seventh embodiment)
Next, the configuration of the electronic circuit according to the seventh embodiment will be described with reference to FIG. FIG. 7 is a circuit diagram showing a configuration of an electronic circuit according to the seventh embodiment. In the seventh embodiment, n = 2 current output units 120 in FIG. 1 are connected in parallel and the output currents of the current output units are added, and then m = 1 gate ground amplifier 122 (FIG. 2). The case of a square sum circuit connected to the current adder 121 is shown.

As shown in FIG. 7, the electronic circuit 7 is configured such that the gate terminal is grounded via the bias power source 702 between the output lines 713 and 714 of the current output units 722 and 723 that are the current output unit 120 of FIG. The grounded gate amplifying unit 726 including the NMOS transistor 701 is connected. The NMOS transistor 701 is an amplification stage using a grounded gate that is DC-biased to the gate by a bias power supply 702, and adds and amplifies the output currents of the current output units 722 and 723.
By the action of the NMOS transistor 701, the shunting due to the drain output resistance of the NMOS transistors 103 and 104 inside the current output units 722 and 723 is reduced to boost the gain. The output impedance becomes higher, and the sum of the currents flowing out from the output lines 713 and 714 can be taken out more accurately even when the resistance 710 and the load fluctuation increase.
In this electronic circuit 7, the cascade connection by the NMOS transistor 701 makes it possible to detect the square value of the signal while amplifying even a weak signal.

(Eighth embodiment)
Next, the configuration of the electronic circuit according to the eighth embodiment will be described with reference to FIG. FIG. 8 is a circuit diagram showing a configuration of an electronic circuit according to the eighth embodiment. In the eighth embodiment, a case of a square sum circuit in which n = 2 current output units 320 in FIG. 3 are connected in parallel to a current adding unit 321 through m = 1 grounded gate amplification units 322 (FIG. 4). Show.

  As shown in FIG. 8, the electronic circuit 8 is configured such that the gate terminal is grounded via the bias power source 802 between the output lines 813 and 814 of the current output units 822 and 823 which are the current output units 320 of FIG. The grounded gate amplifying unit 826 including the NMOS transistor 801 is connected. The NMOS transistor 801 is an amplification stage using a grounded gate that is DC biased to the gate by a bias power source 802, and adds and amplifies the output currents of the current output units 822 and 823.

(Ninth embodiment)
Next, the configuration of the electronic circuit according to the ninth embodiment will be described with reference to FIG. FIG. 9 is a circuit diagram showing a configuration of an electronic circuit according to the ninth embodiment. In the ninth embodiment, the case of a square sum circuit in which n = 2 current output units 120 in FIG. 1 are connected in parallel to a current adding unit 921 through m = 2 common-gate amplifiers 122 (FIG. 2). Show.

  As shown in FIG. 9, the electronic circuit 9 includes an NMOS transistor whose gate terminal is grounded via a bias power source 902 between the output line 913 of the current output unit 922 which is the current output unit 120 of FIG. 1 is connected, and the gate terminal is grounded via the bias power source 902 between the output line 933 and the resistor 910 of the current output unit 923 which is the current output unit 120 of FIG. It is configured by connecting a grounded gate amplification unit 927 configured by an NMOS transistor 903. The NMOS transistors 901 and 903 are amplifying stages based on a grounded gate that is DC-biased to the gate by a bias power source 902. The output currents of the current output units 922 and 923 are amplified, and the output currents are added together in parallel connection. To enter.

The resistance value of the resistor 910 is considered to be that the current output units 922 and 923 are connected in parallel, and may be half the resistance value in the case of an individual circuit (second embodiment, that is, FIG. 2), The resistance value may be the same as the resistance value at that time. When the same resistance value is set, the voltage drop due to the DC term β (Vb−Vt) ² in (Equation 8) is doubled. If the resistance value is set to half, the voltage drop does not increase, but if the intended βvi ² term is converted to voltage and taken out, the amplitude value becomes half. Taking both into consideration, the resistance value of the resistor 910 can be set to a third appropriate value. In addition, an inductance can be used instead of the resistor 910 in order to extract only the change in current. When the inductance is used, the voltage drop due to the DC term β (Vb−Vt) ² can be eliminated.

Here, the signal input to the input terminal 924 of the current output unit 922 is vi1, the signal input to the input terminal 925 of the current output unit 923 is vi2, and the loss of amplitude due to the balun 102 is ignored (that is, the transistors 103 and 103). When the voltages applied to the gate 104 are ± vi1 and ± vi2), the current I0 flowing through the resistor 910 is the sum of the current I01 of the current output unit 922 and the current I02 of the current output unit 923 (Equation 8 See)
I0 = I01 + I02 = β {vi1 ² + (Vb−Vt) ² } + β {vi2 ² + (Vb−Vt) ² } = β (vi1 ² + vi2 ² ) + 2β (Vb−Vt) ² (Equation 14)
Thus, the same result as in (Equation 12) is obtained. The first term on the right side of (Expression 14) is the sum of vi1 ² and vi2 ² , and this is the target output. Further, the second term on the right side of (Equation 14) is a direct current component and can be easily cut off by a capacitor.

  Regardless of how the bias voltage Vb is selected, only a direct current component that can be easily eliminated remains as an error term, so that the NMOS transistors 103 and 104 can be set in a stable operating region. In particular, when noise characteristics are concerned, noise depending on the drain current such as shot noise can be reduced by adjusting the bias voltage Vb.

  The electronic circuit 9 of the ninth embodiment is obtained by wire-OR connection of the electronic circuit 2 of the second embodiment having a gate-grounded cascade stage. Due to the cascade stage, even weak signals can be detected effectively. In addition, since the output impedance of the current output units 922 and 923 is further increased, the shunt due to the output impedance is reduced, and errors due to current addition can be reduced. In addition, low input impedance characteristics facilitate input circuit matching design.

  Since the electronic circuit 9 for obtaining the square value of the signal according to the ninth embodiment can be constituted by a field effect transistor, it can be formed on-chip by a semiconductor process. Since it can operate, it can be applied to a system that requires high-speed operation such as IR communication. Thereby, a demodulator circuit and a pulse detection circuit of a receiver that can be easily integrated can be realized.

(10th Embodiment)
Next, the configuration of the electronic circuit according to the tenth embodiment will be described with reference to FIG. FIG. 10 is a circuit diagram showing a configuration of an electronic circuit according to the tenth embodiment. In the tenth embodiment, a case of a square sum circuit in which n = 2 current output units 320 of FIG. 3 are connected in parallel to a current adding unit 321 via m = 2 common-gate amplifiers 322 (FIG. 4). Show.

  As shown in FIG. 10, the electronic circuit 10 includes an NMOS transistor in which a gate terminal is grounded via a bias power supply 1002 between an output line 1013 of a current output unit 1022 which is the current output unit 320 of FIG. 1001 is connected to the grounded gate amplification unit 1026, and the gate terminal is grounded via the bias power supply 1004 between the output line 1033 of the current output unit 1023 which is the current output unit 320 of FIG. It is configured by connecting a grounded gate amplification unit 1027 configured by an NMOS transistor 1003. The NMOS transistors 1001 and 1003 are amplification stages using a grounded gate that is DC-biased to the gates by the bias power supplies 1002 and 1004, and add and amplify the output currents of the current output units 1022 and 1023.

(Eleventh embodiment)
Next, the configuration of a receiving device that is an electronic device including the electronic circuit according to the eleventh embodiment will be described with reference to FIGS. 11 and 12. FIG. 11 is a circuit diagram showing a configuration of a receiving apparatus according to the eleventh embodiment. FIG. 12 is a timing chart showing the operation of the receiving apparatus according to the eleventh embodiment.

  In the eleventh embodiment, a case will be described as an example in which a waveform as shown in FIG. 12 in which a rectangular pulse is multiplied by a sine wave having a carrier frequency fc is used as a UWB-IR pulse signal. It is not limited. A Gaussian monopulse, Hermitian pulse, or an n-th order differential waveform frequently used as an IR signal, a pulse obtained by multiplying the sine wave of the carrier frequency fc and moving the spectrum on the frequency axis, and other pulses may be used. In particular, a pulse obtained by multiplying a sine wave having a carrier frequency fc is frequently used because it does not contain a direct current component and the spectrum is symmetrical about the carrier frequency fc. In the eleventh embodiment, a UWB-IR receiver (electronic device) that uses a pulse obtained by multiplying the simplest rectangular pulse by a sine wave as an IR signal will be described as an example.

  As shown in FIG. 11, the receiving device 11 includes an antenna 1101, a low noise amplifier circuit (LNA: Low Noise Amplifier) 1102, a square circuit 1103 (FIGS. 1 to 4), and a low-pass filter (LPF: Low). -Pass Filter) 1104 and a discrimination circuit 1105 as a signal processing unit.

  A received signal a (FIG. 12) received by the antenna 1101 is amplified by the LNA 1102. When the LNA 1102 having a balanced output is configured as an amplifier circuit, the baluns 102 and 302 shown in FIGS. 1 to 4 can be omitted. The square circuit 1103 squares the received signal a and outputs a square signal b (FIG. 12). The LPF 1104 removes the high frequency component of the square signal b and outputs an LPF signal c (FIG. 12). The LPF 1104 may use an integration circuit. The discrimination circuit 1105 performs binarization processing of the LPF signal c, outputs a binarization signal d (FIG. 12), and can detect the presence or absence of a pulse.

  In UWB-IR, a modulation method called “OOK (On-Off-Keying)” is used by controlling not to send a pulse according to bit 1 or 0 of information to be transmitted. Further, if the pulse position is controlled according to the transmission bit information, a modulation method called PPM (Pulse Position Modulation) is obtained. In the configuration of the receiving device 11, since the presence or position of the transmitted pulse can be detected, UWB-IR can be demodulated. When the timing of the pulse signal to be received next can be predicted by the pulse detected by the determination circuit 1105, the operation of the circuit for the previous period is stopped by the signal 1107, and the power consumption of the receiving device 11 can be reduced. is there.

  If the squaring circuit 1103 is used as in the eleventh embodiment, the receiving device 11 that can easily realize UWB-IR communication can be configured. Any circuit used in the receiving device 11 can be integrated with a semiconductor integrated circuit or the like using CMOS, and a highly reliable and low-cost receiving device can be realized.

  The configuration of the receiver 11 according to the eleventh embodiment can also be used for a signal receiver using amplitude modulation. In that case, the determination circuit 1105 is unnecessary, and the envelope of the received signal is output to the LPF 1104. That is, the envelope can be detected from the amplitude modulation signal, which is nothing but demodulation of the amplitude modulation signal.

(Twelfth embodiment)
Next, the configuration of a receiving device that is an electronic device including the electronic circuit according to the twelfth embodiment will be described with reference to FIGS. 13 and 14. FIG. 13 is a circuit diagram showing a configuration of a receiving apparatus according to the twelfth embodiment. FIG. 14 is a timing chart showing the operation of the receiving apparatus according to the twelfth embodiment.

  As shown in FIG. 13, the receiving device 13 includes an antenna 1301, an LNA 1302, mixers 1303 and 1304, LPFs 1305 and 1306, a square sum circuit 1307 (FIGS. 5 to 10), a template generation circuit 1308, and a discrimination circuit. 1309 and an AD conversion circuit 1311.

  Similarly to the eleventh embodiment, the twelfth embodiment uses a waveform as shown in the received signal a of FIG. 14 obtained by multiplying a rectangular pulse by a sine wave of the carrier frequency fc as a UWB-IR pulse signal. However, this is not a limitation. A Gaussian monopulse, Hermitian pulse, or an n-th order differential waveform frequently used as an IR signal, a pulse obtained by multiplying them by a sine wave of the carrier frequency fc, and moving the spectrum on the frequency axis may be used. In particular, a pulse obtained by multiplying a sine wave having a carrier frequency fc does not include a direct current component, and is frequently used because the spectrum is symmetrical about the carrier frequency fc. In the twelfth embodiment, a UWB-IR receiver 13 that uses a pulse obtained by multiplying the simplest rectangular pulse by a sine wave as an IR signal will be described as an example.

  There is a method called synchronous detection as a demodulation method when configuring the reception device 13. In this method, a correlation between a template prepared on the receiver side and a received signal is calculated, and information transmitted from the correlation value is extracted. The correlation value is obtained by multiplying the template and the received signal and further integrating the result. Integration has the same effect as high-pass removal by a low-pass filter, and often integration is substituted by a low-pass filter.

  The twelfth embodiment is a UWB-IR receiver for synchronous detection using a square sum circuit (FIGS. 5 to 10).

  A reception signal a (FIG. 14) that is a UWB-IR signal received by the antenna 1301 is amplified by the differential LNA 1302 and input to the mixers 1303 and 1304. Each of the mixers 1303 and 1304 is multiplied by two orthogonal template signals generated by the template generation circuit 1308, and outputs multiplication waveforms b and c (FIG. 14). As for these multiplication waveforms b and c, LPF signals d and e (FIG. 14) from which high-frequency components have been removed by LPFs 1305 and 1306 are input to a square sum circuit 1307, and the sum of squares of the respective LPF signals d and e is the sum of squares. It is output as a signal f (FIG. 14). This square sum signal f is equal to the square value of the envelope of the received signal a. The LPFs 1305 and 1306 can use an integration circuit. By discriminating the presence or absence of a pulse from the square sum signal f by the discrimination circuit 1309, the information transmitted from the received signal can be extracted and restored, and output from the output terminal 1310 as a restoration signal g (FIG. 14). .

  If the signals of the LNA 1302, the mixers 1303 and 1304, and the template generation circuit 1308 are configured by a balanced circuit that can handle a balanced signal (differential signal), the signal input to the square sum circuit 1307 is balanced. Thus, the baluns 102 and 302 in FIGS. 5 to 10 can be omitted.

  The determination circuit 1309 also controls the operation of the entire receiving apparatus. That is, if the next timing when the received signal a arrives can be predicted based on the information of the restored signal g, the operation of the circuit is stopped by the control signals h1, h2, and h3 so as to save power consumption. Can do. The template signal generated by the template generation circuit 1308 may be generated intermittently for a time during which the signal will be received, or may be generated continuously when it cannot be predicted.

  In the following, the fact that the amplitude (square value) of a signal can be detected without accurate frequency and phase synchronization with the above-described configuration will be described using equations as a supplement to the above description.

  First, as a UWB-IR signal, assuming that a signal obtained by multiplying the above-described rectangular pulse (with pulse width Tp) by the carrier frequency fc is transmitted every time interval Tb, the received UWB-IR signal S The period of nTb ≦ t ≦ nTb + Tp is represented by S = cos (2πfct), and the period of nTb + Tp <t <(n + 1) Tb can be represented by S = 0. Here, t is time and n is an integer. The received signal a in FIG. 14 has this waveform.

  Further, if two orthogonal template signals generated by the template generation circuit 1308 are PI and PQ, they can be expressed as PI = cos {(ωc + Δω) t + φ}, PQ = sin {(ωc + Δω) t + φ}. Here, ωc = 2πfc and Δω = 2πΔfc, and Δfc is an error from the carrier frequency fc of the template signal. Φ is a phase difference indicating that the phases do not match.

Since the outputs IFI and IFQ of the mixers 1303 and 1304 are multiplications of S, PI, and PQ, respectively, the period of nTb ≦ t ≦ nTb + Tp is
IFI = SPI = cos (ωct) cos {(ωc + Δω) t + φ} = (1/2) {cos ((2ωc + Δω) t + φ) + cos (Δωt + φ)} (Equation 15)
IFQ = SPQ = cos (ωct) sin {(ωc + Δω) t + φ} = (1/2) {sin ((2ωc + Δω) t + φ) + sin (Δωt + φ)} (Expression 16)
In the period of nTb + Tp <t <(n + 1) Tb, IFI = IFQ = 0. The multiplication waveforms b and c in FIG. 14 are this waveform.

The LPFs 1305 and 1306 remove the first term from the high-frequency component from this signal, that is, the right side of (Expression 15) and (Expression 16). Therefore, if the IFI and IRQ signals that have passed through the LPFs 1305 and 1306 are IFI ′ and IQ ′, the period of nTb ≦ t ≦ nTb + Tp is:
IFI ′ = (1/2) cos (Δωt + φ) (Expression 17)
IFQ ′ = (1/2) sin (Δωt + φ) (Equation 18)
Thus, IFI ′ = IFQ ′ = 0 during the period of nTb + Tp <t <(n + 1). Here, the signal delay due to the LPF was ignored. The LPF signals d and e in FIG. 14 have this waveform. Therefore, if the output of the square sum circuit 1307 is B, the period of nTb ≦ t ≦ nTb + Tp is
B = IFI ′ ² + IFQ ′ ² = (1/4) {cos ² (Δωt + φ) + sin ² (Δωt + φ)} = 1/4 (Equation 19)
In the period of nTb + Tp <t <(n + 1), B = 0, and a pulse having an amplitude of 1/4 is output when the UWB-IR signal is received regardless of the error Δfc and the phase shift φ of the carrier frequency fc. The

Also, even when the carrier phase is modulated like BPM,
Φ = tan ⁻¹ (IFI ′ / IFQ ′) (Equation 19)
It is easy to know by calculating In the calculation of (Equation 19), the value of (IFI ′ / IFQ ′) is sufficient if it has a resolution of 1 to 2 bits, and can be easily known by the AD converter circuit 1311 using a simple comparator. The AD conversion circuit 1311 is an AD conversion circuit 1311 for BPM, AD-converts the output values of the LPFs 1305 and 1306, and the discrimination circuit 1309 displays a square sum circuit 1307 representing the square of the absolute value of the UWB-IR signal S. Together with the output, the transfer information is extracted and demodulated by the output of the AD conversion circuit 1311. In the case of OOK or PPM, the AD conversion circuit 1311 can be omitted.

  As described above, when the sum of squares circuit 1307 is used, synchronous detection can be performed without accurate phase and frequency synchronization. Thereby, the structure of the receiving device 13 can be remarkably simplified.

(13th Embodiment)
Next, the configuration of a receiving device that is an electronic device including the electronic circuit according to the thirteenth embodiment will be described with reference to FIG. FIG. 15 is a circuit diagram showing a configuration of a receiving apparatus according to the thirteenth embodiment.

  In the twelfth embodiment, the case where two orthogonal template signals are used has been described. The twelfth embodiment can be extended when using two or more orthogonal template signals.

  In addition to UWB-IR communication, in general, a signal can be regarded as a position vector representing one point on an n-dimensional (n is an integer or infinity) space, and analysis and processing thereof can be performed. The description of the thirteenth embodiment will be made using this method. Such techniques are obvious to those skilled in the art, but for confirmation, the following outlines how this technique would look when looking at the prior art.

A vector consisting of a number of numbers enclosed in parentheses is called a vector, and can represent a quantity with direction and size. If sampling is performed at a predetermined interval in, for example, one symbol section of the signal waveform, n sampling values s1, s2,. These sampling values are arranged in order and enclosed in parentheses (s1, s2,... Sn) are vectors. Since n numbers are arranged, it is an n-dimensional vector and can represent coordinates in an n-dimensional space. If this is now expressed as s ^→ , then s ^→ = (s1, s2,... Sn). Since the vector s ^→ can represent a signal or a position as a position vector, it may be simply referred to as “signal s ^→ ” or “point s ^→ ”.

In n-dimensional space, a set of n linearly independent vectors can be chosen, and any vector in this space can be represented as a linear combination thereof. In particular, a set of n vectors that are orthogonal to each other with an absolute value of 1 is called an orthonormal basis. If this is assumed to be e1 ^→ , e2 ^→ ,... En, an arbitrary vector x ^→
x ^→ = (x ^→ , e1 ^→ ) e1 ^→ + (x ^→ , e2 ^→ ) e2 ^→ + ... + (x ^→ , en ^→ ) en ^→ ... (formula 20)
It can be expressed as Here, (x ^→ , y ^→ ) represents an inner product of vectors x ^→ and y ^→ . In this expression, when e1 ^→ , e2 ^→ ,... En ^→ are taken as coordinate axes on an n-dimensional space, the position coordinates representing the point X are ((x ^→ , e1 ^→ ), (x ^→ , e2 ^→ )). ,... (X ^→ , en ^→ )). The discrete Fourier series expansion uses a set of trigonometric functions of an integer i of a period T as e1 ^→ , e2 ^→ ,... en ^→ . Here, i is an integer of 1 ≦ i ≦ n.

Now, considering a case where (m) omits arbitrary m terms on the right side and approximates only with k = n−m terms,
x ′ ^→ = (x ^→ , e1 ^→ ) e1 ^→ + (x ^→ , e2 ^→ ) e2 ^→ +... + (x ^→ , ek ^→ ) ek ^→ ... (formula 21)
It becomes.

When x ^→ is approximated by x ′ ^→ , the error x ^→ −x ′ ^→ when the coefficient of ei ^→ (where i is an integer of 1 ≦ i ≦ k) is set to (x ^→ , ei ^→ ) as described above. It is known that the square of the absolute value of (the error in energy) is minimized.

For the magnitude of the vector x ^→ , it is convenient to calculate the square value of its absolute value. It can be easily found by calculating the inner product (x ^→ , x ^→ ) with itself. In addition, from (Equation 20),
(X ^→ , x ^→ ) = Σ (x ^→ , ei ^→ ) ² (Equation 22)
(Σ is the sum of i = 1 to n).

In the conventional correlation detection, the correlation between the received signal r ^→ and the templates p0 ^→ , p1 ^→ , that is, the inner product is calculated, and the “similarity” between r ^→ and p0 ^→ , p1 ^→ is known and demodulated. Here, p0 ^→ and p1 ^→ are templates representing that the transmitted information is bit 0 and bit 1, respectively. When the template and r ^→ coincide with each other, the value becomes the largest, so that both can be compared and the transmitted information can be known with higher accuracy. However, in the conventional synchronous detection, it is necessary to completely match the timings of r ^→ , p0 ^→ , and p1 ^→ . The vector r ^→ in the n-dimensional space needs to be in (or very close to) the two-dimensional subspace spanned by p0 ^→ and p1 ^→ . In general, when the number of templates k is increased on the transmitting side, the amount of information that can be transmitted per symbol can be increased, but k may be increased only by the receiving device. In this case, since the range in which the existence of r ^→ is allowed is expanded to the k-dimensional subspace in the n-dimensional space, the degree of freedom such as the synchronization accuracy and the method of selecting the template signal is further increased.

The phase information of r ^→ can be obtained as follows. That is, {(x ^→ , ei ^→ ) | i is an integer of 1 ≦ i ≦ k} represents a position coordinate in a k-dimensional subspace, and a direction cosine of r ^→ with respect to {ei} is obtained by normalization. In many cases, the vector of signal symbols is arranged so that the distance between the symbols is as large as possible, and is arranged so as to be symmetric about the origin in the n-dimensional space. In the case of k = 2 in the twelfth embodiment, it is obtained by (Equation 19), but this is merely a ratio of the direction cosine of the UWB-IR signal S to PI and PQ. In the case of BPM, since signal symbols are taken at two symmetrical positions with the origin as the center, IFI 'and IFQ' are demodulated if the sign (correlation value is positive or negative) is obtained by 1-bit AD conversion. Was possible. That is, if it is known in which quadrant in the k-dimensional subspace the received signal exists, it can be demodulated. When the signal-to-noise ratio is poor, or when the accuracy of the template, the carrier frequency, or the phase shift is large, high-precision AD conversion is necessary when k = 2. It is possible to accurately determine (that is, just know whether the sign is positive or negative).

In the above description, r ^→ and {pi ^→ } are described as n-dimensional vectors obtained by n samplings, that is, discrete (time) functions. However, it should be noted that the above description can also be applied to continuous functions such as general signals by well-known linear algebra techniques. In that case, the limit (infinite dimension) where the sampling number n is infinite is considered. As the inner product, the sum of products is used in the case of a discrete quantity, but the integral is used as the limit in the case of a continuous quantity.

  As illustrated in FIG. 15, the reception device 15 includes an antenna 1501, an LNA 1502, k correlation circuits 1508, 1509,... 1510, a square sum circuit 1506 (FIGS. 5 to 10), and an AD conversion circuit 1507. And a discriminating circuit 1511.

A reception signal received by the antenna 1501 is amplified by the LNA 1502 and sent to k correlation circuits 1508, 1509,. The output signal vector of the LNA 1502 is represented by r ^→ .

Since the configuration of the k correlation circuits 1508, 1509,..., 1510 is the same, the configuration of the correlation circuit 1508 will be described in detail. The correlation circuit 1508 includes a template generation circuit 1505, a multiplication circuit 1503, and an integration circuit (or LPF) 1504. The template generation circuit 1505 generates a template p1 ^→ , is multiplied by the reception signal r ^→ in the multiplication circuit 1503, and is integrated in the integration circuit 1504 to obtain a correlation value ρ1. The correlation value ρ1 is a scalar quantity. Similarly, the correlation circuit 1509 outputs the correlation value ρ2 of the received signal r ^→ and the template p2 ^→ , and the correlation circuit 1510 outputs the correlation value ρk of the received signal r ^→ and the template pk ^→ . These correlation values ρ1, ρ2,... Ρk are input to the square sum circuit 1506 and the AD conversion circuit 1507.

The sum of squares circuit 1506 outputs the absolute value of r ^→ based on (Equation 22). In this case, the square sum circuit 1506 is a k-input square sum circuit in which k electronic circuits 1 to 4 of FIGS. (The case where k = 2 is illustrated in FIGS. 5 to 10. The necessary number of current output units may be connected in parallel also when k> 2.) In the determination circuit 1511, the sum of squares circuit 1506 and the AD conversion circuit 1507 are connected. Information transmitted from the output value is estimated and demodulated.

The discriminating circuit 1511 also takes control of the entire receiving device 15, estimates the timing when the next signal reception can be expected from the timing obtained from the received signal, activates the template, or turns off the device power when there is no received signal. To save power consumption. It also captures at the beginning of the communication link. Further, when the carrier frequency is shifted in transmission / reception, the shift from the template is shifted at every reception, and this phase shift is also corrected. That is, since the signal position to be received next can be estimated from the position of r ^→ (in the k-dimensional space) previously received by the AD conversion circuit 1507, correction is performed based on the signal position.

  In the thirteenth embodiment, since the number of templates can be increased in the configuration of the receiving device 15, there is no accurate carrier frequency and phase synchronization, and even a low-resolution simple AD conversion circuit 1507 is used. The accuracy during demodulation can be further increased. As described above, the square sum circuit 1506 can greatly simplify the structure of the receiver.

1 is a circuit diagram showing a configuration of an electronic circuit according to a first embodiment. The circuit diagram which shows the structure of the electronic circuit which concerns on 2nd Embodiment. The circuit diagram which shows the structure of the electronic circuit which concerns on 3rd Embodiment. The circuit diagram which shows the structure of the electronic circuit which concerns on 4th Embodiment. The circuit diagram which shows the structure of the electronic circuit which concerns on 5th Embodiment. The circuit diagram which shows the structure of the electronic circuit which concerns on 6th Embodiment. The circuit diagram which shows the structure of the electronic circuit which concerns on 7th Embodiment. The circuit diagram which shows the structure of the electronic circuit which concerns on 8th Embodiment. A circuit diagram showing composition of an electronic circuit concerning a 9th embodiment. A circuit diagram showing composition of an electronic circuit concerning a 10th embodiment. The circuit diagram which shows the structure of the receiver which concerns on 11th Embodiment. The timing diagram which shows operation | movement of the receiver which concerns on 11th Embodiment. The circuit diagram which shows the structure of the receiver which concerns on 12th Embodiment. The timing diagram which shows operation | movement of the receiver which concerns on 12th Embodiment. The circuit diagram which shows the structure of the receiver which concerns on 13th Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1-10 ... Electronic circuit, 101 ... Input terminal, 102 ... Balun, 103, 104 ... NMOS transistor, 105, 106 ... Capacitor, 107, 108 ... Resistance, 109 ... Bias power supply, 110 ... Resistance, 111 ... Power supply voltage line, DESCRIPTION OF SYMBOLS 112 ... Output terminal, 113 ... Output line, 120 ... Current output part, 121 ... Current addition part, 122 ... Grounded gate amplification part, 201 ... NMOS transistor, 202 ... Bias power supply, 301 ... Input terminal, 302 ... Balun, 303, 304 ... NMOS transistor, 305, 306 ... capacitor, 307, 308 ... resistor, 309 ... bias power supply, 310 ... resistor, 311 ... power supply voltage line, 312 ... output terminal, 313 ... output line, 320 ... current output unit, 321 ... Current adding unit, 322... Grounded gate amplification unit, 401... NMOS transistor, 402. Ias power supply, 510 ... resistor, 511 ... power supply voltage line, 513,514 ... output line, 515 ... output terminal, 521 ... current adding unit, 522,523 ... current output unit, 524,525 ... input terminal, 610 ... resistor, 611 ... Power supply voltage line, 613, 614 ... Output line, 615 ... Output terminal, 621 ... Current adding unit, 622,623 ... Current output unit, 624,625 ... Input terminal, 701 ... NMOS transistor, 702 ... Bias power supply, 710 ... resistor, 713, 714 ... output line, 715 ... output terminal, 722, 723 ... current output unit, 726 ... grounded gate amplification unit, 801 ... NMOS transistor, 802 ... bias power supply, 807 ... sum of square circuit, 810 ... resistor, 813, 814: output line, 815: output terminal, 822, 823: current output unit, 826: grounded gate amplification unit, 901 DESCRIPTION OF SYMBOLS 03 ... NMOS transistor, 902 ... Bias power supply, 910 ... Resistance, 913 ... Output line, 922, 923 ... Current output part, 924, 925 ... Input terminal, 926, 927 ... Gate ground amplification part, 933 ... Output line, 1001, DESCRIPTION OF SYMBOLS 1003 ... NMOS transistor, 1002, 1004 ... Bias power supply, 1010 ... Resistance, 1013 ... Output line, 1022, 1023 ... Current output part, 1026, 1027 ... Grounded gate amplification part, 1033 ... Output line, 1101 ... Antenna, 1102 ... LNA DESCRIPTION OF SYMBOLS 1103 ... Square circuit, 1104 ... LPF, 1105 ... Discrimination circuit, 1107 ... Signal, 1301 ... Antenna, 1302 ... LNA, 1303, 1304 ... Mixer, 1305, 1306 ... LPF, 1307 ... Square sum circuit, 1308 ... Template generation circuit , 1309... Discrimination circuit, 13 DESCRIPTION OF SYMBOLS 10 ... Output terminal, 1311 ... AD conversion circuit, 1501 ... Antenna, 1502 ... LNA, 1503 ... Multiplication circuit, 1504 ... Integration circuit, 1505 ... Template generation circuit, 1506 ... Square sum circuit, 1507 ... AD conversion circuit, 1508, 1509 ... correlation circuit, 1511 ... discrimination circuit.

Claims (9)

A first field effect transistor having one of the balanced signals connected to the gate terminal and the source terminal grounded;
A second field effect transistor having the other one of the balanced signals connected to the gate terminal and the source terminal grounded;
An output terminal for connecting a drain terminal of the first field effect transistor and a drain terminal of the second field effect transistor to each other and outputting a drain current;
N (n is an integer greater than or equal to 1) current output units configured to include:
A current adder connected to the n output terminals of the n current output units and outputting a signal proportional to the sum of the drain currents output from the n current output units;
including,
An electronic circuit characterized by that.   2. The electronic circuit according to claim 1, wherein the electronic circuit is connected between the output terminal of the n current output units and the current addition unit, and a gate terminal is grounded via a first bias voltage. And a third field effect transistor (m is an integer of 1 to n). A first field effect transistor having one of the balanced signals connected to the source terminal and a gate terminal grounded via a second bias voltage;
A second field-effect transistor having a source terminal connected to the other one of the balanced signals and a gate terminal grounded via the second bias voltage;
An output terminal for connecting a drain terminal of the first field effect transistor and a drain terminal of the second field effect transistor to each other and outputting a drain current;
N (n is an integer greater than or equal to 1) current output units configured to include:
A current adder connected to the n output terminals of the n current output units and outputting a signal proportional to the sum of the drain currents output from the n current output units;
including,
An electronic circuit characterized by that.   4. The electronic circuit according to claim 3, wherein the electronic circuit is connected between the output terminal of the n current output units and the current addition unit, and a gate terminal is grounded via a first bias voltage. And a third field effect transistor (m is an integer of 1 to n).   An electronic device comprising the electronic circuit according to claim 1.   6. The electronic apparatus according to claim 5, wherein the electronic apparatus includes a signal processing unit that detects a pulse carried by a supplied UWB signal. The electronic device according to claim 5 or 6,
The electronic device is
A template signal generator for generating a first signal and a second signal orthogonal to each other;
A first multiplier that outputs a first multiplied signal obtained by multiplying the first signal and the received signal;
A second multiplier that outputs a second multiplied signal obtained by multiplying the second signal and the received signal;
A first low-pass filter that outputs a first low-pass filtered signal obtained by removing high-frequency components from the first multiplication signal;
A second low-pass filter that outputs a second low-pass filtered signal obtained by removing high-frequency components from the second multiplication signal;
An electronic device comprising: A template signal generator for generating a first signal and a second signal orthogonal to each other;
A first multiplier that outputs a first multiplied signal obtained by multiplying the first signal and the received signal;
A second multiplier that outputs a second multiplied signal obtained by multiplying the second signal and the received signal;
A first low-pass filter that outputs a first low-pass filtered signal obtained by removing high-frequency components from the first multiplication signal;
A second low-pass filter that outputs a second low-pass filtered signal obtained by removing high-frequency components from the second multiplication signal;
An electronic circuit according to any one of claims 1 to 4,
A method for detecting a pulse of an electronic device comprising:
The first low-pass filtered signal and the second low-pass filtered signal are square sum output by the electronic circuit to detect a pulse,
A method for detecting a pulse of an electronic device.   9. The pulse detection method for an electronic device according to claim 8, wherein the pulse carried by the supplied UWB signal is detected.

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