JP2010114454A - Method of manufacturing electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique which can improve reliability of a module using a PCB as a module substrate. <P>SOLUTION: Solder connection by Pb free solder between a single chip component 43, an integrated chip component 44 and a semiconductor chip IC2 is carried out by heating treatment at a temperature lower than 280°C using a heat block, and solder connection of the semiconductor chip IC1 by high melting point solder is carried out by heating treatment at 280°C or higher using hot jet. Consequently, it is possible to perform solder connection for the semiconductor chip IC1 to a PCB 38 by using high melting point solder without generating damage of the PCB 38 due to heat, such as burning of solder resist and peeling of prepreg from a core material. As a result, the semiconductor chip IC1 can be mounted on the PCB 38 by high connection strength. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an electronic device manufacturing technique, and more particularly to a technique effective when applied to a module manufacturing method.

  In a mobile communication device such as a cellular phone, for example, a surface-mounted semiconductor chip on which a power amplifier or an antenna switch is formed, and a surface-mounted chip component on which a capacitor, a resistor, or the like is formed. Adopting a module with a structure mounted on the same substrate. The semiconductor chip and the chip component are mounted on the module substrate by solder connection, and both are covered and protected by an insulating resin.

  For example, Japanese Patent Laid-Open No. 2002-208668 (Patent Document 1) discloses a semiconductor chip in which a plurality of pads are formed on the main surface, a chip component in which connection terminals are formed on both ends, and a semiconductor chip and a chip component. Low elasticity resin such as insulating silicone resin that covers the module substrate to be mounted, the solder connection portion for connecting the chip component and the board side terminal of the module substrate by solder, and the semiconductor chip, the chip component and the solder connection portion The semiconductor device which consists of the sealing part formed by this is disclosed.

  Japanese Patent Laid-Open No. 2002-368186 (Patent Document 2) discloses that at least one of a plurality of circuit elements mounted on a wiring board and electrically connected to an outer lead uses a thermosetting resin composition. A resin-sealed module device is described in which the entire wiring substrate and all elements and the connection side of the outer lead substrate are sealed with a transfer mold.

JP 2002-208668 A JP 2002-368186 A

  However, there are various technical problems described below for the module manufacturing method.

  In a module for a mobile phone examined by the present inventors, a ceramic substrate that is resistant to heat and has good electrical insulation is used as a module substrate on which a semiconductor chip and chip components are mounted. However, the ceramic substrate is relatively expensive, and the problem remains that it is easily broken by dropping or impact. In addition, modules for cellular phones are always required to be small and thin. However, since ceramics are easily broken when processed thinly, a semiconductor chip and chip components are mounted on a ceramic substrate and the entire package is sealed with resin. It is difficult to make the thickness of 1 mm or less.

  Therefore, we examined the use of PCB (Printed Circuit Board), which is a resin substrate that is less expensive than a ceramic substrate and resistant to impact, as a module substrate. However, the present inventors have also found the following problems with respect to modules using PCB as a module substrate.

  That is, when a semiconductor chip having a power amplifier with a large calorific value is bonded to a PCB, an Ag paste with a silver (hereinafter referred to as Ag) filler content of, for example, about 70 wt% is generally used. This is to improve heat dissipation, but on the other hand, there is a problem that the adhesive strength is weak. This problem can be improved by using a solder paste (for example, lead (hereinafter referred to as Pb) -10 tin (hereinafter referred to as Sn)) having a high melting point (for example, 280 ° C. or higher) instead of Ag paste, for example. Is possible. However, new problems such as burning of the solder resist covering the wiring formed on the surface of the PCB and peeling of the prepreg, which is an insulating resin sheet constituting the PCB, from the core material due to the high-temperature treatment at 280 ° C. or higher. It will occur. In addition, in response to the trend of Pb regulations in Europe, Pb-free solder that does not contain Pb is used for the connection between the chip component and the PCB. Since this Pb-free solder melts at a temperature of about 220 ° C., 280 High-temperature treatment at or above ° C cannot be applied to PCB.

  Further, after the semiconductor chip and the chip component are mounted on the PCB and further covered and protected with an insulating resin, the module is mounted on the motherboard by solder connection and incorporated into the product. However, during reflow processing (for example, about 250 ° C.) after the solder connection, the Pb-free solder that connects the chip component to the PCB in the module may be partially melted, resulting in problems such as a short circuit. Specifically, for example, the semi-dissolved Pb-free solder flows in a flash state, and the connection terminals of the chip components are connected to cause a short circuit. When the resin is sealed, the Pb-free solder is not yet inserted into the narrow gap between the chip components and the PCB. When the filling void is formed, the short circuit appears remarkably.

  The objective of this invention is providing the technique which can improve the reliability of the module which uses PCB as a module board | substrate.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  According to the present invention, in a module in which a semiconductor chip and a chip component having a power amplifier circuit are mounted on a PCB by solder connection, the back surface of the semiconductor chip and the substrate side terminal of the PCB are connected by high melting point solder, The terminal and the board side terminal of the PCB are connected by Pb-free solder.

  The present invention relates to a method of manufacturing a module in which a semiconductor chip having a power amplifier and a chip component are mounted on a PCB by soldering, and by heating the PCB at a temperature of less than 280 ° C., the connection terminal of the chip component and the PCB substrate The side terminals are connected with Pb-free solder, and at the same time, by locally heating at a temperature of 280 ° C. or higher, the back surface of the semiconductor chip and the substrate side terminal of the PCB are connected with high melting point solder, and the semiconductor chip and the chip component are further connected. Resin sealing is performed in a reduced-pressure atmosphere, and the gap between the chip component and the PCB is filled with resin.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  Without damaging the PCB, a semiconductor chip having high adhesive strength can be mounted on the PCB, and a short circuit due to soldering between the connection terminals of the chip components can be prevented. Thereby, the reliability of the module in which the semiconductor chip and the chip component are mounted on the PCB can be improved.

It is a block diagram which shows an example of the system configuration | structure of the digital mobile telephone which is this Embodiment 1. FIG. FIG. 3 is a circuit diagram illustrating an example of a power amplifier used in the digital cellular phone according to the first embodiment. (A) is principal part sectional drawing which shows an example of the structure of the low pass filter mounted in the front end apparatus which is this Embodiment 1, (b) is a circuit block diagram similarly. 2 is a plan view of a principal part showing an example of an internal configuration of a semiconductor chip in which an amplification stage of the power amplifier according to the first embodiment is configured by an nMOS. FIG. 3 is a cross-sectional view of a main part showing an example of an internal configuration of a semiconductor chip in which an amplification stage of the power amplifier according to the first embodiment is configured by an nMOS. FIG. 3 is a plan view of a principal part showing an example of an internal configuration of a semiconductor chip in which an amplification stage of the power amplifier according to the first embodiment is configured with a heterojunction bipolar transistor. It is principal part sectional drawing in the AA of FIG. FIG. 3 is a schematic cross-sectional view showing an example of primary mounting of a module in the digital mobile phone according to the first embodiment. FIG. 3 is a schematic cross-sectional view showing an example of secondary mounting of a module in the digital mobile phone according to the first embodiment. It is process drawing explaining the assembly procedure of the module which is this Embodiment 1. FIG. FIG. 6 is a main-portion cross-sectional view of the semiconductor device for describing the manufacturing method of the semiconductor device that is Embodiment 1; FIG. 12 is a fragmentary cross-sectional view of the semiconductor device, explaining the method for manufacturing the semiconductor device following FIG. 11; FIG. 13 is a fragmentary cross-sectional view of the semiconductor device, explaining the method for manufacturing the semiconductor device following FIG. 12; FIG. 14 is a fragmentary cross-sectional view of the semiconductor device for describing the manufacturing method of the semiconductor device following FIG. 13; FIG. 15 is a fragmentary cross-sectional view of the semiconductor device, explaining the method for manufacturing the semiconductor device following FIG. 14; FIG. 16 is a main part cross-sectional view of the semiconductor device, explaining the method for manufacturing the semiconductor device following FIG. 15; FIG. 17 is a main part cross-sectional view of the semiconductor device, explaining the method for manufacturing the semiconductor device following FIG. 16; FIG. 18 is a fragmentary cross-sectional view of the semiconductor device, explaining the method for manufacturing the semiconductor device following FIG. 17; FIG. 19 is a fragmentary cross-sectional view of the semiconductor device, explaining the method for manufacturing the semiconductor device following FIG. 18; It is a schematic sectional drawing which shows the other example of the mounting process which solder-connects each surface mount component which is this Embodiment 2 to a module board collectively. It is a schematic sectional drawing which shows the other example of the mounting process which solder-connects each surface mounting component which is this Embodiment 3 to a module board collectively. It is a schematic sectional drawing which shows the other example of the mounting process which solder-connects each surface mounting component which is this Embodiment 4 to a module board collectively.

  In this embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. Some or all of the modifications, details, supplementary explanations, and the like are related. Further, in this embodiment, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), unless otherwise specified, or in principle limited to a specific number in principle. The number is not limited to the specific number, and may be a specific number or more. Further, in the present embodiment, the constituent elements (including element steps and the like) are not necessarily essential unless particularly specified and apparently essential in principle. Yes. Similarly, in this embodiment, when referring to the shape, positional relationship, etc. of the component, etc., the shape, etc. substantially, unless otherwise specified, or otherwise considered in principle. It shall include those that are approximate or similar to. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted.

  Before describing this embodiment in detail, the meaning of terms in this embodiment will be described as follows.

  GSM (Global System for Mobile Communication) is one of the wireless communication systems or standards used for digital mobile phones. GSM has three frequency bands of radio waves to be used. 900 MHz band is GSM900 or simply GSM, 1800 MHz band is GSM1800, DCS (Digital Cellular System) 1800 or PCN (Personal Communication Network), 1900 MHz band is GSM1900, DCS1900 or PCS (Personal Communication Services). GSM1900 is mainly used in North America. In North America, GSM850 in the 850 MHz band may be used.

  The GMSK (Gaussian filtered Minimum Shift Keying) modulation method is a method used for communication of audio signals, and is a method for shifting the phase of a carrier wave according to transmission data. Further, the EDGE (Enhanced Data GSM Environment) modulation method is a method used for data communication and is a method in which an amplitude shift is further added to the phase shift of GMSK modulation.

  Further, in this embodiment, a MOS • FET (Metal Oxide Semiconductor Field Effect Transistor) representing a field effect transistor is abbreviated as MOS, and an n-channel MOS • FET is abbreviated as nMOS.

  In the present embodiment, a chip in which one or a plurality of active elements are formed on one substrate among a plurality of surface-mounted components mounted on one module substrate is called a semiconductor chip. A chip on which a passive element such as a capacitor, an inductor, or a resistor is formed on one substrate is called a chip component. Furthermore, a chip in which one passive element is formed on one substrate is referred to as a single chip component, and a chip in which a plurality of passive elements are formed on one substrate is referred to as an integrated chip component. If there is, it is described as an integrated chip component or a single chip component.

(Embodiment 1)
In the first embodiment, for example, a case where the present invention is applied to a digital cellular phone that transmits information using a GSM network will be described.

  FIG. 1 shows an example of a digital mobile phone system according to the first embodiment. In the figure, PM is a power amplifier, ANT is an antenna for transmitting and receiving signal radio waves, 1 is a front-end device, 2 is a voice signal converted into a baseband signal, a received signal is converted into a voice signal, and a modulation method is switched. Baseband circuit 3 for generating signals and band switching signals, 3 down-converts the received signal and demodulates it, generates a baseband signal and modulates the transmission signal, FLT1 and FLT2 receive It is a filter that removes noise and interference from signals. The filter FLT1 is for GSM, and the filter FLT2 is for DCS.

  The front end device 1 includes impedance matching circuits MN1 and MN2, low-pass filters LPF1 and LPF2, switch circuits 4a and 4b, capacitors C1 and C2, and a duplexer 5. Impedance matching circuits MN1 and MN2 are connected to the transmission output terminal of the power amplifier PM to perform impedance matching, low-pass filters LPF1 and LPF2 are circuits that attenuate harmonics, and switch circuits 4a and 4b are circuits for switching between transmission and reception. Capacitors C1 and C2 are elements for cutting a direct current component from a received signal, and a demultiplexer 5 is a circuit for demultiplexing a GSM900 signal and a DCS1800 signal. In the digital cellular phone according to the first embodiment, the power amplifier PM and the front-end device 1 are assembled into one module MA.

  The switching signals CNT1 and CNT2 of the switch circuits 4a and 4b are supplied from the baseband circuit 2. The baseband circuit 2 includes a plurality of semiconductor integrated circuits such as a DSP (Digital Signal Processor), a microprocessor, and a semiconductor memory.

  FIG. 2 shows an example of a circuit of the power amplifier PM.

  The power amplifier PM can use, for example, two frequency bands of GSM900 and DCS1800 (dual band system), and can use two communication systems of the GMSK modulation system and the EDGE modulation system in each frequency band.

  The power amplifier PM includes a power amplifier circuit A for GSM900, a power amplifier circuit B for DCS1800, and a peripheral circuit 6 that controls and corrects the amplification operation of the power amplifier circuits A and B. . Each of the power amplifier circuits A and B has three amplification stages A1 to A3 and B1 to B3 and three matching circuits AM1 to AM3 and BM1 to BM3. That is, the input terminals 7a and 7b of the power amplifier PM are electrically connected to the inputs of the first amplification stages A1 and B1 via the input matching circuits AM1 and BM1, and are connected to the first amplification stage A1, The output of B1 is electrically connected to the inputs of the second amplification stages A2 and B2 via interstage matching circuits AM2 and BM2, and the outputs of the second amplification stages A2 and B2 are for interstage use. The matching circuits AM3 and BM3 are electrically connected to the inputs of the final amplification stages A3 and B3, and the outputs of the final amplification stages A3 and B3 are electrically connected to the output terminals 8a and 8b. In the first embodiment, elements constituting such power amplifier circuits A and B are provided in one semiconductor chip IC1.

  The peripheral circuit 6 includes a control circuit 6A and a bias circuit 6B for applying a bias voltage to the amplification stages A1 to A3 and B1 to B3. The control circuit 6A is a circuit that generates a desired voltage to be applied to the power amplifier circuits A and B, and includes a power supply control circuit 6A1 and a bias voltage generation circuit 6A2. The power supply control circuit 6A1 is a circuit that generates a first power supply voltage to be applied to the outputs of the amplification stages A1 to A3 and B1 to B3. The bias voltage generation circuit 6A2 is a circuit that generates a first control voltage for controlling the bias circuit 6B.

  In the first embodiment, when the power supply control circuit 6A1 generates the first power supply voltage based on the output level designation signal supplied from the baseband circuit 2 outside the power amplifier PM, the bias voltage generation circuit 6A2 generates the power supply control circuit. The first control voltage is generated based on the first power supply voltage generated by 6A1. The baseband circuit 2 is a circuit that generates an output level designation signal. This output level designation signal is a signal that designates the output level of the power amplifier circuits A and B, and is generated based on the distance between the mobile phone and the base station, that is, the output level corresponding to the strength of radio waves. It is like that. In the first embodiment, the elements constituting such a peripheral circuit 6 are also provided in one semiconductor chip IC1.

  Also, external terminals formed on the main surface (surface on which circuit elements are formed) of the semiconductor chip IC1 constituting the power amplifier PM, and a substrate formed on the component mounting surface of the module substrate on which the semiconductor chip IC1 is mounted. The side terminals are connected via a bonding material (for example, a bonding wire BW), and through this connection material, the input and output of each amplification stage are transmission lines 9a1 to 9a5, 9b1 to 9b5, 9c on the component mounting surface of the module substrate. And are electrically connected.

  The transmission lines 9a1 and 9b1 connected to the inputs of the first amplification stages A1 and B1 through the bonding wires BW are electrically connected to the input terminals 10a and 10b through the capacitors Cm1 and Cm2, respectively. The transmission lines 9a2 and 9b2 that are electrically connected to the outputs of the first amplification stages A1 and B1 through the bonding wires BW are electrically connected to the high-potential side power supply terminals 11a1 and 11b1, respectively. The power supply terminals 11a1 and 11b1 are electrically connected to the ground potential GND through capacitors Cm3 and Cm4 disposed in the vicinity. The transmission lines 9a3 and 9b3 electrically connected to the outputs of the second amplification stages A2 and B2 through the bonding wires BW are electrically connected to the high potential side power supply terminals 11a2 and 11b2, respectively. The power supply terminals 11a2 and 11b2 are electrically connected to the ground potential GND through capacitors Cm5 and Cm6 disposed in the vicinity. The transmission lines 9a4 and 9b4 electrically connected to the outputs of the final amplification stages A3 and B3 through the bonding wires BW are electrically connected to the high potential side power supply terminals 11a3 and 11b3, respectively. The power supply terminals 11a3 and 11b3 are electrically connected to the ground potential GND through capacitors Cm7 and Cm8 disposed in the vicinity. Further, the transmission lines 9a5 and 9b5 electrically connected to the outputs of the final amplification stages A3 and B3 through the bonding wires BW are electrically connected to the output terminals 12a and 12b via the capacitors Cm9 and Cm10, respectively. And electrically connected to the ground potential GND through capacitors Cm11 and Cm12 arranged in the middle of the respective lines. The transmission line 9 c electrically connected to the external terminal for control of the peripheral circuit 6 through the bonding wire BW is electrically connected to the control terminal 13. The bonding wire BW has a function as an inductor. Further, the transmission lines 9a1 to 9a5 and 9b1 to 9b5 have a function as inductors for impedance matching. Capacitors Cm1 to Cm12 have a function as capacitors for impedance matching and are constituted by chip parts.

  Next, the structure of typical elements in the front end device 1 and the power amplifier PM mounted on the module MA will be described. FIG. 3 is an explanatory diagram of the structure of the low-pass filters LPF1 and LPF2 constituting the front end device 1, and FIGS. 4 to 7 are explanatory diagrams of the structures of the amplification stages A1 to A3 and B1 to B3 constituting the power amplifier PM. Indicates.

  First, an example of the structure of the low-pass filters LPF1 and LPF2 constituting the front end device 1 will be described with reference to a cross-sectional view of relevant parts shown in FIG. The low-pass filters LPF1 and LPF2 are integrated chip components in which a plurality of passive elements are formed on one substrate, so-called IPD (Integrated Passive Device), and an example of the circuit configuration is shown in FIG. 3A, the structure of the capacitor Cp2 and the inductor Lp2 in the circuit configuration (capacitors Cp1 to Cp3 and Lp1 to Lp3) shown in FIG. 3B will be described.

A semiconductor substrate (hereinafter simply referred to as a substrate) S1 that constitutes the integrated chip component ID is made of, for example, p ⁺ type silicon (Si) single crystal. Although not described on the substrate S1, other elements, For example, a register or the like is formed and covered with an insulating film 14. On the insulating film 14, a capacitor Cp2 including a lower layer electrode 15b, a capacitive insulating film CSL, and an upper layer electrode 15t is formed. The lower layer electrode 15b and the upper layer electrode 15t are made of, for example, an aluminum (Al) alloy film, and the capacitive insulating film CSL is made of, for example, silicon nitride (SiN or the like). In the region where the capacitor insulating film CSL is not formed, the lower electrode 15b and the upper electrode 15t are insulated by a silicon oxide (SiO ₂ or the like) film 16a. The upper electrode 15t is covered with an insulating film in which a silicon nitride (SiN ₂ or the like) film 16b, a silicon oxide film 16c, and a polyimide resin film 16d are sequentially deposited from the lower layer, and the surface of the polyimide resin film 16d is flattened. Has been.

  On the polyimide resin film 16d, an inductor Lp2 made of, for example, a copper (hereinafter referred to as Cu) film is formed. The inductor Lp2 is formed by forming a groove in a predetermined region of the insulating film 17 deposited on the polyimide resin film 16d and burying a Cu film inside the groove. The inductor Lp2 is connected to the upper layer electrode 15t that is one electrode of the capacitor Cp2 through connection holes 18a to 18c formed in the silicon nitride film 16b, the silicon oxide film 16c, and the polyimide resin film 16d. The inductor Lp2 is covered with a polyimide resin film 20, and a part of the inductor Lp2 is opened, and a bump electrode 21 that is a bump-like protruding electrode made of solder is connected to the inductor Lp2. Between the inductor Lp2 and the bump electrode 21, a nickel (hereinafter referred to as Ni) film and a gold (hereinafter referred to as Au) film are sequentially deposited from the lower layer, and a patterned plating layer 22 is formed. .

  Thus, in the low-pass filters LPF1 and LPF2, the capacitors Cp1 to Cp3 and the inductors Lp1 to Lp3 are formed on one substrate S1. The integrated chip component ID on which the low pass filters LPF1 and LPF2 are formed is mounted on the module substrate with the main surface facing downward (face down), and is formed on the main surface of the integrated chip component ID. The connection terminals (for example, the bump electrodes 21) and the board side terminals formed on the component mounting surface of the module board are electrically connected.

  Next, an example of the internal configuration of the power amplifier PM1 in which the amplification stage is composed of nMOS will be described with reference to a plan view of relevant parts shown in FIG. The power amplifier PM1 is formed on one semiconductor chip IC1.

The substrate S2 on which the power amplifier PM1 is formed is made of, for example, p ⁺ type silicon single crystal, and its resistivity is, for example, a low resistance substrate of about 1 to 10 mΩ · cm. On the substrate S2, an epitaxial layer EP made of, for example, p ⁻ type silicon single crystal is formed. The resistivity of the epitaxial layer EP is higher than the resistivity of the substrate S2. The main surface of the epitaxial layer EP includes an nMOS Qn for the amplification stages A1 to A3, B1 to B3, an inductor L for the matching circuits AM1 to AM3 and BM1 to BM3, a capacitor C having a high Q (Quality factor) value and a transmission. A track is formed. Here, nMOS Qn1 and Qn2 of two amplification stages are shown. Actually, however, all the amplification stages A1 to A3 and B1 to B3 of two to three stages are actually the same substrate S2 as described above. Is formed. The nMOS Qn shown here represents a unit MOS, and actually, a plurality of unit MOSs are connected in parallel to form one amplification stage A1 to A3, B1 to B3.

The nMOS Qn is formed of a lateral MOS such as an LDMOS (Laterally Diffused MOS). A p-type well PWL is formed in the epitaxial layer EP in the formation region of the nMOS Qn. The well PWL is formed by ion-implanting impurities such as boron (B) into the epitaxial layer EP. Further, an nMOSQn gate insulating film 23 is formed on the well PWL. The gate insulating film 23 is made of, for example, silicon oxide, and is formed by, for example, a thermal oxidation method. On the gate insulating film 23, an nMOS Qn gate electrode 24 is formed. The gate electrode 24 is composed of, for example, a laminated conductor film of polycrystalline silicon and a metal silicide layer (for example, a titanium silicide (TiSi ₂ ) layer or a cobalt silicide (CoSi) layer) formed thereon. The channel of the nMOS Qn is formed above the well PWL under the gate electrode 24.

An n ⁺ type semiconductor region 25 is formed in the well PWL region in the vicinity of one end of the gate electrode 24. The n ⁺ -type semiconductor region 25 is a region that functions as a source of the nMOS Qn, and is formed, for example, by ion-implanting impurities such as phosphorus (P) into the well PWL. An n ⁻ type semiconductor region 26 a is formed in the epitaxial layer EP near the other end of the gate electrode 24. Then, n from the other end of the gate electrode 24 ^- the amount apart locations type semiconductor region 26a is, n ⁺ -type semiconductor region 26b the n ^- are formed in the semiconductor region 26a is electrically connected state (LDD (Lightly Doped Drain) structure). The n ⁻ type semiconductor region 26 a and the n ⁺ type semiconductor region 26 b are regions that function as the drain of the nMOS Qn, and are formed by ion-implanting impurities such as phosphorus into the well PWL.

Further, in the epitaxial layer EP in the formation region of each nMOS Qn, the p ⁺⁺ type semiconductor region 27a is formed so as to be in contact with the n ⁺ type semiconductor regions 25 and 26b. The p ⁺⁺ type semiconductor region 27a is doped with, for example, boron, and is formed so as to surround the nMOS Qn when viewed in plan, and is formed so as to reach the substrate S2 from the main surface of the epitaxial layer EP when viewed in cross section. ing. Further, ^{n +} -type semiconductor region 25 for source of each nMOSQn is, ^{p ++} type semiconductor region 27a and are electrically connected via the plug PL1, electrically connected to the low resistance substrate S2 via the ^{p ++} type semiconductor region 27a Has been.

  As will be described later, the semiconductor chip IC1 is mounted on the module substrate with its back surface facing the component mounting surface of the module substrate. The substrate S2 is electrically connected to the substrate-side terminal of the module substrate on which the semiconductor chip IC1 is mounted via the electrode BL formed of metal on the entire back surface, and a reference potential (for example, 0 V at the ground potential GND) through the wiring. Degree: fixed potential). That is, the substrate S2 serves as a common ground portion for the plurality of nMOS Qn formed in the semiconductor chip IC1.

The plug PL1 connected to the n ⁺ -type semiconductor region 25 for the source of the preceding nMOS Qn1 is electrically connected to the first layer wiring M1. The gate electrode 24 of the nMOS Qn1 is electrically connected to the second layer wiring M2 through the plug PL2 and the first layer wiring M1. The second layer wiring M2 is an input wiring for the nMOS Qn1. The n ⁺ -type semiconductor region 26b for drain of the nMOS Qn1 is electrically connected to the first layer wiring M1 through the plug PL3. The first layer wiring M1 is electrically connected to one end of the inductor L.

The inductor L is formed of, for example, a spiral second layer wiring M2. The outer periphery of the inductor L is surrounded by a first layer wiring M1, a second layer wiring M2, a plug PL4, and a p ⁺⁺ type semiconductor region 27b for shielding. The shielding first layer wiring M1, second layer wiring M2, plug PL4, and p ⁺⁺ type semiconductor region 27b are electrically connected to each other (insulated from the inductor L), and the p ⁺⁺ type semiconductor region. It is electrically connected to the low-resistance substrate S2 through 27b and set to the ground potential GND. The other end of the inductor L is electrically connected to the upper electrode Ca of the capacitor C through the second layer wiring M2.

In the wiring layer below the upper electrode Ca of the capacitor C, a lower electrode Cb is provided so as to face the upper electrode Ca with an insulating film interposed therebetween. The lower electrode Cb is, ^{p ++} type semiconductor region 27c and is electrically connected through the plug PL5, it is further connected a low-resistance substrate S2 and the electrically through ^{p ++} type semiconductor region 27c. The outer periphery of the capacitor C is also surrounded by the first layer wiring M1, the second layer wiring M2, the plug PL6, and the p ⁺⁺ type semiconductor region 27d for shielding. The shielding first layer wiring M1, second layer wiring M2, plug PL6, and p ⁺⁺ type semiconductor region 27d are electrically connected to each other (insulated from the capacitor C1), and the p ⁺⁺ type semiconductor region. It is electrically connected to the low-resistance substrate S2 through 27d and set to the ground potential GND. The upper electrode Ca of the capacitor C is electrically connected to the gate electrode 24 of the nMOS Qn2 through the second layer wiring M2. The plugs PL1 to PL6 are made of a metal such as tungsten (W), for example. Further, the first layer wiring M1 and the second layer wiring M2 are formed of metal using, for example, aluminum or Cu as a main wiring material.

  The semiconductor chip IC1 on which the power amplifier PM1 is formed is mounted on the module substrate with the main surface facing upward (face up), and is formed on the external terminals of the semiconductor chip IC1 and the component mounting surface of the module substrate. The substrate-side terminal is electrically connected by a bonding material, for example, a bonding wire BW made of a fine Au wire.

  Next, an example of the internal configuration of the power amplifier PM2 in which the amplification stage is configured by a hetero-junction bipolar transistor (HBT) is illustrated in a plan view of the main part shown in FIG. 6 and a cross-sectional view of the main part shown in FIG. This will be described with reference to (a cut surface along line AA in FIG. 6). The power amplifier PM1 is formed on one semiconductor chip IC1 as in the case where the amplification stage is configured by an nMOS.

  Of the amplification stages A1 to A3 and B1 to B3 shown in FIG. 2, the amplification stages A1 and B1 used in the first stage are required to be reduced in noise. The amplification stages A3 and B3 used for the stages are preferably composed of, for example, an HBT because a high amplification factor is required. The amplification stages A2 and B2 used in the middle stage may use either nMOS or HBT. Therefore, for example, when the amplification stages A1, A2, B1, and B2 are configured by nMOS and the amplification stages A3 and B3 are configured by HBT, the power amplifier is not formed on one semiconductor chip but on two semiconductors. It is divided into chips. Also, in practice, one amplification stage is formed by connecting a plurality of unit HBTs in parallel. Here, for example, three HBT1 to HBT3 constituting the amplification stage A3 used at the final stage are arranged. explain.

The substrate S3 on which the HBT1 to HBT3 are formed is made of, for example, a semi-insulating GaAs substrate S3. HBT1 to HBT3 are formed, for example, on the subcollector layer 28 made of an n ⁺ -type GaAs layer separated from other elements by mesa isolation 28a at a predetermined interval. Here, since HBT1 to HBT3 have the same configuration, among HBT1 to HBT3, for example, the configuration of HBT1 formed at the left end will be described. The HBT 1 has a collector electrode 29 formed on the sub-collector layer 28 and a collector mesa 30 formed with a predetermined distance from the collector electrode 29. The collector electrode 29 is made of, for example, Au.

  The collector mesa 30 is formed of, for example, an n-type GaAs layer, and the collector mesa 30 and the collector electrode 29 are electrically connected via the subcollector layer 28. A base mesa 31 made of, for example, a p-type GaAs layer is formed on the collector mesa 30.

  A base electrode 32 made of Au or the like is formed in the peripheral region on the base mesa 31. That is, a base electrode 32 is formed on the base mesa 31. The base electrode 32 has a shape obtained by rotating a U-shape 90 degrees counterclockwise. An emitter layer 33 is formed on a substantially central portion of the base mesa 31, and an emitter electrode 34 is formed on the emitter layer 33. The emitter layer 33 is formed of, for example, a laminated film in which an n-type InGaP layer, a GaAs layer, and an InGaAs layer are sequentially deposited from the lower layer, and the emitter electrode 34 is formed of, for example, tungsten silicide (WSi).

  Thus, a heterogeneous semiconductor junction (heterojunction) is formed between the base mesa (p-type GaAs layer) 31 and the emitter layer (n-type InGaP layer) 33. The HBT 1 in the first embodiment has a structure in which the collector electrode 29 is formed in the lowermost layer, the emitter electrode 34 is formed in the uppermost layer, and the base electrode 32 is formed in the intermediate layer. It has become.

  The HBT 1 is configured as described above, and the HBT 2 and HBT 3 having the same configuration as the HBT 1 are formed side by side in the horizontal direction.

  The collector electrodes 29 of HBT1 to HBT3 are commonly connected to the first collector wiring M1c through a connection hole 35a in which a conductive material is embedded. That is, the first collector wiring M1c is for electrically connecting the collector electrodes 29 of HBT1 to HBT3 and is formed in the first wiring layer. The base electrodes 32 of the HBT1 to HBT3 are commonly connected to the first base wiring M1b through a connection hole 35b in which a conductive material is embedded. The first base wiring M1b is also formed in a first wiring layer that is the same layer as the first collector wiring M1c.

  Each emitter electrode 34 of HBT1 to HBT3 is commonly connected to the emitter wiring M2e by a connection hole 36a embedded with a conductive material. That is, the emitter wiring M2e extends in the direction in which the HBT1 to HBT3 are arranged, and is connected to each emitter electrode 34 through the connection hole 36a in which a conductive material is embedded. The emitter wiring M2e is formed in the second wiring layer above the first wiring layer. The reason why the emitter wiring M2e is formed in the second wiring layer is that the emitter electrode 34 is formed at a position higher than the base electrode 32 and the collector electrode 29. The first collector wiring M1c is connected to the second collector wiring M2c through a connection hole 36b embedded with a conductive material, and the first base wiring M1b is connected to the second base wiring through a connection hole 36b embedded with a conductive material. It is connected to M2b. The second collector wiring M2c and the second base wiring M2b are formed in the second wiring layer.

  An emitter bump electrode 37a is formed directly on the emitter wiring M2e formed in the second wiring layer. That is, the emitter bump electrode 37a is formed in the third wiring layer, and this third wiring layer is formed directly on the second wiring layer without a connection hole between the third wiring layer and the second wiring layer. .

  The emitter bump electrode 37a extends in the direction in which the HBT1 to HBT3 are arranged, and is electrically connected to each emitter electrode 34 via an emitter wiring M2e formed in the second wiring layer. A collector bump electrode 37c is directly formed on the second collector wiring M2c, and a base bump electrode 37b is directly formed on the second base wiring M2b. Since the collector bump electrode 37c, the emitter bump electrode 37e, and the base bump electrode 37b are formed in the same third wiring layer, the element formation surface of the semiconductor chip IC is flattened.

  The semiconductor chip IC1 on which the power amplifier PM2 is formed is mounted on the module substrate with the main surface facing downward (face-down), and the collector bump electrode 37c, the emitter bump electrode 37e, and the base bump electrode 37b are mounted on the module substrate. To the board-side terminal formed on the component mounting surface.

  Next, the configuration of the module MA after the primary mounting in which the surface mounting component is mounted on the module substrate will be described. FIG. 8 shows an example of the primary mounting of the module MA in the digital mobile phone according to the first embodiment. Here, the front end device 1 and the power amplifier PM described above are assembled into one module MA, but it goes without saying that the present invention is not limited to this. For example, the front end device 1 and the power amplifier PM may be configured as separate modules. Although the semiconductor chip IC1 having the power amplifier PM1 whose amplification stage is composed of nMOS will be described as an example here, a semiconductor chip having the power amplifier PM2 whose amplification stage is composed of HBT may be used. In this case, face-down connection is performed with the main surface facing the main surface of the module substrate. Further, when the preceding stage of the amplification stage is configured by nMOS and the subsequent stage is configured by HBT, two semiconductor chips are used for the power amplifier PM.

  The module MA uses a PCB (first wiring board) 38 having a multilayer wiring structure in which a plurality of insulating plates are stacked and integrated as a substrate. On the component mounting surface (first surface) of the PCB 38, substrate-side terminals 40a1, 40a2, 40b, 40c made of, for example, a Cu film and wirings are formed in a pattern, and on the back surface (second surface), for example, a Cu film Electrodes 42G and 42S made of are patterned. Further, FIG. 8 shows semiconductor chips IC1 and IC2 in which active elements are formed as surface-mounted components to be mounted on the component mounting surface of the PCB 38, and a single chip in which one passive element is formed on one chip substrate. The component 43 and the integrated chip component 44 in which a plurality of passive elements are formed on one chip substrate are illustrated. Further, these surface mount components are covered with a highly elastic sealing resin 45. The resin 45 is, for example, a highly elastic epoxy resin, and its allowable elastic modulus is preferably 2 GPa or higher at a temperature of 180 ° C. or higher.

  Of the two semiconductor chips IC1 and IC2 illustrated in FIG. 8, one semiconductor chip IC1 is an active element that generates more heat than the passive element, for example, the power amplifier PM1, and the other semiconductor chip IC2 is compared to the active element. Active elements that generate less heat, such as antenna switches. A plurality of external terminals (surface electrodes) formed on the main surfaces of the semiconductor chips IC1 and IC2 are connected to the corresponding board side terminals 40c of the PCB 38 by bonding materials. Here, a bonding wire BW made of a fine Au wire is used as the bonding material.

  The back surface of the semiconductor chip IC1 is bonded to a chip mounting substrate side terminal (first substrate side terminal) 40a1 formed on the component mounting surface of the PCB 38, and a solder (first solder) 46 is used as a die bonding material. It is fixed on the top. As the solder 46, for example, a high melting point solder that becomes liquid at a temperature of 280 ° C. or higher, for example, Pb—Sn solder containing Pb is used. The Sn content of the Pb—Sn solder is considered to be an appropriate range of, for example, 2 to 30 wt% (not to be limited to this range depending on other conditions). In addition, a range suitable for mass production is 2 to 10 wt%, and a peripheral range centered on 10 wt% is considered most preferable. By using the high melting point solder, the adhesive strength between the semiconductor chip IC1 and the PCB 38 can be secured even if a large amount of heat is generated, and the peeling of the semiconductor chip IC1 from the PCB 38 can be prevented.

  The back surface electrode of the semiconductor chip IC1 (for example, the back surface electrode BL in FIG. 5) is an electrode formed on the back surface of the PCB 38 through a conductive material in a plurality of heat radiation vias 47 formed so as to penetrate from the component mounting surface of the PCB 38 to the back surface. It is electrically and thermally joined to 42G. A reference potential (for example, about 0 V at the ground potential GND) is supplied to the electrode 42G. That is, the reference potential supplied to the electrode 42G on the back surface of the PCB 38 is supplied to the back surface of the semiconductor chip IC1 through the heat dissipation via 47 and the substrate side terminal 40a1. Conversely, the heat generated during the operation of the semiconductor chip IC1 is transmitted from the back surface of the semiconductor chip IC1 to the electrode 42G formed on the back surface of the PCB 38 through the chip mounting substrate side terminal 40a1 and the heat radiating via 47 so as to be dissipated. It has become. An electrode 42S in the vicinity of the outer periphery formed on the back surface of the PCB 38 represents a signal electrode.

  The back surface of the semiconductor chip IC2 is bonded to a chip mounting board side terminal 40a2 formed on the component mounting surface of the PCB 38, and is fixed on the PCB 38 using a solder 48a as a die bond material. For this solder 48a, for example, Pb-free solder that does not contain Pb that becomes liquid at a temperature of 200 ° C. or higher, for example, Sn containing Ag 3 wt% and Cu 0.5 w% (hereinafter referred to as Sn-3Ag-0.5Cu solder) is used. .

  The single chip component 43 is a surface mount component in which passive elements such as capacitors, inductors, resistors, or ferrite beads are mounted on one substrate. Ferride beads have a structure in which an internal electrode for energization is embedded in a ferrite element, and the ferrite acts as a magnetic material, so that a high-frequency current component that causes electromagnetic interference (EMI) noise is generated. It is an element to absorb. The single chip component 43 is mounted on the PCB 38 with its back surface facing the component mounting surface of the PCB 38, and connection terminals formed at both ends of the single chip component 43 are connected via solder (second solder) 48b. The board side terminal (second board side terminal) 40b formed on the component mounting surface of the PCB 38 is soldered. For this solder connection, Pb-free solder containing no Pb, for example, Sn-3Ag-0.5Cu solder is used. The distance between the back surface of the single chip component 43 and the component mounting surface of the PCB 38 is, for example, about 10 μm. The gap is filled with the sealing resin 45 without forming voids.

  The integrated chip component 44 is a surface-mounted component in which a plurality of passive elements such as the low-pass filters LPF1 and LPF2 shown in FIG. 3 are formed. The integrated chip component 44 is flip-chip connected to the PCB 38, and a connection terminal (for example, FIG. 3) formed on the main surface of the integrated chip component 44 with the main surface of the integrated chip component 44 facing the component mounting surface of the PCB 38. The bump electrode 21) is solder-connected to a substrate side terminal (second substrate side terminal) 40b formed on the component mounting surface of the PCB 38 via a solder (second solder) 48c. For this solder connection, Pb-free solder containing no Pb, for example, Sn-3Ag-0.5Cu solder is used. The distance between the main surface of the integrated chip component 44 and the component mounting surface of the PCB 38 is, for example, about 10 to 20 μm. The gap is filled with the sealing resin 45 without forming voids.

  Although the Pb-free solder is used as the solder material used for the solder connection of the semiconductor chip IC2, the single chip component 43 and the integrated chip component 44, the solder material is not limited to this and can be variously changed. For example, Sn containing Pb (hereinafter referred to as Pb—Sn solder) may be used. However, considering the Pb regulations in Europe, Pb-free solder is preferable.

  Further, since the bonding wires BW are used for the semiconductor chips IC1 and IC2, plating layers are formed on the surfaces of all the substrate side terminals 40a1, 40a2, 40b, and 40c. For example, the plating layer is a laminated film in which a Ni layer and an Au layer are plated in order from the lower layer. Accordingly, the single chip component 43 is solder-connected to the plating layer at its connection terminal, and the integrated chip component 44 is connected to the plating layer at its connection terminal, and is externally formed on the main surface of the semiconductor chips IC1 and IC2. The bonding wire BW connected to the terminal for use is connected to the plating layer on the surface of the substrate side terminal 40c.

  Next, the configuration of the module MA after the secondary mounting in which the module MA is further mounted on a mounting wiring board (motherboard) for incorporation into a product will be described. FIG. 9 shows an example of secondary mounting of the module MA in the digital mobile phone according to the first embodiment.

  The mother board (second wiring board) 50 is composed of, for example, a printed wiring board having a multilayer wiring structure, and the main surface (first surface) is mounted with a module MA and a plurality of other single chip components 51 and the like. Yes. As described above, the module MA employs the PCB 38 as its substrate, and the component mounting surface of the PCB 38 is covered with the resin 45, whereby the semiconductor chips IC1 and IC2 mounted on the component mounting surface of the PCB 38, and the single chip. The component 43, the integrated chip component 44, and the like are sealed. The module MA is mounted on the motherboard 50 with the electrodes 42G, 42S and the like formed on the back surface of the PCB 38 facing the main surface of the motherboard 50. The electrodes 42G and 42S are connected to printed wiring formed on the main surface of the mother board 50 through a bonding material such as solder (third solder) 53, respectively.

  Next, an example of the primary mounting process and the secondary mounting process of the module MA according to the first embodiment will be described in the order of processes with reference to FIGS. FIG. 10 is a process diagram for explaining the assembly procedure of the module MA, FIG. 11 is a partially enlarged view of the PCB 38 on which four layers of copper wiring are formed, and FIGS. 12 to 19 are semiconductor devices showing one module region. FIG.

  The primary mounting process of the module MA will be described.

  First, for example, a PCB 38 shown in FIG. 11 is prepared. The PCB 38 is a multi-piece substrate in which module areas, which are a plurality of device areas (for example, about 120), are partitioned by partition lines. For example, when 120 module areas are formed, the size of the PCB 38 is an example. Is about 80 mm × 80 mm, and the thickness is about 0.3 mm. In the PCB 38, inner layer Cu films 57 (second layer and third layer wiring) are patterned on the upper and lower sides of the core material 56, and these inner layer Cu films 57 are sandwiched between insulating materials called prepregs 58. The inner layer Cu film 57 has a thickness of about 0.2 mm, for example, and the prepreg 58 has a thickness of about 0.06 mm, for example. Further, the outer surface of the prepreg 58 is a surface (component mounting surface) on which a surface mounting component such as a semiconductor chip or a chip component in each module region is mounted. The eyes and the fourth layer wiring) are patterned. The outer layer Cu film 59 is the substrate side terminals 40a1, 40a2, 40b, and 40c shown in FIG. 8, and the thickness thereof is, for example, about 0.02 mm. On the surface of the outer layer Cu film 59, for example, a plating layer in which a Ni layer and an Au layer are sequentially formed from the lower layer is formed. Furthermore, the outer layer Cu film 59 is covered with a solder resist 60 except for a region where a surface mount component such as a semiconductor chip or a chip component is mounted. The thickness of the solder resist 60 is, for example, about 0.025 to 0.05 mm.

  A via 61 in which a Cu film penetrating the core material 56 or the prepreg 58 is embedded between the upper and lower inner layer Cu films 57 or between the inner layer Cu film 57 and the outer layer Cu film 59. It is electrically connected via. In addition, in the area where the semiconductor chip IC1 is mounted in each module area, a heat dissipation via 47 in which a Cu film penetrating the core material 56 and the prepreg 58 is embedded is formed. The core material 56, the prepreg 58, and the solder resist 60 are made of a resin such as epoxy.

  Next, solder printing is performed (step P1 in FIG. 10). First, as shown in FIG. 12, a printing mask 63 is placed on the component mounting surface of the PCB 38. The printing mask 63 is made of, for example, stainless steel having a thickness of about 0.2 mm, and a hole is formed at a desired location by etching. Subsequently, after the positions of the printing mask 63 and the PCB 38 are determined, the solder 48 is placed on one end of the printing mask 63 and the solder 48 is moved using the squeegee 65. The solder 48 is Pb-free solder, for example, Sn-3Ag-0.5Cu solder. As a result, as shown in FIG. 13, the solders 48a, 48b, and 48c are printed on the predetermined board-side terminals 40a2 and 40b formed on the component mounting surface of the PCB 38. At this time, the squeegee 65 is printed so that the solder 48 rolls at an inclination of, for example, about 45 degrees. Subsequently, as shown in FIG. 14, by removing the printing mask 63, solder 48a is formed on the substrate-side terminals 40a2 and 40b to which the single chip component 43, the integrated chip component 44, and the semiconductor chip IC2 are connected in a later process. , 48b, 48c.

  Next, solder for the semiconductor chip IC1 is applied (step P2 in FIG. 10). As shown in FIG. 15, the solder 46 is supplied from the potting nozzle 66 to the place where the semiconductor chip IC1 is mounted, and the solder 46 is applied on the substrate side terminal 40a1 to which the semiconductor chip IC1 is connected. As the solder 46, for example, a high melting point solder containing Pb that is in a liquid state at a temperature of 280 ° C. or higher is used.

  Next, as shown in FIG. 16, the single chip component 43, the integrated chip component 44, and the semiconductor chips IC1 and IC2 are disposed on predetermined substrate side terminals 40a1, 40a2, and 40b (process P3 in FIG. 10). Next, as shown in FIG. 17, the PCB 38 is placed on the heat block 67 and reflowed to melt the solders 46, 48a, 48b, and 48c, and the surface mount components are soldered together (see FIG. 10). Step P4). At this time, the heat block 67 is set to a temperature lower than 280 ° C., for example, 250 ° C., in order to prevent the solder resist 60 constituting the PCB 38 from being burnt and the prepreg 58 from being peeled off from the core material 56. The solder 48a, 48b, and 48c are melted by the heating by the heat block 67, and the connection terminals at both ends of the single chip component 43 and the substrate side terminal 40b are solder-connected by the solder 48b, and the connection terminals of the integrated chip component 44 and the substrate are connected. The side terminal 40b is solder-connected with the solder 48c, and the semiconductor chip IC2 and the substrate side terminal 40a2 are solder-connected with the solder 48c.

  Further, in addition to the heating by the heat block 67, the semiconductor chip IC1 is locally heated at a temperature of 280 ° C. or higher, for example, 330 to 350 ° C. For local heating of the semiconductor chip IC1, for example, a hot jet 68 is used. By blowing dry air of 300 ° C. or more from the nozzle of the hot jet 68, the solder 46 is melted and the semiconductor chip IC1 and the substrate side terminal 40a1 are soldered. The hot jet has a structure in which the circumference of a pipe having an inner diameter of about 1 to 2 mm is wound with a nichrome wire, and the air introduced into the pipe is heated to a desired temperature by the nichrome wire, Blow dry air of 300 ° C or higher from the nozzle. One heating time by the hot jet 68 is, for example, about 5 seconds, and the flow rate of the dry air is, for example, about 8 liters / min. If the back surface of the semiconductor chip IC1 is in contact with the heat block 67 via the solder 46, the heat diffuses and escapes, and the temperature of the semiconductor chip IC1 may not rise. In order to avoid this, a recess 67a is formed in a region of the heat block 67 where the semiconductor chip IC1 is mounted so that the back surface of the semiconductor chip IC1 and the heat block 67 do not contact each other.

  As described above, the solder connection of the single chip component 43, the integrated chip component 44, and the semiconductor chip IC2 using the solders 48a, 48b, and 48c is performed by placing the PCB 38 on which each surface mount component is mounted on the heat block 67 at 280 ° C. At the same time, the solder connection of the semiconductor chip IC1 using the solder 46 is performed by a heat treatment at a temperature of 280 ° C. or higher using a hot jet. This prevents the PCB 38 from being damaged by heat, for example, burning of the solder resist 60, peeling of the prepreg 58 from the core material 56, and melting of the Pb-free solder (solder 48a, 48b, 48c). 46) can be used to solder-connect the semiconductor chip IC1 to the PCB 38. As a result, the semiconductor chip IC1 having strong adhesive strength can be mounted on the PCB 38.

  Next, the PCB 38 to which each surface mount component is soldered is cleaned (step P5 in FIG. 10), and then wire bonding (step P6 in FIG. 10) is performed. Here, as shown in FIG. 18, the pads exposed on the upper surfaces of the semiconductor chips IC1 and IC2 and the substrate side terminal 40c having a plating layer formed on the surface thereof are connected using bonding wires BW, for example, Au wires. .

  Next, transfer molding is performed to seal each surface mount component with the resin 45 (step P7 in FIG. 10). The upper die of the molding apparatus is raised, and the PCB 38 to which each surface mount component is soldered is placed in the lower die. Thereafter, the upper die is lowered to fix the PCB 38. The upper mold is provided with an air vent for sending air and resin in the molding mold between the upper mold and the lower mold to the outside. Subsequently, after the inside of the molding die is forcibly reduced to, for example, 1 Torr or less, the resin tablet is heated with a preheater, and the resin 45 liquefied after reducing the resin viscosity is pumped into the molding die. As the resin 45, for example, a thermosetting epoxy resin is used. Subsequently, after the sealing resin filled in the molding die is cured by a polymerization reaction, the upper die and the lower die are opened, and the PCB 38 covered with the resin 45 is taken out. Thereafter, unnecessary sealing resin 45 is removed, and a baking process is performed (step P8 in FIG. 10) to complete the polymerization reaction, thereby sealing each surface mount component shown in FIG. The completed module MA is completed.

  Thus, by introducing the resin 45 after decompressing the inside of the molding die, the fluidity of the resin 45 can be achieved, so that a narrow gap, for example, between the back surface of the single chip component 43 and the component mounting surface of the PCB 38 can be achieved. The gap 45 (about 10 μm) and the gap (about 30 μm) between the main surface of the integrated chip component 44 and the component mounting surface of the PCB 38 can be filled with the resin 45 while preventing formation of voids. As a result, when the module MA described below is assembled, even if heat at a temperature of about 250 ° C. is applied to cause the Pb-free solder to be partially melted, the flash-like flow of the Pb-free solder can be prevented. For example, the connection terminals on both ends of the single chip component 43 or the connection terminals on the main surface of the integrated chip component 44 are not connected, and a short circuit can be avoided.

  Next, the sealing resin 45 and the PCB 38 are cut along dicing lines and separated into individual modules MA (step P9 in FIG. 10). Thereafter, for example, a trademark, a product name, a lot number, etc. are imprinted on the surface of the resin 45 covering the module MA, and then the module MA is selected by measuring the electrical characteristics of the module MA according to items in light of the product standards (FIG. Step P10).

  Next, the secondary mounting process of the module MA will be described.

  On the back surface of the PCB 38, electrodes 42G and 42S for solder connection are formed so as to be mountable on the mother board 50. First, a solder paste is printed on the mother board 50. Subsequently, after the module MA is arranged on the mother board 50, a reflow process is performed at a temperature of about 250 ° C., for example, and the module MA is mounted on the mother board 50. After that, the electrical characteristics are tested and the mounting is completed. In the reflow process in the secondary mounting, a temperature (for example, about 250 ° C.) higher than a temperature (for example, about 220 ° C.) for solder-connecting the single chip component 43, the integrated chip component 44 and the semiconductor chip IC2 to the PCB 38 using Pb-free solder. ), The Pb-free solder may melt. However, since the amount of solder used for solder connection between the module MA and the mother board 50 can be reduced, the amount of Pb-free solder used for solder connection between the single chip component 43, the integrated chip component 44 or the semiconductor chip IC2 and the PCB 38 can be reduced. The amount of solder to be melted is so small that it becomes a flash and does not short-circuit between the connection terminals of the single chip component 43 or the integrated chip component 44.

  In the first embodiment, the case where each surface mount component mounted on the PCB 38 is covered with the highly elastic resin 45 has been described. However, the present invention is not limited to this. For example, a low elasticity resin such as silicone is used. It is also possible to use a resin.

  Further, the case where the present invention is applied to a dual band system capable of handling radio waves in two frequency bands of GSM900 and GSM1800 has been described, but the present invention is not limited to this. For example, three frequencies of GSM900, GSM1800, and GSM1900 are used. You may apply to the triple band system which can handle the electromagnetic wave of a belt. Moreover, it can respond also to 800 MHz band and 850 MHz band.

  As described above, according to the first embodiment, the solder connection between the single chip component 43 and the integrated chip component 44 is performed by the heat treatment using the heat block 67 at a temperature of less than 280 ° C. Therefore, the Pb-free solder is used. Further, damage to the PCB 38 due to heat, for example, burning of the solder resist 60 and peeling of the prepreg 58 from the core material 56 can be avoided. Furthermore, since the solder connection of the semiconductor chip IC1 at the same time as the solder connection is performed by a heat treatment at a temperature of 280 ° C. or higher using a hot jet, a high melting point solder can be used for the solder connection of the semiconductor chip IC1. The semiconductor chip IC1 having strong adhesive strength can be mounted on the PCB.

  Further, by reducing the pressure in the molding die and introducing the resin 45, the fluidity of the resin 45 can be improved. For example, a narrow gap between the back surface of the single chip component 43 and the component mounting surface of the PCB 38, or integration. The resin 45 can be filled without forming a void in a narrow gap between the main surface of the chip component 44 and the component mounting surface of the PCB 38. Thereby, after the module MA is solder-connected to the mother board 50, even if heat at a temperature of about 250 ° C. is applied and the Pb-free solder in the module MA is partially melted, the flash-like flow of Pb-free solder is generated. Therefore, for example, the connection terminals on both ends of the single chip component 43 or the connection terminals on the main surface of the integrated chip component 44 are not connected, and a short circuit can be avoided.

(Embodiment 2)
Another example of the mounting process in which the surface-mounted components according to the second embodiment are collectively solder-connected to the module substrate will be described. FIG. 20 is a fragmentary cross-sectional view of the semiconductor device for explaining the mounting method subsequent to FIG. 16 of the first embodiment.

  As in the first embodiment, the semiconductor chip IC1 is locally heated using the hot jet 68 at a temperature of 280 ° C. or higher, for example, 330 to 350 ° C., so that the semiconductor chip IC1 and the substrate-side terminal 40a1 have a high melting point. At this time, the heat block 67 is not heated, and all the surface mounted components mounted on the PCB 38 are covered with the cover 68a. The Pb-free solder is melted by the residual heat generated by the dry air blown from the nozzles of the hot jet 68 on the semiconductor chip IC1 being diffused in the cover 68a, and the single chip component 43, the substrate side terminal 40b, the integrated chip component 44, The region other than the semiconductor chip IC1 to which the substrate-side terminal 40b and the semiconductor-chip IC2 and the substrate-side terminal 40a2 are connected is heated only by the heat that the dry air blown out from the nozzle of the hot jet 68 escapes. The temperature can be suppressed to, for example, about 150 ° C. As a result, it is possible to prevent the solder resist 60 from being burnt and the prepreg 58 from being peeled off from the core material 56. Since the steps after the solder connection are the same as those in the first embodiment, description thereof is omitted.

  As described above, according to the second embodiment, the solder connection of the single chip component 43, the integrated chip component 44 or the semiconductor chip IC2 using Pb-free solder is performed using diffusion of dry air blown from the hot jet 68 to 280. The heat treatment is performed at a temperature of less than 0 ° C. As a result, the PCB 38 can be prevented from being damaged by melting or heat of the Pb-free solder.

(Embodiment 3)
Another example of the mounting process in which the surface mounting components according to the third embodiment are collectively soldered to the module substrate will be described. FIG. 21 is a fragmentary cross-sectional view of the semiconductor device for explaining the mounting method following FIG. 16 of the first embodiment.

  As in the second embodiment, the heat block 67 is not heated, all the surface mounting components mounted on the PCB 38 are covered with the cover 68a, and the semiconductor chip IC1 is heated to a temperature of 280 ° C. or higher using the hot jet 68. For example, local heating is performed at a temperature of 330 to 350 ° C., and the semiconductor chip IC1 and the substrate-side terminal 40a1 are connected with a high melting point solder. Also, the Pb-free solder is melted by the residual heat generated by the dry air blown from the nozzle of the hot jet 68 being diffused in the cover 68a, so that the single chip component 43 and the substrate side terminal 40b, the integrated chip component 44 and the substrate side terminal 40b. The semiconductor chip IC2 and the substrate side terminal 40a2 are connected.

  Further, in the third embodiment, in order to escape voids generated between the semiconductor chip IC1 and the PCB 38, a weighting pin 69 is provided at the outlet of the hot jet 68, and the semiconductor chip IC1 is connected with the weighting pin 69. Hold down. A connection portion between the outlet of the hot jet 68 and the weighting pin 69 is heated by the heater 70, thereby preventing the temperature of the dry air from being lowered by the weighting pin 69. Note that the heater 70 may not be provided when there is no extreme dry air temperature drop. Since the steps after the solder connection are the same as those in the first embodiment, description thereof is omitted.

  As described above, according to the third embodiment, since the void generated between the semiconductor chip IC1 and the PCB 38 can be released by pressing the semiconductor chip IC1 with the weighting pin 69, the first embodiment described above. As a result, the adhesive strength between the semiconductor chip IC1 and the PCB 38 can be improved.

(Embodiment 4)
Another example of the mounting process in which the surface-mounted components according to the fourth embodiment are collectively solder-connected to the module substrate will be described. FIG. 22 is a fragmentary cross-sectional view of the semiconductor device for explaining the mounting method following FIG. 16 of the first embodiment.

  As in the second embodiment, the heat block 67 is not heated, all the surface mounting components mounted on the PCB 38 are covered with the cover 68a, and the semiconductor chip IC1 is heated to a temperature of 280 ° C. or higher using the hot jet 68. For example, local heating is performed at a temperature of 330 to 350 ° C., and the semiconductor chip IC1 and the substrate-side terminal 40a1 are connected with a high melting point solder. Also, the Pb-free solder is melted by the residual heat generated by the dry air blown from the nozzle of the hot jet 68 being diffused in the cover 68a, so that the single chip component 43 and the substrate side terminal 40b, the integrated chip component 44 and the substrate side terminal 40b. The semiconductor chip IC2 and the substrate side terminal 40a2 are connected.

  Further, in the fourth embodiment, in order to release voids generated between the semiconductor chip IC1 and the PCB 38, a block 71 is provided at the outlet of the hot jet 68, and this block 71 is provided on the entire semiconductor chip IC1. Simultaneously with the heating by the hot jet 68, the hot jet 68 is pressurized. The block 71 contains a heater to prevent the temperature of the dry air from being lowered by bringing the block 71 into contact with the semiconductor chip IC1. Further, at least a portion of the block 71 that contacts the semiconductor chip IC1 is made of ceramic. Since the steps after the solder connection are the same as those in the first embodiment, description thereof is omitted.

  As described above, according to the fourth embodiment, the void generated between the semiconductor chip IC1 and the PCB 38 can be released by pressurizing the semiconductor chip IC1 with the block 71. Therefore, the first embodiment described above. As a result, the adhesive strength between the semiconductor chip IC1 and the PCB 38 can be improved.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  In the above description, the case where the invention mainly made by the present inventor is applied to the digital mobile phone which is the field of use behind the invention has been described. However, the present invention is not limited to this. For example, a PDA having a communication function (Personal The present invention can also be applied to an information processing apparatus such as a mobile information processing apparatus such as Digital Assistants) or a personal computer having a communication function.

  The present invention can be widely used in the manufacturing industry for manufacturing semiconductor devices.

DESCRIPTION OF SYMBOLS 1 Front end apparatus 2 Baseband circuit 3 Modulation / demodulation circuit 4a, 4b Switch circuit 5 Demultiplexer 6 Peripheral circuit 6A Control circuit 6B Bias circuit 6A1 Power supply control circuit 6A2 Bias voltage generation circuit 7a, 7b Input terminal 8a, 8b Output terminal 9a1 9a5, 9b1 to 9b5, 9c Transmission line 10a, 10b Input terminal 11a1 to 11a3, 11b1 to 11b3 Power supply terminal 12a, 12b Output terminal 13 Control terminal 14 Insulating film 15b Lower layer electrode 15t Upper layer electrode 16a Silicon oxide film 16b Silicon nitride film 16c Silicon oxide film 16d Polyimide resin film 17 Insulating films 18a to 18c Connection hole 20 Polyimide resin film 21 Bump electrode 22 Plating layer 23 Gate insulating film 24 Gate electrode 25 n ⁺ type semiconductor region 26a n ⁻ type semiconductor region 26b n ⁺ type semiconductor region Region 27a-27d p ⁺⁺ type semiconductor region 28 subcollector layer 28a mesa isolation 29 collector electrode 30 collector mesa 31 base mesa 32 base electrode 33 emitter layer 34 emitter electrodes 35a, 35b connection holes 36a, 36b, 36c connection holes 37b base bump electrode 37c Collector bump electrode 37e Emitter bump electrode 38 PCB
40a1, 40a2, 40b, 40c Substrate side terminals 42G, 42S Electrode 43 Single chip component 44 Integrated chip component 45 Resin 46 Solder 47 Radiation vias 48, 48a, 48b, 48c Solder 50 Motherboard 51 Single chip component 53 Solder 56 Core material 57 Inner layer Copper film 58 Prepreg 59 Copper film 60 for outer layer Solder resist 61 Via 63 Printing mask 65 Squeegee 66 Potting nozzle 67 Heat block 67a Recess 68 Hot jet 68a Cover 69 Weighting pin 70 Heater 71 Block A Power amplification circuit A1 to A3 Amplification stage AM1-AM3 Matching circuit ANT Antenna B Power amplification circuit B1-B3 Amplification stage BL Back surface electrode BM1-BM3 Matching circuit BW Bonding wire C, C1, C2, Cp1-Cp3, Cm1-Cm12 Capacitor Ca Upper part Pole Cb Lower electrode CNT1, CNT2 Switching signal CSL Capacitance insulating film EP Epitaxial layer GND Ground potential FLT1, FLT2 Filter HBT1-HBT3 Heterojunction type double transistor IC1, IC2 Semiconductor chip ID Integrated chip component L, Lp1-Lp3 Inductor LPF1, LPF2 Low pass filter M1 First layer wiring M2 Second layer wiring M1b First base wiring M1c First collector wiring M2b Second base wiring M2c Second collector wiring M2e Emitter wiring MA Modules MN1, MN2 Impedance matching circuits PL1-PL6 Plug PM, PM1, PM2 Power amplifier PWL Well Qn, Qn1, Qn2 nMOS
S1-S3 Semiconductor substrate

Claims (11)

A method for manufacturing an electronic device, comprising:
(A) preparing a wiring board;
(B) mounting a semiconductor chip via a first solder on a first terminal formed on the surface of the wiring board;
(C) mounting a chip component on a second terminal formed on the surface of the wiring board via a second solder;
(D) melting the first solder and the second solder and electrically connecting the semiconductor chip and the chip component to the wiring board;
(E) sealing the semiconductor chip and the chip component with a resin to form a sealing body,
The melting point of the second solder in the step (c) is lower than the temperature when the electronic device is soldered to the mounting wiring board,
The method (e) is performed in a state where the gap between the wiring board and the chip component is reduced in pressure so that the resin fills. A method of manufacturing an electronic device according to claim 1,
The step (e)
(E1) preparing an upper mold including a space for forming the sealing body and an air vent connected to the space, and a lower mold corresponding to the upper mold;
(E2) placing the wiring board on the lower mold;
(E3) fixing the wiring board with the upper mold and the lower mold so that the semiconductor chip and the chip component are disposed in the space of the upper mold;
(E4) discharging the air and resin in the space from the air vent to the outside, and depressurizing the space;
(E5) a step of pumping the liquefied resin into the space;
(E6) opening the upper mold and the lower mold after the resin is cured, and taking out the wiring board on which the sealing body is formed. Production method. A method of manufacturing an electronic device according to claim 2,
In the step (e1), the pressure is reduced to 1 Torr or less. A method of manufacturing an electronic device according to claim 1,
Connection terminals are formed at both ends of the chip component,
In the step (d), the connection terminal of the chip and the second terminal of the wiring substrate are electrically connected. A method of manufacturing an electronic device according to claim 1,
The method of manufacturing an electronic device, wherein the chip component includes one or more of a capacitor, an inductor, a resistor, and a ferrite bead. A method of manufacturing an electronic device according to claim 1,
The method of manufacturing an electronic device, wherein the second solder is Pb-free solder. A method of manufacturing an electronic device according to claim 6,
The method of manufacturing an electronic device, wherein the Pb-free solder is Sn-3Ag-0.5Cu solder. A method of manufacturing an electronic device according to claim 1,
The method of manufacturing an electronic device according to claim 1, wherein the gap is formed between a back surface of the chip component and a component mounting surface of the wiring board. A method of manufacturing an electronic device according to claim 8,
The distance between the gaps is about 10 μm. A method of manufacturing an electronic device according to claim 1,
A method for manufacturing an electronic device, comprising: a step of electrically connecting the semiconductor chip and the wiring board with a bonding wire between the step (d) and the step (e). A method of manufacturing an electronic device according to claim 1,
A method of manufacturing an electronic device, wherein a temperature of reflow processing when the electronic device is soldered to the mounting wiring board is about 250 ° C.

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