JP2010109386A - Method of manufacturing semiconductor device, and inspection socket - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve yield of a semiconductor device. <P>SOLUTION: A tray 7 is provided with a plurality of pockets 7a in each of which a wafer level CSP5 is stored, each pocket 7a is provided with a seating part 7b which supports a plurality of solder bumps 3 at the wafer level CSP5 and a side wall 7c formed around the seating part 7b, when the wafer level CSP5 is stored in the pocket 7a of the tray 7 in conveyance between steps in a poststep of manufacture of the wafer level CSP5, etc., an organic film on a principal plane of a semiconductor chip is not supported but the plurality of solder bumps 3 are supported by the seating part 7b to prevent a scratch being formed on the organic film, the organic film being peeled to become a foreign matter and adhere to a product, and as a result, the yield and quality of the wafer level CSP5 (semiconductor device) being the product are improved. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a tray, an inspection socket, and a method for manufacturing a semiconductor device, and more particularly to a technique that is effective when applied to the prevention of foreign matter adhesion.

  A conventional tray for housing a semiconductor integrated circuit device includes a surface that supports a BGA (ball grid array type semiconductor integrated circuit device) in a housing portion provided on the surface of the tray and a wall that restricts horizontal movement of the BGA. And a BGA fixing portion that is provided on the back surface of the tray and includes a wall that supports the BGA and a wall that restricts the horizontal movement of the BGA when the tray is turned upside down. It is a structure that fits or meshes (see, for example, Patent Document 1).

Japanese Patent Laid-Open No. 11-11572 (FIG. 9)

  Among small semiconductor devices such as CSP (Chip Scale Package), a CSP type semiconductor device (such a semiconductor device) assembled by a manufacturing technology that integrates a wafer process (pre-process) and a package process (post-process). Called wafer level CSP or wafer process package).

  In the production of the wafer level CSP, in the subsequent process, dicing is performed to separate the wafer state, and the wafer level CSP is once packed in a dedicated jig, and then taken out from the dedicated jig and accommodated in a tray. In addition to performing conveyance between the processes, each inspection process is performed by taking it out of the tray and mounting it on a socket for inspection.

  In the wafer level CSP, an organic film is formed on the wiring layer formed on the main surface of the semiconductor chip for the purpose of protection, and the tray and the inspection socket support the organic film of the wafer level CSP. It becomes the shape to do.

  Therefore, by supporting the organic film, scratches may be formed on the organic film or the organic film may be peeled off. Since the organic film is thin, when the organic film is peeled off, the wiring is exposed, which causes a problem in that electrical characteristic defects such as a wiring short circuit occur.

  Furthermore, there is a problem that the yield is lowered due to electrical characteristic defects and appearance quality degradation.

  In the tray described in Patent Document 1 (Japanese Patent Laid-Open No. 11-11572), when the wafer level CSP is accommodated in the BGA support (also referred to as a pocket), the organic film on the surface of the wafer level CSP is removed. Since it will be supported, scratches may be formed on the organic film, foreign matter may be generated, or the organic film may be peeled off. The problem is that it causes electrical characteristic defects.

  Further, the BGA support portion that is a pocket has a wide range of holes penetrating to the back surface side, so that the front and back of the wafer level CSP cannot be reversed to support the ball electrode that is the external terminal. In addition, there is a concern that when a plurality of trays are stacked, the foreign matter generated from the organic film or the like falls onto the wafer level CSP on the lower tray and the foreign matter adheres to the wafer level CSP.

  An object of the present invention is to provide a tray, an inspection socket, and a semiconductor device manufacturing method capable of improving the yield of products.

  Another object of the present invention is to provide a tray, an inspection socket, and a method for manufacturing a semiconductor device that can improve the quality of a product.

  Furthermore, another object of the present invention is to provide a tray, an inspection socket, and a method for manufacturing a semiconductor device that can reduce costs.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

  That is, the present invention can accommodate a semiconductor device having a semiconductor chip having an organic film covering the wiring layer formed on the main surface and a plurality of ball electrodes electrically connected to the wiring layer. A plurality of storage portions each of which is capable of storing the semiconductor device, and each of the storage portions includes a pedestal portion that supports the plurality of ball electrodes of the semiconductor device; and And a side wall formed in the periphery.

  According to another aspect of the present invention, there is provided a semiconductor device having a semiconductor chip having an organic film covering a wiring layer formed on a main surface and a plurality of ball electrodes which are external terminals. An inspection socket capable of performing an inspection, having an opening in which the ball electrode of the semiconductor device can be disposed, and an insulating sheet member that supports the organic film of the semiconductor device; Corresponding to each of the plurality of ball electrodes of the semiconductor device, disposed in the opening of the sheet member, a plurality of terminal portions that can contact the ball electrode, and in close contact with the sheet member, And a conductor portion provided with a wiring connected to the terminal portion, and a plurality of the terminal portions are arranged in one opening of the sheet member.

  The present invention also provides a plurality of semiconductors each having an organic film covering a wiring layer formed on each main surface and a plurality of ball electrodes which are external terminals disposed in a plurality of openings of the organic film, respectively. A step of preparing a semiconductor wafer provided with a device formation region; a step of dividing the semiconductor wafer by dicing according to the semiconductor device formation region to form a plurality of semiconductor devices; and a step of forming the semiconductor device. And inspecting the semiconductor device while supporting the plurality of ball electrodes.

  The present invention also provides a plurality of semiconductors each having an organic film covering a wiring layer formed on each main surface and a plurality of ball electrodes which are external terminals disposed in a plurality of openings of the organic film, respectively. A step of preparing a semiconductor wafer provided with a device formation region; a step of dividing the semiconductor wafer by dicing according to the semiconductor device formation region to form a plurality of semiconductor devices; and a step of forming the semiconductor device. Thereafter, the semiconductor device is transported in a state where the plurality of ball electrodes of the semiconductor device are supported, and then the semiconductor device is subjected to a burn-in test.

  Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  In a tray capable of accommodating a semiconductor device having a semiconductor chip having an organic film covering a wiring layer on the main surface and a plurality of ball electrodes, each of the plurality of accommodating portions for accommodating the semiconductor devices includes a plurality of ball electrodes. The pedestal that supports the organic film when the semiconductor device is accommodated in the accommodating portion of the tray by inter-process conveyance in the subsequent process of manufacturing the semiconductor device. Since the plurality of ball electrodes are supported by the part, it is possible to prevent the organic film from being scratched, or the organic film from being peeled off and becoming a foreign substance and adhering to the product. As a result, the quality and yield of the semiconductor device Can be improved.

It is a top view which shows an example of the structure of the semiconductor device manufactured by the manufacturing method of the semiconductor device of embodiment of this invention. FIG. 2 is a side view showing the structure of the semiconductor device shown in FIG. 1. It is an enlarged partial top view which shows the structure of the A section shown in FIG. It is a fragmentary sectional view which shows the structure cut | disconnected along the AA line shown in FIG. FIG. 2 is a process flow diagram and a cross-sectional view illustrating an example of a procedure of a previous process in the assembly of the semiconductor device illustrated in FIG. FIG. 7 is a process flow diagram, a perspective view, and a cross-sectional view showing a part of an example of a post-process procedure in the assembly of the semiconductor device shown in FIG. 1. FIG. 7 is a process flow diagram and a perspective view showing a part of an example of a post-process procedure in the assembly of the semiconductor device shown in FIG. 1. It is a top view which shows an example of the structure of the tray of embodiment of this invention. It is sectional drawing which shows an example of the structure of the accommodating part of the tray shown in FIG. It is a fragmentary perspective view which shows an example of the structure of the base part in the accommodating part of the tray shown in FIG. It is sectional drawing which shows an example of the accommodation method of the semiconductor device in the tray shown in FIG. It is a fragmentary sectional view which shows an example of the structure of the tray lamination | stacking state cut | disconnected along the DD line shown in FIG. It is a fragmentary sectional view which shows an example of the structure of the tray lamination | stacking state cut | disconnected along the EE line shown in FIG. It is a fragmentary sectional view which shows an example of the structure of the mounting state of the semiconductor device to the test socket of embodiment of this invention. FIG. 15 is an enlarged partial cross-sectional view illustrating a structure of an F portion illustrated in FIG. 14. It is a top view which shows an example of the structure of the contact sheet in the socket for an inspection shown in FIG. It is a top view which shows an example of the structure of the intermediate | middle pocket part (relay jig | tool) of the automatic attachment / detachment machine used in the post process of the assembly of the semiconductor device shown in FIG. It is sectional drawing which shows the structure of the accommodating part of the intermediate | middle pocket part shown in FIG. FIG. 2 is an enlarged partial sectional view showing an example of a structure of a test socket used in a subsequent process of assembling the semiconductor device shown in FIG. 1.

  In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  Further, in the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments, but they are not irrelevant to each other unless otherwise specified. The other part or all of the modifications, details, supplementary explanations, and the like are related.

  Also, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), particularly when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and it may be more or less than the specific number.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

(Embodiment)
1 is a plan view showing an example of the structure of a semiconductor device manufactured by the method of manufacturing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a side view showing the structure of the semiconductor device shown in FIG. 1, and FIG. 4 is an enlarged partial plan view showing the structure of the A portion shown in FIG. 1, FIG. 4 is a partial cross-sectional view showing the structure cut along the line AA shown in FIG. 3, and FIG. 5 is a view before assembly of the semiconductor device shown in FIG. FIG. 6 and FIG. 7 are each a process flow diagram, a perspective view, and a sectional view showing a part of an example of a post-process procedure in the assembly of the semiconductor device shown in FIG. 8 is a plan view showing an example of the structure of the tray according to the embodiment of the present invention, FIG. 9 is a sectional view showing an example of the structure of the tray accommodating portion shown in FIG. 8, and FIG. 10 is a view of the tray shown in FIG. The partial perspective view which shows an example of the structure of the base part in a accommodating part, 11 is a cross-sectional view showing an example of a method of housing a semiconductor device in the tray shown in FIG. 9, and FIG. 12 is a partial cross-sectional view showing an example of a structure in a tray stacked state cut along the line DD shown in FIG. 13 is a partial cross-sectional view showing an example of a stacked structure of the tray cut along the line EE shown in FIG. 8, and FIG. 14 shows a structure of the semiconductor device mounted on the inspection socket according to the embodiment of the present invention. FIG. 15 is an enlarged partial cross-sectional view showing the structure of part F in FIG. 14, FIG. 16 is a plan view showing an example of the structure of the contact sheet in the inspection socket shown in FIG. 14, and FIG. FIG. 18 is a plan view showing an example of the structure of an intermediate pocket portion (relay jig) of an automatic attachment / detachment machine used in a subsequent process of assembling the semiconductor device shown in FIG. 1, and FIG. 18 is a view of a storage portion of the intermediate pocket portion shown in FIG. A cross-sectional view showing the structure, FIG. Is an enlarged partial sectional view showing an example of the structure of a test socket to be used in subsequent steps of the assembly of the semiconductor device shown in 1.

  The semiconductor device of the present embodiment is a wafer level CSP (also referred to as a wafer process package) 5 that is assembled by a manufacturing technique in which a wafer process (pre-process) and a package process (post-process) are integrated.

  The structure of the wafer level CSP 5 shown in FIGS. 1 to 4 will be described. The main surface 2b, the pads 2a that are a plurality of electrodes arranged on the main surface 2b, the main surface 2b, A semiconductor chip 2 having a rearrangement wiring 2e for changing the arrangement of each pad 2a, an insulating film formed on the main surface 2b, and an arrangement of a plurality of pads 2a connected to the rearrangement wiring 2e. It consists of solder bumps (ball electrodes) 3 which are a plurality of external terminals provided in different arrangements. As shown in FIG. 4, an insulating polyimide or the like is formed on the rewiring layer on which the rearrangement wiring 2e is formed. An organic film 2i made of is formed.

  Further, the configuration of the wafer level CSP 5 will be described. Main surface 2b, back surface 2c facing the main surface, side surface 2d, integrated circuit formed on main surface 2b, organic film 2i covering main surface 2b, Pads 2a that are a plurality of electrodes that are exposed from the organic film 2i and arranged on the main surface 2b at a first interval, and a plurality of rearrangement wirings 2e (wirings) formed on the organic film 2i, Each one end portion is electrically connected to the pad 2a which is the plurality of electrodes, and each other end portion has a plurality of rearrangement wirings 2e arranged at a second interval larger than the first interval. The semiconductor chip 2 includes a plurality of solder bumps 3 disposed on the other end portions of the plurality of rearrangement wirings 2e and electrically connected to the other end portions of the plurality of rearrangement wirings 2e.

  Note that the side surface 2d is a cut surface formed by cutting the wafer into individual packages by dicing from the wafer state.

  The wafer level CSP 5 has a structure in which the side surface 2d and the back surface 2c of the semiconductor chip 2 are exposed, unlike a semiconductor device in which the chip is packaged using a sealing resin or the like.

  Further, in the wafer level CSP 5, as shown in FIGS. 1 and 2, solder bumps (projection electrodes) 3 that are a plurality of external terminals are arranged in an array on the main surface 2 b of the semiconductor chip 2. The above is the same as BGA (Ball Grid Array).

  Further, as shown in FIGS. 3 and 4, in the wafer level CSP 5, the rearrangement wiring 2 e is further connected to the pad 2 a which is an electrode formed on the main surface 2 b of the semiconductor chip 2. A solder bump 3 is connected to 2e via an Au layer 2p. The rearrangement wiring 2e is a relay wiring for replacing the arrangement of the pads 2a made of aluminum or the like with an arrangement on which the solder bumps 3 can be mounted. That is, in the wafer level CSP5, the arrangement pitch of the pads 2a is narrowed, and the solder bumps 3 as external terminals cannot be directly mounted on the pads 2a. Therefore, the rearrangement wiring is performed so that the solder bumps 3 can be mounted. The pitch is increased by 2e, and the solder bump 3 is connected to the rearrangement wiring 2e.

  Thereby, a plurality of solder bumps 3 can be arranged in an array.

  The rearrangement wiring 2e has, for example, a three-layer structure of a Ni layer 2j, a Cu layer 2m, and a Cr layer 2n. The Ni layer 2j, the Cu layer 2m, and the Cr layer 2n are arranged in order from the surface side to the inside. The Cr layer 2n and the pad 2a are connected. The Ni layer 2j is connected to the solder bump 3 through the Au layer 2p so that the connection to the solder bump 3 is good.

  Further, a metal wiring layer is formed on the silicon substrate 2k via an insulating layer 2f which is an interlayer insulating film.

  Further, the pad 2a formed on the main surface 2b is covered with a protective film 2g which is a passivation film except for a connection portion with the rearrangement wiring 2e. Further, a first insulating film 2h is formed on the protective film 2g, and the rearrangement wiring 2e is stacked on the first insulating film 2h. Further, an organic film 2i, which is a second insulating film, is laminated on the rearrangement wiring 2e, excluding the connection portion with the solder bump 3.

  The protective film 2g is made of, for example, SiN, and the first insulating film 2h and the organic film 2i that is the second insulating film are soft films made of, for example, polyimide.

  Next, a method for manufacturing wafer level CSP 5 (semiconductor device) according to the present embodiment will be described by dividing it into a pre-process shown in FIG. 5 and a post-process shown in FIGS.

  First, in the pre-process shown in FIG. 5, after the wafer preparation in step S1, the first insulating film, which is a polyimide film, is formed in step S2. Here, the main surface 1a of the semiconductor wafer 1 is covered with the first insulating film 2h, and then exposure and etching are performed to remove the first insulating film 2h on the pad 2a. The insulating film 2h is baked.

  Thereafter, the formation of the Cr—Cu layer shown in step S3 is performed by sputtering or the like to form the base layer of the rearrangement wiring 2e. Thereafter, a Cr—Ni layer shown in step S4 is formed. Here, a Cr—Ni layer is formed on the Cr—Cu layer by plating, followed by patterning by etching to form the rearrangement wiring 2e made of each layer of Cr—Cu—Ni.

  Thereafter, the organic film 2i which is the second insulating film shown in step S5 is formed. The organic film 2i is, for example, a polyimide film, like the first insulating film 2h. First, the organic film 2i is coated on the rearrangement wiring 2e, and then exposure and etching are performed to remove the organic film 2i on the solder bump connection portion, and further, the organic film 2i is baked.

  Thereafter, an electroless plating process shown in step S6 is performed. That is, the Au layer 2p is formed by plating on the solder bump connection portion of the rearrangement wiring 2e.

  Thereafter, a probe test shown in step S7 is performed, and solder bump formation shown in step S8 is further performed. That is, reflow etc. are performed on the Au layer 2p to connect the solder bumps 3 which are external terminals.

  Thereby, the pre-process in the production of the wafer level CSP 5 is completed.

  Thereafter, the post-process shown in FIGS. 6 and 7 is performed.

  First, wafer preparation in step S11 shown in FIG. 6 is performed. The semiconductor wafer 1 includes an organic film 2i that covers the rearrangement wiring 2e formed on each main surface 2b, and a plurality of solder bumps that are external terminals disposed in a plurality of openings of the organic film 2i. A plurality of device regions (semiconductor device formation regions) 1c provided with (ball electrodes) 3 are provided.

  Thereafter, dicing and jig packing in step S12 shown in FIG. 6 are performed. First, in dicing, the semiconductor wafer 1 is divided along dicing lines 1b according to the device region 1c. That is, the blade 9 is caused to travel along the dicing line 1b to separate the semiconductor wafer 1 into a plurality of wafer levels CSP5.

  Thereafter, the individual wafer level CSP 5 is pushed up by the pickup unit 8, picked up, and then accommodated in the dedicated case jig 10. At that time, the jig is housed in the dedicated case jig 10 with the back surface 2c of the semiconductor chip 2 facing downward so that the plurality of solder bumps 3 which are external terminals of the wafer level CSP 5 face upward.

  Thereafter, the laser mark shown in step S13 is performed. At this time, in the present embodiment, a ball receiving tray 7 is prepared in advance, and each wafer level CSP 5 is accommodated in the tray 7 to perform laser marking.

  The ball receiving tray 7 accommodates a chip size package such as a wafer level CSP 5 while supporting a plurality of solder bumps (ball electrodes) 3 provided as external terminals.

  FIG. 8 is a view showing an example of the structure of the ball receiving tray 7, and on the surface 7 f (see FIG. 12) side of the tray 7, a plurality of pockets (accommodating portions) each capable of accommodating the wafer level CSP 5. 7a are provided in a matrix arrangement, and in each pocket 7a, as shown in FIG. 9, a pedestal portion 7b for supporting a plurality of solder bumps (ball electrodes) 3 of the wafer level CSP 5, and a pedestal portion 7b A side wall 7c formed in the periphery is provided.

  Here, the reason why the tray 7 of this embodiment can support the ball electrodes (solder bumps 3) which are external terminals of the semiconductor device will be described.

  In the semiconductor device that can accommodate the tray 7 of the present embodiment, the side surface 2d and the back surface 2c of the semiconductor chip 2 are exposed as in the wafer level CSP 5, for example, and the package size is substantially equal to the chip size. This is a small and lightweight package in which the weight of the chip 2 is directly used as the weight of the package.

  That is, the external appearance of the semiconductor device that can be accommodated in the tray 7 is a BGA type in which solder bumps 3 that are ball electrodes as external terminals are provided in a matrix arrangement, but a general BGA has a filler or the like. The wafer level CSP 5 has an epoxy resin for sealing, a BGA substrate, a gold wire, a paste material, etc., whereas the wafer level CSP 5 has an epoxy resin for sealing, a BGA substrate, a gold wire, a paste material, etc. Therefore, the weight is much lighter than that of a general BGA and is almost equal to the weight of a single semiconductor chip.

  Therefore, even if the solder bumps 3 are supported by the pedestal portions 7b in the pockets 7a of the tray 7, the solder bumps 3 are not crushed and the ball can be received.

  In the wafer level CSP 5, an organic film 2i such as a polyimide film is formed on the rearrangement wiring 2e on the main surface 2b of the semiconductor chip 2 for the purpose of protection and insulation. In the conventional tray, the organic film 2i on the main surface 2b of the semiconductor chip 2 is supported in the accommodating portion. In this case, since the organic film 2i is a thin film, the organic film 2i is peeled off by vibration during transportation. As a countermeasure, it may be possible to prevent the peeling or dropping of the organic film 2i by thickening it, but it is formed on the organic film 2i to connect the solder bumps 3. The opening to be formed is formed by a photolithography technique.

  At that time, if the organic film 2i is made thick, it becomes difficult to form an opening by photolithography, and if the depth of the opening is too deep, the solder bump 3 does not reach the Au layer 2p. Problems also occur. Further, when the area of the opening is increased, it becomes difficult to cope with the fine pitch of the pad 2a. Therefore, it is not preferable to make the organic film 2i thick. Since the organic film 2i is a soft film, the organic film 2i is easily damaged, and foreign matter may increase even if it is thickened. Furthermore, in order to securely protect the wiring, it is not preferable to increase the thickness of the organic film 2i because the effect cannot be obtained unless the organic film 2i is formed thicker than the height of the solder bump 3.

  Therefore, as in the present embodiment, not only the organic film 2 i is covered on the main surface 2 b of the semiconductor chip 2 but also a semiconductor device having a weight close to the weight of the semiconductor chip 2 in particular. Thus, the tray 7 that enables ball reception is very effective.

  In the wafer level CSP 5, the thickness of the organic film 2i and the first insulating film 2h is, for example, about 5 μm, and the pad pitch of the semiconductor chip 2 is, for example, about 80 μm. The pitch is, for example, about 0.4 to 0.5 mm, and the bump diameter is, for example, about 0.2 to 0.25 mm.

  The tray 7 is made of an insulating resin material mixed with conductive particles such as carbon.

  According to the tray 7 of the present embodiment, when the wafer level CSP5 is accommodated in the pocket 7a of the tray 7 by, for example, conveyance between processes in the subsequent processes of manufacturing the wafer level CSP5, the main surface 2b of the semiconductor chip 2 is stored. Since the plurality of solder bumps 3 are supported by the pedestal portion 7b instead of supporting the organic film 2i, scratches are formed on the organic film 2i, or the organic film 2i peels off and adheres to the product as foreign matter. Can be prevented.

  As a result, it is possible to prevent the wiring from being exposed due to the peeling of the organic film 2i and causing electrical characteristic defects such as a wiring short, and the quality of the wafer level CSP5 (product) can be improved.

  Furthermore, since scratches can be formed on the organic film 2i and peeling of the organic film 2i can be prevented, the appearance quality of the wafer level CSP 5 can be improved.

  As described above, since the quality of the wafer level CSP 5 can be improved, the yield of the wafer level CSP 5 (product) can be improved. By adopting the tray 7 of the present embodiment, for example, the rate of occurrence of peeling of the organic film 2i can be reduced from 50% to 1% or less.

  Further, as shown in FIG. 9, the tray 7 is formed with a first groove portion 7d around the pedestal portion 7b in each pocket 7a. That is, in each pocket 7a, the 1st groove part 7d which was adjacent to the outer peripheral part of the base part 7b and was depressed from the base part 7b is formed.

  Thereby, foreign matters such as silicon scraps generated in the pocket 7a can be dropped into the first groove portion 7d, and the foreign matter can be prevented from adhering to the wafer level CSP5.

  Since the tray 7 is a ball receiving system that supports the solder bumps 3 of the wafer level CSP 5, even if some foreign matter such as silicon dust is generated due to vibration during transportation or the like, Due to the bump height, foreign matter can be prevented from scratching the wafer level CSP body.

  Further, as shown in FIG. 10, the tray 7 of the present embodiment has a second groove portion 7e formed in the pedestal portion 7b. The second groove portion 7e is formed in a cross shape in the pedestal portion 7b, for example. However, the shape of the second groove portion 7e is not limited to a cross shape as long as it is formed in the pedestal portion 7b. However, the second groove portion 7e communicates from the pedestal portion 7b to the first groove portion 7d. Preferably it is formed.

  That is, since the second groove portion 7e is formed in the pedestal portion 7b of the pocket 7a in the tray 7, when the wafer level CSP 5 is not accommodated in the pocket 7a, the vacuum pad 20 is formed as shown in FIG. When the pocket 7a is sucked, the vacuum exhaust leaks from the second groove portion 7e of the pedestal portion 7b, so that the vacuum pad 20 can be prevented from adsorbing the tray 7.

  12 and 13, when the plurality of trays 7 are stacked, the tray 7 is a space surrounded by the back surface 7g of the upper tray 7 and the surface 7f of the lower tray 7. At least a part is shaped to communicate with the outside of the tray 7.

  That is, the tray 7 of the present embodiment has a structure in which no through hole is formed in the pedestal portion 7b and the side wall 7c in each pocket 7a. Therefore, when a plurality of trays 7 are stacked, the space surrounded by the upper tray 7 and the lower tray 7 is not sealed. When the trays 7 are stacked, as shown in FIG. 13, the inner wall portion 7 i provided on the back surface 7 g of the upper tray 7 is supported by the surface 7 f of the outer frame portion 7 j of the lower tray 7. In this case, a slight gap is formed between the outer wall portion 7 h provided on the outer peripheral portion of the upper tray 7 and the outer peripheral portion on the surface 7 f side of the outer frame portion 7 j of the lower tray 7. Therefore, a part of the space surrounded by the upper tray 7 and the lower tray 7 is in communication with the outside of the tray 7 through the gap. Therefore, air can be removed through the gap as shown in FIGS.

  Accordingly, when the upper tray 7 is separated from the lower tray 7 by vacuum suction or manually with the plurality of trays 7 being stacked, the lower tray 7 is brought into close contact with the upper tray 7 so that the upper tray 7 is in contact with the upper tray 7. Ascending with the tray 7 can be prevented.

  As a result, the usability of the tray 7 can be improved and workability can be improved.

  Further, in each pocket 7a of the tray 7, through holes are not formed in the pedestal portion 7b or the side wall 7c, when the plurality of trays 7 are stacked, the tray 7 on the lower stage side from the pocket 7a on the upper side tray 7 is stacked. 7 can prevent foreign matters such as silicon scraps from falling, and foreign matter adhering to the tray 7 during transportation can be reduced.

  As described above, in the method of manufacturing the semiconductor device according to the present embodiment, the tray 7 capable of receiving the wafer level CSP 5 is adopted and assembled.

  In the laser marking step shown in step S13 of FIG. 6, the wafer level CSP5 is marked in a state where the ball level CSP5 is received on the tray 7. That is, after dicing into pieces shown in step S12, the wafer level CSP5 is placed in the pocket 7a of the tray 7 and the solder bumps 3 as a plurality of ball electrodes are supported by the pedestal portion 7b with respect to the wafer level CSP5. Marking is performed using the laser 11.

  In the ball receiver using the tray 7, when the wafer level CSP 5 is accommodated in the pocket 7 a, the back surface 2 c side of the semiconductor chip 2 of the wafer level CSP 5 faces upward, so that the laser 11 is accommodated in the state where the wafer level CSP 5 is accommodated in the tray 7. Marking can be performed.

  Thereafter, the wafer level CSP 5 is accommodated in the tray 7 and conveyed to the next process, and a burn-in (B / I) test and a reliability test such as BIST shown in step S14 are performed. The burn-in test is performed, for example, by attaching a wafer level CSP 5 to a burn-in socket (inspection socket) 4 attached to a burn-in board 12 as shown in FIG.

  When performing the burn-in test, the tray 7 containing the wafer level CSP 5 is set in the automatic attachment / detachment machine 19 as shown in FIG. The wafer level CSP 5 is once transferred and aligned in the pocket (second accommodating portion) 13 a of the intermediate pocket portion 13, and after positioning with the intermediate pocket portion 13, the burn-in socket on the burn-in board 12 from the intermediate pocket portion 13. 4. Move each wafer level CSP5 to 4.

  At that time, each pocket 13a of the intermediate pocket portion 13 is provided with a second pedestal portion 13b capable of supporting the plurality of solder bumps 3 of the wafer level CSP 5, and the intermediate pocket portion 13 has a wafer in the pocket 13a. When the level CSP 5 is accommodated, as shown in FIG. 18, the plurality of solder bumps 3 of the wafer level CSP 5 are supported by the second pedestal portion 13b. In other words, the wafer level CSP 5 is also received by the intermediate pocket portion 13 of the automatic detacher 19.

  As a result, the intermediate pocket portion 13 of the automatic attachment / detachment machine 19 also supports the solder bump 3 by the second pedestal portion 13b instead of supporting the organic film 2i on the main surface 2b of the semiconductor chip 2 of the wafer level CSP5. It is possible to prevent the organic film 2i from being scratched or the organic film 2i from peeling off and becoming a foreign substance and adhering to the product.

  As a result, it is possible to prevent the wiring from being exposed due to the peeling of the organic film 2i and causing electrical characteristic defects such as a wiring short, and the quality of the wafer level CSP 5 can be improved. Furthermore, since scratches can be formed on the organic film 2i and peeling of the organic film 2i can be prevented, the appearance quality of the wafer level CSP 5 can be improved. Further, since the quality of the wafer level CSP 5 can be improved, the yield of the wafer level CSP 5 can be improved.

  Further, as shown in FIG. 18, each pocket 13a is formed with a third groove 13c around the second pedestal 13b, so that foreign matters such as silicon dust generated in the pocket 13a can be removed. It can be dropped into the three grooves 13c, and the foreign matter can be prevented from adhering to the wafer level CSP5. As a result, occurrence of chipping in the semiconductor chip 2 can be prevented. In addition, the second pedestal portion 13b in the intermediate pocket portion 13 is not formed with a vacuum exhaust groove like the second groove portion 7e in the tray 7 because it is aligned once before being transferred from the tray 7 to the burn-in socket 4. Since the semiconductor chips 2 are accommodated in all the pockets 13a because they are arranged, there is no problem that the vacuum pad 20 is attracted to the second pedestal portion 13b. Furthermore, even if there is a pocket 13 a in which no chip is accommodated, the intermediate pocket portion 13 is a fixing jig, so that the problem of sucking up by the vacuum pad 20 as in the tray 7 does not occur. For this reason, the intermediate pocket portion 13 is not provided with a vacuum exhaust groove, so that the manufacturing cost can be reduced.

  The intermediate pocket portion 13 is formed of, for example, an insulating resin material mixed with conductive particles such as carbon, like the tray 7.

  After positioning by the intermediate pocket portion 13, each wafer level CSP 5 is transferred from the intermediate pocket portion 13 to the burn-in socket 4 that is an inspection socket, and a burn-in test is performed.

  The configuration of the burn-in socket 4 shown in FIG. 14 is formed so that the wafer level CSP 5 can be disposed, and a recess 4a formed by the bottom 4b and the inner wall 4d, and a pressing portion that presses the wafer level CSP 5 disposed in the recess 4a. An upper cover 4e provided with 4f, an opening 4i in which the solder bump 3 of the wafer level CSP5 can be disposed, and an insulating sheet member 4j that supports the organic film 2i of the wafer level CSP5; A plurality of terminal portions 4g that are disposed in the openings 4i of the sheet member 4j corresponding to the plurality of solder bumps 3 of the CSP 5 and that can contact the solder bumps 3 as shown in FIG. 15, and a sheet member 4j The sheet portion of the contact sheet 4c shown in FIG. 16 is composed of a conductor portion 4h that is in close contact and provided with wiring that connects to the terminal portion 4g. The one opening 4i of 4j, in which a plurality of terminal portions 4g are arranged.

  The contact sheet 4c of the present embodiment is composed of, for example, a sheet member 4j made of polyimide or the like, a terminal portion 4g with conductive plating, and a conductor portion 4h made of copper foil or the like. Since the burn-in test is performed in a state where the wafer level CSP 5 is pressed by the pressing portion 4f, there is a possibility that a load is applied to the solder bump 3 and the shape of the solder bump 3 is deformed. For this reason, the sheet member 4j is provided as a cushion against pressing, but there is a problem of scratches due to contact with the organic film 2i of the wafer level CSP5 and foreign matters due to peeling. Therefore, in the present embodiment, for example, as shown in FIG. 16, four terminal portions 4g are provided in one opening 4i of the sheet member 4j, and accordingly, each one opening 4i of the sheet member 4j is provided in each opening 4i. Four solder bumps 3 are arranged.

  As a result, the size of one opening 4i of the sheet member 4j is larger than that of the conventional member in which the opening 4i is provided corresponding to each solder bump 3, and as a result, the wafer The contact area between the organic film 2i of the level CSP5 and the sheet member 4j of the contact sheet 4c is reduced, and the generation of foreign matters due to the organic film 2i can be reduced.

  In the burn-in test, as shown in FIG. 15, the solder bumps 3 of the wafer level CSP 5 are brought into contact with the terminal portions 4g, and the burn-in socket 4 so that the organic film 2i of the wafer level CSP 5 is supported by the sheet member 4j. A wafer level CSP5 is mounted on and a burn-in test is performed.

  At that time, since the area of the portion of the sheet member 4j that supports the organic film 2i is reduced, it is possible to reduce the cause of the foreign matter and silicon dust between the sheet member 4j and the wafer level CSP 5 during the test. The occurrence of defects can be reduced.

  After completion of the burn-in test, the wafer level CSP 5 is refilled from the burn-in socket 4 to the tray 7, and retention baking, which is a baking process shown in step S15 of FIG. 6, is performed. The retention baking is performed in a state where the wafer level CSP 5 is accommodated in the tray 7.

  Thereafter, the wafer level CSP 5 is transferred to the next process while being accommodated in the tray 7, where the testing shown in step S 16 is performed. The testing in the testing process is, for example, a function test. The wafer level CSP 5 is transferred from the tray 7 to the test socket 6, and the function test is performed with the test socket 6. As shown in FIG. 19, the test socket 6 has a floating pedestal 6 a that can be moved up and down, contact pins 6 b that contact the solder bumps 3 of the wafer level CSP 5, and the solder bumps 3 contact the contact pins 6. And a support portion 6c for supporting the wafer level CSP5. During testing, the solder bump 3 of the wafer level CSP5 is brought into contact with the contact pin 6b and the test (inspection) is performed with the solder bump 3 supported by the contact pin 6b. Do. The test socket 6 is formed with a fourth groove 6d that drops foreign matter around the support portion 6c and prevents foreign matter from adhering to the wafer level CSP5. In the floating base 6, since the organic film 2i is in contact with the support portion 6c until the solder bump 3 comes into contact with the contact pin 6b, there is a possibility that a problem of foreign matters due to scratches or peeling of the organic film 2i may occur. Therefore, in order to reduce the contact area between the organic film 2i and the support portion 6c as much as possible, the contact surface of the support portion 6c is L-shaped so as to support only the corner portion of the wafer level CSP5.

  After the testing is completed, the wafer level CSP 5 is transferred from the test socket 6 to the tray 7 again, and the wafer level CSP 5 is transferred to the next process while being accommodated in the tray 7, where automatic visual inspection shown in step S17 of FIG. 7 is performed. Do. Here, the wafer level CSP 5 is transferred from the tray 7 to the inspection jig 14 and the appearance inspection of the wafer level CSP 5 is performed on the inspection jig 14.

  Thereafter, the shipping tray is refilled as shown in step S18. That is, as the tray 7, a tray 7 formed of a heat resistant material and a shipping tray 15 formed of a non-heat resistant material are prepared in advance, and dicing (step S12) to automatic appearance inspection ( In the processes up to step S17), the processes in each process excluding the burn-in test and the testing and the inter-process transport include a high-temperature process such as a baking process, and therefore the tray 7 formed of a heat-resistant material is used. Subsequent processes and shipping do not include high-temperature processing such as baking, and therefore a shipping tray 15 formed of a non-heat resistant material is used.

  Therefore, after the completion of the automatic appearance inspection shown in step S17, the wafer level CSP5 is transferred from the tray 7 formed of the heat resistant material to the shipping tray 15 formed of the non heat resistant material. Note that the structure of the shipping tray 15 is exactly the same as the structure of the tray 7, and therefore, also in the shipping tray 15, a ball receiver that supports the plurality of solder bumps 3 of the wafer level CSP 5 by the pedestal portion is performed.

  After the transfer to the shipping tray 15, the final appearance shown in step S19 is performed. Here, the final appearance inspection is performed using a stereoscopic microscope, a metal microscope, or the like in a state where the wafer level CSP 5 is accommodated in the shipping tray 15.

  Then, the foreign material removal shown in step S20 is performed. Here, foreign matter on the shipping tray 15 is removed by blowing air to the shipping tray 15 containing the wafer level CSP 5 by the air blowing device 16 or the like or sucking foreign matter.

  Then, the packing shown in step S21 is performed. That is, a plurality of shipping trays 15 each containing a wafer level CSP 5 are stacked and enclosed in an aluminum moisture-proof bag 17 or the like. Further, after being bundled by the band 18, it is put in an interior box or an exterior box and shipped as shown in step S22. Since the shipping tray 15 has the same structure as that of the tray 7, at the time of shipment, the shipment is performed in a state where the plurality of solder bumps 3 of the wafer level CSP 5 are supported.

  As described above, by preparing the tray 7 formed of the heat resistant material and the shipping tray 15 formed of the non heat resistant material, the wafer level CSP 5 is made of the heat resistant material for inter-process conveyance in the manufacture of the wafer level CSP 5. When the tray 7 is used and the wafer level CSP 5 is shipped, a shipping tray 15 made of a non-heat resistant material can be used. That is, it becomes possible to use the non-heat-resistant material shipping tray 15 and the heat-resistant material tray 7 separately in the inter-process conveyance and at the time of shipment. At that time, the non-heat-resistant material is less expensive than the heat-resistant material. Therefore, the cost of the tray main body can be reduced as compared with the conventional case where only the expensive heat-resistant material tray 7 is used.

  Further, since the shipping tray 15 also has a structure for receiving balls, the organic film 2i caused by vibration is caused in the transportation after shipping by shipping with the shipping tray 15 supporting the solder bumps 3 of the wafer level CSP5. It is possible to suppress the generation of foreign matter due to dropping off.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the embodiments of the invention, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

  For example, in the above-described embodiment, the tray 7 formed of a heat resistant material and the shipping tray 15 formed of a non-heat resistant material are prepared, transported between processes, and predetermined processing (for example, high temperature processing). Although the case where the tray 7 is sometimes used and the shipping tray 15 is used at the time of shipment has been described, the shipping tray 15 made of a non-heat resistant material is not necessarily prepared, and is a tray formed of a heat resistant material. Only 7 may be prepared and used during inter-process transport or the predetermined processing, and further used for shipping.

  The present invention is suitable for trays and sockets and semiconductor manufacturing technology.

DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 1a Main surface 1b Dicing line 1c Device area | region (semiconductor device formation area)
2 semiconductor chip 2a pad 2b main surface 2c back surface 2d side surface 2e rearrangement wiring 2f insulating layer 2g protective film 2h first insulating film 2i organic film 2j Ni layer 2k silicon substrate 2m Cu layer 2n Cr layer 2p Au layer 3 solder bump ( Ball electrode)
4 Burn-in socket (inspection socket)
4a Concave part 4b Bottom part 4c Contact sheet 4d Inner wall 4e Top cover 4f Press part 4g Terminal part 4h Conductor part 4i Open part 4j Sheet member 5 Wafer level CSP (semiconductor device)
6 Test socket 6a Floating base 6b Contact pin 6c Support part 6d 4th groove part 7 Tray 7a Pocket (accommodating part)
7b Base part 7c Side wall 7d First groove part 7e Second groove part 7f Front surface 7g Rear surface 7h Outer wall part 7i Inner wall part 7j Outer frame part 8 Pickup part 9 Blade 10 Dedicated case jig 11 Laser 12 Burn-in board 13 Intermediate pocket part (relay jig Ingredients)
13a pocket (second housing part)
13b Second pedestal portion 13c Third groove portion 14 Inspection jig 15 Shipping tray 16 Air blow device 17 Aluminum moisture-proof bag 18 Band 19 Automatic attachment / detachment machine 20 Vacuum pad

Claims (8)

(A) A plurality of semiconductor device formation regions each having an organic film covering a wiring layer formed on each main surface, and a plurality of ball electrodes which are external terminals disposed in a plurality of openings of the organic film, respectively. Preparing a semiconductor wafer provided with:
(B) dividing the semiconductor wafer by dicing according to the semiconductor device formation region to form a plurality of semiconductor devices;
(C) After the step (b), a step of inspecting the semiconductor device while supporting the plurality of ball electrodes is provided.   2. The method of manufacturing a semiconductor device according to claim 1, wherein an insulating sheet member that can support the organic film of the semiconductor device, a plurality of terminal portions that can contact each of the ball electrodes of the semiconductor device, and the terminal A test socket in which a plurality of terminal portions are arranged in each of a plurality of openings of the sheet member, and the step (c). Then, the ball electrode of the semiconductor device is brought into contact with the terminal portion, and the semiconductor device is mounted on the inspection socket so that the sheet member supports the organic film of the semiconductor device, and a burn-in test is performed. A method for manufacturing a semiconductor device.   3. The method of manufacturing a semiconductor device according to claim 2, wherein a relay jig having a plurality of second accommodating portions each having a second pedestal portion capable of supporting the plurality of ball electrodes of the semiconductor device is prepared. When the burn-in test of the semiconductor device is performed in the step (c), the semiconductor device is once arranged in the second housing portion of the relay jig and the plurality of the plurality of the plurality of the semiconductor devices are disposed by the second pedestal portion. The ball electrode is supported, and then the semiconductor device is mounted on the inspection socket so that the ball electrode of the semiconductor device is brought into contact with the terminal portion and the organic film of the semiconductor device is supported by the sheet member And performing a burn-in test.   4. The method of manufacturing a semiconductor device according to claim 3, wherein a third groove is formed around the second pedestal portion in the second housing portion of the relay jig. Production method. (A) A plurality of semiconductor device formation regions each having an organic film covering a wiring layer formed on each main surface, and a plurality of ball electrodes which are external terminals disposed in a plurality of openings of the organic film, respectively. Preparing a semiconductor wafer provided with:
(B) dividing the semiconductor wafer by dicing according to the semiconductor device formation region to form a plurality of semiconductor devices;
(C) After the step (b), the semiconductor device is transported in a state where the plurality of ball electrodes of the semiconductor device are supported, and then the semiconductor device is subjected to a burn-in test. A method for manufacturing a semiconductor device.   6. The method of manufacturing a semiconductor device according to claim 5, further comprising: a plurality of accommodating portions each having a pedestal portion capable of supporting the plurality of ball electrodes of the semiconductor device and a side wall formed around the pedestal portion. A tray formed of a non-heat-resistant material is prepared, and after the step (c), the semiconductor device is disposed in the accommodating portion of the tray, and the plurality of ball electrodes are supported by the pedestal portion. A method of manufacturing a semiconductor device, wherein the semiconductor device is shipped in a state.   6. The method of manufacturing a semiconductor device according to claim 5, further comprising: a plurality of accommodating portions each having a pedestal portion capable of supporting the plurality of ball electrodes of the semiconductor device and a side wall formed around the pedestal portion. After the step (b), the semiconductor device is disposed in the accommodating portion of the tray, the plurality of ball electrodes are supported by the pedestal portion, and the semiconductor device is supported in the supported state. A manufacturing method of a semiconductor device, wherein marking is performed. A semiconductor device having an organic film covering the wiring layer formed on the main surface and having a plurality of ball electrodes as external terminals can be mounted to perform electrical inspection of the semiconductor device. An inspection socket,
An insulating sheet member having an opening in which the ball electrode of the semiconductor device can be disposed and supporting the organic film of the semiconductor device;
A plurality of terminal portions arranged in the opening of the sheet member corresponding to the plurality of ball electrodes of the semiconductor device, respectively, and capable of contacting the ball electrodes;
A conductor portion that is in close contact with the sheet member and provided with a wiring connected to the terminal portion;
The inspection socket, wherein a plurality of the terminal portions are arranged in one opening of the sheet member.

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