JP2010103671A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To furthermore reduce the power consumption of a semiconductor integrated circuit for a real-time clock and to make a generated clock signal available even in peripheral circuits. <P>SOLUTION: The semiconductor integrated circuit includes:a constant voltage circuit which generates a first power supply voltage and a second power supply voltage on the basis of a power supply voltage supplied from the outside; an oscillation circuit to which the second power supply voltage is supplied to generate an original oscillation clock signal by oscillating operation; a frequency division circuit to which the second power supply voltage is supplied to generate a plurality of kinds of frequency-divided clock signals by frequency division of the original oscillation clock signal; a logic circuit to which the first power supply voltage is supplied to manage time count information on the basis of at least one kind of frequency-divided clock signals generated by the frequency division circuit; a selector circuit which selects one of the original oscillation clock signal and the prescribed number of frequency divided clock signals; and an output circuit which supplies the selected clock signal to an output terminal. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit for a real-time clock that manages timekeeping information.

  In a semiconductor integrated circuit (IC) for a real time clock (RTC) that manages timekeeping information, an oscillation circuit generates an original clock signal and divides the original clock signal based on the divided clock signal. The logic circuit operates. Here, the oscillation circuit can operate by being supplied with a power supply voltage lower than the power supply voltage supplied to the logic circuit.

  Conventionally, a frequency dividing circuit that divides the original clock signal is provided in the logic circuit, so that noise of the logic circuit is likely to be mixed into the divided clock signal, and the power supply voltage for the logic circuit is divided. Since the frequency divider circuit operates after being supplied to the circuit, the power consumption is large. Further, since the original clock signal or the divided clock signal is used only within the semiconductor integrated circuit for the real time clock and is not supplied to the peripheral circuit, the original clock signal or the divided clock signal is not supplied to the peripheral circuit. When a clock signal having the same frequency as the peripheral clock signal is required, it is necessary to prepare a separate clock signal source for the peripheral circuit, resulting in an increase in circuit scale, power consumption and component cost. It was.

  As a related technique, Patent Document 1 discloses a real-time clock device capable of realizing low current consumption and stable operation, and a semiconductor device and an electronic apparatus using the real-time clock device. The real-time clock device includes a crystal oscillation circuit, a clock circuit that divides the output of the crystal oscillation circuit and outputs a real-time clock signal, and an interface circuit for exchanging signals with the outside. A real-time clock device, wherein the crystal oscillation circuit is driven by a first voltage VR1, at least a part of the timing circuit is driven by a second voltage VR2, and the rest of the timing circuit and the interface circuit are 3, and each of the voltages has a relationship of first voltage VR <b> 1 <second voltage VR <b> 2 <third voltage VDD.

According to Patent Document 1, it is possible to reduce power consumption in at least a part of the time measuring circuit to some extent. However, since the power supply voltage is higher than the power supply voltage of the crystal oscillation circuit, the power consumption is not sufficiently reduced. Further, Patent Document 1 does not particularly disclose use of a clock signal generated in a real-time clock device in a peripheral circuit.
JP 2008-85414 A (page 4, FIG. 1)

  In view of the above, the present invention further reduces the power consumption of a semiconductor integrated circuit for a real-time clock that manages timekeeping information, and generates a clock signal generated in the semiconductor integrated circuit for a real-time clock in a peripheral circuit. The purpose is to make it available.

  In order to solve the above problems, a semiconductor integrated circuit according to one aspect of the present invention includes a first power supply voltage and a first power supply voltage lower than the first power supply voltage based on a power supply voltage supplied from the outside. A constant voltage circuit that generates a power supply voltage of 2, a second power supply voltage generated by the constant voltage circuit is supplied, an oscillation circuit that generates an oscillation clock signal by performing an oscillation operation, and a constant voltage circuit The second power supply voltage is supplied and a frequency dividing circuit that generates a plurality of types of frequency-divided clock signals by frequency-dividing the original oscillation clock signal generated by the oscillation circuit and a first voltage generated by the constant voltage circuit 1 is supplied with a power supply voltage, and a logic circuit that manages timing information based on at least one frequency-divided clock signal generated by the frequency-dividing circuit, and a source clock generated by the oscillation circuit Comprising a selector circuit for selecting one of a predetermined number of divided clock signal generated by the signal dividing circuit, and an output circuit for supplying a clock signal selected by the selector circuit to the output terminal.

  Here, the logic circuit may control the selector circuit so as to select a clock signal required from the outside by communicating with the outside. The semiconductor integrated circuit may further include an output control terminal for controlling whether or not the output circuit supplies a clock signal to the output terminal.

  According to the present invention, in a semiconductor integrated circuit for a real-time clock, a frequency dividing circuit that divides an original clock signal by being supplied with a second power supply voltage lower than the first power supply voltage, By further providing a selector circuit that selects one of the predetermined number of divided clock signals and an output circuit that supplies the clock signal selected by the selector circuit to the output terminal, the power consumption is further reduced. The generated clock signal can be used also in the peripheral circuit.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same referential mark is attached | subjected to the same component and description is abbreviate | omitted.
FIG. 1 is a circuit diagram showing a configuration of a semiconductor integrated circuit for a real-time clock according to an embodiment of the present invention.

  As shown in FIG. 1, the semiconductor integrated circuit includes a constant voltage circuit 10, an oscillation circuit 20, a frequency dividing circuit 30, level shifters 41 and 42, a logic circuit 50, a selector circuit 60, and an output circuit (see FIG. 1). 1 shows an AND circuit 70) and a level shifter 80.

This semiconductor integrated circuit operates with power supply potentials V _DD and V _SS supplied from the outside. In the following, the power supply potential _{V DD} is 5.5V, the power supply voltage _{V SS} is described when a 0V (ground potential). The constant voltage circuit 10 includes a first power supply voltage HV _DD (for example, 2.4 V) and a second power supply lower than the first power supply voltage HV _DD based on a power supply voltage V _DD supplied from the outside. A voltage LV _DD (for example, 0.8 V) is generated.

The oscillation circuit 20 is supplied with the second power supply voltage LV _DD generated by the constant voltage circuit 10, and generates an oscillation clock signal by performing an oscillation operation. As the oscillation circuit 20, for example, a crystal oscillation circuit using a crystal resonator is used. The frequency of the original clock signal is, for example, 32.768 kHz.

FIG. 2 is a circuit diagram showing a configuration example of the oscillation circuit shown in FIG. As shown in FIG. 2, in the oscillation circuit 20, a crystal resonator 21 and a feedback resistor 22 are connected in parallel between the input and output terminals of the inverter 23, and further, between the input terminal of the inverter 23 and the ground potential. A capacitor 24 is connected, and a capacitor 25 is connected between the output terminal of the inverter 23 and the ground potential. The output signal of the inverter 23 is given a predetermined phase rotation by the crystal resonator 21 or the like, and is fed back to the input terminal of the inverter 23, whereby the oscillation operation is performed. Since the oscillation circuit 20 operates when a power supply voltage that enables the inverter 23 to operate is supplied, even if the second power supply voltage LV _DD is 0.8 V, it is sufficient for the oscillation circuit 20 to operate. .

  Here, the crystal unit 21 may be externally attached to the outside of the semiconductor integrated circuit, and other elements may be built in the semiconductor integrated circuit. Further, the feedback resistor 22 or the capacitors 24 and 25 may be externally attached. As the oscillation circuit 20, in addition to the crystal oscillation circuit, an oscillation circuit using a vibrator such as a ceramic vibrator, a SAW (Surface Acoustic Wave) vibrator, an oscillation circuit using CR or LC, An oscillation circuit using an inverter connected in multiple stages can be used.

Referring back to FIG. 1, the frequency dividing circuit 30 is supplied with the second power supply voltage LV _DD generated by the constant voltage circuit 10, and divides the original oscillation clock signal generated by the oscillation circuit 20. A plurality of types of divided clock signals are generated. The frequency dividing circuit 30 is configured by, for example, connecting a plurality of 1/2 frequency dividing circuits using flip-flops. The frequencies of the plurality of types of divided clock signals are, for example, 16.384 kHz, 8.192 kHz, 4.096 kHz,.

FIG. 3 is a circuit diagram showing a configuration example of the frequency dividing circuit shown in FIG. The frequency dividing circuit 30 includes a plurality of flip-flops 31, 32,. Each flip-flop inputs the inverted output signal output from the inverted output terminal Q bar to the data input terminal D, thereby dividing the clock signal input to the clock signal input terminal C by 1/2. Therefore, if the number of flip-flops included in the frequency divider circuit 30 is N, the original oscillation clock signal generated by the oscillation circuit 10 is divided by 1/2 ^N. The cycle is ^2N times the cycle of the original clock signal.

  FIG. 4 is a circuit diagram showing a configuration example of the flip-flop shown in FIG. As shown in FIG. 4, this flip-flop includes a first analog switch composed of a P channel MOS transistor QP11 and an N channel MOS transistor QN11, and a first analog switch composed of a P channel MOS transistor QP12 and an N channel MOS transistor QN12. 1 inverter, a second inverter constituted by a P channel MOS transistor QP13 and an N channel MOS transistor QN13, and a second analog switch constituted by a P channel MOS transistor QP14 and an N channel MOS transistor QN14. Yes.

  Further, the flip-flop includes a third analog switch constituted by a P channel MOS transistor QP21 and an N channel MOS transistor QN21, a third inverter constituted by a P channel MOS transistor QP22 and an N channel MOS transistor QN22, A fourth inverter constituted by P channel MOS transistor QP23 and N channel MOS transistor QN23 and a fourth analog switch constituted by P channel MOS transistor QP24 and N channel MOS transistor QN24 are included.

  When the clock signal CLK is at a low level and the inverted clock signal CLK bar is at a high level, the first analog switch is turned on and the second analog switch is turned off. Thereby, the data input to the data input terminal D passes through the first analog switch, is input to the first inverter, is inverted by the first inverter, and is inverted again by the second inverter. .

  When the clock signal CLK becomes high level and the inverted clock signal CLK bar becomes low level, the first analog switch is turned off and the second analog switch is turned on. As a result, data output from the second inverter is input to the first inverter, and a stable state is obtained by positive feedback. At the same time, the third analog switch is turned on and the fourth analog switch is turned off. Thereby, the data output from the first inverter passes through the third analog switch, is input to the third inverter, is inverted by the third inverter, and is inverted again by the fourth inverter. Therefore, when the clock signal CLK is at a low level, the data input to the level data input terminal D is output from the data output terminal Q, and the inverted data is output from the inverted data output terminal Q bar. The inverted data is supplied to the data input terminal D.

  When the clock signal CLK becomes low level and the inverted clock signal CLK bar becomes high level, the third analog switch is turned off and the fourth analog switch is turned on. As a result, data output from the fourth inverter is input to the third inverter, and a stable state is achieved by positive feedback. At the same time, the first analog switch is turned on and the second analog switch is turned off. As a result, the inverted data supplied to the data input terminal D is taken in through the first analog switch, and then output from the data output terminal Q when the clock signal CLK goes high. The In this manner, a divided clock signal having a cycle twice that of the clock signal CLK is generated.

Since this flip-flop operates when a power supply voltage enabling the first to fourth analog switches and the first to fourth inverters to operate is supplied, the second power supply voltage LV _DD is 0.8V. However, it is sufficient for the frequency divider 30 (FIG. 3) to operate. Referring to FIG. 1 again, by separating the frequency divider 30 from the logic circuit 50, the operation noise of the logic circuit 50 is not received. Further, the second power supply voltage LV _{DD, which} is the same as that supplied to the oscillation circuit 20, is supplied to the frequency dividing circuit 30, so that low power consumption can be realized.

The original oscillation clock signal generated by the oscillation circuit 20 is supplied to the level shifter 41, and the level is shifted so as to have an amplitude corresponding to the first power supply voltage HV _DD . The predetermined number of frequency-divided clock signals generated by the frequency dividing circuit 30 are supplied to the level shifter 42 and the level is shifted so as to have an amplitude corresponding to the first power supply voltage HV _DD .

The logic circuit 50 is supplied with the first power supply voltage HV _DD generated by the constant voltage circuit 10, and based on the frequency-divided clock signal of at least 1 Hz generated by the frequency divider circuit 30 and shifted in level by the level shifter 42, Manage timekeeping information. For example, the logic circuit 50 includes a plurality of counters, and counts 1 Hz frequency-divided clock signals to generate current date / time data of year / month / day / hour / minute / second. The current date and time data generated by the logic circuit 50 is output to the outside of the semiconductor integrated circuit via the communication data terminal.

Further, the original oscillation clock signal generated by the oscillation circuit 20 and shifted in level by the level shifter 41 and the predetermined number of divided clock signals generated by the frequency dividing circuit 30 and shifted in level by the level shifter 42 are the selector circuit 60. To be supplied. The selector circuit 60 is supplied with the first power supply voltage HV _DD generated by the constant voltage circuit 10 and selects one clock signal from the original oscillation clock signal and a predetermined number of divided clock signals. The selector circuit 60 can be configured by a multiplexer including a plurality of analog switches, for example.

  Here, the logic circuit 50 performs communication with the outside via the communication clock terminal and the communication data terminal to set the internal register, thereby selecting the clock signal required from the outside. Also good. The logic circuit 50 generates a selector control signal for controlling the selector circuit 60 so as to select a clock signal required from the outside, and supplies the selector control signal to the selector circuit 60.

  The AND circuit 70 serving as an output circuit obtains the logical sum of the output control signal applied to the output control terminal and the clock signal selected by the selector circuit 60, thereby enabling the output control signal to be activated to a high level. In addition, the clock signal selected by the selector circuit 60 is output.

  In this way, it is possible to control whether the output circuit supplies a clock signal to the output terminal using the output control terminal. As the output circuit, in addition to the AND circuit, a logic circuit such as a NAND circuit, an OR circuit, or a NOR circuit can be used. Alternatively, an analog switch may be used.

The clock signal output from the output circuit is supplied to the level shifter 80, and the level is shifted so as to have an amplitude corresponding to the power supply voltage V _DD supplied from the outside. As a result, the clock signal generated in the semiconductor integrated circuit for the real-time clock can be used also in the peripheral circuit operating with the power supply voltage V _DD supplied. Further, by setting the internal register by the logic circuit 50 communicating with the outside, it becomes possible to supply a clock signal with a wide range of frequencies.

1 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to an embodiment of the present invention. FIG. 2 is a circuit diagram illustrating a configuration example of an oscillation circuit illustrated in FIG. 1. FIG. 2 is a circuit diagram illustrating a configuration example of a frequency dividing circuit illustrated in FIG. 1. FIG. 4 is a circuit diagram illustrating a configuration example of the flip-flop illustrated in FIG. 3.

Explanation of symbols

  10 constant voltage circuit, 20 oscillation circuit, 21 crystal oscillator, 22 feedback resistor, 23 inverter, 24, 25 capacitor, 30 frequency dividing circuit, 31, 32, ... flip-flop, 41, 42, 80 level shifter, 50 logic Circuit, 60 selector circuit, 70 AND circuit, QP11 to QP24 P channel MOS transistor, QN11 to QN24 N channel MOS transistor

Claims (3)

A constant voltage circuit for generating a first power supply voltage and a second power supply voltage lower than the first power supply voltage based on a power supply voltage supplied from the outside;
An oscillation circuit that is supplied with a second power supply voltage generated by the constant voltage circuit and generates an oscillation clock signal by performing an oscillation operation;
A frequency dividing circuit that is supplied with a second power supply voltage generated by the constant voltage circuit and generates a plurality of types of frequency-divided clock signals by dividing the original clock signal generated by the oscillation circuit;
A logic circuit that is supplied with a first power supply voltage generated by the constant voltage circuit and manages timing information based on at least one frequency-divided clock signal generated by the frequency divider circuit;
A selector circuit for selecting one of the original oscillation clock signal generated by the oscillation circuit and the predetermined number of divided clock signals generated by the divider circuit;
An output circuit for supplying a clock signal selected by the selector circuit to an output terminal;
A semiconductor integrated circuit comprising:   The semiconductor integrated circuit according to claim 1, wherein the logic circuit controls the selector circuit to select a clock signal required from the outside by performing communication with the outside.   3. The semiconductor integrated circuit according to claim 1, further comprising an output control terminal for controlling whether or not the output circuit supplies a clock signal to the output terminal.

Images