JP2010103410A - Method of manufacturing wiring board, and wiring board - Google Patents

Abstract

An object of the present invention is to provide a fine wiring pattern on an insulating plate with consistency with a formation process of an interlayer connection body and a formation process of a conductor layer pattern that does not require fineness and without causing an increase in cost.
A first conductor is provided on each of the first and second main surfaces of an insulating plate having a first main surface and a second main surface facing the first main surface. On the first conductor layer, a second conductor layer having a second conductor different from the first conductor is formed to form a laminate of at least five layers. The second conductor layer is patterned to expose a part of the first conductor layer, and a resist pattern is formed on a part of the first conductor layer. Using the resist pattern as a mask, A third conductor layer is formed on a part of the first conductor layer from which the resist pattern has been removed, the resist pattern is removed, and the first conductor layer is masked by using the second conductor layer and the third conductor layer as a mask. The conductor layer is removed.
[Selection] Figure 1

Description

  The present invention relates to a method of manufacturing a wiring board having a wiring pattern on an insulating board and the wiring board, and more particularly to a method of manufacturing a wiring board and a wiring board suitable for providing a fine wiring pattern on an insulating board.

  In recent years, the functionality of wiring boards has been increasing due to multilayer wiring layers, high density wiring patterns, and miniaturization of interlayer connectors. As a result, a useful position is obtained for various portable electronic devices that are required to be small and light.

  In general, in order to make the wiring pattern finer, it is more advantageous to form the wiring pattern by plating growth, for example, than the known method using etching. When etching is used, the etching proceeds isotropically with respect to the metal foil on the insulating plate, so it is difficult to ensure the perpendicularity of the etched metal foil side surface. The cross-sectional shape is such that the cross-sectional shape is pulled, or the cross-sectional shape is such that the side-etching is performed by side etching. Neither cross-sectional structure is preferred in terms of line / space dimensional control.

  On the other hand, in the case of a wiring pattern grown by plating, it can be grown in a pattern almost following the fine pattern of the resist mask. Therefore, the wiring pattern can be formed with a fineness obtained by exposure and development of the resist.

On the other hand, if the wiring pattern formation process is grasped in the whole manufacturing process as a wiring board, even if this is formed by plating for miniaturization of the wiring pattern, this process is another process, for example, formation of an interlayer connection body. It is preferable to be performed in a process that is consistent with the process and the process of forming a wiring pattern that does not require much fineness, and that does not cause much cost increase. For example, the following patent document discloses a method of manufacturing a wiring board having a step of forming a wiring pattern, but the relationship between the step of forming an interlayer connection and the step of forming a wiring pattern that does not require much fineness. However, features as disclosed herein are not disclosed.
Japanese Patent Laid-Open No. 2003-23256

  The present invention has been made in consideration of the above-described circumstances, and a method for manufacturing a wiring board having a wiring pattern on an insulating board and a conductive material that does not require much formation process and fineness of an interlayer connection in the wiring board. It is an object of the present invention to provide a method of manufacturing a wiring board and a wiring board that can be provided with a fine wiring pattern on an insulating board with consistency with a body layer pattern forming process and the like and without causing much cost increase.

  In order to solve the above-described problem, a method for manufacturing a wiring board according to one aspect of the present invention includes a first main surface and a second main surface opposite to the first main surface. A second conductor layer having a second conductor different from the first conductor is stacked on the first conductor layer having the first conductor on each of the first and second main surfaces. Forming at least five layers of laminated plates provided in a shape, patterning the second conductor layer of the laminate, exposing a part of the first conductor layer, and the first Forming a resist pattern on the part of the first conductor layer, and using the resist pattern as a mask, a third conductor on the part of the first conductor layer from which the resist pattern is removed Forming a layer, removing the resist pattern, the second conductor layer, and the first Characterized by comprising the step of said conductor layer as a mask removing the first conductive layer.

  That is, the at least five-layer laminate is provided with a conductor layer having a two-layer structure on each main surface of the insulating plate, and a lower layer (first conductor layer) is provided there. After that it has great significance for the process. First, by patterning the upper layer (second conductor layer), formation of a conductor layer pattern that does not require much fineness is almost completed. In this patterning, since the first conductor layer serves as a buffer and the etchant does not reach the insulating plate, there is no possibility of altering the interlayer connection that may be embedded in the insulating plate.

  Further, since the third conductor layer is formed on the first conductor layer exposed by the etching of the second conductor layer using the resist pattern as a mask, this can be a fine wiring pattern. Then, by removing the first conductor layer using the second conductor layer remaining after the etching and the formed third conductor layer as a mask, a conductor layer pattern that does not require much fineness And a fine wiring pattern are electrically separated. In the removal of the first conductor layer, the etchant cannot contact the interlayer connection which may be embedded in the insulating plate, so there is no possibility of altering it.

  These processes are possible with the minimum necessary process increase. Therefore, the cost is not increased so much, and the formation process of the interlayer connection body and the formation process of the conductor layer pattern which does not require the fineness are required. A fine wiring pattern can be provided on the insulating plate with consistency.

  The wiring board according to one embodiment of the present invention is different from the first conductor on the insulating board and the first conductor layer that protrudes from the insulating board and has the first conductor. A conductor layer pattern having a second conductor layer having a second conductor and having a side surface which is an etching removal surface; and a third conductor projecting on the insulating plate and having the first conductor And a wiring pattern having a fourth conductor layer having the second conductor on the conductor layer, and a side surface of the fourth conductor layer being a side surface of conductive material deposition. Features.

  This wiring board is a wiring board that can be manufactured by the above manufacturing method.

  According to the present invention, a fine wiring pattern can be formed on an insulating plate with consistency with a formation process of an interlayer connection body and a formation process of a conductor layer pattern that does not require much fineness and without causing much cost increase. A wiring board manufacturing method and a wiring board that can be provided can be provided.

  As an embodiment of the present invention, the step of forming at least five layers of laminates includes a step in which one of the second conductor layers is laminated on one of the first conductor layers. Forming a conductive bump on the first conductor layer of the first conductor laminate, and a prepreg to be the insulating plate on the first conductor layer of the first conductor laminate. And the other of the second conductor layers is placed on the other of the first conductor layers so as to face the prepreg. A step of facing the side of the first conductor layer of the laminated second conductor laminate, and the first conductor layer of the second conductor laminate is pressed against the conductive bump. The three members of the first conductor laminate, the prepreg, and the second conductor laminate are stacked. It may be, and a step of integrating pressurized direction.

  This is an example of a process for providing an insulating plate included in at least five laminated plates with an interlayer connector penetrating the insulating plate. According to these steps, a fine interlayer connection can also be formed efficiently.

  Here, the step of forming the conductive bump may be performed by screen printing a conductive composition in which conductive fine particles are dispersed in a paste-like resin. A large number of conductive bumps can be efficiently formed by using screen printing.

  As an embodiment, after the step of exposing a part of the first conductor layer and before the step of forming a resist pattern, at least on the part of the first conductor layer. After the step of forming a seed layer for forming the third conductor layer and the step of removing the resist pattern, before the step of removing the first conductor layer, the first layer is formed. And the step of removing the seed layer using the conductor layer 3 as a mask. By forming the seed layer, it is possible to improve the formation quality of the plating layer continuous with the seed layer and to further reduce the electric resistance.

  As an embodiment, the first conductor is titanium nitride or titanium, the second conductor is copper, and the third conductor layer is made of copper. be able to. These are examples of materials for the first and second conductors and the third conductor layer. These materials have advantages in terms of handling and cost.

  Further, as an embodiment as a wiring board, the wiring patterns are provided on both main surfaces of the insulating plate, and pass through the insulating plate between the wiring patterns of the two main surfaces of the insulating plate. It may further include an interlayer connection body that is sandwiched and made of a conductive composition and has an axis that coincides with the stacking direction and has a diameter that changes in the direction of the axis. This wiring board is a mode in which fine wiring patterns are provided on both main surfaces, and an interlayer connection body (the diameter changes in the axial direction) of a conductive composition is provided to electrically connect them. Yes. Such an interlayer connection can be finely and efficiently formed by screen printing, for example.

  Based on the above, embodiments of the present invention will be described below with reference to the drawings. 1 to 3 are process diagrams schematically showing a method of manufacturing a wiring board according to an embodiment of the present invention. This process proceeds in the order shown in FIGS. 1A to 3B. In these drawings, the same reference numerals are assigned to the same equivalent portions.

  First, as shown in FIG. 1A, an etching stopper layer 12 which is a conductor made of a different material is formed on a copper foil 11 having a thickness of, for example, 10 μm to 35 μm. The film forming method can be selected from various known methods such as sputtering, vapor deposition, ion plating, thermal spraying, and CVD (chemical vapor deposition). As the copper foil 11, an electrolytic copper foil or a rolled copper foil can be used. It is also possible to use a conductive foil such as a metal other than copper, such as nickel, silver or gold, or a compound or alloy containing these metals.

  As a material of the etching stopper layer 12, for example, titanium, nickel, chromium, gold, molybdenum, tantalum, tungsten, silver, or a compound or alloy containing these metals can be used. Here, the following description will be made assuming that a titanium nitride film is formed as the etching stopper layer 12 by sputtering. The surface of the copper foil 11 may be subjected to a roughening treatment in advance for the purpose of improving the adhesion between the etching stopper layer 12 formed on this surface and a prepreg 14 described later by an anchor effect.

  Sputtering of the etching stopper layer 12 can be reactive sputtering using a magnetron DC sputtering apparatus, for example, by adding nitrogen to argon as a sputtering gas. In order to improve the cleanliness of the surface on which the etching stopper layer 12 on the copper foil 11 is formed in advance, for example, argon plasma treatment is performed on the surface.

More specifically, from argon plasma treatment to sputtering treatment, first, the copper foil 11 which is the substrate to be treated is heated to room temperature or 50 ° C. to 180 ° C., the plasma treatment pressure is 3 Pa to 10 Pa, and the substrate to be treated is 0. .RF of 5 W / cm ^{2 to 3} W / cm ² is added and argon plasma treatment is performed. The sputtering Then, by applying a DC of ^1W / cm ^{2 ~3W} / cm 2 in the titanium electrode is a target electrode for facing the target substrate, the sputtering pressure 0.2Pa～1Pa, nitrogen gas argon gas flow ratio Do this as 1% to 10%. In sputtering, a bias voltage may be applied to the substrate to be processed. The thickness of the titanium nitride film (= etching stopper layer 12) to be obtained is, for example, 10 nm to 200 nm.

  Next, as shown in FIG. 1B, conical conductive bumps 13 serving as interlayer connection bodies are formed on predetermined positions (positions necessary as wiring boards to be manufactured) of the formed etching stopper layer 12. For example, it is formed to a height of, for example, 20 μm to 300 μm using screen printing. The material of the conductive bump 13 is, for example, a synthetic resin (for example, polycarbonate resin, polyester resin, polysulfone resin) in which conductive fine particles made of silver, gold, copper, solder, or the like are used as a filler and an organic solvent is added. , Polyimide resin, phenol resin, epoxy resin, and the like) as a binder.

  In the screen printing, for example, a screen plate having a plate thickness, for example, 80 μm to 300 μm stainless plate provided with through holes at predetermined positions is used. Printing may be performed a plurality of times while sandwiching the drying process until the height of the conductive bump 13 to be formed becomes a predetermined height. By using screen printing, fine and numerous conductive bumps 13 can be efficiently formed.

  Next, as shown in FIG. 1C, a prepreg 14 having a thickness of, for example, 30 μm to 160 μm is laminated on the etching stopper layer 12, and the conductive bumps 13 are penetrated or embedded. When exposed, the tip may then be crushed by plastic deformation (in any case, the conductive bump 13 is derived from the original shape and has an axis that coincides with the stacking direction and has a diameter in the axial direction. Becomes a changing shape.) The prepreg 14 is, for example, a resin such as a polyester resin, a polysulfone resin, a polyimide resin, a phenol resin, or an epoxy resin, or a resin having a structure in which a glass cloth or the like is impregnated as a reinforcing material. Here, description will be continued below using an epoxy resin impregnated with glass cloth.

  Next, as shown in FIG. 1 (d), an etching stopper of a laminated plate (having a copper foil 15 and an etching stopper layer 16) having the same configuration as that shown in FIG. The layers 16 are laminated with the sides facing each other. In this laminating step, for example, first, the prepreg 14 is made into a thermoplastic state at a temperature of 90 ° C. to 150 ° C., and a laminating pressure of about 1 MPa is applied to establish an electrical connection state between the conductive bump 13 and the etching stopper layer 16. Subsequently, the temperature is increased to 180 ° C. to 240 ° C. and the pressure is increased to about 5 MPa, and the prepreg 14 is thermally cured to integrate the whole. As a result, the prepreg 14 is cured to become the insulating plate 14A.

  Note that various modifications can be considered for the five-layer laminate including the conductive bumps 13 shown in FIG. First, even a configuration that does not have the conductive bumps 13 is not a hindrance to the processes described below. In addition, the conductive bumps 13 are not formed by screen printing, but various types of densely structured bumps (for example, conductive compositions filled in through holes, deposited and grown by plating, and etching metal plates) And the like having a truncated cone shape). Moreover, even if it is a laminated board of 5 layers or more, it can be used as long as the outer two layers are the etching stopper layer 12 and the copper foil 11, and the etching stopper layer 16 and the copper foil 15, respectively. .

  After the five-layer laminate is formed, the copper foils 11 and 15 on both sides are then etched using, for example, a well-known photolithography technique, and this is used as a second conductor as shown in FIG. Patterning is performed on the patterned copper foils 11 </ b> A and 15 </ b> A as layers (processing into a pattern necessary as a wiring board to be manufactured). That is, as a photolithography process, a resist film (not shown) is formed on the copper foils 11 and 15 on both sides, and exposure is performed and plate making is performed. Subsequently, a resist pattern (not shown) by plate making is used as a mask. The copper foils 11 and 15 are wet etched using a ferric chloride solution as an etchant. After etching, the resist pattern is removed. The side surfaces of the patterned copper foils 11A and 15A become etching removal surfaces.

The etching process will be described more specifically. For example, first, a dry film H-6138 manufactured by Hitachi Chemical Co., Ltd. is used as a resist film, and this is laminated by a thermal laminating method. In the exposure, exposure is performed with a light intensity of 40 mJ / cm ² using a parallel light exposure machine, and in the development, spray development is performed with a 2% by weight solution of calcium carbonate. As an etchant, a ferric chloride solution having a specific gravity of 1.2 to 1.5 is used and sprayed at 45 ° C. for etching. For removing the resist film, for example, a 2 wt% solution of sodium hydroxide is used and sprayed at a temperature of 40 ° C.

  The patterned copper foils 11A and 15A obtained in this etching process become part of a conductor layer pattern (which may be used as a wiring pattern) that does not require much fineness. In this etching, the etching stopper layers 12 and 16 serve as buffers, and the etchant does not reach the insulating plate 14A. Therefore, there is no possibility of altering the conductive bumps 13 penetrating the insulating plate 14A, and the compatibility with the wiring board manufacturing method including the process of forming the conductive bumps 13 is good.

  After obtaining the patterned copper foils 11A and 15A, next, as shown in FIG. 1F, seed layers 17 and 18 are formed on both surfaces after the etching. The seed layers 17 and 18 improve the formation quality of the plating layer (plating quality) which is the third (fourth) conductor layer to be formed on the seed layers 17 and 18 and reduce the electric resistance. It is formed for the purpose of lowering and improving high frequency characteristics. Depending on the quality specifications of the plating layer, the formation of the seed layers 17 and 18 may be omitted.

  The seed layers 17 and 18 are required to be made of a material that meets the above-mentioned purpose, but here, copper of the same material is used on the premise that the plating layer formed thereon is formed of copper. As a specific example of forming, for example, in order to form this by sputtering, a magnetron DC sputtering apparatus is used and argon is used as a sputtering gas. In order to improve the adhesion between the seed layers 17 and 18 to be formed and the etching stopper layers 12 and 16, it is preferable to perform plasma treatment on the surfaces of the etching stopper layers 12 and 16 in advance.

More specifically, from plasma treatment to sputtering treatment, first, plasma treatment is performed by applying a RF of about 1 W / cm ² to the substrate to be treated with the substrate to be treated at room temperature and a plasma treatment pressure of 3 Pa to 8 Pa. The sputtering Then, by applying a DC to the copper electrode of ^1W / cm ^{2 ~3W} / cm 2 is a target electrode for facing the target substrate, do this sputtering pressure of 0.2Pa～1Pa. In sputtering, a bias voltage may be applied to the substrate to be processed. The thickness of the seed layers 17 and 18 to be obtained is, for example, 50 nm to 500 nm.

  In addition, about the adhesiveness of the seed layers 17 and 18 to be formed and the etching stopper layers 12 and 16, since the portion is incorporated as a fine wiring pattern thereafter, the cleanliness of the surfaces of the etching stopper layers 12 and 16 is maintained. For this reason, it is preferable to pay sufficient attention to the handling of the substrate to be processed during the transition from plasma processing to sputtering processing.

Next, as shown in FIG. 2A, resists 19 and 20 are laminated on both sides. More specifically, for example, as the resists 19 and 20, Hitachi Chemical dry film RY-3215 is used, and this is laminated using a vacuum laminating method. Subsequently, the resists 19 and 20 are exposed and developed, and are patterned into resist patterns 19A and 20A, which are patterns in which a region where a plating layer is to be grown is removed, as shown in FIG. The area where the layer is to be grown is the area necessary for the wiring board to be manufactured). In the exposure of the resists 19 and 20, for example, exposure is performed with a light intensity of 10 mJ / cm ² using a parallel light exposure machine, and in the development, spray development is performed with a 2 wt% solution of calcium carbonate.

Next, using the resist patterns 19A and 20A as a mask, as shown in FIG. 2C, plating layers 21 and 22 are deposited and grown on the seed layers 17 and 18 by, for example, copper sulfate plating. In this plating step, the etching stopper layers 12 and 16 and the seed layers 17 and 18 become cathodes. More specifically, for example, the anode current density is 2 A / dm ² , the cathode current density is 1.5 A / dm ² , the temperature is 25 ° C., and Cubelite VF2 made by Ebara Eugene is used as the plating solution, and air stirring is performed. Can be carried out in an electrolytic copper plating process. The adhesion between the seed layers 17 and 18 and the plating layers 21 and 22 is incorporated as a fine wiring pattern. Therefore, in order to maintain the cleanliness of the surface of the seed layers 17 and 18, the oxidation is performed. It is preferable to take great care to prevent this.

  Next, as shown in FIG. 2D, the resist patterns 19A and 20A are removed. This can be done, for example, by spraying at 40 ° C. with a 2% by weight solution of sodium hydroxide. The pattern of the plating layers 21 and 22 formed here is a pattern that follows the fineness of the resist patterns 19A and 20A. Therefore, the pattern is more precise than the pattern (patterned copper foils 11A and 15A) formed by etching. / Satisfies the space specifications. The side surfaces of the patterns of the plating layers 21 and 22 are the side surfaces of the plating quality (conductive material) deposition.

  After the resist patterns 19A and 20A are peeled off, the exposed seed layers 17 and 18 are then removed as shown in FIG. This step is performed as a previous step of removing the etching stopper layers 12 and 16 using the patterned copper foils 11A and 15A and the plating layers 21 and 22 as a mask.

  Since the seed layers 17 and 18 are very thin and are made of the same material as the patterned copper foils 11A and 15A and the plating layers 21 and 22, etching control is easy rather than etching with a ferric chloride solution. Thus, etching with a flash etchant can be performed. More specifically, Meltex CU-3930 is used as a flash etching solution, and this is performed under normal temperature and immersion conditions. At this time, pay careful attention to the etching time setting for etching control. By removing the exposed seed layers 17 and 18, seed layers (residual seed layers 17 </ b> A and 18 </ b> A) remain only under the plating layers 21 and 22.

  Next, as shown in FIG. 3B, the etching stopper layers 12 and 16 are removed using the patterned copper foils 11A and 15A and the plating layers 21 and 22 as masks. At this time, etching such as dipping or spraying with a flash etching solution can be performed so as to facilitate etching control. More specifically, for example, as a flash etching solution, a solution prepared by mixing Meltex Ti-3991, 35% hydrogen peroxide water, and pure water in a ratio of 1: 2: 2, respectively, at 35 ° C., immersion Do this with conditions. In the removal of the etching stopper layers 12 and 16, since the etchant does not come into contact with the conductive bumps 13 penetrating the insulating plate 14A, there is no possibility of altering the etching stopper layers 12 and 16.

  As a result, as shown in FIG. 3B, conductor layer patterns 51 and 52 that do not require much fineness and wiring patterns 61 and 62 with finer specifications are provided on the insulating plate 14A. A wiring board is obtained. Here, the conductor layer patterns 51 and 52 have a structure in which the patterned copper foils 11A and 15A are stacked on the residual etching stopper layers 12A and 16A as shown in the figure. In this structure, the residual seed layers 17A and 18A and the plating layers 21 and 22 are stacked on the residual etching stopper layers 12A and 16A.

  Although the subsequent steps from the state shown in FIG. 3B are not shown, for example, a well-known solder resist pattern is formed, or further, on the conductor layer patterns 51 and 52 not covered with the solder resist or the same wiring pattern. A well-known Ni / Au plating layer having corrosion resistance may be formed on 61 and 62. Further, the wiring board shown in FIG. 3B can be further multilayered by using the wiring board as a material to manufacture the wiring board.

  In the above, the manufacturing method of the wiring board which concerns on this embodiment was demonstrated. According to this manufacturing method, an increase in the number of steps for providing the wiring patterns 61 and 62 with finer specifications can be minimized as described above. Therefore, the insulation does not cause much cost increase and is consistent with the formation process of the conductive bumps 13 as the interlayer connection body and the formation process of the conductive layer patterns 51 and 52 that do not require much fineness. Finer wiring patterns 61 and 62 can be provided on the plate 14A.

  In addition, as for the production equipment, it is assumed that the existing production equipment is used for the production of the wiring board of the existing specification. It is possible to prepare as a production facility that can handle the production of such wiring boards. Therefore, it is not necessary to introduce new equipment in a lump, and the capital investment burden can be eased.

Process drawing which shows the manufacturing method of the wiring board which concerns on one Embodiment of this invention typically. FIG. 2 is a continuation diagram of FIG. 1, and a process diagram schematically showing a method for manufacturing a wiring board according to an embodiment of the present invention. FIG. 3 is a continuation diagram of FIG. 2, and a process diagram schematically showing a method for manufacturing a wiring board according to an embodiment of the present invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Copper foil, 11A ... Patterned copper foil (2nd conductor layer), 12 ... Etching stopper layer, 12A ... Residual etching stopper layer (1st or 3rd conductor layer), 13 ... Conductive bump ( Interlayer connection body), 14 ... prepreg, 14A ... insulating plate, 15 ... copper foil, 15A ... patterned copper foil (second conductor layer), 16 ... etching stopper layer, 16A ... residual etching stopper layer (first or (Third conductor layer), 17 ... seed layer, 17A ... residual seed layer, 18 ... seed layer, 18A ... residual seed layer, 19 ... resist, 19A ... resist pattern, 20 ... resist, 20A ... resist pattern, 21 ... Plating layer (third or fourth conductor layer), 22 ... plating layer (fourth conductor layer), 51 ... conductor layer pattern, 52 ... conductor layer pattern, 61 ... wiring pattern, 62 Wiring pattern.

Claims (7)

A first conductive material having a first conductor on each of the first and second main surfaces of an insulating plate having a first main surface and a second main surface opposite to the first main surface. Forming a laminate of at least five layers in which a second conductor layer having a second conductor different from the first conductor is provided on the body layer, and
Patterning the second conductor layer of the laminate and exposing a portion of the first conductor layer;
Forming a resist pattern on the part of the first conductor layer;
Forming a third conductor layer on the part of the first conductor layer from which the resist pattern has been removed, using the resist pattern as a mask;
Removing the resist pattern;
And a step of removing the first conductor layer by using the second conductor layer and the third conductor layer as a mask. After the step of exposing a portion of the first conductor layer and before the step of forming a resist pattern, the third conductive layer is formed on at least the portion of the first conductor layer. Forming a seed layer for forming a body layer;
And after the step of removing the resist pattern and before the step of removing the first conductor layer, further comprising a step of removing the seed layer using the third conductor layer as a mask. The method for manufacturing a wiring board according to claim 1. The step of forming at least five layers of laminates,
Conductive bumps are formed on the first conductor layer of the first conductor laminate in which one of the second conductor layers is laminated on one of the first conductor layers. Forming, and
Laminating a prepreg to be the insulating plate on the first conductor layer of the first conductor laminate, and passing the conductive bumps through the prepreg;
The first conductor of the second conductor laminate in which the other of the second conductor layers is laminated on the other of the first conductor layers facing the prepreg. A step of facing the side of the layer;
3 of the first conductor laminate, the prepreg, and the second conductor laminate so that the first conductor layer of the second conductor laminate is pressed against the conductive bump. The method for manufacturing a wiring board according to claim 1, further comprising a step of pressing and integrating the operator in the stacking direction.   4. The method of manufacturing a wiring board according to claim 3, wherein the step of forming a conductive bump is performed by screen printing a conductive composition in which conductive fine particles are dispersed in a paste-like resin. Method. The first conductor is titanium nitride or titanium;
The second conductor is copper;
The method for manufacturing a wiring board according to claim 1, wherein the third conductor layer is made of copper. An insulating plate;
Having a second conductor layer projecting on the insulating plate and having a second conductor different from the first conductor on the first conductor layer having the first conductor; and A conductor layer pattern whose side surface is an etching removal surface;
A fourth conductor layer projecting on the insulating plate and having a second conductor layer on the third conductor layer having the first conductor; and the fourth conductor layer. A wiring board comprising: a wiring pattern in which a side surface of the layer is a side surface of conductive material deposition. The wiring patterns are provided on both main surfaces of the insulating plate,
There is an axis that penetrates the insulating plate and is sandwiched between the surfaces of the wiring patterns of the two main surfaces of the insulating plate, and is made of a conductive composition and has an axis that coincides with the stacking direction. The wiring board according to claim 6, further comprising an interlayer connector having a shape whose diameter is changed.

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