JP2010102764A - Memory module, control method used for the memory module, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory module that is used efficiently with low power consumption, by arranging memory cells into a matrix form. <P>SOLUTION: When a normal access mode is configured, the word lines of memory cells 22 are activated in units of rows. Meanwhile, when a sorting access mode is configured, memory cells 22 corresponding to a fixed number of rows (8 rows) are handled as a single unit block, since the row of a word line to be activated is changed (fed) by memory cells 22 of a fixed column (a column) within the range of one unit block, specific memory cells 22 astride across a plurality of rows are accessed by a single-sitting access. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a memory module, a control method used for the memory module, and an electronic apparatus. For example, a processor provided in an embedded device, a PC (personal computer), a data server, a DSP (Digital Signal Processor), A memory module suitable for use as a cache memory or a temporary buffer provided between an active module such as SoC (System on Chip) and a passive module such as SDRAM (Synchronous DRAM), a control method used for the memory module, And an electronic device.

  In an active module such as a processor, the computing power and processing power have been improved by increasing the clock frequency and the number of parallel processes. On the other hand, it is difficult to increase the access speed of a memory used as a main storage device such as an SDRAM or a secondary storage device such as a disk in response to an increase in the processing speed of the processor. For this reason, it is possible to improve the data transfer throughput (bandwidth) by accessing a large number of SDRAMs simultaneously in parallel, or to use an SRAM (Static Random Access Memory) that can be accessed at high speed in an active module as a cache memory or internal local memory. As a result, a device has been devised to fill this gap in speed. However, the scale of the memory that can be arranged in the active module is limited and is usually very small. For this reason, it is important to ensure that the memory is used efficiently in system design and software design in order to ensure the effective performance of the system.

  However, in an ordinary SRAM cell, access in the Row (row) direction is efficiently performed. However, in the case where access is made to vertical data continuous in the Column (column) direction or data across a plurality of Rows, a plurality of rows are accessed. After performing access in the row direction, it is necessary to select data, resulting in inefficient access. For example, when image data or the like is arranged in SRAM, SRAM access by processing such as rotating the image by 90 degrees or image reference updating when data is arranged across multiple lines in the Row direction is not There is a problem that it becomes efficient. In order to improve such a problem, an SRAM has been proposed in which data across a plurality of rows is efficiently accessed simultaneously.

As this type of related technology, for example, there is an image processing memory described in Patent Document 1.
As shown in FIG. 10, the image processing memory includes a memory array (MC-Array) 1, a row decoder (XDEC) 2, a data predecoder (XDPD) 3, a data predecoder (XDPD2) 4, Column decoder (YDEC0) 5, column decoder (YDEC1) 6, data predecoder (YDADD) 7, data predecoder (YDPD) 8, memory address (ADDR) 9, and vertical / horizontal selection signal (VH) input circuit 10. In this image processing memory, the memory array 1 is constituted by an SRAM, and the inside of the SRAM is divided in units of 8 bits in the Column direction to constitute a Column block. Based on the vertical / horizontal selection signal, the decoder 2, 4, 7, 8 accesses the memory array 1 from the decoders 2, 4, 7, 8 every 8 bits based on a certain rule. Is done.

  For example, when a vertical selection signal is input from the vertical / horizontal selection signal input circuit 10, the row decoder 2 selects 8 consecutive rows having different blocks, and the column decoders 5 and 6 select 8 different columns of the blocks to be accessed. Thus, the vertical data on the image frame is accessed. When the horizontal selection signal is input from the vertical / horizontal selection signal input circuit 10, the row decoder 2 selects four consecutive rows, the column decoders 5 and 6 select eight different columns to be accessed, and the image Access the horizontal data on the frame.

FIG. 11 is a diagram showing an internal configuration of the memory array 1 in FIG. 10 and is described in Non-Patent Document 1.
In this memory array 1, as shown in FIG. 11, access to the memory cell group 13 is governed by an AND gate 12, and both the column signal group CS and the global word line GWL are valid for each memory cell group 13. It is controlled so that it becomes effective only when In the global word line GWL, all necessary global word lines GWL are activated by the logic gate 11 and the logic signal LS, and further, necessary signals of the column signal group CS are activated, so that which row of each column is activated. It is determined whether to access the memory cell group 13, and an arbitrary row is accessed. As a result, it is possible to read and write data in the vertical direction or data across two adjacent rows by one access, and it is possible to increase the processing speed and reduce the power consumption.

  On the other hand, in embedded devices and the like, SoC (System on a Chip) in which a plurality of active modules such as general-purpose processors, DSPs, and hardware accelerators are integrated on a single chip in order to meet the demand for system miniaturization and low power consumption. ) Is increasingly used. In such a SoC, an on-chip bus for performing data communication between active modules and passive modules existing in the SoC is provided. As typical examples, activities such as AMBA (Advanced Microcontroller Bus Architecture), AHB (Advanced High-performance Bus), and AXI (Advanced eXtensible Interface) standards proposed by ARM are being promoted. There is an OCP (Open Core Protocol) standard. In these on-chip buses, the bit width and operating frequency of the bus are determined by the SoC designer according to the number of SoC data transfer requests and the maximum frequency at which each module can operate. An example in which a bus configuration having a wide bit width such as 128 bits is adopted is increasing.

  When an SDRAM is connected outside the SoC, the bit width of the connection data tends to increase according to the wide bit width bus configuration, and the number of SDRAM elements activated by one data access Tend to increase. For example, a single inline memory module (SIMM), a dual inline memory module (DIMM), and the like are obtained by collecting a plurality of SDRAM elements on a single substrate in order to access data having a wide bit width.

FIG. 12 is a block diagram illustrating an example of an electrical configuration of a main part of the DIMM.
In this DIMM 14, SDRAMs 15 ₀ , 15 ₁ ,..., 15 ₇ , 16 are mounted on the same substrate as shown in FIG. The SDRAMs 15 ₀ , 15 ₁ ,..., 15 ₇ each have 8-bit data input / output buses # D0, # D1,..., # D7, and the data input / output buses # D0, # D1,. , Corresponding data lines ([0: 7], [8:15], [16:23], [24:31], [32: in 64 bits ([0:63]) constituting the data line 17). 39], [40:47], [48:55]). The SDRAM 16 has an 8-bit data input / output bus #ECC (Error Correcting Code), and the data input / output bus #ECC is connected to the ECC line 18 ([0: 7]). The control signal line group 19 is connected to the SDRAMs 15 ₀ , 15 ₁ ,..., 15 ₇ , 16 and receives control signals such as a clock, a command, and an address from a processor (not shown).

  On the other hand, in information equipment, low power consumption is an essential issue from the viewpoint of reducing the amount of heat generation, extending the battery driving time, and adapting to global environmental problems. The SDRAM has power saving modes such as a power-down mode and a self-refresh mode in order to save power consumption during standby when no access is being performed, and is switched to the power saving mode or the active mode during normal access. It has become. In the power saving mode, the current consumption is reduced to about 1/2 to 1/5 that of the active mode. However, when switching from the power saving mode to the normal mode, an overhead of several cycles to several tens of cycles occurs, resulting in performance degradation. During that period, power equivalent to the normal mode is consumed, so switching from the power saving state It is more efficient to reduce the number of times as much as possible. From this point of view, if the data bus is widened and a large number of SDRAMs are accessed simultaneously, the power efficiency will decrease.

When accessing an amount of data that exceeds or exceeds the burst access unit of the SDRAM, simultaneously activating a plurality of SDRAMs in parallel, such as SIMM and DIMM, improves the data transfer efficiency. In SDRAM, burst transfer of data is performed about 4 to 16 times continuously for one read command or write command. On the other hand, there may be a state where a single data read / write is necessary depending on the processing contents of the active module. In this case, in the case of a single read, processing is performed by discarding the remaining data. In the case of a single write, other data in the burst cycle is masked. Processing is performed. In this case, for example, as shown in FIG. 13, when only the write data W3 is written to the SDRAM, the write mask signal and the ECC are used except in the second half of the cycle T5 in which the data W3 is written. The mask signal is enabled, and the data W1 to W2 and the data W4 to W8 and the corresponding ECC signal are not written to the SDRAM element. In order to reduce useless transfer cycles, burst access may be interrupted when access to necessary data is completed.
JP 2008-33431 A (Abstract, FIG. 2) J. Miyakoshi, Y. Murachi, T. Ishihara, H. Kawaguchi, and M. Yoshimoto, "A Power-and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal / Vertical Accessibility for Super-Parallel Video Processing," IEICE Trans.Electronics, Vol.E89-C, No.11, pp.1629-1636, Nov.2006

However, the above techniques including the above documents have the following problems.
That is, in the SIMM and the DIMM of FIG. 12, even when single data read transfer or write transfer as shown in FIG. 13 is performed, it is necessary to make all SDRAMs on the SIMM or DIMM active and perform further access. Therefore, there is a problem that almost the same power as that of normal burst transfer is consumed. In the SRAM module of the image processing memory described in Patent Document 1, data can be rearranged. In the SRAM, an arbitrary row can be selected for each of a plurality of memory cell groups. However, there are many column lines and logic gates, and the hardware scale is excessive.

  The present invention has been made in view of the above-described circumstances, and includes a memory module in which memory cells are arranged in a matrix and efficiently used with low power consumption, a control method used for the memory module, and an electronic device The object is to provide a device.

  In order to solve the above-described problem, the first configuration of the present invention is based on a memory cell group in which memory cells are arranged in a matrix of predetermined rows and columns, and based on an input row address. A row address decoder for deciding a row of memory cells to be accessed from the group and activating a word line of the memory cell, the memory cell having the word line activated by the row address decoder According to a memory module for writing or reading data, when a normal access mode is set, the word line of the memory cell is activated for each row, while when a sort access mode is set, a certain number The memory cell corresponding to a row of one row is a unit block, and the row of the word line to be activated is a fixed column within the range of the one unit block. Word line extension means for changing for each serial memory cell is characterized by being provided.

  According to a second configuration of the present invention, a memory cell group in which memory cells are arranged in a matrix of a predetermined row and a predetermined column, and a memory cell accessed from the memory cell group based on an input row address And a row address decoder that activates the word line of the memory cell by determining the row of the memory cell, and writes or reads data to or from the memory cell in which the word line is activated by the row address decoder According to the control method used for the module, when the normal access mode is set, the word line of the memory cell is activated for each row, while when the sort access mode is set, the word line is set to a certain number of rows. The corresponding memory cell forms one unit block, and the row of the word line to be activated is within the range of the one unit block. It is characterized by performing a word line extended process of changing every Riseru.

  According to the configuration of the present invention, when the rearrangement access mode is set, the memory cells corresponding to a certain number of rows form one unit block, and the word line row to be activated is within the range of the one unit block. By changing every memory cell in a certain column, a specific memory cell is accessed across multiple rows in a single access, so the data can be rearranged without increasing the processing cycle due to the rearrangement of data. Transfer is possible, and overhead of processing time can be reduced.

  When the normal access mode is set, the word line of the memory cell is activated for each row, while when the sort access mode is set, the memory cell corresponding to a certain number of rows is made into one unit block and activated. Word line expansion for accessing a specific memory cell across multiple rows in a single access by changing the row of the word line for each memory cell in a certain column within the range of the unit block A memory module is provided in which means are provided.

  Also, in the present invention, the word line extension means sets the row of the word line to be activated for each memory cell in a certain column within the range of the one unit block when the rearrangement access mode is set. In addition to a line feed, when the access reaches the rear end row in the one unit block, the access is continued from the front end row of the next column after the end end row is reached.

  In the present invention, the word line extension means connects the word lines of the memory cells for each row when the input mode selection signal indicates the normal access mode, while the mode selection signal When indicating the rearrangement access mode, the word line row is broken for each fixed column within the range of the unit block, and the last column of each fixed column other than the rear end column in the unit block is displayed. Word line connecting means for connecting from the rear end row to the front end row of the next column after the last column.

  According to the present invention, the row address decoder outputs a first word line activation signal based on the input row address when the input mode selection signal indicates the normal access mode. When the mode selection signal indicates the rearrangement access mode, the second word line activation signal is output based on the row address, and the word line extension means activates the first word line activation. While supplying a signal to the word line of the memory cell for each row, the second word line activation signal is broken into lines for each fixed column within the range of the one unit block. The word line of the memory cell in the leading row of the next column after the last column from the last row of the fixed column other than the trailing column in the one unit block is supplied to the word line Having an activation signal supplying means for supplying.

  Further, according to the present invention, a memory cell group in which memory cells are arranged in a matrix of a predetermined row and a predetermined column, and a row of the memory cell to be accessed from the memory cell group based on an input row address. And a row address decoder that activates a word line of the memory cell to determine and relates to a memory module that writes or reads data to or from the memory cell in which the word line is activated by the row address decoder The row address decoder includes a first decoder that outputs a first word line activation signal based on a first row address corresponding to the normal access mode, and a second row corresponding to the rearranged access mode. And a second decoder for outputting a second word line activation signal based on an address, the first word line activation signal While supplying the word line of the memory cell for each row to the word line of the memory cell, the second word line activation signal is broken into lines every predetermined column within the range of the unit block, and the word line of the corresponding memory cell To the word line of the memory cell in the leading row of the next column after the last column from the trailing row of the last column of each fixed column other than the trailing column in the one unit block. A signal supply means is provided.

  In the present invention, the first write / read for writing / reading data to / from the memory cell in which the word line is activated based on the first write / read selection signal corresponding to the normal access mode. Based on the read means and the second write / read selection signal corresponding to the rearranged access mode, the second write / read is performed to write / read data to / from the memory cell in which the word line is activated. Means.

FIG. 1 is a circuit diagram showing an electrical configuration of a main part of a memory module according to a first embodiment of the present invention.
As shown in the figure, the memory module in this example is an SRAM module 21, and includes a memory cell 22, an address decoder 23, a word line 24, a read / write line 25, a read data buffer 26, and data reading. A line 27, a write data buffer 28, a data write line 29, a selection signal line 30, and a word line selector 31 are included. The memory cells 22 are arranged in a matrix of, for example, 2048 rows (Rows) and 8 columns (Columns) to form a memory cell group, and each memory cell 22 has a storage capacity of, for example, 8 bits (bits). . As a result, the SRAM module 21 has a storage capacity of 64 bits * 2048 words.

  The read / write line 25 is connected in common to the read / write selection port of each memory cell 22, the enable terminal of each read data buffer 26, and the enable terminal of each write data buffer 28, and receives a read / write selection signal RW. Each read data buffer 26 is provided for each column (Column 0, 1,..., 7) of the memory cells 22 and is connected in common to the read port of the memory cell 22 for each column via each data read line 27. Has been. When the read / write selection signal RW is in the read mode, each read data buffer 26 reads data from the memory cell 22 for each column via each data read line 27 and outputs it as output data in the data input / output signal D. To do. Each write data buffer 28 is provided for each column (Column 0, 1,..., 7) of the memory cell 22, and is connected in common to the write port of the memory cell 22 for each column via each data write line 29. Has been. Each write data buffer 28 writes the input data in the data input / output signal D to the memory cells 22 for each column via the data write lines 29 when the read / write selection signal RW is in the write mode.

  When the access valid signal AS is in the active mode, the address decoder 23 determines a row of memory cells to be accessed from the memory cell group based on the input address input signal AD (row address), and the memory cell The word line is activated. In particular, in this embodiment, each word line 24 is connected to each output side of the address decoder 23, and the selection signal line 30 is connected in common to the selection input terminal of each word line selector 31, so that the normal access mode or the array is arranged. A mode selection signal MS for setting a replacement access mode is input. When the normal access mode is set by the mode selection signal MS, the word line of the memory cell 22 is activated for each row, while when the reordering access mode is set, a certain number of rows (for example, 8 The memory cell 22 corresponding to a row) is set as one unit block, and the row of the activated word line is changed for each memory cell 22 in a certain column (for example, one column) within the range of this one unit block (line feed). As a result, a specific memory cell 22 is accessed across a plurality of rows (eight rows) by one access.

  When the access reaches the rear end row in one unit block, the access is continued from the front end row of the column next to the column when the rear end row is reached. In this case, each word line selector 31 connects the word lines of the memory cells 22 for each row when the mode selection signal MS indicates the normal access mode, while when the mode selection signal MS indicates the rearranged access mode, The line row is broken for each fixed column (1 column) within the range of one unit block, and the last row (Row 7) of the last column of each fixed column other than the rear column (Column 7) in one unit block To the top row (Row 0) of the next column of the last column.

FIG. 2 is a block diagram showing an electrical configuration of a main part of a SoC (System on Chip) in which the SRAM module 21 of FIG. 1 is used as a system cache.
In this SoC 41, as shown in FIG. 2, a processor core 43, a dedicated active module 44 such as a hardware accelerator, and an LCD (Liquid Crystal Display) display control module 45 are connected to the system bus 42 as active modules. ing. In addition, a dedicated passive module 46, an on-chip memory 47, a system cache 48, and a memory controller 49 are connected to the system bus 42 as passive modules. An LCD panel 50 is connected to the LCD display control module 45 outside, and an external main memory 51 is connected to the memory controller 49 via a memory bus 52. The SRAM module 21 shown in FIG. 1 is provided in the system cache 48.

FIG. 3 is a block diagram showing an electrical configuration of a main part of the system cache 48 in FIG.
As shown in FIG. 3, the system cache 48 includes a cache data memory 61, a cache tag memory 62, a data selector / multiplexer 63, and a system bus interface 64 with a system cache controller 60 as a center. Yes. The cache data memory 61 includes the SRAM module 21 of FIG. 1 and is connected to the memory controller 49 in FIG. 2 via the data selector / multiplexer 63 and holds a copy of a part of the data in the external main memory 51. The data of the data input / output signal D is exchanged with the external main memory 51. The cache data memory 61 is connected to the system bus 42 in FIG. 2 via the data selector / multiplexer 63 and the system bus interface 64, and exchanges data of the data input / output signal D with each part of the SoC 41.

  The system cache controller 60 exchanges the control signal CTa with the system bus interface 64 and exchanges the control signal CTb with the data selector / multiplexer 63, thereby giving a mode selection signal MS to the cache data memory 61 to perform normal access. In addition to setting the mode or rearrangement access mode, a read / write selection signal RW, an access valid signal AS, and an address input signal AD are input. Further, the system cache controller 60 gives a read / write selection signal RWT and an address input signal ADT to the cache tag memory 62 and exchanges tag data TD. The cache tag memory 62 holds, as tag data TD, information for the system cache controller 60 to determine a cache hit / miss. The information includes the address of data cached in the cache data memory 61 and the validity of access. / Invalid distinction etc.

FIG. 4 is a diagram showing an arrangement order of data when burst transfer of data is performed between the external main memory 51 and the system cache 48.
The processing contents of the control method used for the memory module (SRAM module 21) of this example will be described with reference to this figure.
In the SRAM module 21, when the normal access mode is set, the word line of the memory cell 22 is activated for each row. On the other hand, when the rearrangement access mode is set, the SRAM module 21 has a certain number of rows (eight rows). The corresponding memory cell 22 is set as one unit block, and the row of the word line to be activated is changed (new line) for each memory cell 22 in a certain column (one column) within the range of the one unit block. In this access, a specific memory cell 22 is accessed across a plurality of rows (word line expansion processing).

  When performing burst transfer of data between the external main memory 51 and the system cache 48, as shown in FIG. 4, 8-word burst data of 1 word is transferred as shown in FIG. 64-bit data composed of “0x0”, “0x9”, “0x12”, “0x1b”, “0x24”, “0x2d”, “0x36”, “0x3f” is transferred. Further, in the second transfer, data including addresses “0x1”, “0xa”, “0x13”, “0x1c”, “0x25”, “0x2e”, “0x37”, “0x38” is continued, and the last In the eighth time, data composed of addresses “0x7”, “0x8”, “0x11”, “0x1a”, “0x23”, “0x2c”, “0x35”, “0x3e” is transferred.

Hereinafter, the operation of the SRAM module 21 in such burst transfer will be described in time series.
First, when data is read from the external main memory 51 and written to the portions corresponding to Rows 0 to 7 of the SRAM module 21, burst transfer is performed from the external main memory 51 via the memory bus 52. In the first time, 64-bit data composed of addresses “0x0”, “0x9”, “0x12”, “0x1b”, “0x24”, “0x2d”, “0x36”, “0x3f” arrives. At this time, the cache data includes the address “0” as the address input signal AD, the information “reordering access mode” as the mode selection signal MS, and the information “write” as the read / write selection signal RW. The data is sent to the memory 61 (that is, the SRAM module 21).

  In the cache data memory 61 (SRAM module 21), the address decoder 23 activates the word line 24 corresponding to Row0 and enters the rearrangement mode. At this time, since the word line selector 31 selects a word line in the shift direction, the activated memory cells 22 are [Row 0, Column 0], [Row 1, Column 1], [Row 2, Column 2], [Row 3], respectively. , Column3], [Row4, Column4], [Row5, Column5], [Row6, Column6], and [Row7, Column7], the data read from the external main memory 51 is written into the corresponding memory cell 22.

  In the next cycle, the address becomes “1”, and the word line 24 corresponding to Row 1 is activated. Subsequently, since the mode is the rearrangement mode, the activated memory cells 22 are [Row1, Column0], [Row2, Column1], [Row3, Column2], [Row4, Column3], [Row5, Column4, respectively. ], [Row 6, Column 5], [Row 7, Column 6] and [Row 0, Column 7]. Here, since the rearrangement mode of the SRAM module 21 is one unit every 8 rows, when the row reaches “7” in the rearrangement mode, the row returns to “0” in the next column. By repeating these operations eight times, all the data shown in FIG. 4 is written into the memory cell 22 at the corresponding position in the cache data memory 61. After the data is written in the cache data memory 61, when the active module in the SoC 41 accesses the cache data memory 61, the mode selection signal MS becomes the “normal access mode” and the word line selector 31 sets the normal word line. Is selected. As a result, data can be accessed in the same way as a normal cache memory, and data rearrangement is realized only by the system cache 48.

  On the other hand, when the portions corresponding to Rows 0 to 7 of the SRAM module 21 are written back to the external main memory 51, data is expelled from the system cache 48, so that the data is read from the cache data memory 61 and the external main memory 61 Forwarded to At this time, from the system cache controller 60, information “0” as the address input signal AD, “reorder access mode” as the mode selection signal MS, and “read” as the read / write selection signal RW are stored in the cache data memory 61. (SRAM module 21). At this time, since the word line selector 31 selects a word line in the shift direction, the activated memory cells 22 are [Row 0, Column 0], [Row 1, Column 1], [Row 2, Column 2], [Row 3], respectively. , Column3], [Row4, Column4], [Row5, Column5], [Row6, Column6], [Row7, Column7]. Therefore, the data obtained from this is byte data located at addresses “0x0”, “0x9”, “0x12”, “0x1b”, “0x24”, “0x2d”, “0x36”, “0x3f”. The data is written back to the external main memory 51.

  In the next cycle, the address is “1”, and [Row1, Column0], [Row2, Column1], [Row3, Column2], [Row4, Column3], [Row5, Column4], [Row6, Column5], [Row The word lines of the memory cells 22 corresponding to [Row 7, Column 6], [Row 0, Column 7] are activated. Here, since the rearrangement mode of the SRAM module 21 is one unit every 8 Rows, when the Row reaches “7” in the rearrangement mode as in the case of writing, the Row is set to “ Return to 0 ”. The data obtained from this is byte data located at addresses “0x1”, “0xa”, “0x13”, “0x1c”, “0x25”, “0x2e”, “0x37”, “0x38”, and these are external main data. It is written back to the storage memory 51.

  By repeating these operations eight times, writing to the external main memory 51 is performed in the permutation of all the data shown in FIG. In the case of writing to the external main memory 51, only the operation of writing from the cache data memory 61 is performed, and the data from the active module is not directly written back, so that the processing cycle due to data rearrangement does not increase. Reordering and transfer are performed, and processing time overhead is reduced.

  As described above, in the first embodiment, when the rearrangement access mode is set, the memory cell 22 corresponding to a certain number of rows (eight rows) constitutes one unit block, and the row of the word line to be activated However, since a line feed is made for each memory cell 22 in a certain column (one column) within the same unit block, a specific memory cell 22 is accessed across a plurality of rows in one access. Data can be rearranged and transferred without an increase in processing cycles due to data rearrangement, and processing time overhead is reduced.

FIG. 5 is a circuit diagram showing the electrical configuration of the main part of the memory module according to the second embodiment of the present invention, and is common to the elements common to those in FIG. 1 showing the first embodiment. The code | symbol is attached | subjected.
As shown in FIG. 5, the memory module in this example is an SRAM module 21A, which replaces the address decoder 23, word line 24 and word line selector 31 in FIG. 1 with an address decoder 23D and word lines 24A and 24B. And an OR circuit 32 is provided. When the mode selection signal MS indicates “normal access mode”, the address decoder 23D outputs a word line activation signal wa (first word line activation signal) based on the address input signal AD (ie, active). On the other hand, when the mode selection signal MS indicates the “reordering access mode”, the word line activation signal wb (second word line activation signal) is output based on the address input signal AD (that is, a second word line activation signal). Active mode).

  The word line 24A supplies the word line activation signal wa output from the address decoder 23D to the word line of the memory cell 22 for each row via each OR circuit 32. The word line 24B converts the word line activation signal wb output from the address decoder 23D into a line for each predetermined column (for example, one column) within the range of one unit block, and passes through the corresponding OR circuit 32 to the memory cell. And supplied to the word line of the memory cell 22 in the leading row of the next column after the last column from the last row of each fixed column other than the trailing column in one unit block. To do. The other configuration is the same as that shown in FIG.

  In the SRAM module 21A, when the mode selection signal MS indicates “normal access mode”, the word line activation signal wa output from the address decoder 23D is stored in the memory for each row via the word line 24A and each OR circuit 32. It is supplied to the word line of the cell 22. On the other hand, when the mode selection signal MS indicates “reordering access mode”, the word line activation signal wb output from the address decoder 23D is within the range of one unit block via the word line 24B and each OR circuit 32. The line is broken for each fixed column (one column) and supplied to the word line of the corresponding memory cell 22, and the final row is started from the rear end row of each fixed column other than the rear end column in one unit block. This is supplied to the word line of the memory cell 22 in the leading row of the next column.

  As described above, in the second embodiment, the SRAM module 21A having a hardware configuration different from that of the SRAM module 21 of the first embodiment has the same advantages as the first embodiment.

FIG. 6 is a circuit diagram showing the electrical configuration of the main part of the memory module according to the third embodiment of the present invention. Elements common to the elements in FIG. 1 showing the first embodiment are common. The code | symbol is attached | subjected.
As shown in FIG. 6, the memory module in this example is an SRAM module 21B, and includes the address decoder 23, word line 24, read / write line 25, read data buffer 26, data read line 27, write in FIG. Instead of the data buffer 28 and the data write line 29, address decoders 23A and 23B, word lines 24C and 24D, read / write lines 25A and 25B, read data buffers 26A and 26B, data read lines 27A and 27B, a write data buffer 28A and 28B and data write lines 29A and 29B are provided, and the selection signal line 30 and the word line selector 31 are omitted.

  When the access valid signal ASA is in the active mode, the address decoder 23A uses the word line activation signal wc (first word line activation signal) based on the address input signal ADA (first address input signal) corresponding to the normal access mode. Output). When the access valid signal ASB is in the active mode, the address decoder 23B generates a word line activation signal wd (second word line) based on the address input signal ADB (second address input signal) corresponding to the rearranged access mode. Activation signal). The word line 24C supplies the word line activation signal wc to the word line of the memory cell 22 for each row. The word line 24D supplies the word line activation signal wd to the word line of the corresponding memory cell 22 by making a line feed every predetermined column (for example, one column) within the range of one unit block. The data is supplied from the last row of the last column of each fixed column other than the last column to the word line of the memory cell 22 in the leading row of the next column after the last column.

  The read / write line 25A is commonly connected to the read / write selection port of each memory cell 22, the enable terminal of each read data buffer 26A, and the enable terminal of each write data buffer 28A, and a read / write selection signal RWA (first write). / Reading selection signal) is input. The read / write line 25B is connected in common to the read / write selection port of each memory cell 22, the enable terminal of each read data buffer 26B, and the enable terminal of each write data buffer 28B, and a read / write selection signal RWB (second write). / Reading selection signal) is input. Each read data buffer 26A is provided for each column (Column 0, 1,..., 7) of the memory cells 22, and is commonly connected to the read port of the memory cell 22 for each column via each data read line 27A. Has been. When the read / write selection signal RWA is in the read mode, each read data buffer 26A reads data from the memory cell 22 for each column via each data read line 27A and outputs it as output data in the data input / output signal DA. To do.

  Each read data buffer 26B is provided for each column (Column 0, 1,..., 7) of the memory cells 22, and is commonly connected to the read port of the memory cell 22 for each column via each data read line 27B. Has been. When the read / write selection signal RWB is in the read mode, each read data buffer 26B reads data from the memory cell 22 for each column via each data read line 27B and outputs it as output data in the data input / output signal DB. To do. Each write data buffer 28A is provided for each column (Column 0, 1,..., 7) of the memory cell 22, and is commonly connected to the write port of the memory cell 22 for each column via each data write line 29A. Has been. When the read / write selection signal RWA is in the write mode, each write data buffer 28A writes the input data in the data input / output signal DA to the memory cell 22 for each column via each data write line 29A. The write data buffer 28B is provided for each column (Column 0, 1,..., 7) of the memory cells 22, and is commonly connected to the write port of the memory cell 22 for each column via each data write line 29B. ing. Each write data buffer 28B writes the input data in the data input / output signal DB to the memory cell 22 for each column via each data write line 29B when the read / write selection signal RWB is in the write mode.

  As described above, the SRAM module 21B is configured as a two-port memory, and the connection on the system bus 42 side in FIG. 2 and the connection with the external main memory 51 are each performed by one port. One port A is connected to the system bus 42 for normal access, and the other port B is connected to the external main memory 51 for rearrangement access.

FIG. 7 is a block diagram showing an electrical configuration of a main part of a system cache in which the SRAM module 21B of FIG. 6 is used as a cache data memory, and is common to the elements in FIG. 3 showing the first embodiment. Elements are given common symbols.
The system cache 48A is provided in place of the system cache 48 shown in FIG. 2 showing the first embodiment. As shown in FIG. 7, the system cache controller 60 and the cache data memory 61 shown in FIG. Instead, a system cache controller 60A and a cache data memory 61A having different functions are provided, and the data selector / multiplexer 63 is deleted. Further, in this embodiment, a memory controller 49A having a different configuration is provided in place of the memory controller 49 in the SoC of FIG. The cache data memory 61A is composed of the SRAM module 21B of FIG. 6, and is connected to the memory controller 49A to hold a copy of a part of the data in the external main memory 51, and so on. Data of the signal DB is exchanged. The cache data memory 61A is connected to the system bus 42 in FIG. 2 via the system bus interface 64, and exchanges data of the data input / output signal DA with each part of the SoC 41.

  The system cache controller 60A exchanges the control signal CTa with the system bus interface 64 and also exchanges the control signal CTb with the memory controller 49A, whereby the read / write selection signal RWA and the read / write selection signal RWB are sent to the cache data memory 61A. The access valid signal ASA and the access valid signal ASB, and the address input signal ADA and the address input signal ADB are input simultaneously. Further, the system cache controller 60 gives a read / write selection signal RWT and an address input signal ADT to the cache tag memory 62 and exchanges tag data TD.

FIG. 8 is a time chart for explaining the operation of the 1-port memory and the 2-port memory, and FIG. 9 is a time chart showing the cache operation of the SRAM module 21B of FIG.
The processing contents of the control method used for the memory module (SRAM module 21B) of this example will be described with reference to these drawings.
In the SRAM module 21B, the address decoder 23A outputs the word line activation signal wc based on the address input signal ADA corresponding to the normal access mode, and the address decoder 23B outputs an address corresponding to the rearranged access mode. A word line activation signal wd is output based on the input signal ADB. The word line activation signal wc is supplied to the word line of the memory cell 22 for each row, while the word line activation signal wd is broken for every predetermined column (for example, one column) within the range of one unit block. Are supplied to the word line of the corresponding memory cell 22 and from the last row of the last column of each of the fixed columns other than the rear row of the one unit block to the leading row of the next column of the last column. It is supplied to the word line of the memory cell 22 (activation signal supply process).

  That is, since the SRAM module 21B has a 2-port memory configuration, the circuit scale is larger than that of the 1-port memory. However, access from the active module to the system cache 48A and access from the external main storage memory 51 are different. As long as the same memory cell 22 is not accessed (that is, access contention does not occur), data can be written back to the main memory 51 due to a cache miss, or from the main memory 51 Writing read data and accessing an active module due to a cache hit can be performed simultaneously, and a reduction in data transfer capacity (throughput) due to data rearrangement when successive cache misses are prevented is prevented.

  For example, as shown in FIG. 8, when reading out burst data [1] and burst data [2] from the external main memory 51, the 1-port SRAM module has a burst as shown in FIG. 8 (a). After writing to the cache memory in the main memory storage array of data [1], it is necessary to go through the steps of reading out in the normal array, writing to the cache memory in the main memory storage array of burst data [2], and reading out in the normal array. There is. On the other hand, in the 2-port SRAM module, as shown in FIG. 8B, the burst data [1] is read in the normal array and the burst data [2] is written in the cache memory in the main memory storage array. Can be executed simultaneously, and the processing time can be shortened. The same operation as described above is possible by dividing the 1-port SRAM module into a plurality of banks and distributing the data to different banks.

  Although the burst data transfer has been described above, the overall power consumption of the SoC provided with the SRAM module 21B is reduced when the single main data is read from or written to the external main memory 51. Of the SDRAM elements constituting the above, those to be activated are limited, and the others are realized by maintaining the low power consumption mode. For this reason, at the time of reading, it arrives as a single data, not as burst data that fills all the cache lines. For example, the data of the address “0x18” in FIG. 4 is transferred over 8 cycles in the area [24:31] of the memory bus 52. At that time, another area, that is, the area [0:23, 32: 63], no valid data is transferred. Therefore, as in this embodiment, when data is rearranged in the system cache 48A, the cache line in which only a part of the data is written is not made effective and needs to be used only for transferring the single data. .

  FIG. 9A shows the cache operation of the SRAM module 21B when there is a data read request twice from the active module with the same burst data (burst data [1]). Further, in FIG. 9B, the cache operation of the SRAM module 21B when there is a single data read request from the active module for the first time and a read request for burst data including the first single data for the second time. It is shown.

  That is, in FIG. 9A, the cache miss data is fetched from the external main memory 51 to the system cache 48A at the time t0, and the cache line storing this data is valid at the time t1 when the fetching is completed. It becomes. Therefore, when burst data is read again at time t2, a cache hit occurs, and this transfer is completed at time t3. This is the same even if the second reading is single data. On the other hand, in FIG. 9B, data reading from time t0 is single data, but only a part of the memory bus 52 is used, so the transfer time is as shown in FIG. Similarly, it takes until time t1. However, since only a part of the data is taken into the cache memory at the time t1, the cache line remains invalid. Therefore, if a read request is made with burst data including single data for the first time until time t2, a cache miss occurs, and from time t2, the cache miss data is transferred from the external main memory 51 to the system cache 48A. It is captured. In this case, since all data is captured, the cache line is validated at time t3.

  For these reasons, it is advantageous to read all burst data for data that is likely to be read again, even when the first access is a single data read. On the other hand, when writing single data from the active module, by writing back only necessary data to the external main memory 51, the number of SDRAM elements activated in the external main memory 51 is efficiently reduced. At this time, it is necessary to rearrange the data in the system cache 48A while keeping the cache line invalid.

  As described above, in the third embodiment, the word line activation signal wc is supplied to the word line of the memory cell 22 for each row, while the word line activation signal wd is constant within the range of one unit block. Each line (for example, one column) is broken and supplied to the word line of the corresponding memory cell 22, and from the rear row of the last column of each fixed column other than the rear column in the one unit block, Since it is supplied to the word line of the memory cell 22 in the leading row of the next column of the last column, it is possible to simultaneously access the system cache 48A from the active module and access from the external main memory 51. Become. As a result, for example, when accessing the external main memory 51 for exchanging single data, the data can be rearranged so that it is not necessary to activate all SDRAM elements on the SIMM / DIMM. Thus, it is possible to achieve both low power consumption and low hardware scale without providing a hardware buffer for rearranging the data array of the system bus 42.

The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to the embodiment, and even if there is a design change without departing from the gist of the present invention, Included in the invention.
For example, in each of the above embodiments, the line of the word line to be activated is broken for each memory cell 22 in one column within the range of one unit block. A line feed may be made for each memory cell 22 in the column.

  The present invention can be applied to all memory modules in which memory cells are arranged in a matrix.

1 is a circuit diagram showing an electrical configuration of a main part of a memory module according to a first embodiment of the present invention. It is a block diagram which shows the electric constitution of the principal part of SoC in which the SRAM module 21 of FIG. 1 is used as a system cache. FIG. 3 is a block diagram showing an electrical configuration of a main part of the system cache 48 in FIG. 2. It is a figure which shows the arrangement sequence of the data at the time of performing burst transfer of data between the external main memory 51 and the system cache 48. FIG. It is a circuit diagram which shows the electrical constitution of the principal part of the memory module which is 2nd Example of this invention. It is a circuit diagram which shows the electrical constitution of the principal part of the memory module which is the 3rd Example of this invention. It is a block diagram which shows the electric constitution of the principal part of the system cache in which the SRAM module 21B of FIG. 6 is used as a cache data memory. It is a time chart explaining operation | movement of 1 port memory and 2 port memory. 7 is a time chart showing the cache operation of the SRAM module 21B of FIG. 2 is a configuration diagram of an image processing memory described in Patent Literature 1. FIG. It is a figure which shows the internal structure of the memory array 1 in FIG. It is a block diagram which shows an example of the electrical constitution of the principal part of DIMM. 13 is a time chart for explaining the operation of the DIMM of FIG.

Explanation of symbols

21, 21A, 21B SRAM module (memory module)
22 Memory cells (part of memory cells)
23,23D address decoder (row address decoder, part of memory module)
23A, 23B Address decoder (decoder, part of memory module)
24, 24A, 24B Word line (part of word line expansion means)
24C, 24D word line (activation signal supply means)
25, 25A, 25B Read / write line (part of memory module)
26, 26A, 26B Read data buffer (part of memory module, part of write / read means)
27, 27A, 27B Data read line (part of memory module)
28, 28A, 28B Write data buffer (part of memory module, part of write / read means)
29, 29A, 29B Data write line (part of memory module)
30 selection signal line (part of word line expansion means)
31 Word line selector (part of word line expansion means, word line connection means)
32 OR circuit (part of word line expansion means, activation signal supply means)
41 SoC (electronic equipment)
42 System bus (part of electronic device)
43 Processor core (part of electronic device)
44 Dedicated active module (part of electronic device)
45 LCD (Liquid Crystal Display) display control module (part of electronic device)
46 Dedicated passive module (part of electronic device)
47 On-chip memory (part of electronic device)
48 System cache (part of electronic device)
49 Memory controller (part of electronic device)
60 System cache controller (part of electronic device, control means)
61 Cache data memory (part of electronic device)
62 Cash tag memory (part of electronic device)
63 Data selector / multiplexer (part of electronic device)
64 System bus interface (part of electronic device)

Claims (12)

A group of memory cells in which memory cells are arranged in a matrix of predetermined rows and columns;
A row address decoder for determining a row of a memory cell to be accessed from the memory cell group based on an input row address and activating a word line of the memory cell;
A memory module for writing or reading data to a memory cell in which the word line is activated by the row address decoder,
When the normal access mode is set, the word line of the memory cell is activated for each row, while when the sort access mode is set, one unit block is set in the memory cell corresponding to a certain number of rows. And a word line extending means for changing the row of the word line to be activated for each of the memory cells in a fixed column within the range of the one unit block. A group of memory cells in which memory cells having a predetermined storage capacity are arranged in a matrix of predetermined rows and columns;
A row address decoder for determining a row of a memory cell to be accessed from the memory cell group based on an input row address and activating a word line of the memory cell;
A memory module for writing or reading data to a memory cell in which the word line is activated by the row address decoder,
When the normal access mode is set, the word line of the memory cell is activated for each row, while when the sort access mode is set, one unit block is set in the memory cell corresponding to a certain number of rows. By changing the row of the word line to be activated for each of the memory cells in a certain column within the range of the one unit block, a specific memory cell is extended over a plurality of rows by one access. A memory module comprising word line expansion means for accessing. The word line extension means includes:
When the reordering access mode is set, the row of the word line to be activated is changed for each of the memory cells in a certain column within the range of the unit block, and the access is performed later in the unit block. 3. The memory module according to claim 2, wherein when the end row is reached, the access is continued from the leading row of the next column after the end row is reached. The word line extension means includes:
When the input mode selection signal indicates the normal access mode, the word lines of the memory cells are connected to each row, while when the mode selection signal indicates the rearrangement access mode, the word line row In each unit column within the range of the unit block, and from the last row of the last column in each unit column other than the end column in the unit block, 4. The memory module according to claim 3, further comprising word line coupling means coupled to the leading row. The row address decoder
When the input mode selection signal indicates the normal access mode, the first word line activation signal is output based on the input row address, while the mode selection signal indicates the rearrangement access mode The second word line activation signal is output based on the row address.
The word line extension means includes:
The first word line activation signal is supplied to the word line of the memory cell for each row, while the second word line activation signal is fed to a predetermined line within a unit block. To the word line of the corresponding memory cell, and from the rear end row of the fixed column other than the rear end column in the unit block, 4. The memory module according to claim 3, further comprising an activation signal supply means for supplying the word line of the memory cell. A group of memory cells in which memory cells are arranged in a matrix of predetermined rows and columns;
A row address decoder for determining a row of a memory cell to be accessed from the memory cell group based on an input row address and activating a word line of the memory cell;
A memory module for writing or reading data to a memory cell in which the word line is activated by the row address decoder,
The row address decoder
A first decoder for outputting a first word line activation signal based on a first row address corresponding to the normal access mode;
A second decoder for outputting a second word line activation signal based on a second row address corresponding to the rearrangement access mode;
The first word line activation signal is supplied to the word line of the memory cell for each row, while the second word line activation signal is fed to a predetermined line within a unit block. To the word line of the corresponding memory cell, and from the rear end row of the fixed column other than the rear end column in the unit block, An activation signal supply means for supplying the word line of the memory cell is provided. First write / read means for writing / reading data to / from a memory cell in which the word line is activated based on a first write / read selection signal corresponding to the normal access mode;
Second write / read means for writing / reading data to / from the memory cell in which the word line is activated based on a second write / read selection signal corresponding to the rearrangement access mode is provided. The memory module according to claim 6, wherein the memory module is provided. A group of memory cells in which memory cells are arranged in a matrix of predetermined rows and columns;
A row address decoder for determining a row of a memory cell to be accessed from the memory cell group based on an input row address and activating a word line of the memory cell;
A control method used in a memory module for writing or reading data to or from a memory cell in which the word line is activated by the row address decoder,
When the normal access mode is set, the word line of the memory cell is activated for each row, while when the sort access mode is set, one unit block is set in the memory cell corresponding to a certain number of rows. And a word line expansion process for changing the row of the word line to be activated for each of the memory cells in a certain column within the range of the one unit block. A group of memory cells in which memory cells having a predetermined storage capacity are arranged in a matrix of predetermined rows and columns;
A row address decoder for determining a row of a memory cell to be accessed from the memory cell group based on an input row address and activating a word line of the memory cell;
A control method used in a memory module for writing or reading data to or from a memory cell in which the word line is activated by the row address decoder,
When the normal access mode is set, the word line of the memory cell is activated for each row, while when the sort access mode is set, one unit block is set in the memory cell corresponding to a certain number of rows. By changing the row of the word line to be activated for each of the memory cells in a certain column within the range of the one unit block, a specific memory cell is extended over a plurality of rows by one access. A control method characterized by performing a word line expansion process to be accessed. A group of memory cells in which memory cells are arranged in a matrix of predetermined rows and columns;
A row address decoder for determining a row of a memory cell to be accessed from the memory cell group based on an input row address and activating a word line of the memory cell;
A control method used in a memory module for writing or reading data to or from a memory cell in which the word line is activated by the row address decoder,
The row address decoder includes a first decoder that outputs a first word line activation signal based on a first row address corresponding to the normal access mode, and a second row address corresponding to the rearranged access mode. And a second decoder that outputs a second word line activation signal,
The first word line activation signal is supplied to the word line of the memory cell for each row, while the second word line activation signal is fed to a predetermined line within a unit block. To the word line of the corresponding memory cell, and from the rear end row of the fixed column other than the rear end column in the unit block, An activation signal supply process for supplying to the word line of the memory cell is performed. A memory module according to any one of claims 1 to 5;
An electronic apparatus comprising: control means for inputting the row address to the memory module and setting the normal access mode or the rearranged access mode. A memory module according to any one of claims 6 to 7,
An electronic apparatus comprising: control means for inputting the first row address and the second row address to the memory module.

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