JP2010102582A - Information processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processor efficiently processing a plurality of data processed in parallel and written into a system memory without increasing a CPU load. <P>SOLUTION: The information processor 1 includes: a system control CPU 6 for generating a descriptor for use in information processing, and storing the generated descriptor in a system memory 2; a plurality of hardware logic processors 4 for processing unprocessed data retrieved based on the descriptor; and a reserved start-up controller 5. The reserved start-up controller 5 includes: a descriptor address storage 50 for setting therein first descriptor addresses of a plurality of descriptors 3 in association with a post-stage hardware logic processor 4b; and a hardware logic controller 51 for outputting, upon input of an end signal of a pre-stage hardware logic processor 4a, the corresponding descriptor address and a start signal to the post-stage hardware logic processor 4b. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention provides an information processing system including a plurality of hardware logic processing units that execute predetermined information processing on pre-processing data and write the post-processing data to a system memory based on a descriptor generated by a system control CPU. Relates to the device.

  2. Description of the Related Art Conventionally, there is an information processing IC that includes a plurality of hardware logic processing units made up of hardware modules and executes desired information processing by one or more of the plurality of hardware logic processing units. An information processing apparatus is configured by the information processing IC, a system control CPU that selects a hardware logic processing unit that executes desired information processing, and a system memory (for example, RAM) that serves as a work area.

  Patent Document 1 discloses an information processing circuit serving as such an information processing apparatus. The information processing circuit includes a system memory, first and second functional blocks that acquire data from the system memory, perform information processing based on the acquired data, and write output data to the system memory, and the system The area designation data for designating the input area and the output area on the memory is supplied to each functional block, the acquisition of the data from the input area of the area designation data to be supplied, and the writing of the data to the output area The function block is operated by causing each function block to operate, and the output area of the area specifying data supplied to the first function block is changed to the area specifying data supplied to the second function block. A control computer for the input area; and a control computer provided in the second functional block. Each time the processing of the second functional block relating to one area specifying data to be buffered is double buffered from the computer to the second functional block, the control is performed in advance. A double buffer circuit for starting execution of processing to be performed next by the second functional block based on the next area designation data acquired and buffered from the computer, and the first function block from the first functional block. A signal indicating the writing of the resultant output data to the system memory is acquired from the block and counted up, and from the second functional block to the second functional block, the second functional block. A countdown is performed by acquiring a signal indicating acquisition of the output data of one functional block. And an execution control for causing the second functional block to perform the processing based on the area designation data only while the count value of the counter circuit indicates that the count-up is at least once more than the count-down count. Circuit.

  Note that the first and second functional blocks of Patent Document 1 correspond to hardware logic processing units, and the control computer corresponds to a system control CPU.

In the information processing circuit disclosed in Patent Document 1, after the output data is written in the system memory by the first functional block, the processing of the output data is executed in the second functional block by the function of the counter circuit. Therefore, there is no problem (so-called overrun) that processing by the second functional block is started in a state where output data is not written.
JP 2008-112283 A

  The system memory has an area for storing pre-processing data before executing information processing in the hardware logic processing unit and post-processing data that is output data after executing information processing in the hardware logic processing unit. ing. Each hardware logic processing unit reads pre-processing data from the area specified by the descriptor generated by the system control CPU and written to the system memory, and writes the post-processing data to the area specified by the descriptor. It is configured.

  The operation of the plurality of hardware logic processing units when executing predetermined information processing in cooperation with the plurality of hardware logic processing units will be described below.

  FIG. 1 is a diagram showing a configuration of a descriptor. The descriptor includes a “read start address” that is the start address of the area in which the pre-process data is stored, a “write start address” that is the start address of the area in which the post-process data is stored, and a “data capacity before process”. The “next descriptor address” that is the start address of the area where the next descriptor is stored, the “IRQ bit” that sets whether or not to generate an interrupt at the end of writing of the processed data, and the processed data A “LINK bit” for setting whether to automatically start processing of pre-processing data corresponding to the next descriptor after writing is defined.

  FIG. 2A is a diagram illustrating an information processing apparatus including a plurality of hardware logic processing units. The information processing apparatus 9 includes a front-stage hardware logic processing unit 90, a reservation activation control unit 91, a rear-stage hardware logic processing unit 92, a system memory 93, and a system control CPU (not shown).

  When starting the information processing, the system control CPU generates descriptors for the hardware logic processing units 90 and 92 and stores them in the system memory 93.

  The hardware logic processing unit 90 in the previous stage reads the pre-processing data of “data size before processing” from the “reading start address” defined in the corresponding descriptor (not shown), executes the information processing, Based on the prescribed “write start address”, the post-process data is written in the areas (area 1, area 2, area 3). When writing of the processed data is completed, an end signal indicating that the information processing has been completed is output. The end signal is input to the reservation activation control unit 91.

  The reservation activation control unit 91 includes a counter circuit (not shown) disclosed in Patent Document 1. If the counter value of the counter circuit is “1” or more, an activation signal for instructing the start of information processing is input to the hardware logic processing unit 92 at the subsequent stage. The counter value of the counter circuit is incremented when an end signal is input from the preceding hardware logic processing unit 90, and is decremented when a processing start signal described later is input from the following hardware logic processing unit 92.

  The hardware logic processing unit 92 at the subsequent stage inputs a processing start signal to the reservation activation control unit 91 when starting the information processing, and the area (area 1) based on the “reading start address” defined in the corresponding descriptor 94. , Region 2, region 3), data before processing (post-processing data written by the hardware logic processing unit 90 in the previous stage) is read out, and the target is based on the “write start address” defined in the descriptor 94. The post-processing data is written in an area (not shown).

  Here, in the “LINK bit” of each descriptor, a bit indicating that processing of pre-processing data corresponding to the next descriptor is started is set. For example, when “1” is set in the bit, the preceding hardware logic processing unit 90 and the following hardware logic processing unit 92 perform post-processing data corresponding to the pre-processing data based on the corresponding descriptor. Is written in the specified area, and the information processing of the pre-processing data is started based on the descriptor next to the descriptor without obtaining a command from the system control CPU.

  For example, the hardware logic processing unit 92 in the subsequent stage writes the post-processing data corresponding to the pre-processing data written in the area 1 on the basis of the descriptor 94 (1), and then “next descriptor address The descriptor 94 (2) is read out on the basis of “” and the information processing of the pre-processing data written in the area 2 on the basis of the descriptor 94 (2) is automatically started.

  As described above, the hardware logic processing unit 90 in the previous stage and the hardware logic processing unit 92 in the subsequent stage continuously execute information processing corresponding to each descriptor without obtaining a command from a system control CPU (not shown). can do.

  Here, the operation of the information processing apparatus when data processed by a plurality of preceding hardware logic processing units 90 is processed by a common subsequent hardware logic processing unit 92 will be described.

  As described above, the hardware logic processing unit 90 (90A, 90B) in the previous stage writes the post-processing data corresponding to the pre-processing data in the specified area based on the corresponding descriptor, and then the next of the descriptor. Since the information processing of the pre-processing data is started based on the descriptor, the information processing corresponding to each descriptor is continuously executed without obtaining a command from the system control CPU.

  However, the hardware logic processing unit 92 at the subsequent stage cannot continuously execute information processing corresponding to each descriptor without obtaining a command from the system control CPU.

  For example, as shown in FIG. 2B, when the post-processing data of the preceding-stage hardware logic processing unit 90A and the preceding-stage hardware logic processing unit 90B is processed by one subsequent-stage hardware logic processing unit 92, Predicting which of the preceding hardware logic processing unit 90A and the preceding hardware logic processing unit 90B can write the post-processing data in the corresponding area (area A, area B) first. This is because it cannot be done.

  Accordingly, the “LINK bit” of the descriptor 94 corresponding to the hardware logic processing unit 92 in the subsequent stage when executing such information processing indicates that processing of pre-processing data corresponding to the next descriptor is started. The bit is not set. The hardware logic processing unit 94 at the subsequent stage waits when the information processing corresponding to a certain descriptor 94 is completed, obtains a command from the system control CPU, reads the next descriptor 94, and executes the information processing.

  That is, when a plurality of post-processing data written in the system memory 93 by the plurality of pre-stage hardware logic processing units 90 is used as pre-process data, the common post-stage hardware logic processing unit 92 executes information processing. The intervention of a control CPU is necessary.

  When the end signal is input to the interrupt input terminal from the hardware logic processing unit 90 in the previous stage, the system control CPU interrupts the process being executed, selects the corresponding descriptor 94, and selects the descriptor of the selected descriptor 94. The process of inputting the address and the activation signal to the hardware logic processing unit 92 at the subsequent stage must be executed.

  In view of the above-described problems, an object of the present invention is to process a plurality of data processed in parallel and written in a system memory efficiently and without increasing the load on the CPU. This is in providing an information processing apparatus that can perform the processing.

  In order to achieve the above-described object, the first characteristic configuration of the information processing apparatus according to the present invention is based on descriptor information stored in the system memory, as described in claim 1 of the claims. A plurality of hardware logic processing units for executing predetermined information processing on pre-processing data input from an input unit or pre-processing data read from the system memory, and writing the post-processing data to the system memory; A data read start address, a pre-process data capacity, a post-process data write start address, and a next descriptor address, a plurality of descriptors associated with each hardware logic processing unit, and defined by the descriptor System memory that stores data to be processed and hardware logic in the subsequent stage When a descriptor address storage unit in which the top descriptor addresses of a plurality of descriptors associated with the processing unit are set and an end signal of the preceding hardware logic processing unit are input, it corresponds to the preceding hardware logic processing unit. A descriptor activation is read from the descriptor address storage unit, and a reservation activation control unit including a hardware logic control unit that outputs the descriptor address and activation signal to a hardware logic processing unit at a subsequent stage, and the descriptor is stored in the system memory. A system control CPU that generates and sets the head descriptor address in the descriptor address storage unit and activates each hardware logic control unit.

  Since the descriptor address storage unit stores the top descriptor addresses of a plurality of descriptors related to information processing executed by the hardware logic processing unit in the subsequent stage, the hardware logic control unit can efficiently perform without taking time. An activation signal and a target top descriptor address can be input to the hardware logic processing unit at the subsequent stage.

  Further, the hardware logic processing unit at the subsequent stage reads the corresponding descriptor from the system memory based on the descriptor address input from the hardware logic control unit, and executes information processing. Therefore, the system control CPU does not need to be involved in the information processing, and an increase in the load of the system control CPU related to the information processing can be prevented.

  In the second feature configuration, as described in claim 2, in addition to the first feature configuration described above, the hardware logic control unit simultaneously receives end signals from a plurality of hardware logic processing units in the previous stage. When an input is made, an arbitration circuit is provided that selects any one and outputs a descriptor address and an activation signal corresponding to the hardware logic processing unit in the subsequent stage.

  Since the selection of the descriptor associated with the pre-processing data to be processed and the input of the descriptor address and activation signal of the selected descriptor are executed by the arbitration circuit, the system control CPU performs the processing related to the selection and the input. There is no need to do it.

  In the third feature configuration, in addition to the first or second feature configuration described above, the hardware logic control unit is terminated for each hardware logic processing unit in the previous stage. A counter that counts up with a signal and counts down with a processing start signal of a subsequent hardware logic processing unit is provided, and when the counter value is not zero, an activation signal is output to the subsequent hardware logic processing unit. .

  According to the above-described configuration, after the data processed by the hardware logic processing unit in the previous stage is written to the system memory, the hardware logic processing unit in the subsequent stage starts information processing. Information processing is reliably executed.

  As described above, according to the present invention, it is possible to efficiently process a plurality of pieces of data processed in parallel and written to the system memory without increasing the load on the CPU. An information processing apparatus can be provided.

  Hereinafter, an information processing apparatus adopting the present invention will be described.

  As shown in FIG. 3, the information processing apparatus 1 executes predetermined information processing on the pre-processing data read from the system memory 2 based on the descriptor information stored in the system memory 2, and performs post-processing data. A plurality of hardware logic processing units 4 (4a, 4b) that write data to the system memory 2, the read start address of the pre-process data, the capacity of the pre-process data, the write start address of the post-process data, and the next descriptor address In addition, a plurality of descriptors associated with each hardware logic processing unit 4, a system memory 2 in which processing target data defined by the descriptors are stored, and a plurality of descriptors associated with the hardware logic processing unit 4b in the subsequent stage Descriptor address in which the top descriptor address of descriptor 3 is set When the end signal of the hardware storage processor 50 and the preceding hardware logic processing unit 4a is input, the descriptor address corresponding to the preceding hardware logic processing unit 4a is read from the descriptor address storing unit 50, and the subsequent hardware The reservation activation control unit 5 including the hardware logic control unit 51 that outputs the descriptor address and activation signal to the logic processing unit 4b, and the descriptor is generated in the system memory 2 and the first descriptor address is set in the descriptor address storage unit 50 And a system control CPU 6 that activates each hardware logic control unit 4.

  The hardware logic processing unit 4 and the reservation activation control unit 5 are functional blocks provided in the information processing IC. Each hardware logic processing unit 4 executes preset information processing based on the associated descriptor. The information processing IC, the system control CPU 6 and the system memory 2 are connected via a data bus and a command bus.

  The system control CPU 6 operates based on an algorithm defined in the operation program, and controls the information processing apparatus 1. An activation signal is output to the hardware logic processing unit 4 and the reservation activation control unit 5 to start information processing, and an end signal is output to stop the information processing.

  The reservation activation control unit 5 includes a register for setting its own operation. As shown in FIG. 4, the register includes an “operation control register” and a “hardware logic processing unit selection register”. The system control CPU 6 sets the “1” or “0” bit in the “operation control register” to enable / disable reservation activation control that activates the reservation activation control unit 5 to reduce its own load. To do.

  When “1” is set in the “operation control register”, the reservation activation control unit 5 executes activation control of the hardware logic processing unit 4b in the subsequent stage. That is, the reservation activation control unit 5 is activated, and the reservation activation control is enabled. When “0” is set, the system control CPU 6 executes. That is, the reservation activation control unit 5 is not activated, and the reservation activation control becomes invalid.

  The “hardware logic processing unit selection register” has the same number of bits as the number of hardware logic processing units 4 provided in the information processing IC. The system control CPU 6 sets a bit of “1” or “0” in each bit configuring the “hardware logic processing unit selection register”, and each hardware logic processing unit 4 outputs it at the end of information processing. Whether to input an end signal to the reservation activation control unit 51 is set. When “1” is set, input is allowed, and when “0” is set, input is rejected.

  The end signal is used for reservation activation control. Therefore, the system control CPU 6 relates to the selected hardware logic processing unit 4 so that the end signal output from the hardware logic processing unit 4 is input to the reservation activation control unit 5 when the reservation activation control is validated. Set the bit to “1”.

  The system control CPU 6 selects a hardware logic processing unit 4 related to execution of desired information processing from the plurality of hardware logic processing units 4 provided in the information processing apparatus 1, and selects the selected hardware logic processing unit 4. Is generated and stored in the system memory 2.

  The descriptor is generated for each information processing unit of each hardware logic processing unit 4. For example, when the hardware logic processing unit 4 whose data processing unit specified by the data capacity is “α” processes data before processing with a data capacity five times “α”, five descriptors are included. Generated.

  When the activation signal is input from the system control CPU 6, the hardware logic processing unit 4 is based on the descriptor address (first descriptor address) of the first descriptor among a plurality of associated descriptors. Read the descriptor from. Based on the descriptor, pre-processing data is read from the system memory 2, information processing is executed, and the post-processing data is written to the system memory 2.

  Then, based on the descriptor address of the second descriptor, which is the next descriptor defined for the descriptor, the second descriptor is read, and data before processing is processed in the same manner as described above. Similarly, the third and subsequent descriptors are read out and information processing relating to each descriptor is executed. When the information processing for all the descriptors is completed and an end signal is input from the system control CPU 6, the processing stops.

  When “1” is set in the “LINK bit” defined in each descriptor, the hardware logic processing unit 4 does not obtain a command from the system control CPU 6 and obtains the next specified in each descriptor. The next descriptor is read based on the descriptor address, and information processing is executed.

  However, when each post-processing data written in the system memory 2 by the plurality of previous-stage hardware logic processing units 4a is processed by the common subsequent-stage hardware logic processing unit 4b, which of the previous-stage hardware logic processing units 4a It is unclear whether the post-processing data writing will be terminated first. Therefore, the system control CPU 6 cannot predict the order in which the descriptor 3 corresponding to each preceding hardware logic processing unit 4a should be read by the following hardware logic processing unit 4b.

  Therefore, in the above-described case, the system control CPU 6 generates the descriptor 3 corresponding to each hardware logic processing unit 4a in the previous stage and stores it in the system memory 2. In the descriptor 3, “next descriptor address” is defined, but “LINK bit” is set to “0”.

  Therefore, the hardware logic processing unit 4b in the subsequent stage interrupts the processing when the information processing related to a certain descriptor 3 is completed. When the activation signal and the descriptor address of the descriptor 3 to be read out next are input from the system control CPU 6 or the reservation activation control unit 5, the corresponding descriptor 3 is read out from the system memory 2 based on the descriptor address, and information processing is performed. Execute.

  When the reservation activation control is invalid, the system control CPU 6 inputs the activation signal and the next descriptor address to the hardware logic processing unit 4b in the subsequent stage.

  More specifically, when the end signal output from the preceding hardware logic processing unit 4a is input to the interrupt input terminal when the information processing related to each descriptor is ended, the system control CPU 6 determines the descriptor corresponding to the activation signal. The address is input to the hardware logic processing unit 4b at the subsequent stage.

  When a plurality of end signals are simultaneously input to the interrupt input terminal, the start signal and the descriptor address corresponding to one of the end signals selected by the round robin are input to the hardware logic processing unit 4b at the subsequent stage.

  Then, the hardware logic processing unit 4b in the subsequent stage reads the descriptor 3 corresponding to the input descriptor address from the system memory 2, and executes information processing based on the descriptor 3.

  On the other hand, when the reservation activation control is valid, the reservation activation control unit 5 inputs the activation signal and the next descriptor address to the hardware logic processing unit 4b in the subsequent stage.

  When the reservation activation control is valid, the system control CPU 6 uses the descriptor 3 for the subsequent hardware logic processing unit 4 corresponding to each post-processing data written to the system memory 2 by each preceding hardware logic processing unit 4a. Are respectively generated and stored in the system memory 2. Then, the first descriptor address (descriptor address of the first descriptor 3) of each descriptor 3 is set in the descriptor address storage unit 50 provided in the reservation activation control unit 5.

  When an end signal is input from any preceding hardware logic processing unit 4a, the hardware logic control unit 51 reads the descriptor address corresponding to the preceding hardware logic processing unit 4a from the descriptor address storage unit 50. .

  Here, as described above, the descriptor address storage unit 50 stores the first descriptor address corresponding to each preceding hardware logic processing unit 4a before the information processing is started by the following hardware logic processing unit 4b. . As will be described later, when the hardware logic processing unit 4b in the subsequent stage reads the descriptor 3 from the system memory 2, it refers to the next descriptor address defined in the descriptor 3 and stores the descriptor address.

  As described above, the descriptor address storage unit 50 stores the descriptor address of each descriptor 3 relating to information processing that may be executed next by the hardware logic circuit 4b in the subsequent stage. Therefore, the hardware logic control unit 51, regardless of which end signal is input from the preceding hardware logic processing unit 4a, immediately sends the corresponding descriptor address and activation signal corresponding to the input to the subsequent hardware logic. The data can be output to the processing unit 4b.

  Further, when the end signals are simultaneously input from the plurality of preceding hardware logic processing units 4a, the hardware logic control unit 51 selects one of the descriptor addresses corresponding to the subsequent hardware logic processing unit 4b, and An arbitration circuit 52 that outputs a start signal is provided.

  The arbitration circuit 52 can select a descriptor address corresponding to any one of the round robin, and can output the selected descriptor address to the hardware logic processing unit 4b in the subsequent stage together with the activation signal immediately after the selection. After the information processing related to the descriptor 3 at the selected descriptor address is completed in the hardware logic processing unit 4b in the subsequent stage, the end signal is input to the reservation activation control unit 5 from the hardware logic processing unit 4b in the subsequent stage. The descriptor address on the side that has not been output is output to the hardware logic processing unit 4b in the subsequent stage together with the activation signal.

  Furthermore, the hardware logic control unit 51 includes a counter 53 that counts up with an end signal and counts down with a processing start signal of the subsequent hardware logic processing unit 4b for each preceding hardware logic processing unit 4a.

  The hardware logic control unit 51 (arbitration circuit 52) is configured to output an activation signal to the subsequent hardware logic processing unit 4b when the value of the counter 53 is not zero. Therefore, the post-processing data is not written in the system memory 2 by the pre-stage hardware logic processing unit 4a and the pre-processing data to be processed is not ready, but the post-processing hardware logic processing unit Information processing is not started in 4b.

  In the following, the information processing apparatus 1 when information is processed by the common subsequent-stage hardware logic processing unit 4b as each-processed data written by the plurality of preceding-stage hardware logic processing units 4a in the system memory 2 as pre-processing data. Will be described with reference to the flowcharts shown in FIGS.

  When starting the information processing (S1), the system control CPU 6 selects the hardware logic processing unit 4 used for the information processing, generates a corresponding descriptor (S2), and stores each descriptor in the system memory 2. (S3).

  Further, the first descriptor address of the descriptor 3 for the hardware logic processing unit 4b in the subsequent stage corresponding to each hardware logic processing unit 4a in the previous stage is stored in the descriptor address storage unit 50 (S4). Thereafter, an activation signal is output to the hardware logic processing unit 4 and the reservation activation control unit 5 (S5). Each of the activation signals is activated, and the preceding hardware logic processing unit 4a reads the descriptor corresponding to itself from the system memory 2. Execute information processing.

  When the end signal is input from the hardware logic processing unit 4a in the previous stage (S8), the counter 53 increments the counter value corresponding to the end signal (S9). Further, the arbitration circuit 52 determines whether or not the end signal is input from the other previous hardware logic processing unit 4a simultaneously with the end signal.

  Then, when the end signals are simultaneously input (S10), the arbitration circuit 52 selects a descriptor address corresponding to any end signal selected by the round robin arbitration (S11), and is a single input. Sometimes (S10), the descriptor address corresponding to the input end signal is selected.

  When the count value of the counter 53 is not “0” (S12), the activation signal and the selected descriptor address are output to the hardware logic processing unit 4b in the subsequent stage (S13).

  When the activation signal and the descriptor address are input (S17), the hardware logic processing unit 4b at the subsequent stage outputs a processing start signal to the reservation activation control unit 5 (S18), and the counter 53 decrements the corresponding counter value. (S14).

  When the hardware logic processing unit 4b at the subsequent stage reads the corresponding descriptor 3 from the system memory 2 (S19), the descriptor address storage unit 50 stores the next descriptor address defined in the descriptor 3 (S15).

  The hardware logic processing unit 4b at the subsequent stage executes information processing based on the read descriptor 3 (S20), and ends the information processing (S21), and outputs an end signal (S22).

  When the end signal is input from the hardware logic processing unit 4b at the subsequent stage, the system control CPU 6 determines whether or not the information processing of all data has been completed. When information processing of all data is completed (S6), a stop signal is output to the hardware logic processing unit 4 and the reservation activation control unit 5.

  If the stop signal is not input from the system control CPU 6 after the hardware logic processing unit 4b in the subsequent stage outputs the end signal, the hardware logic processing unit 4 and the reservation activation control unit 5 start from step S8 and step S17. The operation is repeated (S16, S23). When the stop signal is input (S16, S23), the operation is stopped.

  An image forming apparatus equipped with the information processing apparatus of the present invention will be described below.

  As shown in FIG. 7, an image forming apparatus equipped with an information processing apparatus according to the present invention, and a copying machine 8 employing an electrophotographic system, includes an operation unit 80 which is a man-machine interface, and an image read from a document image. A first scanner 81 and a second scanner 82 that generate data, and image data generated by the first scanner 81 and the second scanner 82 is subjected to image processing based on copy conditions set by the operation unit 80, and an output image An image processing unit 84 that generates data, and a printer engine 85 that transfers a toner image onto a sheet based on output image data generated by the image processing unit 84 and discharges the sheet on which the toner image has been thermally fixed. ing.

  The operation unit 80 displays a display unit 80a that displays an operation screen on which software keys for setting copy conditions such as enlargement / reduction conditions and copy density conditions are arranged, a numeric key for inputting the number of copies, and a copy start instruction. A hardware key 80b such as a copy key to be operated is provided.

  An operation control unit 800 that controls the operation unit 80, a first scanner control unit 810 that controls the first scanner 81, a second scanner control unit 820 that controls the second scanner 82, an image processing unit 84, and a printer engine An engine control unit 850 that controls 85 and a system control unit 86 that performs overall control of the copier 8 use a command bus (a bus indicated by a thin line in FIG. 7) and an image bus (a bus indicated by a thick line in FIG. 7). Connected through.

  The system control unit 86 is connected to these buses via a bus interface unit 860, and a hard disk 83 for storing image data is connected to the bus via a hard disk control unit 830.

  The operation control unit 800, the first scanner control unit 810, the second scanner control unit 820, the engine control unit 850, the system control unit 86, and the hard disk control unit 830 store a CPU and a CPU operation program. A ROM, a system memory which is a work area of the CPU, and peripheral circuits are provided. Each CPU executes an operation program read from the ROM, and operates based on an algorithm defined for each. The image processing unit 84 is composed of an image processing ASIC.

  The copying machine 8 includes an image processing apparatus 7 that is an information processing apparatus employing the present invention. As shown in FIG. 8, the image processing apparatus 7 includes a system control unit 86 and an image processing unit 84. The image processing unit 84 includes a reservation activation control unit 840 and an image processing execution unit 841 that executes image processing based on copy conditions.

  The reservation activation control unit 840 includes a descriptor address storage unit 842 and a hardware logic control unit 843.

  The image processing execution unit 841 is a hardware logic processing unit at the subsequent stage. The shading correction unit, the line correction unit, the encoding unit that compresses the image data after the line correction and writes the data to the hard disk, and the hard disk stored in the hard disk A plurality of functional blocks that execute predetermined image processing such as a decoding unit that reads and decompresses image data, a rotation / magnification processing unit, a color space conversion unit, a filter processing unit, and a binarization processing unit I have.

  When the copy key of the operation unit 80 is operated, the copy condition set via the operation screen displayed on the display unit 80a is input to the system control unit 86 via the operation control unit 800.

  The system control unit 86, based on the copy conditions set in the image processing unit 84 by the operation unit 80, and the image processing execution unit 841, the first hardware logic processing unit that is the input unit of the present invention and the preceding stage. Descriptors 70 for the scanner 81 and the second scanner 82 are generated and stored in the system memory 861.

  In addition, each head descriptor address of the descriptor 73 for the image processing execution unit 841 corresponding to the first scanner 81 and the second scanner 82 is set in the descriptor address storage unit 842.

  Further, the image processing execution unit 841 selects a function block that executes image processing related to the copy condition, and sets the image processing to be executed by each selected function block. The first scanner 81 and the second scanner 82 and an image processing unit 84 (image processing execution unit 841).

  Here, the system control unit 87 generates a descriptor 70 for each predetermined data capacity, which is a preset processing unit, and for each original document. For example, when copying two originals of a certain size, if the data capacity of the processing unit is 10 KB and the data capacity for the image data of one original is 100 KB, first the descriptor corresponding to the first original 10 pieces of 70 are generated.

  Then, the top descriptor addresses of the ten descriptors 73 are set in the descriptor address storage unit 842, and an activation signal is output. After completion of the image processing of the image data of the original, an end signal is output to the first scanner 81, the second scanner 82, and the image processing unit 84 to stop them, and the descriptor 70 corresponding to the second original is set to 10 Generate. Then, the top descriptor addresses of the ten descriptors 73 are set in the descriptor address storage unit 842, and an activation signal is output.

  The first scanner 81 reads the image on the front side of the document, and the second scanner 82 reads the image on the back side of the document at substantially the same timing. Then, the first scanner 81 and the second scanner 82 write the generated image data in the system memory 861 based on the respective descriptors 71 and 72. An end signal is input to the reservation activation control unit 840 every time image processing of image data having a data capacity (capacity in image processing units) defined in the descriptors 71 and 72 is completed.

  The hardware logic control unit 843 increments the count value corresponding to the end signal with a counter (not shown). As will be described later, when a processing start signal is input from the image processing execution unit 841, the corresponding count value is decremented. If the count value is not “0”, the corresponding descriptor address is read from the descriptor address storage unit 842 and the descriptor address is input to the image processing execution unit 841 together with the activation signal.

  The image processing execution unit 841 inputs a processing start signal to the reservation activation control unit 840, and reads the corresponding descriptor 73 from the system memory 861 based on the descriptor address. At this time, the descriptor address storage unit 842 reads and stores the next descriptor address defined in the descriptor 73.

  The image processing execution unit 841 reads image data from the system memory 861 based on the read descriptor 73, and executes image processing related to the set copy condition on the image data in cooperation with the selected functional block. Thus, output image data is generated.

  When the image processing of all the image data corresponding to the generated descriptor 70 is completed, the system control unit 87 outputs an end signal to the first scanner 81, the second scanner 82, and the image processing unit 84 (image processing execution unit 841). Then, the first scanner 81, the second scanner 82, and the image processing unit 84 are stopped.

  Another embodiment will be described below.

  In the above-described embodiment, the first scanner 81 and the second scanner 82 are used as the front-stage hardware logic processing unit in the copying machine 8 equipped with the information processing apparatus of the present invention, and the image is used as the back-end hardware logic processing unit. Although the image processing unit 84 composed of the processing ASIC is adopted, the present invention is not limited to this.

  For example, an image processing ASIC may be employed as both the front-stage hardware logic processing unit and the rear-stage hardware logic processing unit.

  For example, the shading correction unit and the line correction unit are employed as the preceding hardware logic processing unit, and are employed as the preceding hardware logic processing unit including the decoding unit, and the rotation / magnification processing unit, the color space conversion unit, and the filter You may employ | adopt a process part and a binarization process part as a hardware logic process part.

  In this case, for example, the image of the image data stored in the hard disk 83 serving as the system memory of the present invention is combined with the original image read by the first scanner 81 or the second scanner 82 serving as the input unit of the present invention and copied. This configuration can be adopted when a composite copy or the like is performed by the copying machine 8.

  In the above-described embodiment, the system control unit 87 generates the descriptor 70 for each predetermined data capacity that is a preset processing unit and for each document. Alternatively, the descriptor 70 may be generated for each predetermined data capacity and for each predetermined number of originals. This reduces the waiting time for image processing that occurs while generating the descriptor 70.

  In the above-described embodiment, the hardware logic control unit 51 includes the arbitration circuit 52. However, the hardware logic processing unit 4a in the previous stage is configured so that end signals are not input simultaneously. For example, it is not necessary to provide the arbitration circuit 52. Further, the system control CPU 6 may be configured to perform the arbitration process performed by the arbitration circuit 52.

  In the above embodiment, the hardware logic control unit 51 includes the counter 53. However, the information processing speed of the preceding hardware logic processing unit 4a is faster than the information processing speed of the following hardware logic processing unit 4b. In such a case, the counter 53 may not be provided.

  The above-described embodiments are merely examples of the present invention, and the scope of the present invention is not limited by the description, and the specific configuration of each part is appropriately changed within the scope of the effects of the present invention. It goes without saying that it can be done.

Descriptor illustration (A) is a functional block diagram of a conventional information processing apparatus, (b) is a functional block diagram of a conventional information processing apparatus. Functional block diagram of information processing device Explanatory drawing of the register that sets the operation of the reservation activation control Flowchart explaining operation of information processing apparatus Flowchart explaining operation of information processing apparatus Functional block diagram of image forming apparatus Functional block diagram of the information processing apparatus provided in the image forming apparatus

Explanation of symbols

1: Information processing device 2: System memory 3: Descriptor 4a: Previous hardware logic processing unit 4b: Later hardware logic processing unit 5: Reservation activation control unit 6: System control CPU
50: Descriptor address storage unit 51: Hardware logic control unit 52: Arbitration circuit 53: Counter

Claims (3)

Based on the descriptor information stored in the system memory, predetermined information processing is executed on the pre-process data input from the input unit or the pre-process data read from the system memory, and the post-process data is stored in the system memory. A plurality of hardware logic processing units to write to,
Predetermined data read start address, preprocessed data capacity, postprocessed data write start address, and next descriptor address, multiple descriptors associated with each hardware logic processing unit and specified by the descriptor System memory for storing the processing target data to be processed,
When the descriptor address storage unit in which the top descriptor addresses of a plurality of descriptors associated with the subsequent-stage hardware logic processing unit are set and the end signal of the preceding-stage hardware logic processing unit are input, the preceding-stage hardware logic A reservation activation control unit including a hardware logic control unit that reads a descriptor address corresponding to a processing unit from the descriptor address storage unit and outputs the descriptor address and an activation signal to a hardware logic processing unit at a subsequent stage;
A system control CPU for generating the descriptor in the system memory, setting the head descriptor address in the descriptor address storage unit, and starting each hardware logic control unit;
An information processing apparatus comprising:   When the end signal is simultaneously input from a plurality of preceding hardware logic processing units, the hardware logic control unit selects any one and outputs a descriptor address and an activation signal corresponding to the following hardware logic processing unit The information processing apparatus according to claim 1, further comprising an arbitration circuit.   The hardware logic control unit includes a counter that counts up with an end signal and counts down with a process start signal of a subsequent hardware logic processing unit for each preceding hardware logic processing unit, and the value of the counter is not zero The information processing apparatus according to claim 1 or 2, wherein an activation signal is output to a hardware logic processing unit at a later stage.

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