JP2010098244A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which satisfies both high integration degree and improvement of yield while securing a lithographic margin in consideration of ground level difference and a manufacturing method thereof. <P>SOLUTION: An interlayer insulating film ID11 after CMP has a first surface SF11 and a second surface SF12 located nearer the substrate side than the first surface SF11, and a diameter (D11d) of the uppermost part of a first hole CH11 to be formed on the first surface SF11 is provided so as to be larger than a diameter (D12d) of the uppermost part of a second hole CH12 to be formed on the second surface SF12. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention affects the product yield, and in particular, focuses on holes such as via holes and contact holes. In order to suppress the influence of the base step, the hole size is adjusted according to the base pattern occupancy ratio and linked with the surrounding wiring spacing margin. The present invention relates to a semiconductor device whose hole size is adjusted and a method for manufacturing the same.

  Except for the memory area of SoC (System on a Chip) and the like, a semiconductor device generally composed of random logic has conventionally used via holes and contact holes having a single size. However, due to the progress of miniaturization of semiconductor devices, the focus margin of lithography sharply decreases. As a result, the manufacturing margin of semiconductor devices decreases, and a slight dimensional change triggers, resulting in a decrease in yield and reliability of semiconductor devices. This is one of the causes.

  In manufacturing a semiconductor device with a single hole size such as a via hole or a contact hole, there is a certain merit in the deposition and planarization control of a metal film embedded in the hole. However, with the progress of miniaturization of semiconductor devices, slight changes in the base level and dimensional changes caused by device fluctuations have started to affect the yield, and have become a factor that hinders stable manufacturing.

  As one of countermeasures, a layout in which a plurality of holes are arranged instead of one has been used. However, in general, the arrangement of a plurality of via holes causes an increase in the chip area and is difficult to optimize.

  In addition, there is a step on the surface of the film that covers the wiring between regions with different wiring occupancy ratios located in the lower layer, and in order to reduce this step, the wiring is formed using a CMP (Chemical Mechanical Polishing) method. The planarization of the surface of the covering film is performed.

  However, even if CMP is used, the step generated on the surface of the film covering the wiring cannot be completely flattened, and therefore, the remaining step (step of several tens of nm) hinders stable semiconductor device manufacturing. It has become like this. Patent Documents 1 to 3 listed below are disclosed as a patent document disclosing a technique for solving the lithography problem caused by the step generated in the film covering the wiring.

  In Patent Document 1, a step generated in a film covering a wiring is reduced by forming an organic low dielectric constant film by a coating method, and a margin of depth of focus is ensured by forming an inorganic antireflection film thereon. Technology is disclosed. In Patent Document 2, by forming a contact hole shallower than a deep contact hole, contact holes having different depths can be selectively formed by steps of a film covering a wiring, and the contact hole can be embedded with tungsten. Technology is disclosed.

Patent Document 3 uses an attenuation type phase shift mask that can accurately expose a predetermined pattern in the same process in all regions of the exposed material even when a step occurs in the exposed material. A technique related to the exposure method has been disclosed.
JP 2003-86793 A Japanese Patent Application Laid-Open No. 09-172074 JP 08-31711 A

  The problem to be solved by the present invention is that, due to the progress of miniaturization of a semiconductor device, a slight change in the level difference or a dimensional change caused by the device change starts to affect the yield, thereby hindering stable manufacturing. . Accordingly, it is an object of the present invention to provide a semiconductor device and a method for manufacturing the same that can achieve both high integration and improved yield while ensuring a litho margin in consideration of a base step.

  In the semiconductor device and the manufacturing method thereof in the present embodiment, a semiconductor substrate, a plurality of gate electrodes formed on the semiconductor substrate, and a first surface provided from the first surface are provided above the semiconductor substrate. An interlayer insulating film having a second surface located on the substrate side, having a plurality of these gate electrodes therein, and having been subjected to surface planarization by CMP, and a first surface formed on the first surface It has a hole and a second hole formed in the second surface. The diameter of the uppermost part of the first hole is set larger than the diameter of the uppermost part of the second hole.

  Further, in the semiconductor device and the manufacturing method thereof according to another embodiment, a semiconductor substrate, a first surface provided above the semiconductor substrate, and a second surface positioned on an upper layer side than the first surface are provided. An interlayer insulating film having a plurality of Cu wirings embedded in the trench and subjected to surface planarization by CMP, and a first hole formed in the first surface of the interlayer insulating film; And a second hole formed in the second surface of the interlayer insulating film. The diameter of the uppermost part of the first hole is set larger than the diameter of the uppermost part of the second hole.

  According to the semiconductor device and the manufacturing method thereof of the present embodiment described above, by adjusting the hole size according to the base pattern occupancy rate, while ensuring a litho margin in consideration of the base step, high integration and yield improvement It is possible to achieve both.

  Also, since the hole size can be adjusted according to the surrounding layout, the yield of via holes can be improved without increasing the chip area. In addition, the effect of increasing the hole size can be expected to improve wiring reliability against electromigration and stress migration of the semiconductor device.

  Embodiments of the present invention will be described below. Note that the same or corresponding portions are denoted by the same reference numerals, and the description thereof may not be repeated. In the embodiments described below, when referring to the number, amount, and the like, the scope of the present invention is not necessarily limited to the number, amount, and the like unless otherwise specified.

(Reference Example 1)
First, the structure of the semiconductor device in Reference Example 1 for explaining the first embodiment will be described with reference to FIGS. 1 is a plan view showing the structure of the semiconductor device in Reference Example 1, and FIG. 2 is a cross-sectional view taken along the line II-II in FIG. 1 showing the structure of the semiconductor device in Reference Example 1. . 3 is a cross-sectional view showing a method for manufacturing a semiconductor device in Reference Example 1, and FIG. 4 is a cross-sectional view showing a structure of the semiconductor device in Reference Example 1 and a method for manufacturing the semiconductor device.

  As shown in FIG. 1, in order to improve the capacity per unit area in a CMOS (Complementary Metal Oxide Semiconductor), the gate electrode GE11 is generally viewed in a plan view as shown in (A) and (B). Need to be arranged in an array. (A) shows area | region R11 with a high pattern occupation rate of gate electrode GE11, (B) has shown area | region R12 with a low pattern occupation rate of gate electrode GE11.

  In the drawings described later, (A) shows a region where the pattern occupancy of the gate electrode GE11 is high, and (B) shows a region R12 where the pattern occupancy of the gate electrode GE11 is low. In the drawing, the MOS structure in which the gate electrode GE11 is provided with the oxide film interposed on the semiconductor substrate S11 is shown in a simplified manner. The impurity diffusion region such as the source / drain region, the sidewall Illustration is omitted.

  In order to improve the capacitance per unit area in the MOS, it is preferable to arrange the wiring pattern of the gate electrode GE11 with a higher occupation ratio. However, the following problems arise.

  In the semiconductor chip, a region R11 having a high pattern occupancy ratio of the gate electrode GE11 and a region R12 having a low pattern occupancy ratio corresponding to a normal logic circuit region are mixed, such as the capacitive element region. Thus, when the region R11 having a high pattern occupancy ratio and the region R12 having a low pattern occupancy ratio coexist, a step is formed on the surface of the interlayer insulating film ID11 that is a gate contact layer covering the gate electrode GE11 as shown in FIG. Occurs. CMP is performed on the surface of the interlayer insulating film ID11 in order to eliminate this step and planarize the surface of the interlayer insulating film ID11.

  However, as shown in the cross-sectional view of FIG. 2, it is difficult to completely eliminate the step of the interlayer insulating film ID11. Between the region R11 having a high pattern occupancy ratio and the region R12 having a low pattern occupancy ratio, A step ST11 having a height of several tens of nm remains. The height of the gate electrode GE11 is about 100 nm, and the thickness of the interlayer insulating film ID11 from the surface of the semiconductor substrate S1 is about 300 nm.

  When the mask RF11 made of a resist film or the like formed on the interlayer insulating film ID11 is exposed using the photolithography technique with the step ST11 remaining, a pattern that occupies most of the region of the semiconductor chip. The focus is on the region R12 side where the occupation ratio is low.

  As a result, as shown in FIG. 3, when the mask film RF11 is developed, the diameter (uppermost end diameter) D11a of the resist hole RH11 formed in the region R11 with a high occupation ratio is changed to the region R12 with a low occupation ratio. The resist hole RH12 is formed to be smaller than the diameter (uppermost end diameter) D12a.

  FIG. 4 is a cross-sectional view of the semiconductor device after the etching process of the interlayer insulating film ID11 is completed using the mask RF11 after the pattern etching is completed. In the etching of the interlayer insulating film ID11, contact holes CH11 and CH12 reflecting the shapes of the resist holes RH11 and RH12 of the mask RF11 shown in FIG. 3 are formed.

  As a result, as shown in FIG. 4, the diameter (topmost diameter) of the contact hole CH12 formed in the region R12 with a low occupancy rate is D12b, and the diameter of the contact hole CH11 formed in the region R11 with a low occupancy rate When (the uppermost end diameter) is D11b, the relationship is D11b <D12b. FIG. 5 and FIG. 6 explain the reason. FIG. 5 is a diagram showing the relationship between the focus margin and the process node, and FIG. 6 is a diagram showing the relationship between the dimension and the focus.

  As shown in FIG. 5, when scaling by miniaturization of the MOS advances (the process node moves from A to B), a high pattern resolution is required for the lithography technique. As a result, the focus margin (μm) is reduced. As a result, the focus formed in the residual step portion (region R11 with a high occupation ratio) becomes defocused, and the finished dimension of the resist hole RH11 becomes smaller as the process node moves from A to B as shown in FIG. .

  The following (a) and (b) can be given by arranging the reasons for D11b <D12b. (A) The resist size is reduced due to the step. (B) Since the interlayer insulating film ID11 is formed thick, the hole bottom diameter is qualitatively reduced. For these reasons, the yield was reduced with a certain probability in the place where the step exists.

(Embodiment 1)
Therefore, in the first embodiment, a contact hole arranged in advance in the region R11 where the occupation ratio of the gate electrode GE11 is high is extracted using a recognition device, and the hole size on the photomask side for forming the contact hole Is formed larger than the hole size on the photomask side for forming a contact hole arranged in the region R12 where the occupation ratio of the gate electrode GE11 is low.

  FIG. 7 shows a cross-sectional view when the lithography process is performed using the data, and FIG. 8 shows a cross-sectional view of the semiconductor device after etching. FIG. 7 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment based on the present invention. FIG. 8 shows a structure of the semiconductor device according to the first embodiment based on the present invention and a method for manufacturing the same. FIG.

  As shown in FIG. 8, the semiconductor device according to the first embodiment includes an interlayer insulating film (gate contact layer) ID11 whose surface is subjected to planarization processing above the semiconductor substrate S11, and this interlayer insulating film ID11. The surface has a first surface SF11 and a second surface SF12 located on the semiconductor substrate S11 with respect to the first surface SF11.

  The uppermost portion of the first hole CH11 has a first hole CH11 formed in the first surface SF11 of the interlayer insulating film ID11 and a second hole CH12 formed in the second surface SF12 of the interlayer insulating film ID11. The diameter (D11d) of the second hole CH12 is larger than the diameter (D12d) of the uppermost portion of the second hole CH12.

  Referring to FIG. 7 again, in the method of manufacturing the semiconductor device having this configuration, first, a gate electrode is formed on a semiconductor substrate, whereby region R11 having a high occupation ratio of gate electrode GE11 and gate electrode GE11 are formed. And a region R12 having a low occupation ratio. Next, an interlayer insulating film ID11 is formed on the semiconductor substrate having these gate electrodes. Thereafter, the surface of the interlayer insulating film ID11 is planarized by CMP or the like.

  At this time, a step ST11 remains on the surface of the interlayer insulating film ID11 between the region R11 where the occupation ratio of the gate electrode GE11 is high and the region R12 where the occupation ratio of the gate electrode GE11 is low. As a result, the first surface SF11 and the second surface SF12 located on the substrate side of the first surface SF11 are formed on the surface of the interlayer insulating film ID11.

  Next, as described above, the hole size on the photomask side for forming the contact hole is the hole size arranged in the region R11 where the occupancy rate of the gate electrode GE11 is low, and the region where the occupancy rate of the gate electrode GE11 is low It is formed larger than the hole size arranged in R12.

  As a result, even if the step ST11 is slightly defocused, the influence is not so much, and the diameter (uppermost end diameter) D11c of the resist hole RH11 formed in the region R11 with a high occupancy rate is in the region R12 with a low occupancy rate. The resist hole RH12 to be formed is formed larger than the diameter (uppermost end diameter) D12c.

  Next, as shown in FIG. 8, the etching process of the interlayer insulating film ID11 is performed using the mask RF11 after the pattern etching is completed. In the etching of the interlayer insulating film ID11, contact holes CH11 and CH12 reflecting the shapes of the resist holes RH11 and RH12 of the mask RF11 shown in FIG. 7 are formed. If the diameter (top end diameter) of the contact hole CH12 formed in the low occupancy region R12 is D12d, and the diameter (top end diameter) of the contact hole CH11 formed in the low occupancy region R11 is D11d. , D11d> D12d.

  Further, the diameters of the bottom portions of the contact holes CH11 and CH12 (portions in contact with the semiconductor substrate S1) can be ensured to be equal to or larger than the normal portion. As a result, pattern formation can be performed without reducing the yield even in the region R11 where the occupation ratio of the gate electrode GE11 is high.

  Thus, when the structure of the semiconductor device shown in FIG. 8 is seen, the interlayer insulating film ID11 after CMP has the first surface SF11 and the second surface SF12 located on the substrate side with respect to the first surface SF11. The uppermost diameter (D11d) of the first hole CH11 formed in the first surface SF11 is larger than the uppermost diameter (D12d) of the second hole CH12 formed in the second surface SF12. Yes.

  Here, as a precondition for the semiconductor device, it is important that the wiring interval and the margin with the hole have a layout that does not cause a problem such as a short circuit between wirings even if a large hole is formed. Originally, the metal wiring pattern pitch used in the MOS capacitor element is often loose, and even if the pitch is widened, the area does not increase. The wiring pitch and hole pitch of the capacitive element region R11 are usually set to be twice or more the wiring pitch and hole pitch of the logic circuit region R12 so that problems such as a short circuit between wirings do not occur.

  Therefore, even if the conditions shown in this embodiment are introduced, the degree of integration does not decrease. In addition, if a plurality of holes are arranged in such a region, it is effective for improving the yield. As described above, according to the present embodiment, it is possible to achieve both high integration and yield improvement while ensuring a litho margin in consideration of the base step.

  Next, FIG. 9 shows an example of a specific semiconductor device having the structure shown in FIG. In the semiconductor device shown in FIG. 9, well regions S111 and S112 separated by trench insulating films TI10, TI11, and TI12 are formed on the main surface of the semiconductor substrate S11. The well region S111 constitutes a capacitive element region R11, and the well region S112 constitutes a normal logic circuit region R12. The capacitive element region R11 is a region where the wiring occupation ratio of the gate electrode is high, and the normal logic circuit region R12 is a region where the wiring occupation ratio of the gate electrode is low.

  In the capacitive element region R11, a gate electrode GE11 and a sidewall SW11 having a predetermined shape are formed on the main surface of the well region S111 with a gate insulating film interposed therebetween. A first impurity diffusion region IR111 and a second impurity diffusion region IR112 are formed in a predetermined region in the well region S111.

  Also in the normal logic circuit region R12, a gate electrode GE11 and a sidewall SW11 having a predetermined shape are formed on the main surface of the well region S112 with a gate insulating film interposed. A first impurity diffusion region IR111 and a second impurity diffusion region IR112 are formed in a predetermined region in the well region S112.

  On the main surfaces of the well region S111 and the well region S112, an interlayer insulating film ID11 is provided so as to cover the gate electrode GE11. The surface of the interlayer insulating film ID11 is subjected to CMP in order to reduce the level difference, but a level difference ST11 having a height of several tens of nm remains between the capacitive element region R11 and the normal logic circuit region R12.

  In each of the capacitive element region R11 and the normal logic circuit region R12, the interlayer insulating film ID11 is formed with contact holes CH11 and CH12 that communicate with the impurity diffusion region IR111. When the diameter of the uppermost portion of the contact hole CH11 is D11d and the diameter of the uppermost portion of the contact hole CH12 is D12d, the contact hole CH11 is provided so as to satisfy the relationship of D11d> D12d.

  Contact members CD11 and CD12 that are electrically connected to the impurity diffusion region IR111 are embedded in the contact holes CH11 and CH12.

  As described above, according to the semiconductor device and the method shown in FIG. 9, the first surface SF11 on the capacitor element region R11 side of the interlayer insulating film ID11 and the side of the normal logic circuit region R12 located on the substrate side with respect to the first surface SF11. The uppermost diameter (D11d) of the first hole CH11 formed in the first surface SF11 is equal to the uppermost diameter (D12d) of the second hole CH12 formed in the second surface SF12. ) Is larger than.

  As a result, it is possible to achieve both high integration and yield improvement while securing a litho margin in consideration of the base step. In addition, by adjusting the contact hole size according to the layout and arranging a plurality of holes, it is possible to provide a semiconductor device that can improve the yield of contact holes without increasing the chip area. It is also possible to provide a semiconductor device that can improve wiring reliability against electromigration and stress migration due to the effect of increasing the contact hole size.

(Reference Example 2)
Next, the structure of the semiconductor device in Reference Example 2 for explaining the second embodiment will be described with reference to FIGS. 10 is a plan view showing the structure of the semiconductor device in Reference Example 2, and FIG. 11 is a cross-sectional view taken along the line XI-XI in FIG. 10 showing the structure of the semiconductor device in Reference Example 2. . 12 is a cross-sectional view showing a method for manufacturing a semiconductor device in Reference Example 2, and FIG. 13 is a cross-sectional view showing a structure of the semiconductor device in Reference Example 2 and a method for manufacturing the semiconductor device.

  As shown in FIG. 10, in the semiconductor device, there are a region R21 in which the pattern occupancy ratio of the metal wiring patterns ML21, ML22, and ML23 is high and a region R22 in which the pattern occupancy is low. In the damascene process using Cu as a wiring material, a step due to dishing after CMP polishing, which is not so large in a single layer, has a plurality of interlayer insulating films ID21, ID22, ID22 including metal wiring patterns ML21, ML22, ML23 as shown in FIG. When ID23 is laminated, the steps generated in the respective layers are accumulated, and a large residual step T21 is generated on the surface of the interlayer insulating film ID23.

  In such a case, a problem occurs in the lithography process of the via hole BH21 provided in the interlayer insulating film ID24 shown in FIGS. Usually, the focus is on the region R22 side that occupies most of the region of the semiconductor chip and has a low pattern occupancy. As a result, when development of the mask RF21 made of a resist film or the like is performed, as shown in FIG. 12, as a result of focusing on the region R22, which occupies most of the region of the semiconductor chip and has a low occupation rate, the occupation rate is high. The diameter (uppermost end diameter) D21a of the resist hole RH21 formed in the region R21 is formed smaller than the diameter (uppermost end diameter) D22a of the resist hole RH22 formed in the region R22 having a low occupation ratio.

  FIG. 13 is a cross-sectional view after the etching process of the interlayer insulating film ID24 is completed using the mask RF21 after the pattern etching is completed. In the etching of the interlayer insulating film ID24, via holes BH21 and BH22 reflecting the shapes of the resist holes RH21 and RH22 of the mask RF21 shown in FIG. 12 are formed.

  As a result, the diameter (uppermost end diameter) of the via hole BH22 formed in the region R22 with a low occupancy rate is D22b, and the diameter (uppermost diameter) of the via hole BH21 formed in the region R21 with a high occupancy rate is D21b. Then, for the same reason as in the first embodiment, the relationship D21b <D22b is established. In particular, in the damascene process, there is a problem that the pattern on the base step is not finished as desired even in the subsequent wiring trench formation step.

(Embodiment 2)
Therefore, in the second embodiment, a photomask for extracting via holes, which are arranged in advance in region R21 where the pattern occupancy ratio of metal wiring patterns ML21, ML22, ML23 is high, using a recognition device and forming via holes. The hole size on the side is formed larger than the hole size on the photomask side for forming the via hole arranged in the region R22 where the pattern occupancy of the metal wiring patterns ML21, ML22, ML23 is low.

  FIG. 14 shows a cross-sectional view when the lithography process is performed using the data, and FIG. 15 shows a cross-sectional view of the semiconductor device after etching. FIG. 14 is a sectional view showing a method for manufacturing a semiconductor device according to the second embodiment based on the present invention, and FIG. 15 shows a structure of the semiconductor device according to the second embodiment based on the present invention and a method for manufacturing the same. FIG.

  As shown in FIG. 15, the semiconductor device according to the first embodiment includes an upper interlayer insulating film (Cu damascene wiring layer) ID24 whose surface is subjected to planarization treatment above the semiconductor substrate S21. The surface of the insulating film ID24 has a first surface SE21 and a second surface SF22 located on the upper layer side of the first surface SF21.

  Further, the first hole BH21 formed in the first surface SF21 of the upper interlayer insulating film ID24 and the second hole BH22 formed in the second surface SF22 of the upper interlayer insulating film ID24 are provided. The uppermost diameter (D21d) is larger than the uppermost diameter (D22d) of the second hole BH22.

  Referring to FIG. 14 again, in the method of manufacturing a semiconductor device having this configuration, first, region R21 having a high occupation ratio of metal wiring patterns ML21, ML22, and ML23, and the occupation ratio of metal wiring patterns ML21, ML22, and ML23. A plurality of interlayer insulating films ID21, ID22, and ID23 having a low region R22 are formed. Each of the interlayer insulating films ID21, ID22, and ID23 having the metal wiring patterns ML21, ML22, and ML23 is provided with a groove in the interlayer insulating film after forming the interlayer insulating film, and a metal material such as Cu is formed in the groove. After embedding, a planarization process is performed by a CMP method. Next, an upper interlayer insulating film ID24 is formed on the interlayer insulating film ID23. Thereafter, the surface of the upper interlayer insulating film ID24 is planarized by CMP or the like.

  At this time, on the surface of the upper interlayer insulating film ID24, a region R21 in which the metal wiring patterns ML21, ML22, and ML23 have a high occupation ratio and a region R22 in which the metal wiring patterns ML21, ML22, and ML23 have a low occupation ratio are provided. A residual step ST21 resulting from accumulation of steps generated in the respective layers of the interlayer insulating films ID21, ID22, and ID23 is formed. As a result, the first surface SF21 and the second surface SF22 located on the upper layer side of the first surface SF21 are formed on the surface of the upper interlayer insulating film ID24.

  Next, as described above, the hole size on the photomask side for forming the via hole is set to the metal wiring pattern ML21, ML22, ML23, the hole size arranged in the region R21 in which the occupation ratio of the metal wiring patterns ML21, ML22, ML23 is high. It is formed larger than the hole size arranged in the region R22 where the occupation ratio of ML22 and ML23 is low.

  As a result, even if the step ST21 is somewhat defocused, the influence is not so much, and the diameter (uppermost end diameter) D21c of the resist hole RH21 formed in the region R21 with a high occupancy rate is in the region R22 with a low occupancy rate. The resist hole RH22 to be formed is formed larger than the diameter (uppermost end diameter) D22c.

  Next, as shown in the cross-sectional view of FIG. 15, an etching process of the upper interlayer insulating film ID24 is performed using the mask RF21 after the pattern etching is completed. In the etching of the upper interlayer insulating film ID24, via holes BH21 and BH22 reflecting the shapes of the resist holes RH21 and RH22 of the mask RF21 shown in FIG. 14 are formed, and the diameter of the via hole CH22 formed in the region R22 with a low occupation ratio ( Assuming that the diameter of the uppermost end (D22d) is D22d and the diameter of the via hole BH21 formed in the low-occupancy region R21 (the diameter of the uppermost end) is D21d, the relationship D21d> D22d is established.

  Further, the diameter of the bottom part of the via holes BH21 and 22 (the part in contact with the metal wiring pattern ML23) can be ensured to be equal to or larger than the normal part. As a result, pattern formation can be performed without reducing the yield even in the region R21 where the pattern occupancy of the metal wiring patterns ML21, ML22, and ML23 is high.

  As described above, when the structure of the semiconductor device shown in FIG. 15 is seen, the upper interlayer insulating film ID24 after CMP includes the first surface SF21 and the second surface SF22 positioned on the upper layer side of the first surface SF21. And the uppermost diameter (D21d) of the first hole BH21 formed in the first surface SF21 is larger than the uppermost diameter (D22d) of the second hole BH22 formed in the second surface SF22. ing.

  In general, the area where the occupation ratio of the Cu damascene wiring must be increased is limited to a circuit in which the wiring resistance is to be lowered, and there is no area loss due to a slight pitch relaxation or a widening of the wiring width or interval. In addition, if a plurality of via holes are arranged in such a region, it is effective for improving the yield. Therefore, according to the present embodiment, it is possible to achieve both high integration and yield improvement while securing a litho margin in consideration of the base step.

  Next, FIG. 16 shows an example of a specific semiconductor device having the structure shown in FIG. In the semiconductor device shown in FIG. 16, well regions S211 and S212 separated by trench insulating films TI20, TI21, and TI22 are formed on the main surface of the semiconductor substrate S11. The well region S211 constitutes a power supply circuit region R21, and the well region S212 constitutes a normal logic circuit region R22. The power supply circuit region R21 is a region where the occupation ratio of the Cu damascene wiring is high, and the normal logic circuit region R12 is a region where the occupation ratio of the Cu damascene wiring is low. The power supply circuit area R21 is a ring including an area including at least one analog circuit area such as a CPU (Central Processing Unit) area, a memory circuit area, an AD conversion circuit, a DA conversion circuit, and a PLL circuit, each having a normal logic circuit area R22. It is surrounded by a shape.

  In power supply circuit region R21, gate electrode GE21 and sidewall SW21 having a predetermined shape are formed on the main surface of well region S211 with a gate insulating film interposed. A first impurity diffusion region IR211 and a second impurity diffusion region IR212 are formed in a predetermined region in the well region S211.

  Also in power supply circuit region R21, gate electrode GE21 and sidewall SW21 having a predetermined shape are formed on the main surface of well region S212 with a gate insulating film interposed. A first impurity diffusion region IR211 and a second impurity diffusion region IR212 are formed in a predetermined region in the well region S212.

  On the main surfaces of the well region S211 and the well region S212, an interlayer insulating film ID21 is provided so as to cover the gate electrode GE21. In the interlayer insulating film ID21, contact holes CH21 and CH22 communicating with the impurity diffusion regions IR211 and IR212 are formed. Contact members CD21 and CD22 that are electrically connected to the impurity diffusion region IR211 are embedded in the contact holes CH21 and CH22. Further, a Cu damascene wiring layer ML21 is provided on the upper end portions of the contact members CD21 and CD22.

  Over the interlayer insulating film ID21, an interlayer insulating film ID22 including a Cu damascene wiring layer ML22, an interlayer insulating film ID23 including a Cu damascene wiring layer ML23, an interlayer insulating film ID24 including a Cu damascene wiring layer ML24, and a Cu damascene wiring An interlayer insulating film ID25 including the layer ML25 is stacked.

  An upper interlayer insulating film ID26 is further provided on the interlayer insulating film ID25. On the surface of the upper interlayer insulating film ID26, a step S21 having a height of several tens of nanometers, in which steps generated in the respective layers are accumulated, is generated.

  In each of the power supply circuit region R21 and the normal logic circuit region R22, via holes BH21 and BH22 communicating with the lower Cu damascene wiring layer ML25 are formed in the upper interlayer insulating film ID26. When the diameter of the uppermost part of the via hole BH21 is D21d and the diameter of the uppermost part of the via hole BH22 is D22d, the via hole BH21 is provided so as to satisfy the relationship D21d> D22d.

  Contact members BD21 and BD22 that are electrically connected to the Cu damascene wiring layer ML25 are embedded in the via holes BH21 and BH22.

  As described above, in the semiconductor device shown in FIG. 16, the first surface SF21 on the power supply circuit region R21 side of the upper interlayer insulating film ID26 after CMP and the side of the normal logic circuit region R22 located on the upper layer side of the first surface SF21. The uppermost diameter (D21d) of the first hole CH11 formed in the first surface SF21 is equal to the uppermost diameter (D22d) of the second hole CH22 formed in the second surface SF22. ) Is larger than.

  As a result, it is possible to achieve both high integration and yield improvement while securing a litho margin in consideration of the base step. Further, by adjusting the via hole size according to the layout and arranging a plurality of holes, it is possible to provide a semiconductor device that can improve the yield of via holes without increasing the chip area. In addition, it is possible to provide a semiconductor device capable of improving wiring reliability against electromigration and stress migration due to the effect of increasing the via hole size.

  Each embodiment disclosed this time must be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a top view which shows the structure of the semiconductor device in the reference example 1 for demonstrating Embodiment 1 based on this invention. FIG. 2 is a cross-sectional view taken along the line II-II in FIG. 1, showing the structure of the semiconductor device in Reference Example 1 for explaining the first embodiment based on the present invention. It is sectional drawing which shows the manufacturing method of the semiconductor device in the reference example 1 for demonstrating Embodiment 1 based on this invention. It is sectional drawing which shows the structure of the semiconductor device in the reference example 1 for demonstrating Embodiment 1 based on this invention, and its manufacturing method. It is a figure which shows the relationship between a focus margin and a process node. It is a figure which shows the relationship between a dimension and a focus. It is sectional drawing which shows the manufacturing method of the semiconductor device in Embodiment 1 based on this invention. It is sectional drawing which shows the structure of the semiconductor device in Embodiment 1 based on this invention, and its manufacturing method. It is sectional drawing which shows the specific application example of the semiconductor device in Embodiment 1 based on this invention. It is a top view which shows the structure of the semiconductor device in the reference example 2 for demonstrating Embodiment 2 based on this invention. FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 10 showing the structure of the semiconductor device in Reference Example 2 for explaining the second embodiment based on the present invention; It is sectional drawing which shows the manufacturing method of the semiconductor device in the reference example 2 for demonstrating Embodiment 2 based on this invention. It is sectional drawing which shows the structure of the semiconductor device in the reference example 2 for demonstrating Embodiment 2 based on this invention, and its manufacturing method. It is sectional drawing which shows the manufacturing method of the semiconductor device in Embodiment 2 based on this invention. It is sectional drawing which shows the structure of the semiconductor device in Embodiment 2 based on this invention, and its manufacturing method. It is sectional drawing which shows the specific application example of the semiconductor device in Embodiment 2 based on this invention.

Explanation of symbols

  BD21, BD22 contact member, BH21 first hole (via hole), BH22 second hole (via hole), CD11, CD12, CD21, CD22 contact member, CH11 first hole (contact hole), CH12 second hole (contact hole), CH21, CH22 contact hole, GE11, GE21 gate electrode, ID11, ID21, ID22, ID23, ID24, ID25, ID26 interlayer insulation film, IR111, IR211, IR211 first impurity diffusion region, IR112, IR212 second impurity diffusion region, ML21 , ML22, ML23, ML24, ML25 Metal wiring pattern (Cu damascene wiring layer), R11 pattern occupancy region (capacitor element region), R12 pattern occupancy region ( Normal logic circuit area), R21 pattern occupancy high area (power supply circuit area), R22 pattern occupancy low area (normal logic circuit area), RF11, RF21 mask (resist film), RH11, RH12, RH21, RH22 resist Hole, S11 semiconductor substrate, S111, S112, S211, S212 well region, SF11, SF21 first surface, SF12, SF22 second surface, ST11, ST21 step, SW11, SW21 sidewall, TI10, TI11, TI12, TI20, TI21 , TI22 Trench insulation film.

Claims (6)

A semiconductor substrate;
A plurality of gate electrodes formed on the semiconductor substrate;
A surface planarization process is performed by a CMP method provided above the semiconductor substrate, having a first surface and a second surface located on the substrate side of the first surface, and having the plurality of gate electrodes inside. An applied interlayer insulating film;
A first hole formed in the first surface;
A second hole formed in the second surface,
The semiconductor device, wherein a diameter of an uppermost part of the first hole is provided larger than a diameter of an uppermost part of the second hole. The semiconductor device has a gate capacitor element region and a logic circuit region,
The first surface is located in the gate capacitor element region,
The second surface is located in the logic circuit region;
2. The semiconductor device according to claim 1, wherein an occupation ratio of the plurality of gate electrodes in the gate capacitance element region is higher than an occupation ratio of the plurality of gate electrodes in the logic circuit region. A semiconductor substrate;
A surface formed by CMP that has a first surface and a second surface located above the first surface, and has a plurality of Cu wirings embedded in the groove. A planarized interlayer insulating film; and
A first hole formed in the first surface of the interlayer insulating film;
A second hole formed in the second surface of the interlayer insulating film,
The semiconductor device, wherein a diameter of an uppermost part of the first hole is provided larger than a diameter of an uppermost part of the second hole. The semiconductor device has a power supply circuit region and a logic circuit region,
The first surface is located in the power supply circuit region,
The second surface is located in the logic circuit region;
The semiconductor device according to claim 3, wherein an occupation ratio of the plurality of Cu wirings in the power supply circuit region is higher than an occupation ratio of the plurality of Cu wirings in the logic circuit region. Preparing a semiconductor substrate having a region having a high occupation ratio of the gate electrode and a region having a low occupation ratio of the gate electrode;
Forming an interlayer insulating film on the semiconductor substrate;
Performing a planarization process on the surface of the interlayer insulating film, and forming a first surface and a second surface located closer to the semiconductor substrate than the first surface on the surface of the interlayer insulating film;
Forming a mask having a hole for forming a contact hole in the interlayer insulating film on the interlayer insulating film;
Forming a contact hole in the interlayer insulating film using the mask having the hole, and
The size of the hole formed in the mask is formed such that the hole size arranged in the region where the occupation ratio of the gate electrode is high is larger than the hole size arranged in the region where the occupation ratio of the gate electrode is low. Thus, the diameter of the uppermost portion of the contact hole formed on the first surface of the interlayer insulating film is larger than the diameter of the uppermost portion of the contact hole formed on the second surface of the interlayer insulating film. A method for manufacturing a semiconductor device. A step of forming a plurality of interlayer insulating films having a region where the metal wiring pattern occupancy is high and a region where the metal wiring pattern occupancy is low; and
Forming an upper interlayer insulating film on the interlayer insulating film;
A step of planarizing the surface of the upper interlayer insulating film by a CMP method to form a first surface and a second surface positioned on the upper layer side of the first surface on the surface of the upper interlayer insulating film. When,
Forming a mask having a hole for forming a via hole in the upper interlayer insulating film on the upper interlayer insulating film;
Using the mask having the holes, forming a via hole in the upper interlayer insulating film,
The size of the hole formed in the mask is formed such that the hole size arranged in a region where the occupation ratio of the metal wiring pattern is high is larger than the hole size arranged in a region where the occupation ratio of the metal wiring pattern is low. As a result, the diameter of the uppermost portion of the via hole formed on the first surface of the upper interlayer insulating film is larger than the diameter of the uppermost portion of the via hole formed on the second surface of the upper interlayer insulating film. Provided,
The interlayer insulating film includes a step of forming a groove in the interlayer insulating film, a step of filling Cu metal in the groove, and the Cu metal on the interlayer insulating film is removed by CMP. A method for manufacturing a semiconductor device, wherein the metal wiring pattern is formed in a groove.

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