JP2010097965A - Semiconductor wafer and monitoring method of the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for arranging a watermark monitoring pattern on a semiconductor wafer without reducing the number of chip regions. <P>SOLUTION: In the scribe line region 5 of the semiconductor wafer, a first monitoring pattern 7, a second monitoring pattern 9 and a third monitoring pattern 11 are formed as the watermark monitoring patterns. The first monitoring pattern 7 is formed of a recessed part formed at the surface of a semiconductor substrate. The second monitoring pattern 9 is formed of a plurality of insulating material patterns 9a formed on the surface of the semiconductor substrate. The third monitoring pattern 11 comprises a semiconductor film 11a formed on the semiconductor substrate, and a first semiconductor film region 11b where impurities are not introduced and a second semiconductor film region 11c where the impurities are introduced and which is formed adjacently to the first semiconductor film region 11b are formed in the semiconductor film 11a. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor wafer, and more particularly to a semiconductor wafer provided with a watermark monitor pattern capable of monitoring the presence or absence of circular spots called watermarks that cause gate breakdown voltage failure.

  In manufacturing a semiconductor device, in a wafer cleaning and drying process, when shortage of drying occurs, a circular spot (such as an oxide film residue) called a watermark is formed. For example, Patent Document 1 discloses a watermark generation mechanism. The watermark is formed with a size of several μm (micrometer) to several mm (millimeter). When the watermark is formed on the oxide film, the breakdown voltage of the oxide film is lowered.

  When semiconductor device manufacturing facilities are introduced, the presence or absence of watermarks is checked using bare wafers or wafers with simple patterns. In actual semiconductor device manufacturing processes, cleaning is performed in various patterns and film states. Since the wet etching process is performed, a watermark that was not seen at the time of installation of the equipment may be confirmed.

  As a countermeasure, if a watermark check is performed in all cleaning processes and wet etching processes based on the semiconductor manufacturing process, it takes a lot of time. Further, even if there is no problem at the time of starting up the equipment, it is also possible that a watermark is generated due to equipment trouble or the like.

  Further, for example, Patent Document 2 discloses a method for detecting a watermark using a monitor pattern. In the monitoring method disclosed in Patent Document 2, an oxide film having a plurality of irregularities that are the same as or larger than the chip area for a product and that have the same or smaller irregularities as the irregular pattern formed in the chip area. A monitor pattern consisting of a pattern is formed.

Japanese Patent Laid-Open No. 11-312659 Japanese Patent No. 3641378

  The watermark monitor pattern disclosed in Patent Document 2 is formed with an area that is the same as or larger than that of the product chip area, so that the chip area for one semiconductor wafer can be compared with the case where there is no monitor pattern. The number decreases, and the number of chips that can be taken decreases.

  Therefore, an object of the present invention is to provide a semiconductor wafer in which a watermark monitor pattern can be arranged without reducing the number of chip areas, and a monitoring method using the same.

  A semiconductor wafer according to the present invention is a semiconductor wafer in which a plurality of chip regions separated from each other by a scribe line region are arranged in a matrix on a semiconductor substrate, and a watermark monitor pattern is formed on the scribe line region. As described above, a first monitor pattern made of a recess formed on the surface of the semiconductor substrate, a second monitor pattern made of a plurality of insulating material patterns formed on the surface of the semiconductor substrate, and formed on the semiconductor substrate Of the third monitor pattern, which is formed of a semiconductor film and includes a first semiconductor film region into which no impurity is introduced and a second semiconductor film region into which an impurity is formed adjacent to the first semiconductor film region. At least one of the above.

The watermark monitor pattern needs to be large enough to be detected as a defect by an appearance inspection apparatus. Specifically, an example having a size of 0.1 μm or more can be given.
In addition, since the watermark is often formed with a size of several μm to several mm, the plane size of the watermark monitor pattern is more preferably 10 μm or more. Here, the plane size of the watermark monitor pattern is 10 μm or more. The minimum plane size of the recess is 10 μm or more for the first monitor pattern, and the minimum dimension of the arrangement region of the plurality of insulating material patterns is for the second monitor pattern. Means that the minimum planar size of the semiconductor film and the planar dimension of the boundary between the first semiconductor film region and the second semiconductor film region are 10 μm or more for the third monitor pattern.

  In addition, since there are various patterns in which a watermark is easily formed depending on the cleaning apparatus and process, the first monitor pattern, the second monitor pattern, and the second monitor pattern are used as the watermark monitor pattern in the semiconductor wafer of the present invention. More preferably, a plurality or all of the three monitor patterns are provided.

  The semiconductor wafer monitoring method according to the present invention uses the semiconductor wafer of the present invention, and detects the occurrence of a watermark by visually inspecting a watermark monitor pattern formed on the semiconductor wafer.

  In the semiconductor wafer of the present invention, in the scribe line region, as a watermark monitor pattern, a first monitor pattern composed of a recess formed on the surface of the semiconductor substrate and a plurality of insulating material patterns formed on the surface of the semiconductor substrate. And a first semiconductor film region in which no impurity is introduced and an impurity formed adjacent to the first semiconductor film region. Since at least one of the third monitor patterns composed of the two semiconductor film regions is provided, the watermark monitor pattern can be arranged without reducing the number of chip regions.

  By arranging the watermark monitor pattern in the scribe line region, it is possible to detect the occurrence of the watermark using a wafer on which a mass-produced chip region is mounted. In other words, it is possible to constantly monitor the presence or absence of a watermark even after confirmation at the time of installation without periodically flowing a dedicated wafer for monitoring the watermark to the production line. Further, since the scribe line exists everywhere in the wafer surface, a wide range of information can be collected.

  Further, in the semiconductor wafer of the present invention, if the plane size of the watermark monitor pattern is 10 μm or more, it is easy to generate a watermark in the watermark monitor pattern.

  In addition, if the watermark monitor pattern includes a plurality of or all of the first monitor pattern, the second monitor pattern, and the third monitor pattern, a watermark is formed in a plurality of steps. It is possible to detect the presence or absence of occurrence.

  In the semiconductor wafer monitoring method of the present invention, the occurrence of a watermark is detected by visual inspection of the watermark monitor pattern formed on the semiconductor wafer using the semiconductor wafer of the present invention. The occurrence of a watermark can be detected without reducing the number of chip areas.

FIG. 1 is a plan view schematically showing a watermark monitor pattern of one embodiment. FIG. 2 is a plan view showing the entire semiconductor wafer.
As shown in FIG. 2, a plurality of chip regions 3 that are separated from each other by a scribe line region 5 on the semiconductor wafer 1 are arranged in a matrix on the semiconductor substrate.
As shown in FIG. 1, a first monitor pattern 7, a second monitor pattern 9, and a third monitor pattern 11 are formed in the scribe line area 5 as watermark monitor patterns.

  The first monitor pattern 7 is formed by a recess formed on the surface of the semiconductor substrate. In this embodiment, four first monitor patterns 7 are formed in the region shown in FIG. The planar size of the first monitor pattern 7 is, for example, several μm to several tens of μm, and in this embodiment is 20 μm. The depth of the first monitor pattern 7 is several nm to several μm, for example, 150 nm here. The planar shape of the first monitor pattern 7 is not limited to a circle, and the first monitor pattern 7 can be formed in an arbitrary planar shape.

  If a step is formed on the surface of the semiconductor substrate by the first monitor pattern 7, the liquid is not completely removed at the corners of the step in the wet etching process when drying after the cleaning process, and a watermark is likely to occur.

  The second monitor pattern 9 is formed by a plurality of insulating material patterns 9a formed on the surface of the semiconductor substrate. For example, the insulating material pattern 9a is formed of an oxide film. For example, the planar size of the insulating material pattern 9a is several μm, and the thickness of the insulating material pattern 9a is several hundred nm. In FIG. 1, the second monitor pattern 9 is formed by 8 × 8 insulating material patterns 9a. However, FIG. 1 schematically shows the second monitor pattern 9. For example, when the width of the scribe line region 5 is 100 μm, the insulating pattern 9 a is about 20 × 20 in the second monitor pattern 9. Be placed. The planar size of the second monitor pattern 9 is, for example, 10 μm × 10 μm to 100 μm × 1000 μm, here 100 μm × 100 μm. The planar shape of the insulating material pattern 9a is not limited to a circle, and the insulating material pattern 9a can be formed in an arbitrary planar shape. The number and arrangement of the insulating material patterns 9a in the second monitor pattern 9 are also arbitrary.

  When a plurality of hydrophilic insulating material patterns 9a are formed on the surface of the hydrophobic semiconductor substrate as in the second monitor pattern 9, it is caused by the boundary between the hydrophobic surface of the semiconductor substrate and the hydrophilic surface of the insulating material pattern 9a. Water mark is likely to occur. In particular, when a large number of insulating material patterns 9a are formed as in the second monitor pattern 9, a watermark is likely to occur.

  The third monitor pattern 11 is formed by a semiconductor film 11a formed on the semiconductor substrate. In the semiconductor film 11a, a first semiconductor film region 11b into which no impurity is introduced and a second semiconductor film region 11c into which an impurity is formed adjacent to the first semiconductor film region 11b are formed. . The planar size of the semiconductor film 11a is 5 μm × 5 μm to 100 μm × 1000 μm, for example, 50 μm × 50 μm here.

  In the third monitor pattern 11, the first semiconductor film region 11 b into which no impurities are introduced and the second semiconductor film region 11 c into which impurities are introduced have different liquid wettability on their surfaces. Therefore, a watermark is likely to occur at the boundary between the first semiconductor film region 11b and the second semiconductor film region 11c.

  The monitor patterns 7, 9, and 11 are also formed on the scribe line 5 in the region of the semiconductor wafer 1 other than the region shown in FIG. Preferably, the monitor patterns 7, 9, 11 are formed on the scribe line 5 in the entire semiconductor wafer 1.

  In this embodiment, the first monitor pattern 7, the second monitor pattern 9 and the third monitor pattern 11 as the watermark monitor patterns are formed in the scribe line area 5. Watermark monitor patterns can be arranged without reduction.

  Furthermore, since three types of monitor patterns 7, 9, and 11 are provided, various types of watermark generation conditions can be accommodated. However, all of the three types of monitor patterns 7, 9, and 11 are not necessarily provided, and one or two of the monitor patterns 7, 9, and 11 may be provided.

FIG. 3 is a schematic process cross-sectional view for explaining an example of the manufacturing process of the first monitor pattern. Steps (1) to (5) described below correspond to the parenthesized numerals in FIG.
(1) A sacrificial oxide film 15 and a protective film 17 serving as a mask during oxidation are formed on the semiconductor substrate 13. The protective film 17 may be a nitride film, for example, but is not particularly limited as long as it serves as a mask during oxidation and has a large selectivity with respect to the oxide film during etching.

(2) Using a photoengraving technique, a photoresist pattern 19 having an opening 19a of several μm to several 100 μm is formed at a position where a concave portion of the first monitor pattern 7 is to be formed.
(3) For example, the dry etching technique is used to etch away the protective film 17 at the position where the concave portion of the first monitor pattern 7 is to be formed using the photoresist pattern 19 as a mask. Thereafter, the photoresist pattern 19 is removed.
(4) A thick oxide film 21 is formed at a position where the concave portion of the first monitor pattern 7 is to be formed by performing a thermal oxidation process using the protective film 17 as a mask.

(5) The protective film 17, the thick oxide film 21, and the sacrificial oxide film 15 are removed using a wet etching technique. At this time, the first monitor pattern 7 made of a recess is formed on the surface of the semiconductor substrate 13 where the thick oxide film 21 has been formed. If a step due to the first monitor pattern 7 is formed on the surface of the semiconductor substrate 13, the liquid at the corner of the step cannot be completely removed during wet etching or drying after cleaning, and a watermark tends to occur. .

FIG. 4 is a schematic process sectional view for explaining an example of the manufacturing process of the second monitor pattern. Steps (1) to (5) described below correspond to the parenthesized numerals in FIG.
(1) A sacrificial oxide film 15 and a protective film 17 serving as a mask during oxidation are formed on the semiconductor substrate 13. Similar to the manufacturing process described with reference to FIG. 3, for example, a nitride film can be used as the protective film 17 serving as a mask at the time of oxidation. However, the protective film 17 serves as a mask at the time of oxidation and is a film having a large selectivity with respect to the oxide film at the time of etching. If there is no particular limitation.

(2) Using a photoengraving technique, a photoresist pattern 23 including a large number of openings 23a of several μm is formed at a position where the insulating material pattern 9a of the second monitor pattern 9 is to be formed.
(3) For example, the dry etching technique is used to etch away the protective film 17 where the insulating material pattern 9a is to be formed using the photoresist pattern 23 as a mask. Thereafter, the photoresist pattern 23 is removed.

(4) An insulating material pattern 9a made of a thick oxide film is formed on the surface of the semiconductor substrate 1 by performing thermal oxidation using the protective film 17 as a mask.
(5) Using the wet etching technique, the protective film 17 and the sacrificial oxide film 15 are removed so that the insulating material pattern 9a remains. For example, as shown in FIG. 1, by forming a large number of insulating material patterns 9a in a matrix or zigzag pattern in the formation region of the second monitor pattern 9, a large number of boundaries between the hydrophobic surface and the hydrophilic surface are formed. , Water mark is likely to occur.

  Further, in the manufacturing process of the first monitor pattern 7 and the second monitor pattern 9, the photoresist pattern 19 shown in FIG. 3 and the photoresist pattern 23 shown in FIG. 4 are simultaneously formed with the same photoresist layer, The thick oxide film 21 shown in FIG. 3 and the insulating material pattern 9a shown in FIG. 4 are simultaneously formed in the same thermal oxidation process, and the thick oxide film 21, protective film 17 and sacrificial oxide film 15 shown in FIG. If the protective film 17 and the sacrificial oxide film 15 shown in FIG. 4 are removed at the same time, the first monitor pattern 7 and the second monitor pattern 9 can be formed simultaneously in the same manufacturing process. .

FIG. 5 is a schematic process cross-sectional view for explaining an example of the manufacturing process of the third monitor pattern. Steps (1) to (4) described below correspond to the parenthesized numerals in FIG.
(1) A semiconductor film 11 d is formed on the semiconductor substrate 13 via a gate insulating film 25. The semiconductor film 11d is formed of polycrystalline silicon or amorphous silicon into which no impurity is introduced.

(2) Using the photoengraving technique, a photoresist pattern 27 having an opening 27a including the position where the second semiconductor film region 11c of the third monitor pattern 11 is to be formed is formed.
(3) Using the ion implantation technique, ion implantation is performed on the semiconductor film 11d using the photoresist pattern 27 as a mask to form a semiconductor film 11e doped with impurities. Thereafter, the photoresist pattern 27 is removed.

(4) The semiconductor films 11d and 11e are patterned using a photoengraving technique and an etching technique, and a semiconductor film area 11b made of a semiconductor film into which no impurity is introduced, and a semiconductor film made up of a semiconductor film into which an impurity is introduced A third monitor pattern 11 made of a semiconductor film 11a having a region 11c is formed. At this time, the gate electrode of the transistor is simultaneously formed in the chip region. Here, the gate insulating film 25 may be removed by performing an etching process on the gate insulating film 25 except the regions under the third monitor pattern 11 and the gate electrode.

  In the third monitor pattern 11, since the liquid wettability is different between the semiconductor film region 11b into which the impurity is not introduced and the semiconductor film region 11c into which the impurity is introduced, the semiconductor film region 11b on the surface of the semiconductor film 11a. As a result, a watermark is likely to occur at the boundary between the semiconductor film region 11c.

FIG. 6 is a schematic process cross-sectional view for explaining another example of the third monitor pattern manufacturing process. Steps (1) to (5) described below correspond to the parenthesized numerals in FIG.
(1) A semiconductor film 11 d is formed on the semiconductor substrate 13 via a gate insulating film 25.

(2) An oxide film 29 is formed on the semiconductor film 11d by using, for example, an LPCVD (Low Pressure Chemical Vapor Deposition) method. Using the photoengraving technique, a photoresist pattern 31 having an opening 31 a including a position where the second semiconductor film region 11 c of the third monitor pattern 11 is to be formed is formed on the oxide film 29.
(3) A portion of the oxide film 29 is removed by etching using the photoresist pattern 31 as a mask, for example, using a wet etching technique to form an opening 29a in the oxide film 29. Thereafter, the photoresist pattern 31 is removed.
(4) Phosphor glass is deposited on the semiconductor film 11d and the oxide film 29 by using LPCVD, and phosphorus is diffused into the semiconductor film 11d to form a semiconductor film 11f into which impurities are introduced. Thereafter, the oxide film 29 is removed using, for example, a wet etching technique.

(5) The semiconductor films 11e and 11f are patterned using a photoengraving technique and an etching technique, and a semiconductor film area 11b made of a semiconductor film into which no impurity is introduced and a semiconductor film made up of a semiconductor film into which an impurity is introduced A third monitor pattern 11 made of a semiconductor film 11a having a region 11c is formed. At this time, the gate electrode of the transistor is simultaneously formed in the chip region. Here, the gate insulating film 25 may be removed by performing an etching process on the gate insulating film 25 except the regions under the third monitor pattern 11 and the gate electrode.

  Even with such a method, it is possible to form the third monitor pattern 11 including the semiconductor film region 11b having the semiconductor film region 11b into which impurities are not introduced and the semiconductor film region 11c into which impurities are introduced.

The monitor patterns 7, 9, and 11 need to be large enough to be detected as defects by the appearance inspection apparatus. Specifically, the size needs to be 0.1 μm or more. Further, since the watermark is often formed with a size of several μm to several mm, the monitor patterns 7, 9, and 11 are more preferably 10 μm or more.
Further, since the monitor patterns 7, 9, 11 are arranged in the scribe line area 5, the dimensions of the monitor patterns 7, 9, 11 in the width direction of the scribe line area 5 are larger than the width dimension of the scribe line area 5. small.

  A chip area where it is difficult to confirm the presence or absence of a watermark by performing cleaning and drying in a state where the monitor patterns 7, 9, and 11 are formed, and confirming with a visual inspection apparatus capable of seeing pattern defects. The presence or absence of a watermark can be confirmed without looking at the screen.

  In addition, these monitor patterns 7, 9, and 11 are not produced in the chip area 3, but are produced in the mass-produced scribe line area 5, so that a dedicated wafer for watermark monitoring is produced on the production line. By inspecting the monitor patterns 7, 9, and 11 formed in the scribe line region 5 for mass-produced products, it is possible to constantly monitor the presence or absence of the watermark. Further, since the scribe line region 5 exists everywhere in the surface of the semiconductor wafer 1, if the monitor patterns 7, 9, 11 are arranged in the scribe line region 5 in the entire region of the semiconductor wafer 1, a wide range is obtained. Information can be collected.

  Further, as described above, each of the monitor patterns 7, 9, and 11 can be used to detect the occurrence of a watermark when the formation of the monitor patterns 7, 9, and 11 is completed. However, if the film formed on the upper layer of the monitor patterns 7, 9, 11 in the process after the formation of the monitor patterns 7, 9, 11 is removed in the region where the monitor patterns 7, 9, 11 are formed. The monitor patterns 7, 9, and 11 can also be used to detect the occurrence of a watermark in the process after the monitor patterns 7, 9, and 11 are formed.

  For example, the third monitor pattern 11 is formed after the monitor patterns 7 and 9 are formed, but when the third monitor pattern 11 is formed, that is, when the formation of the gate electrode made of a semiconductor film is completed, the monitor pattern 7 is formed. , 9 is exposed, it is possible to detect the occurrence of a watermark when the formation of the third monitor pattern 11 is completed by the three types of monitor patterns 7, 9, 11.

  As mentioned above, although the Example of this invention was described, material, a shape, arrangement | positioning, etc. are examples, this invention is not limited to these, Various within the range of this invention described in the claim Can be changed.

It is a top view which shows roughly the pattern for watermark monitors of one Example. It is a top view which shows the whole semiconductor wafer of one Example. It is a schematic process sectional drawing for demonstrating the example of a manufacturing process of the pattern for 1st monitors. It is a schematic process sectional drawing for demonstrating the example of a manufacturing process of the pattern for 2nd monitors. It is a schematic process sectional drawing for demonstrating the example of a manufacturing process of the pattern for 3rd monitors. It is a schematic process sectional drawing for demonstrating the other example of the manufacturing process of the pattern for 3rd monitors.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 3 Chip area 5 Scribe line area 7 First monitor pattern 9 Second monitor pattern 9a Insulating material pattern 11 Third monitor pattern 11a Semiconductor film 11b First semiconductor film area 11c Second semiconductor film area 13 Semiconductor substrate

Claims (4)

In a semiconductor wafer in which a plurality of chip regions separated from each other by a scribe line region are arranged in a matrix on a semiconductor substrate,
In the scribe line area, as a monitor pattern for the watermark, a first monitor pattern made of a recess formed on the surface of the semiconductor substrate, and a second monitor pattern made of a plurality of insulating material patterns formed on the surface of the semiconductor substrate And a first semiconductor film region in which no impurity is introduced and a second semiconductor in which an impurity formed adjacent to the first semiconductor film region is introduced. A semiconductor wafer comprising at least one of third monitor patterns comprising a film region.   The semiconductor wafer according to claim 1, wherein a planar size of the watermark monitor pattern is 10 μm or more.   3. The semiconductor wafer according to claim 1, wherein a plurality or all of the first monitor pattern, the second monitor pattern, and the third monitor pattern are provided as the watermark monitor pattern. Using the semiconductor wafer according to any one of claims 1 to 3,
A method for monitoring a semiconductor wafer, wherein the occurrence of a watermark is detected by visual inspection of the watermark monitor pattern.

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