JP2010093011A - Apparatus for manufacturing semiconductor device and method for manufacturing the semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To manufacture a reliable semiconductor device efficiently. <P>SOLUTION: This semiconductor device has: a depressurized chamber 62; a substrate holder 64 for supporting a plurality of semiconductor substrates 1 having an exposed resist film 49 inside the chamber 62; a gas feed pipe 71 provided outside of an area with the substrate holder 64 disposed therein, and having feed holes 72 for feeding oxygen gas into the chamber 62 in a plurality of places; an exhaust pipe 74 provided with an exhaust hole for sucking in a fluid inside the chamber 62; and a high frequency power source 66 for activating the oxygen gas for ashing the resist film 49. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing apparatus and a semiconductor device manufacturing method, and more particularly, to a manufacturing apparatus and a manufacturing method of a ferroelectric memory including a ferroelectric capacitor formed on a semiconductor substrate and holding data. .

  In recent years, with the progress of digital technology, there is an increasing tendency to process or store a large amount of data at high speed. For this reason, high integration and high performance of semiconductor devices used in electronic devices are required.

  Therefore, for a semiconductor memory device, for example, in order to achieve high integration of DRAM (Dynamic Random Access Memory), as a capacitive insulating film of a capacitive element constituting the DRAM, instead of conventional silicon oxide or silicon nitride, Technologies using ferroelectric materials or high dielectric constant materials are beginning to be widely researched and developed. As such a semiconductor memory device, a nonvolatile memory such as a flash memory or a ferroelectric memory (FeRAM), in which stored information is not lost even when the power is turned off, is known.

A ferroelectric memory stores information by utilizing the hysteresis characteristic of a ferroelectric that constitutes a ferroelectric capacitor. A ferroelectric capacitor has a configuration in which a ferroelectric film is sandwiched between a pair of electrodes, an upper electrode and a lower electrode. Here, the lower electrode, for example, platinum film is used, the ferroelectric film, the remnant polarization amount is 10μC _/ cm ² ~30μC _/ cm 2 of about PZT (Pb (Zr, Ti) O 3) film Ya A ferroelectric oxide having a perovskite crystal structure such as an SBT (SrBi ₂ Ta ₂ O ₉ ) film is mainly used. For example, an iridium oxide film is used for the upper electrode.

  By the way, it is known that when moisture enters this type of ferroelectric film from the outside, it reacts with oxygen in the film to generate oxygen defects and deteriorate crystallinity. Degradation of the crystallinity of the ferroelectric film causes performance degradation such as a decrease in residual polarization and dielectric constant. In order to prevent such performance degradation, conventionally, after forming a ferroelectric capacitor, a barrier film made of an aluminum oxide film, a titanium oxide film, or the like is formed to cover the entire ferroelectric capacitor to prevent moisture from entering. It was preventing.

  After covering the ferroelectric capacitor with the barrier film, an interlayer insulating film and a metal wiring are formed. When forming the metal wiring, first, the interlayer insulating film is etched to form a via hole that exposes each of the lower electrode and the upper electrode, and a metal is buried in the via hole to form a plug. Further, metal wiring is formed on the plug. For example, when forming a via hole communicating with the upper electrode, a resist film is applied on the interlayer insulating film, and then an opening is formed above the upper electrode by lithography. Etching is then performed using the resist film as a mask. When the etching is completed, the resist is removed with an ashing apparatus.

Here, the conventional ashing apparatus employs a single wafer type. The apparatus configuration includes a chamber capable of accommodating one substrate on which a ferroelectric capacitor is formed, and a gas ejection portion disposed in the chamber so as to face the substrate, and is disposed between the substrate and the gas ejection portion by an elevating mechanism. The distance can be adjusted. At the time of ashing, oxygen gas is supplied from the gas jetting part, oxygen radicals are generated, and the resist film is removed by ashing. Carbon dioxide, carbon monoxide, water, and the like generated at this time are moved from the substrate surface in a gas state and discharged.
Japanese Patent Laid-Open No. 62-165923

However, the single-wafer type ashing apparatus has a low productivity because the substrates are processed one by one.
Further, when the resist is removed by a conventional ashing apparatus, the performance of the ferroelectric film may be deteriorated. This is because, when ashing is performed with the lower electrode exposed in the previous process, hydrogen generated when the resist is decomposed deprives oxygen in the ferroelectric film by the catalytic action of platinum constituting the lower electrode. This is thought to be due to the deterioration of the ferroelectric film. Such a phenomenon occurred remarkably in a region close to the portion where the lower electrode film was exposed.
The present invention has been made in view of such circumstances, and a main object of the present invention is to enable efficient manufacture of a highly reliable semiconductor device.

  According to one aspect of the present invention, a chamber to be decompressed, a substrate holder that supports a plurality of semiconductor substrates having an exposed resist film in the chamber, an outside of a region where the substrate holder is disposed, and the chamber A gas supply pipe having a plurality of supply holes for supplying oxygen gas therein, an exhaust pipe provided with an exhaust hole for sucking the fluid in the chamber, and activating the oxygen gas for ashing the resist film And a high-frequency power source for manufacturing the semiconductor device.

  According to another aspect of the present invention, a step of disposing a plurality of semiconductor substrates on which a resist film having a pattern exposing a noble metal film is disposed on the outer periphery of the substrate holder in the chamber, and the outer periphery of the substrate holder. A step of supplying oxygen from the gas supply holes of the plurality of gas supply pipes toward each of the resist films of the semiconductor substrate, and generating a plasma of oxygen by generating a high-frequency electric field in a reduced-pressure atmosphere in the chamber And a step of ashing the resist film. A method of manufacturing a semiconductor device is provided.

  According to the present invention, oxygen gas can be sufficiently supplied to a semiconductor substrate in a batch type ashing process. As well as preventing variations in ashing, productivity can be improved as compared to the conventional single wafer type. In addition, the flow from the gas supply pipe to the exhaust pipe through the center on the semiconductor substrate is formed, so that the retention of reaction products during ashing is prevented, and the performance deterioration of the ferroelectric film can be prevented. it can.

(First embodiment)
A first embodiment of the present invention will be described in detail with reference to the drawings.
1A to 1I are cross-sectional views of the semiconductor device according to the first embodiment of the present invention during manufacture. The present embodiment relates to a method of manufacturing a semiconductor device (ferroelectric memory) having a planar structure capacitor, and a semiconductor device manufacturing apparatus.

First, steps required until a sectional structure shown in FIG. 1A is obtained will be described.
First, an element isolation insulating film 2 that defines an active region of a transistor is formed on the surface of an n-type or p-type silicon substrate 1 (semiconductor substrate). In this embodiment, the element isolation insulating layer 2 is formed by a LOCOS (Local Oxidation of Silicon) method. The element isolation insulating layer 2 may be shallow trench isolation (STI) formed by forming a trench in the element isolation region of the silicon substrate 1 and embedding an insulating film such as silicon oxide therein. .

  Next, a p-type impurity such as boron is introduced into the transistor active region in the memory cell region of the silicon substrate 1 to form a p-well 3. Then, the surface of the transistor active region is thermally oxidized to form the gate insulating film 5. In this case, the gate insulating film 5 is a silicon oxide film formed by thermal oxidation and has a thickness of about 6 to 7 nm.

  Further, after an amorphous silicon film, a tungsten silicide film, and a silicon oxide film are sequentially formed on the entire surface of the silicon substrate 1 by a CVD method, the silicon film and the tungsten silicide are patterned by using a photolithography technique. Gate electrodes 6A and 6B are formed from the film. For example, the silicon film is about 50 nm thick, the tungsten silicide film is about 150 nm, and the silicon oxide film is about 45 nm, for example.

Two gate electrodes 6A and 6B are formed in parallel with each other on the p-well 3, and each of them constitutes a part of a word line. Further, by ion implantation using the gate electrodes 6A and 6B as masks, n-type impurities such as phosphorus are introduced into the surface layer of the silicon substrate 1 on both sides of the gate electrodes 6A and 6B, and source / drain extensions 8A and 8B having low impurity concentrations are introduced. Form.
Thereafter, an insulating film is formed on the entire upper surface of the silicon substrate 1 including the gate electrodes 6A and 6B, and the insulating film is etched back to form insulating sidewalls 10 leaving only both side portions of the gate electrodes 6A and 6B. To do. For the insulating film, for example, a silicon oxide film formed by a CVD method is used.

  Subsequently, n-type impurities such as arsenic are ion-implanted again into the surface layer of the silicon substrate 1 using the insulating sidewall 10 and the gate electrodes 6A and 6B as a mask, and the silicon substrate 1 beside the gate electrodes 6A and 6B is implanted. Source / drain regions 11A and 11B (high concentration impurity diffusion regions) are formed.

  Up to this step, two MOS transistors T1 and T2 constituted by the gate insulating film 5, the gate electrodes 6A and 6B, the source / drain regions 11A and 11B, and the like are formed for each active region of the silicon substrate 1.

  Next, a silicon oxynitride (SiON) film having a thickness of about 200 nm is formed as an antioxidant insulating film 13 (cover film) on the entire upper surface of the silicon substrate 1 including the gate electrodes 6A and 6B by plasma CVD. Further, a non-doped silicate glass (NSG) film having a thickness of about 600 nm is formed on the antioxidant insulating film 13 as the first interlayer insulating film 14 by plasma CVD using TEOS (tetra ethoxy silane) gas. Then, the surface of the first interlayer insulating film 14 is polished and planarized by about 200 nm by a chemical mechanical polishing (CMP) method.

Next, steps required until a sectional structure shown in FIG. From FIG. 1B to the following FIG. 1H, a part of one MOS transistor T1 shown in FIG. 1A is omitted.
First, an NSG film having a thickness of 100 nm is formed as a second interlayer insulating film 18 on the first interlayer insulating film 14 by plasma CVD using TEOS. Subsequently, the first and second interlayer insulating films 14 and 18 are dehydrated for about 30 minutes by setting the substrate temperature to 650 ° C. in a nitrogen atmosphere, for example.
Next, a first antioxidant film 19 is formed on the second interlayer insulating film 18. As the first antioxidant film 19, alumina (Al ₂ O ₃ ) is formed to a thickness of 20 nm by a PVD method such as sputtering.

Next, an alumina (Al ₂ O ₃ ) film is formed on the first antioxidant film 19 as a lower electrode adhesion film 24 to a thickness of about 20 nm by sputtering. Thereafter, the lower electrode adhesion film 24 is oxidized for 60 seconds in an oxygen atmosphere at 650 ° C. by rapid thermal annealing (RTA).

  Subsequently, a lower electrode film 25 (lower conductive film) that is a first metal film is formed on the lower electrode adhesion film 24. As the lower electrode film 25, for example, a Pt film formed by sputtering is used, and its thickness is about 155 nm. The lower electrode film 25 is preferably a noble metal film such as an Ir film or a Ru film.

Next, steps required until a sectional structure shown in FIG.
A PZT film as a ferroelectric film 27 is formed on the lower electrode film 25 to a thickness of 150 nm to 200 nm by, for example, sputtering.
Thereafter, heat treatment is performed by RTA in order to crystallize the ferroelectric film 27. The heat treatment condition is, for example, about 563 ° C. and 90 seconds in an atmosphere in which argon and oxygen are mixed. In this case, argon gas is allowed to flow at a flow rate of about 1.95 milliliters (ml) / min and oxygen gas at a flow rate of 0.55 ml / min.
Further, a first upper electrode film 29 and a second upper electrode film 30 are sequentially formed on the upper surface of the ferroelectric film 27 by a PVD method such as sputtering.

Here, an iridium oxide film is formed as the first upper electrode film 29. Thereafter, the first upper electrode film 29 is heat-treated by RTA. The heat treatment conditions are, for example, about 708 ° C. and 90 seconds in an atmosphere in which argon and oxygen are mixed. In this case, argon gas is supplied at a flow rate of about 2.00 ml / min and oxygen gas is supplied at a flow rate of 0.02 ml / min.
Further, an iridium oxide film is formed as the second upper electrode film 30 on the first upper electrode film 29 by the PVD method. The conditions may be different from those of the first upper electrode film 29. For example, the gas flow ratio of oxygen is increased.
Thereafter, a photoresist is applied onto the second upper electrode film 30, and this is exposed and developed, thereby forming a resist pattern 34 in the shape of the upper electrode of the capacitor. Further, the first and second upper electrode films 29 and 30 are etched using the resist pattern 34 as a mask.

Then, the first and second upper electrode films 29 and 30 left under the resist pattern 34 are used as the upper electrode 35 of the capacitor. After the etching, the resist pattern 34 is removed. For example, a plurality of upper electrodes 35 are formed at intervals along the word lines.
Thereafter, the resist pattern 32 is removed. Next, the silicon substrate 1 is put into a vertical furnace, and heat treatment is performed for 60 minutes in an oxygen atmosphere at a substrate temperature of 650 ° C., for example. The amount of oxygen introduced into the vertical furnace is, for example, 20 liters / minute. The vertical furnace is a batch type in which a plurality of silicon substrates 1 can be placed.

  Next, the ferroelectric film 27 is patterned into a stripe shape by etching using a photoresist pattern as a mask (not shown). As shown in FIG. 2A, the ferroelectric film 27 has, for example, a rectangular planar shape that extends in a direction substantially parallel to the word line and passes under the plurality of upper electrodes 35. Next, the silicon substrate 1 is placed in an oxygen atmosphere in a vertical furnace, and the substrate temperature is set to 300 ° C. to 400 ° C., for example, 350 ° C., and heat treatment is performed for 30 minutes to 120 minutes, for example, 60 minutes. For example, the oxygen introduced into the oxygen atmosphere is 20 liters / minute.

Thereafter, as shown in FIG. 1E, an Al ₂ O ₃ film having a thickness of about 50 nm is formed on the upper electrode 35 and the ferroelectric film 27 as the first protective film 41 by, for example, sputtering, CVD, or ALD. Form. Thereafter, the silicon substrate 1 is placed in an oxygen atmosphere in a vertical furnace, for example, and the substrate temperature is set to 500 ° C. to 700 ° C., for example, 550 ° C., and heat treatment is performed for 30 minutes to 120 minutes, for example, 60 minutes. For example, the oxygen introduced into the oxygen atmosphere is 20 liters / minute.

Next, steps required until a sectional structure shown in FIG.
A photoresist film is formed on the entire surface of the first protective film 30 by, eg, spin coating. The photoresist film is patterned into a predetermined planar shape, that is, the planar shape of the lower electrode of the ferroelectric capacitor by photolithography.
Subsequently, the first protective film 41 and the lower electrode film 25 are etched using the patterned photoresist film as a mask to form a lower electrode 36 made of the lower electrode film 25. Thereafter, the photoresist film is removed.
The lower electrode 36 has a substantially rectangular planar shape. The end portion is sized to protrude from the ferroelectric film 27 as shown in the side sectional view of FIG. 2B. A ferroelectric capacitor 37 is formed by the upper electrode 35, the ferroelectric film 27, and the lower electrode 36 thus patterned.
In FIG. 1F to FIG. 1H, the lower electrode 36 does not actually appear, but in order to make the structure of the ferroelectric capacitor 37 easier to understand, the end of the lower electrode 36 protruding to the back side in the figure is on the right side. Protrusively described.

  Subsequently, the silicon substrate 1 is placed in a vertical furnace, and heat treatment is performed for 60 minutes in an oxygen atmosphere, for example, at a substrate temperature of 650 ° C. The amount of oxygen introduced into the vertical furnace is, for example, 20 liters / minute.

Further, after removing the photoresist film, an Al ₂ O ₃ film is formed as the second protective film 42 on the ferroelectric capacitor 37 and the second interlayer insulating film 19 by, for example, a sputtering method, a CVD method, or an ALD method. .
Thereafter, the silicon substrate 1 is placed in an oxygen atmosphere of a vertical furnace, and the substrate temperature is set to, for example, 500 ° C. to 700 ° C., for example, 550 ° C. In this case, the flow rate of the oxygen gas introduced into the oxygen atmosphere is set to 20 liters / minute, for example. As a result, oxygen is supplied to the ferroelectric film 27 and the electrical characteristics of the ferroelectric capacitor 37 are recovered.

Next, steps required until a sectional structure shown in FIG.
An NSG film having a thickness of 1500 nm is formed as a third interlayer insulating film 43 on the entire surface of the second protective film 42 by, for example, a plasma CVD method using TEOS. Thereafter, the surface of the third interlayer insulating film 43 is planarized by, eg, CMP.

Next, heat treatment is performed, for example, at 350 ° C. for 2 minutes in a plasma atmosphere generated using N ₂ O gas or N ₂ gas. As a result of the heat treatment, moisture in the third interlayer insulating film 43 is removed, and the film quality of the third interlayer insulating film 43 changes, making it difficult for moisture to enter the film. By this heat treatment, the surface of the third interlayer insulating film 43 is nitrided to form a SiON film.

Next, steps required until a sectional structure shown in FIG.
First, the third interlayer insulating film 43 to the antioxidant insulating film 13 are patterned by a photolithography method using a photoresist to form contact holes 15A and 15B having a depth reaching the source / drain regions 11A and 11B. .

Then, conductive plugs 16A and 16B electrically connected to the source / drain regions 11A and 11B are formed in the contact holes 15A and 15B. Specifically, a titanium (Ti) film having a thickness of 20 nm and a titanium nitride (TiN) film having a thickness of 50 nm are sequentially formed on the inner surfaces of the contact holes 15A and 15B by a PVD method such as sputtering. An adhesion film (glue film) 17A having a two-layer structure is produced. Further, a tungsten (W) film 17B is grown on the adhesion film 17A by the CVD method. This film thickness is, for example, 500 nm on the first interlayer insulating film 14, and the W film 17B fills the spaces of the contact holes 15A and 15B.
Excess W film 17B and adhesion film 17A grown on the upper surface of first interlayer insulating film 14 are removed by CMP. Thereby, conductive plugs 16A and 16B made of the W film 17B and the adhesion film 17A are formed in the contact holes 15A and 15B, respectively.

Next, in order to nitride the surface of the third interlayer insulating film 43, for example, a CVD apparatus is used, and plasma annealing is performed on the third interlayer insulating film 43 in the chamber. The plasma annealing is performed, for example, by flowing N ₂ O into the chamber to generate the plasma and setting the substrate temperature at 350 ° C. for about 2 minutes.
Subsequently, an antioxidant film 48 is formed on the third interlayer insulating film 43 and the conductive plugs 16A and 16B. As the antioxidant film 48, a SiON film having a thickness of 100 nm is formed by plasma CVD.

Next, a resist film 49 is formed on the upper surface of the antioxidant film 48, and this is exposed and developed to form an opening on the contact region at one end of the upper electrode 35 and the lower electrode of the ferroelectric capacitor 37. An organic compound such as a novolac resist or a chemically amplified resist is used as the resist film 49, and contains an element such as carbon, hydrogen, or nitrogen.
Subsequently, the antioxidant film 48, the third interlayer insulating film 43, the first, second, and second protective films 41 and 42 are etched by using the resist film 49 as a mask so as to penetrate through these films and ferroelectric. A via hole 46 reaching the upper electrode 35 of the body capacitor 37 is formed. At the same time, as shown in the side sectional view of FIG. 2C, the antioxidant film 48, the third interlayer insulating film 43, the first, second, and second protective films 41 and 42 are etched using the photoresist film 49, A via hole 47 reaching the lower electrode 36 of the dielectric capacitor 37 is formed.

  Next, the silicon substrate 1 is carried into an ashing apparatus, and the resist film 49 is removed with oxygen gas. Details of the ashing apparatus and process will be described in detail later.

Thereafter, heat treatment is performed for 30 minutes to 120 minutes, for example 60 minutes, in an oxygen atmosphere at 400 ° C. to 600 ° C., for example, 500 ° C. in a vertical furnace. For example, oxygen gas is introduced into the furnace at a flow rate of 20 liters / minute.
As a result, oxygen is supplied to the ferroelectric film 27 and the electrical characteristics of the ferroelectric capacitor 37 are recovered. Note that this heat treatment may be performed not in an oxygen atmosphere but in an ozone atmosphere. Subsequently, the antioxidant film 48 is removed by etching back, and the upper surface of the third interlayer insulating film 43 is exposed.

Next, steps required until a sectional structure shown in FIGS. 1H and 2D is obtained will be described.
First, for example, a TiN film having a thickness of 150 nm, a copper aluminum alloy film having a thickness of 550 nm, a Ti film having a thickness of 5 nm, and a TiN film having a thickness of 150 nm are sequentially formed on the third interlayer insulating film 43. The film is formed by PVD, for example, sputtering. These conductive films are first-layer metal wiring films and fill the via holes 46 and 47 to function as conductive plugs.

Then, using a photoresist (not shown), the first layer metal wiring film is patterned to form wiring.
Here, the wiring 55A connected to the upper electrode 35 is connected to one source / drain region 11B of the side MOS transistor T2 (T1) through the conductive plug 16B. Also, the wiring 55B connected to the lower electrode 36 through the via hole 47 is connected to the plate line of the memory cell. Further, the pattern 56A of the metal wiring film that remains isolated on the conductive plug 16A connected to the shared source / drain region 11A among the two MOS transistors T1 and T2 in the same p-well 3 is the bit line Conductive pad 56A.
Thereafter, although not particularly shown, an interlayer insulating film, a conductive plug, a wiring and the like are sequentially formed on the wirings 55A and 55B, the conductive pad 56A and the third interlayer insulating film 43 to complete the ferroelectric memory cell. .

Next, the process of removing the resist film 49 used to form contact holes on the upper electrode 35 and the lower electrode 36 of the ferroelectric capacitor shown in FIGS. 1G and 2C will be described in detail. To do.
First, as shown in FIGS. 3 and 4, an ashing device 61 used for manufacturing a semiconductor device has a hollow chamber 62 and holds a plurality of silicon substrates 1 in a processing chamber 63 in the chamber 62. The holder 64 can be inserted.

  An external electrode 65 is provided on the outer peripheral wall of the chamber 62, and the external electrode 65 is connected to a high frequency power source 66 having a frequency of 13.56 MHz, for example. In addition, a cylindrical internal electrode 67 made of a wire mesh is disposed in the processing chamber 63. The internal electrode 67 is grounded, and the two electrodes 65 and 67 constitute a counter electrode. Control of the high frequency power supply 66 and movement of the substrate holder 64 are performed by the control device 68.

For example, eight gas supply pipes 71 are inserted at equal intervals in the circumferential direction between the inner wall surface of the chamber 62 and the wire mesh internal electrode 67. These gas supply pipes 71 are connected to a gas source (not shown), and an ashing gas, for example, oxygen gas is flowed from the upper side to the lower side.
As shown in FIG. 5, the gas supply pipe 71 has a plurality of supply holes 72 formed at equal intervals in the length direction. The opening area of each supply hole 72 is constant regardless of the location. One or more supply holes 72 are formed with respect to one silicon substrate 1.
By providing a plurality of supply holes 72, variation in the amount of oxygen gas in the processing chamber 63 is improved, and oxygen gas can be supplied uniformly to a large number of silicon substrates 1.

Further, like the supply hole 73 shown in FIG. 6, the uppermost opening area may be the smallest, gradually increase toward the lower side, and the lowest may be the largest. In this case, the size of each supply hole 73 and the increase amount of the opening area are set so that the amount of gas to be ejected is substantially constant regardless of the location.
These supply holes 73 are formed at a ratio of one or more to one silicon substrate 1. By using such a supply hole 73, the supply amount of oxygen gas supplied to each silicon substrate 1 becomes substantially constant without being affected by the distance of the gas source, and ashing can be performed more evenly. .

  Further, one exhaust pipe 74 is inserted from the top to the bottom in the center of the chamber 62. The exhaust pipe 74 is provided with at least one exhaust hole (not shown). The exhaust pipe 74 extends in parallel with the gas supply pipe 71, is drawn out from the upper part of the chamber 62, and is connected to a vacuum pump (not shown). When only one exhaust hole is provided in the exhaust pipe 74, it is preferably provided at the lower end of the exhaust pipe 74.

  The substrate holder 64 is mounted on a vertically movable stage 76 provided below the chamber 62. The substrate holder 64 has a cylindrical shape extending in parallel with the center line of the chamber 62. The shape orthogonal to the center line is an octagon, and each surface 78 is slightly inclined with respect to the central axis so that the lower side is widened. A large number of support members 79 that support the silicon substrate 1 from below are attached to the outside of each surface 78.

  For example, as shown in FIG. 7, the support member 79 is a lower outer edge portion of the silicon substrate 1 and has a shape that supports the peripheral area of the wafer where the ferroelectric memory is not formed. Since each surface 78 of the substrate holder 64 is inclined with respect to the central axis, the silicon substrate 1 is inclined such that the upper portion thereof is closer to the center line of the chamber 62 than the lower portion.

  The inclination angle of each surface 78 is such that the silicon substrate 1 can be reliably prevented from falling toward the internal electrode 67. Therefore, the distance between the silicon substrate 1 supported on the upper end side and the supply holes 72 and 73 of the gas supply pipe 71 and the distance between the silicon substrate 1 supported on the lower end side and the supply holes 72 and 73. There is no big difference.

  In this embodiment, since the substrate holder 64 is octagonal in plan view, eight silicon substrates 1 are supported in the circumferential direction. Further, a plurality of, for example, six pieces can be held in the vertical direction, and a maximum of 48 silicon substrates 1 can be supported. Further, although not shown, the substrate holder 64 is provided with a plurality of gas passage portions through which gas can pass. As such a configuration, for example, each surface of the substrate holder 64 is formed in a mesh shape, or the substrate holder 64 is formed in a frame shape.

  The planar shape of the substrate holder 64 may be any shape as long as the exhaust pipe 74 can be passed through the central portion, such as a triangle, a quadrangle, a pentagon, and a hexagon, in addition to an octagon. Moreover, the number and form of the openings for allowing the gas to pass therethrough and the number of the silicon substrates 1 held are not limited to the above. The number of gas supply pipes 71 arranged in the circumferential direction is preferably made to coincide with the number of silicon substrates 1 that can be arranged in a plan view. Different piping structures may be used as long as they are arranged toward 73.

When performing ashing processing, the following operations are performed.
First, the stage 76 is lowered, the substrate holder 64 is pulled out from below the chamber 62, and the supporting members 79 support the required number of silicon substrates 1. At this time, each of the silicon substrates 1 is supported so that the resist film 49 is disposed outside.
Subsequently, the stage 76 is raised to introduce the substrate holder 64 into the chamber 62. When the bottom of the chamber 62 is sealed with a flange 76A provided at the top of the stage 76, the processing chamber 63 is evacuated from the exhaust pipe 74. When the degree of vacuum in the processing chamber 63 reaches a predetermined value, oxygen gas is supplied from each gas supply pipe 71. Further, a high frequency voltage is applied from the high frequency power supply 66 to the external electrode 65.

Plasma is generated between the external electrode 65 and the internal electrode 67, and oxygen radicals and oxygen ions (O ⁺ ) are generated from the oxygen gas. Since the inside of the processing chamber 63 is forcibly exhausted by the exhaust pipe 74, oxygen radicals are guided from the outer peripheral portion of the chamber 62 to the substrate surface. At this time, oxygen radicals react with the constituent elements of the resist film 49 directed toward the supply holes 72 and 73 to perform ashing, and thus hydroxyl groups (OH), nitrogen oxides (NO, NO ₂ ), carbon oxides (CO, CO _2). ), Hydrogen (H), water (H ₂ O) and the like are generated. These reaction products and excess oxygen are discharged from the exhaust pipe 74 through the opening of the substrate holder 64.

In the ashing apparatus 61 according to this embodiment, a large number of silicon substrates 1 are arranged so that the resist film 49 is directed to the supply holes 72 and 73 of the gas supply pipe 71, so that a large number of silicon substrates 1 are processed at a time. Work efficiency is improved.
Further, since a smooth flow of fluid from the gas supply pipe 71 through the silicon substrate 1 to the exhaust pipe 74 is formed, it becomes possible to always supply oxygen radicals to the substrate surface, and oxygen deficiency occurs. Is prevented. Even when hydrogen is generated as a reaction product, it is quickly discharged from the substrate surface by forced exhaust.

  Since oxygen gas is ejected from a large number of supply holes 72 as shown in FIG. 5, a necessary amount of oxygen radicals can be supplied to each silicon substrate 1 substantially evenly. Furthermore, as shown in FIG. 6, when the supply holes 73 having different sizes depending on the location are used, the oxygen gas is ejected substantially uniformly regardless of the location, so that the ashing caused by the supply amount of the oxygen gas can be prevented. Variations can be prevented.

Here, the performance deterioration of the ferroelectric capacitor 37 occurring during the ashing process will be considered with reference to FIG.
When the resist film 49 was ashed using a conventional ashing apparatus with the Pt film as the lower electrode 36 exposed from the contact hole 47 at the end thereof, the performance of the ferroelectric film 27 near the via hole 47 deteriorated. This is considered to be because when hydrogen reaches the lower electrode 36 through the via hole 47, hydrogen is easily combined with oxygen in the PZT film constituting the ferroelectric film 27 by the catalytic action of Pt.
If oxygen loss of the PZT film occurs from the upper electrode 35 side, the performance deterioration occurs over a wide range without being limited to the vicinity of the via hole 47 formed on the end of the lower electrode 36. The phenomenon was not confirmed, and characteristic deterioration occurred only in the vicinity of the via hole 47. This is presumably because the upper electrode 35 is formed of an IrO _x film, so that the reduction action hardly occurs.

Therefore, it is considered that when hydrogen generated by ashing of the resist film 49 reaches the end of the lower electrode 36, the performance of the ferroelectric capacitor 37 formed in the vicinity thereof is deteriorated.
In contrast, in the present embodiment, the oxygen supply to the resist film 49 and the contact hole 47 is efficiently supplied to the resist film 49, and hydrogen generated by ashing is quickly discharged. Thereby, the reaction between Pt of the lower electrode 36 and hydrogen is prevented, and the performance deterioration of the ferroelectric capacitor 37 is prevented.

Next, FIG. 9 shows a result of examining fatigue deterioration of a chip of a ferroelectric memory obtained from the silicon substrate 1 processed by the ashing device 61 at a plurality of positions of the silicon substrate 1.
In FIG. 9, the horizontal axis indicates the position of the chip, the center of the silicon substrate 1 is “1”, the outer edge is “7”, and the intervals are “2” to “6” in order.
A line L11 in FIG. 9 shows fatigue deterioration when processed by a conventional batch type ashing apparatus provided with one gas supply pipe and one exhaust pipe. Conventionally, the fatigue deterioration at the center portion of the silicon substrate 1 is large and the fatigue deterioration is small at the peripheral portion.
On the other hand, as shown by the line L12, in this embodiment, the fatigue deterioration of the central portion of the silicon substrate 1 is greatly improved. Furthermore, the variation in fatigue deterioration due to the location on the silicon substrate 1 was also greatly improved.
The conventional batch type ashing apparatus has a structure in which oxygen gas is supplied and exhausted from one hole, and a plurality of silicon substrates are arranged in the surface direction, and the silicon substrates are spaced vertically. It has a structure that is arranged in a stacked manner.

  Further, as a comparative example, the result of examining the relationship between the position on the substrate and the fatigue deterioration when the conventional single-wafer ashing device is used for the line L13 is shown. In the single wafer type, the variation in fatigue deterioration depending on the location was small, but overall, the fatigue deterioration was high. In the ashing device 1 according to the above-described embodiment, the fatigue deterioration value and the variation depending on the location are improved as compared with the single wafer type shown in the line L13.

  Further, in the conventional batch type ashing apparatus, the fatigue deterioration varies depending on the position where the silicon substrate is set in the ashing apparatus. That is, the deterioration of the fatigue property tends to increase in the second and subsequent silicon substrates from the top. Such a phenomenon is considered to be due to the narrow space between the two silicon substrates arranged vertically. That is, when oxygen radicals are consumed at the peripheral portion of the silicon substrate, the amount of oxygen radicals supplied to the central portion of the silicon substrate through a narrow space between the silicon substrates decreases. Furthermore, hydrogen generated by ashing the resist stays in the narrow space. From these facts, it is considered that the resist in the central portion of the silicon substrate 1 is hardly ashed.

The peripheral portion near the gas supply pipe is sufficiently supplied with oxygen radicals, and the oxygen flow can be performed relatively smoothly, so that the ashing speed is increased. Further, ashing is promoted because oxygen radicals are supplied around a wide space outside the silicon substrate at the peripheral portion of the silicon substrate even in the vicinity of the exhaust pipe. In such a position, since the exhaust pipe is close, the reaction product can be easily discharged.
That is, since there is an annular space in the outer peripheral portion of the silicon substrate, sufficient oxygen is secured and sufficient ashing is possible.
Further, since the air flow around the outer periphery of the silicon substrate is increased, oxygen ions that are accelerated and supplied to the inside and the reactants generated by the collision thereof are pushed inward and are likely to stay. In addition, oxygen ions generated on the outside react in the peripheral region of the silicon substrate, and oxygen ions supplied to the inside decrease.

As a result, in the conventional batch type ashing apparatus, the resist film is less likely to be ashed at the central part of the silicon substrate stacked at intervals than the peripheral part, and hydrogen is likely to stay. Degradation of the performance of the ferroelectric capacitor is likely to occur.
On the other hand, in the above embodiment, hydrogen does not stay as compared with the conventional configuration in which the silicon substrates are stacked one above the other, so that the reaction of hydrogen around the Pt film serving as a catalyst can be suppressed. Thereby, the performance deterioration of the ferroelectric capacitor 37 is prevented, and the fatigue deterioration of the ferroelectric memory can be improved. Conventionally, since the fatigue characteristics are partially deteriorated, the operation can be guaranteed only up to 1 × 10 ¹⁰ times, whereas in this embodiment, the operation can be guaranteed up to 1 × 10 ¹¹ times.

Here, a modified example of the ashing device according to the embodiment of the present invention will be described.
The gas supply pipe 71 may be configured such that one supply hole 72, 73 is arranged for one silicon substrate. In each of the supply holes 72 and 73, the distance to the silicon substrate 1 disposed to face each other is substantially constant. As a result, oxygen radicals are supplied more evenly to the silicon substrate 1 and ashing variations are prevented. By performing ashing evenly, variations in the quality of the ferroelectric memory can be prevented. If the exhaust holes of the exhaust pipe 74 correspond to the arrangement of the silicon substrates 1 and the supply holes 72 and 73 and are provided in the same number as the supply holes 72 and 73, the distance from the silicon substrate 1 to the exhaust holes. Is also almost constant. Since the discharge amount of oxygen radicals and reaction products is substantially constant in each silicon substrate 1, ashing variation can be further prevented.

  Further, one supply hole 72 and 73 may be arranged for one silicon substrate, and each supply hole 72 and 73 may be provided toward the center position of the silicon substrate 1. In this case, as shown in FIG. 10, a line segment passing through the supply holes 72 and 73 and the center of the silicon substrate 1 intersects the substrate surface at a substantially right angle.

  As described above, when the arrangement and orientation of the supply holes 72 and 73 are matched to the arrangement of the silicon substrate 1, oxygen gas is sprayed to the approximate center of the silicon substrate 1, and further, substantially uniform from the center of the silicon substrate 1 toward the periphery. Then, a flow from the edge of the silicon substrate 1 toward the exhaust pipe 74 is formed. When the control device 68 adjusts the gas ejection pressure so that the oxygen gas is ejected at a pressure that reaches the silicon substrate 1 linearly, the above-described gas flow can be formed more clearly.

As a result, oxygen radicals are supplied more evenly and continuously over the entire surface of the silicon substrate 1. The entire resist film 49 on the silicon substrate 1 is uniformly ashed and hydrogen is prevented from staying, so that the performance deterioration of the ferroelectric capacitor 37 is prevented.
Also in this modified example, if the exhaust holes of the exhaust pipe 74 correspond to the arrangement of the silicon substrates 1, that is, the supply holes 72 and 73, and the same number as the supply holes 72 and 73 is provided, the ashing variation is further increased. Can be prevented.

(Second Embodiment)
FIG. 11 shows an ashing apparatus which is a semiconductor manufacturing apparatus according to the second embodiment of the present invention, and a cooling means is attached to the outer periphery of the chamber.
Cooling means 81 is attached in close contact with the outer peripheral wall of the chamber 62. The cooling means 81 has a space formed therein, and keeps the temperature in the chamber low by circulating cooling water therein. The cooling means 81 may be configured such that a pipe is wound around the outer periphery of the chamber 62 and the cooling water flows through the pipe. Other configurations are the same as those of the ashing device 61 according to the first embodiment.

FIG. 12 shows the result of examining the relationship between the temperature in the chamber and the processing time. The horizontal axis indicates the processing time, and the vertical axis indicates the chamber temperature.
In FIG. 12, lines L21 and L22 indicate temperature changes when ashing is performed while flowing cooling water in the ashing device 61 according to this embodiment, and the line L21 indicates the temperature change in the first ashing. Shows a temperature change when ashing is continuously performed. For comparison, a change in temperature when ashing is performed once without cooling is shown in line L23, and a change in temperature when ashing is continuously performed a plurality of times without cooling is shown in line L24.
FIG. 12 shows that the substrate temperature increases due to the reaction in the chamber as the processing time increases, but the temperature stabilizes after a certain amount of time has elapsed. Further, as apparent from FIG. 12, the chamber temperature can be kept lower by cooling the chamber 62 with the cooling means 81, whether it is the first ashing or a case where the ashing is continued a plurality of times.

  When the correlation between the performance degradation and the processing temperature was investigated in the ferroelectric memory, the performance degradation was more likely to occur as the processing temperature was higher. This is because the catalytic action of Pt is activated when the treatment temperature increases. For this reason, when the cooling unit 81 is provided in the ashing device 61, it becomes possible by keeping the temperature in the chamber low, and the performance deterioration of the ferroelectric memory can be suppressed.

  In this ashing device 61, it is presumed that the temperature in the chamber increased until the processing time was about 25 minutes, because the amount of hydrogen generated was large during that time. For this reason, the temperature in the chamber can be effectively reduced by keeping the temperature in the chamber low until at least the processing time of about 25 minutes. On the other hand, if the chamber internal temperature is too low, the ashing efficiency is lowered. Therefore, it is preferable to set the chamber internal temperature in the range of 50 ° C. to 90 ° C. by controlling the cooling temperature and the cooling time with the control device 68.

(Third embodiment)
A method for manufacturing a semiconductor device according to the third embodiment of the present invention will be described below. In the present embodiment, a method of controlling to increase the amount of oxygen supplied into the chamber in accordance with the amount of hydrogen generated is adopted. The configuration of the ashing device according to this embodiment is the same as that of the first or second embodiment.

First, FIG. 13 shows the results of examining the relationship between the processing time and the amounts of hydrogen and oxygen in the chamber while a certain amount of oxygen gas is supplied into the chamber 62. Note that the amounts of hydrogen and oxygen shown in FIG. 13 can be calculated from changes in emission spectrum intensity of light caused by hydrogen and oxygen, respectively.
In FIG. 13, lines L31 and L32 indicate characteristics when the number of processed silicon substrates 1 to be ashed at one time is twelve.
As shown by line L31, the amount of hydrogen generated from the resist film reaches a peak around 15 minutes and then gradually decreases. In a time zone in which a large amount of hydrogen is generated, the amount of oxygen decreases as shown by line L32. This indicates that when the amount of hydrogen generated from the resist is large, the resist constituent element is combined with oxygen and consumed so that the resist is ashed.
Similarly, the characteristics when the number of processed silicon substrates 1 to be ashed at one time is 50 are shown in lines L33 and L34. In this case, as shown by the line L33, the amount of generated hydrogen reaches a peak around 20 minutes. And as shown in the line L34, the oxygen amount has decreased correspondingly.

Here, when the number of processed silicon substrates 1 is 50, the amount of hydrogen generated is larger and the amount of oxygen decreased is larger than when the number of processed silicon substrates 1 is 12. This is because when the number of processed sheets is large, the amount of resist also increases, so that the amount of oxygen consumed for the decomposition of the resist composition increases, and the amount of hydrogen generated by the decomposition of the resist composition increases. It is.
By the way, when the line L31 and the line L33 are compared, even if the number of the silicon substrates 1 in the chamber 62 is quadrupled, there is no great difference in the time required to reach the hydrogen peak. Instead, the emission intensity of hydrogen when the number of substrates is 50 is slightly more than three times that of 12 substrates. That is, if the number of processed silicon substrates 1 increases, more hydrogen is generated in the same time than when the number of processed substrates is small.
Therefore, if the number of substrates and / or the amount of resist is large, the ashing may be insufficient in the resist film due to the lack of oxygen unless the amount of oxygen supplied is increased.

Therefore, in this embodiment, as shown in FIG. 14, the amount of oxygen flowing through the gas supply pipe 71 is adjusted according to the number of processed silicon substrates 1. In the figure, the horizontal axis indicates the processing time, and the vertical axis indicates the oxygen flow rate.
Conventionally, as shown in line L41, the oxygen flow rate was constant regardless of the number of processed sheets. However, as the number of processed sheets increased, as shown in lines L42 to L44, a processing time of 5 minutes (at the start of processing). ) To 40 minutes, the oxygen flow rate is increased. In this embodiment, for example, when there are 12 silicon substrates 1, the oxygen flow rate is changed according to the line L42. When the number of the line 1 is 24, the oxygen flow rate is changed according to the line L43, and when the number of the line 1 is 48, the oxygen flow rate is changed. The amount of change is determined by collecting data by experiments in accordance with the change in the amount of hydrogen in the chamber shown in FIG.

The time zone in which the oxygen flow rate is increased is divided because this time zone is a time zone in which hydrogen is generated. Furthermore, if oxygen is excessively supplied, the degree of oxidation of IrO _x that is the upper electrode 35 increases, which affects the performance of the ferroelectric capacitor 37, so that the oxygen flow rate is increased only during the time hydrogen is generated. I am letting. For this reason, after 40 minutes after generation of hydrogen is completed, the amount of oxygen is reduced as compared with the conventional case so that the oxidation degree of IrO _x does not become too large. This prevents oxygen in the PZT of the ferroelectric film 27 from being consumed due to lack of oxygen during ashing, and prevents performance deterioration of the ferroelectric capacitor 37.

  The oxygen flow rate at the time of ashing may be adjusted manually, but may be automatically adjusted by the control device 68 by processing. FIG. 15 shows a flowchart in the case of switching the processing sequence according to the number of processed sheets.

  First, in step S101, it is determined whether or not a noble metal film serving as a hydrogen catalyst is exposed during ashing of the resist film. This is because it is not necessary to change the amount of oxygen when a noble metal film such as Pt is not exposed. In this case (No in step S101), a normal ashing sequence is selected (step S102), and an ashing process is performed along the sequence (step S111). The normal ashing sequence is a sequence performed at a substantially constant oxygen flow rate as indicated by a line L41 in FIG. 14, for example. Note that the determination in step S101 is performed by, for example, a number assigned in advance for each process.

  On the other hand, for example, when the number assigned in advance for each step indicates the ashing step after the via hole 47 is formed in the lower electrode 36, it is determined that the ashing process is performed when the noble metal film is exposed ( Yes in step S101). In this case, a special ashing sequence is selected (step S103). The specific contents of this special ashing sequence are different depending on the number of processed sheets.

  That is, if the number of processed sheets is 12 or less (Yes in Step S104), the first ashing sequence is adopted (Step S105). In this sequence, a profile is selected in which the change in the oxygen flow rate introduced into the chamber 62 is indicated by a line L42 in FIG. Furthermore, if the number of processed sheets is more than 12 and not more than 24 (Yes in Step S106), the second ashing sequence is adopted (Step S107). In this sequence, a profile is selected in which the change in oxygen flow rate is shown by line L43 in FIG.

  If the number of processed sheets is greater than 24 and less than or equal to 36 (Yes in step S108), the third ashing sequence is employed (step S109). This sequence shows a change in the oxygen flow rate passing between the line L43 and the line L44, and after 40 minutes, it is adjusted to a low constant value as in the lines L42 to L44. When the number of processed sheets is greater than 36 (No in step S108), the fourth ashing sequence is employed (step S110). In this sequence, a profile is selected in which the change in oxygen flow rate is indicated by line L44 in FIG.

  Regardless of which ashing sequence is adopted, the ashing process (step S111) is performed using the sequence. When adjusting the oxygen flow rate, the control device 68 adjusts the opening degree of a flow path adjustment valve provided in a gas source (not shown) so that the oxygen flow rate according to the selected sequence is obtained.

  As described above, according to this embodiment, since the oxygen flow rate is increased in accordance with the time zone in which a large amount of hydrogen is generated during ashing, performance deterioration of the ferroelectric capacitor 37 due to oxygen shortage can be prevented. Further, by adjusting so that oxygen is not excessively supplied, the metal film is prevented from being excessively oxidized. Note that the case classification based on the number of processed sheets is not limited to that shown in FIG.

Here, a modified example of this embodiment will be described.
The control device 68 may be configured to select the sequence based on the resist amount instead of the number of silicon substrates 1. In the manufacturing process, depending on the difference in the structure of the semiconductor device to be manufactured, the resist amount may be different even with the same number of silicon substrates 1. Therefore, the resist amount per substrate is registered in advance for each ashing process, and the control device 68 calculates the total resist amount from the resist amount and the number of substrates. Then, a sequence is selected according to the calculated resist amount.
That is, if the resist amount is less than the first threshold value that is the lower limit, the first ashing sequence shown in FIG. 15 is selected, and if it is less than the second threshold value that is equal to or larger than the first threshold value, A second ashing sequence is selected. Similarly, the third and fourth ashing sequences are selected by comparing the plurality of threshold values and the resist amount.
As a result, ashing can be performed reliably even for lots having different resist amounts due to different processes, and performance deterioration can be prevented.

(Fourth embodiment)
16 and 17 show an ashing device according to the fourth embodiment of the present invention. This embodiment relates to a batch type ashing apparatus (semiconductor device manufacturing apparatus) of a type in which semiconductor substrates are horizontally arranged.
As shown in FIGS. 16 and 17, the ashing device 91 has a substrate holder 92 that can be inserted into the chamber 62 from below, and can arrange a large number of silicon substrates 1 at intervals in the vertical direction. Further, in the space between the outer wall of the chamber 62 and the internal electrode 67, the gas supply pipe 71 and the exhaust pipe 74 have a space that allows the substrate holder 92 to enter with the vertical axis at the center of the chamber 62 as the center. Are arranged one by one at symmetrical positions.
As shown in FIG. 5 or FIG. 6, the gas supply pipe 71 is provided with a plurality of supply holes 72 and 73, so that oxygen gas can sufficiently reach the silicon substrates 1 arranged in a plurality of upper and lower sides. ing.
One or more supply holes 72 and 73 of the gas supply pipe 71 may be provided for one silicon substrate. Similarly, it is preferable to form a plurality of exhaust holes of the exhaust pipe 74 in accordance with the arrangement of the silicon substrate 1. A plurality of at least one of the gas supply pipe 71 and the exhaust pipe 74 may be provided. When a plurality of gas supply pipes 71 are arranged, they are arranged around the storage area of the substrate holder 64 as shown in FIG.

  In the substrate holder 92, quartz plates 94 are attached to the upper and lower ends of four support pillars 93 extending in parallel in the vertical direction, and a plurality of silicon substrates 1 are parallel to each other with a space therebetween. A plurality of silicon substrates 1 are supported in a state.

  As shown in FIG. 18, each support column 93 is configured by overlapping substantially cylindrical support units 95. Each support unit 95 is connected to a main body portion 97 provided with one concave portion 96 that supports the peripheral edge of the silicon substrate 1 on its side, and another support unit 95 disposed below, and the main body portion 97 is moved up and down. And an elevating mechanism 98. The elevating mechanism 98 receives, for example, a signal from the control device 68 and raises or lowers the main body 98 by a predetermined amount. The elevating function 98 changes the distance between the two silicon substrates 1 arranged vertically. be able to.

  The control device 68 is configured to change the drive amount of the lifting mechanism 98 according to the number of silicon substrates 1. For example, if the number of substrates is 12 or less, the elevating mechanism 98 is not driven and the main body 97 is left in the lowest initial position. The distance between the silicon substrates 1 at this time is defined as the initial distance. Next, when the number of substrates is 13 to 24 or less, as shown in FIG. 19A, the elevating mechanism 98 is driven to raise the main body portion 97 to the first stage, and between the upper and lower silicon substrates 1. Is 1.5 times the initial distance. Further, when the number of substrates is 25 or more, as shown in FIG. 19B, the lifting mechanism 98 is further driven to raise the main body 97 to the first stage, and the initial distance between the upper and lower silicon substrates 1 is increased. 2 times.

When performing the ashing process of the resist film, the control device 68 adjusts the position of the main body 97 according to the number of substrates, and the distance between the silicon substrates 1 is 1.5 times the initial distance, the initial distance, Set to either twice the initial distance. After or before, the necessary number of silicon substrates 1 are put in the substrate holder 92 in the vertical direction.
As a method for causing the control device 68 to recognize the number of substrates, an operator manually inputs the number of substrates. In addition, the control device 68 may automatically acquire the information from lot information registered in advance. Alternatively, the number of silicon substrates 1 may be counted when the silicon substrate 1 is transferred from the cassette for transporting the substrate to the substrate holder 92.
Note that the upper and lower pitches of the support units 95 may be manually adjusted by rotating the upper and lower support units 95 relative to each other, with the upper part of the support unit 95 and the lifting mechanism 98 as a screw structure.

When the substrate holder 92 is carried into the chamber 62, evacuation is performed, and plasma is generated by applying a high-frequency voltage to the external electrode 65 while flowing oxygen gas. Oxygen radicals formed by the plasma ash the resist film on the substrate surface.
At this time, when the number of substrates is from 13 to 24, the distance between the substrates is 1.5 times the initial distance, so that the oxygen radicals reach the center of the substrate surface sufficiently and the reaction products rapidly It is discharged to the exhaust pipe 74. Similarly, when the number of substrates is 25 or more, since the distance between the substrates is twice the initial distance, oxygen radicals are supplied not only to the periphery of the substrate but also to the central portion of the silicon substrate 1 through a wide open space. It becomes possible to do. Furthermore, since a wide space is secured, the reaction product is quickly discharged into the exhaust pipe 74, and does not hinder the arrival of oxygen radicals.

  If the distance between the silicon substrates 1 is narrow, as described above, oxygen radicals may not reach the substrate surface and reaction products may stay. Accordingly, by giving a sufficient space between the substrates, the ashing is surely performed and the reaction product, particularly hydrogen, can be discharged quickly. As a result, the performance deterioration of the ferroelectric capacitor 37 caused by hydrogen can be prevented. Note that the distance between the silicon substrates 1 may be changed in two steps or four or more steps. The ashing device 91 may include a substrate holder 92 that does not have the lifting mechanism 97. By providing a plurality of supply holes 72 and 73 in the gas supply pipe 71, it becomes possible to supply a sufficient amount of oxygen radicals to each silicon substrate 1. Further, the cooling means 81 according to the second embodiment may be provided, or the oxygen flow rate according to the third embodiment may be adjusted.

Hereinafter, embodiments of the present invention will be additionally described.
(Supplementary Note 1) A chamber to be decompressed, a substrate holder that supports a plurality of semiconductor substrates having an exposed resist film in the chamber, an outside of a region where the substrate holder is disposed, and oxygen gas is introduced into the chamber. A gas supply pipe having a plurality of supply holes to be supplied, an exhaust pipe provided with an exhaust hole for sucking the fluid in the chamber, and a high-frequency power source for activating the oxygen gas for ashing the resist film And a semiconductor device manufacturing apparatus.
(Supplementary note 2) The semiconductor device manufacturing apparatus according to supplementary note 1, wherein the gas supply pipe is provided with at least one supply hole for the semiconductor substrate supported by the support member. .
(Supplementary Note 3) The semiconductor device manufacturing apparatus according to Supplementary Note 1 or 2, wherein the supply hole is formed at a position and a direction in which oxygen gas is ejected toward the center of the semiconductor substrate.
(Supplementary note 4) The method of manufacturing a semiconductor device according to supplementary note 2 or supplementary note 3, wherein a plurality of the gas supply pipes are provided so as to surround the substrate holder, and the supply holes are provided with the exhaust pipe.
(Additional remark 5) The said substrate holder supports the surface in which the said resist of the said semiconductor substrate was formed toward the said supply hole of the said gas supply pipe | tube, It is any one of Additional remark 2 thru | or Additional remark 4 characterized by the above-mentioned The manufacturing apparatus of the semiconductor device of description.
(Additional remark 6) The said substrate holder has a gas passage part which lets the gas in the said chamber pass to the side, The manufacturing apparatus of the semiconductor device of Additional remark 4 or Additional remark 5 characterized by the above-mentioned.
(Supplementary note 7) The semiconductor device manufacturing apparatus according to any one of supplementary notes 1 to 3, further comprising a plurality of concave portions that support the plurality of semiconductor substrates stacked one above the other at intervals.
(Supplementary note 8) The semiconductor device manufacturing apparatus according to any one of supplementary notes 1 to 5, wherein cooling means for cooling the chamber is provided on an outer periphery of the chamber.
(Supplementary Note 9) Control for increasing / decreasing the supply amount of oxygen gas in accordance with at least one of the number of the semiconductor substrates supported by the substrate holder and the amount of the resist on the semiconductor substrate after generating the plasma The apparatus for manufacturing a semiconductor device according to any one of appendices 1 to 8, further comprising an apparatus.
(Additional remark 10) The process of arrange | positioning several semiconductor substrates in which the resist film of the pattern which exposes a noble metal film was formed in the outer periphery of the substrate holder in a chamber, and the gas of the several gas supply pipe | tube arrange | positioned in the outer periphery of the said substrate holder A step of supplying oxygen from the supply hole toward each of the resist films of the semiconductor substrate; and generating a high-frequency electric field in a reduced-pressure atmosphere in the chamber to generate the oxygen plasma to ash the resist film And a method of manufacturing a semiconductor device.
(Additional remark 11) It has the process of increasing / decreasing the supply amount of oxygen gas according to the number of the semiconductor substrates supported by the substrate holder or the amount of resist applied to the semiconductor substrate. The manufacturing method of the semiconductor device of description.

FIG. 1A is a sectional view (No. 1) showing a manufacturing step of the semiconductor device according to the first embodiment of the invention. FIG. 1B is a sectional view (No. 2) showing the manufacturing process of the semiconductor device according to the first embodiment of the invention. FIG. 1C is a cross-sectional view (part 3) illustrating the manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG. 1D is a sectional view (No. 4) showing a manufacturing step of the semiconductor device according to the first embodiment of the invention. FIG. 1E is a cross-sectional view (part 5) illustrating the manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG. 1F is a sectional view (No. 6) showing a manufacturing step of the semiconductor device according to the first embodiment of the invention. FIG. 1G is a sectional view (No. 7) showing the manufacturing process of the semiconductor device according to the first embodiment of the invention. FIG. 1H is a sectional view (No. 8) showing a manufacturing step of the semiconductor device according to the first embodiment of the invention. FIG. 2A is a side sectional view (No. 1) showing a step of manufacturing the semiconductor device according to the first embodiment of the invention, which is substantially parallel to the word line. FIG. 2B is a side sectional view (No. 2) taken in the direction substantially parallel to the word lines, showing the manufacturing process of the semiconductor device according to the first embodiment of the invention. FIG. 2C is a side cross-sectional view (part 3) in the direction substantially parallel to the word lines, showing the manufacturing process of the semiconductor device according to the first embodiment of the invention. FIG. 2D is a side sectional view (No. 4) in the direction substantially parallel to the word lines, showing the manufacturing process of the semiconductor device according to the first embodiment of the invention. FIG. 3 is a diagram illustrating a schematic configuration of a semiconductor device manufacturing apparatus. 4 is a cross-sectional view taken along line AA in FIG. FIG. 5 is a diagram showing an example of the shape and arrangement of the supply holes of the gas supply pipe. FIG. 6 is a diagram showing another example of the shape and arrangement of the supply holes of the gas supply pipe. FIG. 7 is a partial cross-sectional view illustrating a structure for supporting a substrate in the substrate holder. FIG. 8 is a diagram illustrating a mechanism in which performance deterioration is caused by hydrogen. FIG. 9 is a graph in which fatigue deterioration is examined for each place on the substrate. FIG. 10 is a diagram for explaining the arrangement of the gas supply holes and the substrate. FIG. 11 is a cross-sectional view showing a schematic configuration of an ashing device having a cooling means. FIG. 12 is a diagram showing the relationship between the processing time and the temperature in the chamber. FIG. 13 is a graph in which changes in the generation amounts of hydrogen and oxygen are examined for each processing time. FIG. 14 is a graph showing the relationship between the oxygen flow rate and the processing time when the oxygen flow rate is changed according to the number of processed substrates. FIG. 15 is a flowchart for explaining processing when the oxygen flow rate is changed in accordance with the number of processed substrates. FIG. 16 is a diagram showing a schematic configuration of a semiconductor device manufacturing apparatus using a substrate holder that horizontally arranges substrates. 17 is a cross-sectional view taken along line II-II in FIG. FIG. 18 is a diagram showing a configuration of the substrate holder. 19A is a diagram in which the lifting mechanism is driven in one stage, and FIG. 19B is a diagram in which the lifting mechanism is driven in two stages.

Explanation of symbols

1 Silicon substrate (semiconductor substrate)
36 Lower electrode (noble metal film)
49 Resist film 61, 91 Ashing device (semiconductor device manufacturing device)
62 Chamber 63 Processing chamber 64, 92 Substrate holder 65 External electrode 66 High frequency power supply 67 Internal electrode 68 Control device 71 Gas supply pipe 72, 73 Supply hole 74 Exhaust hole 79, 93 Support member 81 Cooling means 97 Main body 98 Drive mechanism

Claims (5)

A chamber to be decompressed;
A substrate holder for supporting a plurality of semiconductor substrates having exposed resist films in the chamber;
A gas supply pipe which is provided outside the arrangement region of the substrate holder and in which supply holes for supplying oxygen gas into the chamber are formed at a plurality of locations;
An exhaust pipe provided with an exhaust hole for sucking the fluid in the chamber;
A high frequency power source for activating the oxygen gas for ashing the resist film;
An apparatus for manufacturing a semiconductor device.   The semiconductor device manufacturing apparatus according to claim 1, wherein the gas supply pipe is provided with at least one supply hole for the semiconductor substrate supported by the support member.   The apparatus for manufacturing a semiconductor device according to claim 2, wherein the substrate holder supports a surface of the semiconductor substrate on which the resist is formed toward the supply hole of the gas supply pipe.   3. The semiconductor device manufacturing apparatus according to claim 1, further comprising a plurality of concave portions that support the plurality of semiconductor substrates stacked one above the other at an interval. Arranging a plurality of semiconductor substrates on which a resist film having a pattern exposing a noble metal film is formed on the outer periphery of a substrate holder in the chamber;
Supplying oxygen from the gas supply holes of a plurality of gas supply pipes arranged on the outer periphery of the substrate holder toward each of the resist films of the semiconductor substrate;
Ashing the resist film by generating a plasma of the oxygen by generating a high-frequency electric field in a reduced-pressure atmosphere in the chamber;
A method for manufacturing a semiconductor device, comprising:

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