JP2010092988A - Semiconductor substrate, method of manufacturing the same, and method of manufacturing solid-state imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor substrate for reducing production cost, and to provide a method of manufacturing the same, and a method of manufacturing a solid-state imaging apparatus. <P>SOLUTION: The semiconductor substrate includes a supporting substrate 71, an impurity introducing layer 77 provided in the supporting substrate and having an impurity concentration of 10<SP>19</SP>/cm<SP>3</SP>or more and 5×10<SP>20</SP>/cm<SP>3</SP>or less, and an epitaxial layer 55 formed on the impurity introducing layer. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor substrate, a manufacturing method thereof, and a manufacturing method of a solid-state imaging device, and is applied to, for example, a CMOS sensor.

  Solid-state imaging devices such as CMOS sensors are currently used in various applications such as digital still cameras, video movies, and surveillance cameras. However, the pixel size tends to be reduced due to the recent demand for increasing the number of pixels and optical size reduction. For example, the pixel size of a CMOS sensor that is frequently used in digital cameras and the like in recent years is as fine as about 1.75 μm to 2.8 μm.

  As a configuration for such a fine pixel, for example, there is a back-illuminated solid-state imaging device (see, for example, Patent Document 1). In a back-illuminated solid-state imaging device, incident light is irradiated from the silicon (Si) surface (back surface) opposite to the silicon (Si) surface (front surface) on which the signal scanning circuit and its wiring layer are formed. The As described above, in the back-illuminated configuration in which the signal scanning circuit and the wiring layer thereof are formed from the back side silicon (Si) surface opposite to the silicon (Si) surface side, light incident on the pixel is applied to the wiring layer. The light-receiving region formed in the silicon (Si) substrate can be reached without being hindered. Therefore, it is expected that high quantum efficiency can be realized even in a fine pixel.

  Here, in order to manufacture such a back-illuminated solid-state imaging device having color filters and microlenses, it is necessary to thin the semiconductor substrate with high accuracy. This is because in recent color filter processing and fine microlens processing, higher density optical characteristics are required.

  When performing this thinning process, the easiest solution is to use an SOI (Silicon On Insulater) substrate. That is, the silicon substrate is etched with high accuracy using the buried oxide film (insulator: BOX layer) of the SOI substrate as a stopper layer.

  However, since the SOI substrate is very expensive, the manufacturing cost is significantly increased. For example, an SOI substrate requires about four times or more the cost of a silicon substrate. Therefore, for example, mounting a solid-state imaging device using an SOI substrate in a price range system such as a mobile phone is considered disadvantageous in terms of manufacturing cost.

As described above, the conventional semiconductor substrate, the manufacturing method thereof, and the manufacturing method of the solid-state imaging device have a problem that the manufacturing cost increases.
JP 2006-128392 A

  The present invention provides a semiconductor substrate capable of reducing the manufacturing cost, a manufacturing method thereof, and a manufacturing method of a solid-state imaging device.

According to one aspect of the present invention, a support substrate, an impurity introduction layer provided in the support substrate and having an impurity concentration of 10 ¹⁹ / cm ³ or more and 5 × 10 ²⁰ / cm ³ or less, and the impurity introduction layer A semiconductor substrate having an epitaxial layer formed thereon can be provided.

According to one embodiment of the present invention, a step of introducing an impurity into the support substrate in a range of a concentration of 10 ¹⁹ / cm ³ or more and 5 × 10 ²⁰ / cm ³ or less to form an impurity introduction layer, and the impurity A method of manufacturing a semiconductor substrate comprising a step of forming an epitaxial layer on the introduction layer can be provided.

According to one aspect of the present invention, a step of introducing an impurity into the first support substrate in a range of a concentration of 10 ¹⁹ / cm ³ or more and 5 × 10 ²⁰ / cm ³ or less to form an impurity introduction layer; Forming an epitaxial layer on the impurity introduction layer; forming an interlayer insulating film on the epitaxial layer; forming a signal scanning circuit portion in the interlayer insulating film in a pixel region; and the interlayer insulating film Adhering a second support substrate thereon, using the impurity introduction layer as a stopper layer, thinning and removing the first support substrate, removing the impurity introduction layer, and the signal scanning circuit unit And a step of forming a pixel region in the epitaxial layer opposite to the surface of the epitaxial layer on which the semiconductor layer is formed.

  According to the present invention, it is possible to obtain a semiconductor substrate, a manufacturing method thereof, and a manufacturing method of a solid-state imaging device that can reduce manufacturing costs.

  Embodiments of the present invention will be described below with reference to the drawings. In this description, common parts are denoted by common reference symbols throughout the drawings.

[First Embodiment]
Here, as an example, a back-illuminated solid-state imaging device in which a light-receiving surface (light irradiation surface) is provided on a semiconductor substrate on the side opposite to the surface of the semiconductor substrate on which the signal scanning circuit unit is formed will be described. Hereinafter, 1. Configuration example, 2. 2. Manufacturing method It demonstrates in order of an effect.

<1. Configuration example>
1-1. Overall configuration example
First, an example of the overall configuration of a semiconductor substrate and a solid-state imaging device according to the first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram illustrating an example of the overall configuration of the solid-state imaging device according to the first embodiment. In this example, a configuration in which an AD conversion circuit is arranged at a column position in a pixel region is shown.

As shown in the figure, the solid-state imaging device 10 according to this example includes a pixel region 12 and a drive circuit region (peripheral region) 14.
The pixel region 12 is formed by arranging a unit pixel matrix including a photoelectric conversion unit and a signal scanning circuit unit on a semiconductor substrate.
The photoelectric conversion unit includes a unit pixel 1 including a photodiode that performs photoelectric conversion and accumulates, and functions as an imaging unit. The signal scanning circuit unit includes an amplification transistor, which will be described later, reads and amplifies a signal from the photoelectric conversion unit, and transmits the signal to the AD conversion circuit 15. In the case of this example, the light receiving surface (photoelectric conversion unit) is provided on the back side of the semiconductor substrate opposite to the semiconductor substrate surface on which the signal scanning circuit unit is formed.

  The peripheral area 14 is formed by arranging driving circuits such as a vertical shift register 13 and an AD conversion circuit 15 for driving the signal scanning circuit section.

  Here, although described as a part of the entire configuration of the CMOS sensor, it is not limited to this. That is, for example, a configuration in which an ADC circuit is not disposed in parallel with a column but an ADC circuit is disposed at a chip level, or a configuration in which an ADC is not disposed on a sensor chip may be employed.

  The vertical shift register 13 (Vertical Shift register) 13 outputs signals LS1 to SLk to the pixel region 12 and functions as a selection unit that selects the unit pixel 1 for each row. Each unit pixel 1 in the selected row outputs an analog signal Vsig corresponding to the amount of incident light via the vertical signal line VSL.

  The AD conversion circuit (ADC) 15 converts the analog signal Vsig input via the vertical signal line VSL into a digital signal.

1-2. Pixel area configuration example
Next, a configuration example of the pixel region (pixel array) 12 in FIG. 1 will be described with reference to FIG. FIG. 2 is an equivalent circuit diagram illustrating a configuration example of the pixel region according to the present example. In this example, a monolithic image sensor that acquires a plurality of color information in a single pixel region 12 will be described as an example.

  As shown in the figure, the pixel region 12 includes a plurality of unit pixels 1 arranged in a matrix at the intersections between the readout signal lines from the vertical shift register 13 and the vertical signal lines VSL.

  The unit pixel (PIXEL) 1 includes an address transistor 21, a photodiode 22, an amplification transistor 23, a read transistor 24, and a reset transistor 29.

  In the above, the photodiode 22 constitutes a photoelectric conversion unit. The address transistor 21, amplification transistor 23, readout transistor 24, and reset transistor 29 constitute a signal scanning circuit unit.

  The gate of the address transistor 21 is connected to the address signal line ADR.

  A reference potential Vss is applied to the cathode of the photodiode 22.

  The amplification transistor 23 is configured to amplify and output a signal from the floating diffusion layer (floating diffusion) 32. The amplification transistor 23 has a gate connected to the floating diffusion layer 32, a source connected to the vertical signal line VSL, and a drain connected to the source of the address transistor 31. The output signal of the unit pixel 1 transmitted through the vertical signal line VSL is output from the output terminal 31 after the noise is removed by the CDS noise removal circuit 38.

  The read transistor 24 is configured to control the accumulation of signal charges in the photodiode 22. The gate of the read transistor 24 is connected to the read signal line TRF, the source is connected to the anode of the photodiode 22, and the drain is connected to the floating diffusion layer 32.

  The reset transistor 29 is configured to reset the gate potential of the amplification transistor 23. The gate of the reset transistor 29 is connected to the reset signal line RST, the source is connected to the floating diffusion layer 32, and the drain is connected to the power supply terminal 35 connected to the drain power supply.

  The gate of the load transistor 26 is connected to the selection signal line SF, the drain is connected to the source of the amplification transistor 23, and the source is connected to the control signal line DC.

Read drive operation
The read driving operation by the configuration of the pixel region 12 is as follows. First, the address transistor 21 of the read row is turned on by a row selection pulse sent from the vertical shift register 13.

  Subsequently, the reset transistor 29 is similarly turned on by the reset pulse sent from the vertical shift register 13 and reset to a voltage close to the potential of the floating diffusion layer 32. Thereafter, the reset transistor 29 is turned off.

  Subsequently, the transfer gate 24 is turned on, the signal charges accumulated in the photodiode 22 are read out to the floating diffusion layer 32, and the potential of the floating diffusion layer 32 is set to the number of signal charges read out. Modulated accordingly.

  Subsequently, the modulated signal is read to the vertical signal line VSL by the MOS transistor constituting the source follower, and the read operation is completed.

1-3. Configuration example of semiconductor substrate for solid-state imaging device
Next, a configuration example of a semiconductor substrate used in the solid-state imaging device according to the first embodiment will be described with reference to FIG.

  As illustrated, the semiconductor substrate includes a first support substrate 71, an impurity introduction layer 77, a p-type impurity layer 57, and an epitaxial layer 55.

The first support substrate 71 is, for example, a silicon (Si) substrate having an impurity concentration of boron (B) of about 10 ¹⁷ / cm ³ .

The impurity introduction layer (p + doped layer) 77 is introduced into the first support substrate 71 in order to function as a stopper layer when the first support substrate 71 is thinned and removed, as will be described later. As will be described later, the impurity introduction layer 77 is, for example, boron (B), oxygen (O), carbon (C), nitrogen in a predetermined depth Dp + of the first support substrate 71 using, for example, an ion implantation method. It is formed by introducing impurities such as (N). As a result, more specifically, the impurity introduction layer 77 includes, for example, a SiB layer, a SiO ₂ layer, a SiC layer, a SiN layer, and the like, and includes a peak of the impurity concentration of the introduced impurity.

The impurity concentration of the impurity introduction layer 77 is preferably within a range in which a desired etching rate with the first support substrate 71 can be obtained when the first support substrate 71 is removed by etching. For example, as described in detail, when the impurity is boron (B), the impurity concentration of the impurity introduction layer 77 is in the range of about 5 × 10 ¹⁹ / cm ³ or more and about 5 × 10 ²⁰ / cm ³ or less. It is desirable. Further, the film thickness Dp + of the impurity introduction layer 77 is preferably about 8 μm, for example.

The p-type impurity layer (p) 57 is an impurity introduction layer formed by thermal diffusion or the like when the impurity introduction layer 77 is formed. For example, when the impurity is boron (B), the impurity concentration of the p-type impurity layer 57 is desirably in the range of about 10 ¹⁷ / cm ^{3 to} about 10 ¹⁹ / cm ³ .

  Here, the case where the p-type impurity layer 57 is formed on the upper side (signal scanning circuit formation side) of the impurity introduction layer 77 is described as an example, but the present invention is not limited thereto. That is, for example, depending on thermal diffusion or the like when forming the impurity introduction layer 77, the p-type impurity layer (57-2) is also formed on the lower side (light irradiation surface side) so as to sandwich the impurity introduction layer 77. It may be a configuration.

The epitaxial layer (n-epi) 55 is formed on the p-type impurity layer 57 by epitaxially growing n-type phosphorus (P) or the like. The concentration of phosphorus (P) in the epitaxial layer 55 is preferably about 2 × 10 ¹⁵ / cm ³ , for example.

  In this description, the case where the semiconductor substrate is applied to a solid-state imaging device will be described, but the present invention is not limited to this.

1-4. Cross-sectional configuration example of solid-state imaging device
Next, a cross-sectional configuration example of the solid-state imaging device according to the first embodiment will be described with reference to FIG. The solid-state imaging device shown in the figure is manufactured using the semiconductor substrate described in FIG.

  As shown in the figure, the solid-state imaging device according to the present example includes a pixel region 12 and a peripheral region 14.

  The pixel region 12 includes unit pixels (Pixels) 1 arranged in a matrix on a second support substrate (Si Support sub) 72. The unit pixel 1 includes a photoelectric conversion unit 51 and a signal scanning circuit unit 52.

  The photoelectric conversion unit 51 includes an epitaxial layer 55, a p-type impurity layer 56 that surrounds a boundary portion of each unit pixel 1 and partitions an element isolation region, and an antireflection film (p-type impurity) that is sequentially provided on the epitaxial layer 55. Layer) 57, a color filter 58, and a microlens 59.

  The signal scanning circuit unit 52 includes the amplification transistor 23 and the like formed in the interlayer insulating film 60 provided on the surface of the second support substrate 72 on the signal scanning circuit forming surface side, and the multilayer wiring layer 61. .

  The peripheral region 14 includes M1Pad, M3Pad, a wiring layer 66, an element isolation insulating film STI, a pad 63, and a bonding wire 65. The peripheral region 14 is, for example, the vertical shift register 13 along the column direction in FIG.

  M1Pad, M3Pad, and the wiring layer 66 are provided in the interlayer insulating film 60. The element isolation insulating film STI is embedded in the epitaxial layer 55, and partitions a component circuit (not shown) and the pixel region 12. The pad 63 is provided on the antireflection film 57 and is electrically connected to the wiring layer 66. The bonding wire 65 is bonded onto the pad 63, and a power supply voltage (for example, VCC, VSS, etc.) is applied from the outside. This power supply voltage is electrically connected to, for example, M1Pad and M3Pad via the wiring layer 66.

1-5. Impurity concentration and etching rate of impurity introduction layer
Next, the relationship between the impurity concentration of the impurity introduction layer 77 and the etching rate according to the first embodiment will be described with reference to FIGS. 5 and 6. Here, the impurity introduced into the impurity introduction layer 77 will be described by taking boron (B) as an impurity and silicon (Si) as an etching rate (μm / h) as an example.

  The relationship between the impurity concentration of the impurity introduction layer 77 and the etching rate when KOH is used as an etchant is shown in FIG. Here, KOH concentrations are 10%, 24%, 42%, and 57%, and the relationship of the <100> plane silicon substrate at 60 ° C. is shown.

As shown in the figure, in any case, the etching rate is reduced to about 1/100 (about 10 ¹ μm / h → about 10 ⁻¹ μm / h). In order to obtain a desired value, the impurity introduction layer It can be seen that the impurity concentration of 77 is desirably in the range of 10 ¹⁹ / cm ³ or more and 5 × 10 ²⁰ / cm ³ or less. As a result, it is understood that the impurity concentration of the p-type impurity layer 57 is desirably in the range of 10 ¹⁷ / cm ³ or more and 10 ¹⁹ / cm ³ or less.

The relationship between the impurity concentration of the impurity introduction layer 77 and the etching rate when EDP (EDP Type S: Ethylene Diamine Pyrocatechol) is used as an etchant is shown in FIG. As shown in the figure, the concentrations near the boundary where the etching rate changes in relation to the <100> -plane silicon substrate are 110 ° C. at a concentration C _D = 2.8 × 10 ¹⁹ cm ³ and 81 ° C., respectively. C _D = 2.9 × 10 ¹⁹ cm ³ or so, and the concentration at 66 ° C. is C _D = 3.0 × 10 ¹⁹ cm ³ or so. From this result, it can be seen that the impurity concentration near the boundary where the etching rate changes is constant regardless of the temperature of the etchant EDP.

Further, in any of the above conditions, the etching rate is reduced to about 1/100 (about 10 ¹ μm / h → about 10 ⁻¹ μm / h). Similarly, it is understood that the impurity concentration is desirably in the range of 5 × 10 ¹⁹ / cm ³ or more and 5 × 10 ²⁰ / cm ³ or less. As a result, it is understood that the impurity concentration of the p-type impurity layer 57 is desirably in the range of 10 ¹⁷ / cm ³ or more and 10 ¹⁹ / cm ³ or less.

1-6. Unit pixel configuration example
Next, a configuration example of the unit pixel according to the first embodiment will be described in more detail with reference to FIG.

  In the cross section shown in the figure, the unit pixel 1 includes a photodiode 22 and a readout transistor 24 provided in the epitaxial layer 55 of the photoelectric conversion unit 51.

  The photodiode 22 includes an n + diffusion layer that is a source 69 of the read transistor 24, a source 69 provided in contact with the source 69, and a P well layer (p-well) 70 that forms a pn junction with the source 69. Consists of.

  The read transistor 24 includes a gate insulating film 67 provided in the interlayer insulating film 60, a gate electrode 68 provided in the interlayer insulating film 60 on the gate insulating film 67, and the epitaxial layer 55 so as to sandwich the gate electrode 68. The source 69 (n + diffusion layer) and the drain 69 (n + diffusion layer) are provided separately from each other.

  The drain 69 is electrically connected to the multilayer wiring layer via a contact wiring layer 80 provided in the interlayer insulating film 60 on the drain 58. The pixels of the unit pixel 1 are displayed according to the electrical signal output from the multilayer wiring layer. Since the configuration of other unit pixels is the same, detailed description thereof is omitted.

Example of color filter plane configuration
Next, a planar configuration example of the color filter 52 included in the solid-state imaging device according to this example will be described with reference to FIG. FIG. 8 is a plan view showing how color filters are arranged in order to obtain a color signal in a monolithic solid-state imaging device structure.

  In the figure, the pixel indicated by R is a pixel in which a color filter that mainly transmits light in the red wavelength region is arranged, and the pixel indicated by G is provided by a color filter that mainly transmits light in the green wavelength region. The pixels indicated by B and the pixels indicated by B are pixels on which color filters that mainly transmit light in the blue wavelength region are arranged.

  In this example, a color filter arrangement that is most commonly used as a Bayer arrangement is shown. As shown in the figure, adjacent color filters (R, G, B) are arranged so as to acquire different color signals in the row direction and the column direction.

<2. Manufacturing method>
Next, a manufacturing method of the solid-state imaging device according to this example will be described with reference to FIGS.

  First, FIG. 9 shows a first support substrate (Si Support sub) 71 before processing.

  Subsequently, as shown in FIG. 10, boron (B), oxygen (O), carbon (C), nitrogen (in the predetermined depth Dp + of the first support substrate 71 using, for example, an ion implantation method. N) or the like is introduced, and an impurity introduction layer 77 is formed. In this example, the depth Dp + is about 1 μm, boron (B) is introduced as an element, and an impurity introduction layer (p + doped layer) 77 including a SiB layer is formed.

  Thereafter, heat treatment is performed to diffuse the introduced impurities, and a p-type impurity layer 57 is formed. As described above, a mode in which the p-type impurity layer (57-2) is further formed on the lower side (light irradiation surface side) so as to sandwich the impurity introduction layer 77 is also conceivable.

  Subsequently, as shown in FIG. 11, for example, n-type phosphorus (P) or the like is epitaxially grown on the p-type impurity layer 57 to form an epitaxial layer (n-epi) 55.

Subsequently, as shown in FIG. 12, for example, a silicon oxide film (SiO ₂ ) or the like is embedded in the element isolation region in the epitaxial layer 55 in the peripheral region 14 to form an element isolation insulating film STI. Subsequently, for example, a silicon oxide film (SiO ₂ ) or the like is deposited on the epitaxial layer 55 to form the interlayer insulating film 60. Subsequently, using a normal LSI (Large Scale Integrated Circuit) manufacturing process, a multilayer wiring layer is formed in the pixel region 12 to form the signal scanning circuit portion 52, and M1 Pad, M3 Pad, trench mark 64, etc. are formed in the peripheral region 14. Form.

  Subsequently, as shown in FIG. 13, a second support substrate (Si Support sub) 72 made of, for example, a silicon substrate is directly bonded (Direct Bonding) on the interlayer insulating film 60 on the signal scanning circuit formation side.

  Subsequently, as shown in FIG. 14, the entire apparatus is turned upside down, and the first support substrate 71 is thinned and removed to the surface of the impurity introduction layer 77 using the impurity introduction layer 77 as a stopper layer.

Specifically, for example, the first support substrate 71 is thinned and removed using the impurity introduction layer 77 as a stopper layer and KOH or EDP (EDP Type S: Ethylene Diamine Pyrocatechol) as an etchant. In this case, as shown in FIGS. 5 and 6, the etching rate of the impurity introduction layer 77 is reduced to about 1/100 under any conditions (about 10 ¹ μm / h → 10 ⁻¹ μm / (about h). Therefore, the first support substrate 71 can be thinned and removed with good selectivity without using an SOI substrate.

  Subsequently, as shown in FIG. 15, the impurity introduction layer 77 is removed up to the surface of the P-type impurity layer 57 by using, for example, a CMP (Chemical Mechanical Polishing) method or the like.

In this process, the relationship between the depth and the boron concentration is shown in FIG. As shown in the figure, since the boron concentration is in the range of about 10 ¹⁹ / cm ³ or more and about 5 × 10 ²⁰ / cm ³ or less until the depth reaches Dp +, the p-type has a boron concentration of about 10 ¹⁹ / cm ³ or less. It can be processed by the CMP method with selectivity with the impurity layer 57. Therefore, the flatness on the surface of the p-type impurity layer 57 can be improved. Therefore, it is advantageous in that the optical characteristics can be improved when the microlens 59 related to the fine pixel in the subsequent process or the color filter 58 (not the monochrome filter) shown in FIG.

  Subsequently, as shown in FIG. 17, a p-type impurity is introduced into the epitaxial layer 55 in the pixel region 12 to form a pixel separation layer 56 that separates the pixels.

  Subsequently, although not shown, the color filter 58 and the microlens 59 are formed in order on the epitaxial layer 55 in the pixel region 12, and the solid-state imaging device shown in FIG. 4 is manufactured. In this step, as described above, the color filter 58 and the microlens 59 can be formed on the surface of the p-type impurity layer 57 with improved flatness, which is advantageous in that the optical characteristics can be improved.

<3. Effect of First Embodiment>
According to the semiconductor substrate, the manufacturing method thereof, and the manufacturing method of the solid-state imaging device according to the first embodiment, at least the following effects (1) to (2) can be obtained.

(1) The manufacturing cost can be reduced.
As shown in FIG. 3, the solid-state imaging device according to the first embodiment is provided in the support substrate 71 and the support substrate, and has an impurity concentration of 5 × 10 ¹⁹ / cm ³ or more and 5 × 10 ²⁰ / cm. It is manufactured using a semiconductor substrate having an impurity introduction layer 77 of ³ or less and an epitaxial layer 55 formed on the impurity introduction layer.

  Therefore, as shown in FIG. 14, the first support substrate 71 can be removed by thinning the surface of the impurity introduction layer 77 using the impurity introduction layer 77 as a stopper layer.

Specifically, for example, the first support substrate 71 is thinned and removed using the impurity introduction layer 77 as a stopper layer and KOH or EDP (EDP Type S: Ethylene Diamine Pyrocatechol) as an etchant. In this case, as shown in FIGS. 5 and 6, the etching rate of the impurity introduction layer 77 is reduced to about 1/100 under any conditions (about 10 ¹ μm / h → 10 ⁻¹ μm / (about h). Therefore, the first support substrate 71 can be thinned and removed with good selectivity without using an SOI substrate.

  Therefore, unlike the comparative example to be described later, it is not necessary to etch the silicon substrate with high accuracy using the buried oxide film (insulator: BOX layer) of the SOI substrate as a stopper layer, so that the SOI substrate is used as a substrate for a solid-state imaging device. There is no need to use it.

  Here, the SOI substrate is very expensive. For example, an SOI substrate requires about four times or more costs compared to a silicon substrate or the like. More specifically, the cost of a SOI substrate of the same size is about 1 to 150,000 yen (/ sheet) compared to the cost of a 12-inch silicon substrate is about 30,000 yen (/ sheet). .

  On the other hand, according to the configuration and the manufacturing method thereof according to this example, the support substrate 71 can be thinned and removed with high density using a silicon substrate without using an SOI substrate. As a result, it is advantageous in that the manufacturing cost can be reduced.

  Therefore, for example, there is an advantage that the solid-state imaging device according to the present example is advantageous in the case where the solid-state imaging device is installed in a price range system such as a mobile phone.

  In addition, since the first support substrate 71 can be thinned and removed with high selectivity, even the recent color filter processing and fine microlens processing satisfy the required higher density optical characteristics. obtain.

(2) Optical characteristics can be improved.
As shown in FIG. 15, in the method for manufacturing the solid-state imaging device according to the first embodiment, the impurity introduction layer 77 can be removed up to the surface of the P-type impurity layer 57 using the CMP method.

In this process, the relationship between the depth and the boron concentration is shown in FIG. As shown, (in this example, about 1 [mu] m) is Dp + depth until the boron concentration ¹⁰ 19 / cm ³ of about above, since the range of less than about 5 × ¹⁰ 20 / cm ^3, boron concentration of ^{10 19} It can be processed by the CMP method with selectivity with respect to the p-type impurity layer 57 of about / cm ³ or less. Therefore, the flatness on the surface of the p-type impurity layer 57 can be improved. Therefore, it is advantageous in that the optical characteristics can be improved when the microlens 59 related to the fine pixel in the subsequent process or the color filter 58 (not the monochrome filter) shown in FIG.

[Second Embodiment (Other Application Examples)]
Next, a semiconductor substrate, a manufacturing method thereof, and a manufacturing method of a solid-state imaging device according to the second embodiment will be described with reference to FIG. The second embodiment relates to another application example such as an etchant. In this description, detailed description of the same parts as those in the first embodiment is omitted.

  In the first embodiment, the example in which the first support substrate 71 is thinned and removed has been described. However, the present invention is not limited to this. For example, as shown in FIG. is there.

Etchant KOH (10%)
In this case, the temperature (Temp) is about 60 ° C. to 90 ° C., the etching rate (Etch Rate (100)) on the silicon <100> plane is about 1 to 2 μm / min, the mask material is Si ₃ N ₄ , The boron (B) concentration of the etching stopper layer (Etch Stop) 77 is about 10 ²⁰ cm ⁻³ or more.

Etchant EDP Type S
In this case, the temperature (Temp) is about 66 ° C. to 110 ° C., the etching rate (Etch Rate (100)) on the silicon <100> plane is about 0.2 to 1 μm / min, and the mask material (Mask Material) is Si ₃ N. ₄ , SiO ₂ , Au, and the etching stopper layer (Etch Stop) 77 have a boron (B) concentration of about 5 × 10 ¹⁹ cm ⁻³ or more.

Etchant TMAH (Tetramethyl Ammonium Hydroxide)
In this case, the temperature (Temp) is about 90 ° C., the etching rate (Etch Rate (100)) on the silicon <100> plane is about 0 to 1 μm / min, and the mask material is Si ₃ N ₄ , SiO ₂ , The boron (B) concentration of Au and the etching stopper layer (Etch Stop) 77 is about 2 × 10 ²⁰ cm ⁻³ or more.

As described above, in the case of the etchant EDP Type S, it can be seen that the boron (B) concentration of the impurity introduction layer 77 serving as an etching stopper layer may be about 5 × 10 ¹⁹ cm ⁻³ or more.

  Since the configuration and the manufacturing method thereof are substantially the same as those of the first embodiment, detailed description thereof is omitted.

  According to the semiconductor substrate, the manufacturing method thereof, and the manufacturing method of the solid-state imaging device according to the second embodiment, at least the same effects as the above (1) to (2) can be obtained.

  Furthermore, it is possible to use an aspect like this example as needed.

[Comparative example (an example using an SOI substrate)]
Next, in order to compare with the semiconductor substrate according to the first and second embodiments, the manufacturing method thereof, and the manufacturing method of the solid-state imaging device, the semiconductor substrate according to the comparative example, the manufacturing method thereof, and the manufacturing method of the solid-state imaging device Will be described with reference to FIGS. This comparative example relates to an example using an SOI substrate. In this description, detailed description of the same parts as those in the first embodiment is omitted.

<About manufacturing method>
First, as shown in FIG. 19, in this comparative example, an SOI (Silicon On Insulater) substrate is used. That is, as shown in the figure, the SOI substrate is a substrate in which a buried oxide film (insulator: BOX layer) 177 and an epitaxial layer (n-epi) 155 are sequentially laminated on a silicon substrate (Si Sensor sub) 171. is there.

  Subsequently, as illustrated in FIG. 20, the photoelectric conversion unit 151 and the signal scanning circuit unit 152 are formed in the pixel region 112 and the peripheral region. Subsequently, a silicon substrate (Si Support sub) 172 is bonded onto the signal scanning circuit unit 152.

  Subsequently, as shown in FIG. 21, the buried oxide film (BOX layer) 177 is used as a stopper layer, the silicon substrate 171 is etched, the silicon substrate 171 is thinned and removed. More specifically, for example, etching is stopped at a high density on the surface of the buried oxide film (BOX layer) 177 with an alkaline etching material such as KOH as an etchant.

  Subsequently, although illustration is omitted, after removing the buried oxide film (BOX layer) 177, a color filter and a microlens are sequentially formed to manufacture a solid-state imaging device.

  As described above, in the comparative example, an SOI substrate is used, and the silicon substrate 171 is etched and removed with high accuracy using the buried oxide film (insulator: BOX layer) 177 of the SOI substrate as a stopper layer.

  Here, the SOI substrate is very expensive. For example, an SOI substrate requires about four times or more costs compared to a silicon substrate or the like. More specifically, the cost of a SOI substrate of the same size is about 1 to 150,000 yen (/ sheet) compared to the cost of a 12-inch silicon substrate is about 30,000 yen (/ sheet). .

  As a result, it is disadvantageous in that the manufacturing cost increases.

  As described above, the present invention has been described using the first and second embodiments and the comparative example. However, the present invention is not limited to the above-described embodiments and comparative examples, and the gist thereof is described in the implementation stage. Various modifications can be made without departing from the scope. The above embodiments and comparative examples include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent elements are deleted from all the constituent elements shown in the embodiments and comparative examples, at least one of the problems described in the column of problems to be solved by the invention can be solved, and the column of the effect of the invention In the case where at least one of the effects described in (1) is obtained, a configuration in which this configuration requirement is deleted can be extracted as an invention.

1 is a block diagram illustrating an example of the overall configuration of a solid-state imaging device according to a first embodiment of the present invention. FIG. 3 is an equivalent circuit diagram illustrating a configuration example of a pixel region according to the first embodiment. FIG. 3 is a diagram illustrating a cross-sectional configuration example of a semiconductor substrate used in the solid-state imaging device according to the first embodiment. 1 is a diagram illustrating a cross-sectional configuration example of a solid-state imaging device according to a first embodiment. The figure which shows the relationship between the impurity concentration of the impurity introduction layer which concerns on 1st Embodiment, and an etching rate. The figure which shows the relationship between the impurity concentration of the impurity introduction layer which concerns on 1st Embodiment, and an etching rate. FIG. 3 is a diagram illustrating a cross-sectional configuration example of a unit pixel according to the first embodiment. FIG. 3 is a plan view showing a color filter arrangement according to the first embodiment. Sectional drawing which shows one manufacturing process of the solid-state imaging device which concerns on 1st Embodiment. Sectional drawing which shows one manufacturing process of the solid-state imaging device which concerns on 1st Embodiment. Sectional drawing which shows one manufacturing process of the solid-state imaging device which concerns on 1st Embodiment. Sectional drawing which shows one manufacturing process of the solid-state imaging device which concerns on 1st Embodiment. Sectional drawing which shows one manufacturing process of the solid-state imaging device which concerns on 1st Embodiment. Sectional drawing which shows one manufacturing process of the solid-state imaging device which concerns on 1st Embodiment. Sectional drawing which shows one manufacturing process of the solid-state imaging device which concerns on 1st Embodiment. The figure which shows the relationship between the depth of the solid-state imaging device which concerns on 1st Embodiment, and a boron density | concentration. Sectional drawing which shows one manufacturing process of the solid-state imaging device which concerns on 1st Embodiment. The figure for demonstrating one application example of the solid-state imaging device which concerns on 2nd Embodiment of this invention. Sectional drawing which shows one manufacturing process of the solid-state imaging device which concerns on a comparative example. Sectional drawing which shows one manufacturing process of the solid-state imaging device which concerns on a comparative example. Sectional drawing which shows one manufacturing process of the solid-state imaging device which concerns on a comparative example.

Explanation of symbols

55... Epitaxial layer (n-epi), 57... P-type impurity layer (p), 77... Impurity introduction layer (p + doped layer), 71... First support substrate (Si Support sub)

Claims (5)

A support substrate;
An impurity introduction layer provided in the support substrate and having an impurity concentration of 10 ¹⁹ / cm ³ or more and 5 × 10 ²⁰ / cm ³ or less;
A semiconductor substrate comprising an epitaxial layer formed on the impurity introduction layer. The semiconductor substrate is a substrate for manufacturing a solid-state imaging device,
The semiconductor substrate according to claim 1, wherein the impurity introduction layer functions as a stopper layer when the support substrate is thinned and removed. A step of introducing an impurity into the support substrate in a concentration range of 10 ¹⁹ / cm ³ or more and 5 × 10 ²⁰ / cm ³ or less to form an impurity introduction layer;
And a step of forming an epitaxial layer on the impurity introduction layer. Introducing an impurity into the first support substrate at a concentration of 10 ¹⁹ / cm ³ or more and 5 × 10 ²⁰ / cm ³ or less to form an impurity introduction layer;
Forming an epitaxial layer on the impurity introduction layer;
Forming an interlayer insulating film on the epitaxial layer, and forming a signal scanning circuit portion in the interlayer insulating film in the pixel region;
Bonding a second support substrate on the interlayer insulating film;
Using the impurity introduction layer as a stopper layer, thinning and removing the first support substrate;
Removing the impurity introduction layer;
Forming a pixel region in an epitaxial layer opposite to the surface of the epitaxial layer on which the signal scanning circuit portion is formed. When forming the impurity introduction layer, an impurity layer is simultaneously formed adjacent to the impurity introduction layer,
The method for manufacturing a solid-state imaging device according to claim 4, wherein the step of removing the impurity introduction layer is a CMP step utilizing selectivity with respect to the impurity layer.

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