JP2010087063A - Semiconductor device, and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a contact resistance similar to that of a top contact type, and to manufacture a minute structure equivalent to that of a bottom contact type. <P>SOLUTION: This semiconductor device includes: a gate electrode 11; a gate insulating film 12 formed on the gate electrode 11; source-drain electrodes 13, 14 formed on the gate insulating film 12 apart from each other; a recessed part 15 formed on the gate insulating film 12 between the source-drain electrodes 13, 14 and formed by entering the undersurface sides of the source-drain electrodes 13, 14; and a semiconductor layer 16 formed in the recessed part 15. Parts of the undersurfaces of the respective source-drain electrodes 13, 14 are connected to the upper surface of the semiconductor layer 16 on both end sides. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device using an organic semiconductor layer and a manufacturing method thereof.

  A semiconductor device using an organic semiconductor can be manufactured at a lower cost than a semiconductor device using a conventional inorganic semiconductor. As a result, the semiconductor device can be provided at a lower cost. In addition, semiconductor devices are expected to be flexible. As organic semiconductor materials, a wide range of materials such as polythiophene, pentacene, and rubrene have been studied, and some have reported that the mobility equivalent to amorphous silicon can be obtained.

As an element structure of a semiconductor device using an organic semiconductor, the following structure has been proposed. For example, there are BCBG (bottom contact / bottom gate) type, BCTG (bottom contact / top gate) type, TCBG (top contact / bottom gate) type, and TCTG (top contact / top gate) type. Of these, BCBG type and TCBG type device structures are well studied.
Usually, a bottom contact type structure takes a process of forming a semiconductor layer after forming an electrode. In this specification, for convenience, a type in which a semiconductor layer is formed after forming an electrode pattern is defined as a bottom contact type, and a type in which an electrode pattern is formed after forming a semiconductor layer is defined as a top contact type. The BCBG structure has a feature that the electrode and the insulating film are always in contact with each other because the semiconductor layer is formed after the electrode pattern is formed.

  In the case of a semiconductor layer formed by a similar film formation process, the TCBG type element structure tends to have a higher mobility than the BCBG type element structure. Most of the organic semiconductor devices that have been reported to have high mobility are TCBG type element structures.

  The reason why the TCBG element structure is likely to have a higher effective mobility than the BCBG element structure is that the contact resistance between the source / drain electrodes and the semiconductor layer tends to be lower than that of the BCBG element structure. It is thought that it is one of these (for example, refer nonpatent literature 1).

  On the other hand, the TC type electrode structure is mainly a method of vapor-depositing an electrode using a shadow mask. Therefore, the TC type electrode structure is more difficult to miniaturize than the BC type electrode structure. It tends to be.

  However, as the length of the channel between the source and drain becomes shorter due to miniaturization, the influence of the contact resistance between the source and drain electrodes and the semiconductor layer increases, and the effective mobility often decreases. It was.

Solid-State Electronics 47 (2003) p.259-262

  The problem to be solved is that it is difficult to realize miniaturization of a semiconductor device and reduction of contact resistance at the same time.

  The present invention realizes a contact resistance similar to that of the TC type and enables the fabrication of a fine structure similar to the BC type.

  The semiconductor device of the present invention (first semiconductor device) includes a gate electrode, a gate insulating film formed on the gate electrode, a source / drain electrode formed on the gate insulating film so as to be spaced apart from each other, and the source A recess formed in the gate insulating film between the drain electrodes and entering the lower surface side of each source / drain electrode; and a semiconductor layer formed in the recess; A part of the lower surface of the electrode is connected to the upper surfaces of both ends of the semiconductor layer.

  In the first semiconductor device of the present invention, a recess that enters the lower surface side of each source / drain electrode is formed in the gate insulating film between the source / drain electrodes. Therefore, in the semiconductor layer formed in the recess, a part of the lower surface of each source / drain electrode is connected to the upper surfaces on both ends of the semiconductor layer. That is, a top contact type electrode in which the semiconductor layer is substantially connected to the lower surface of the source / drain electrode, while having a bottom contact type electrode structure in which the source / drain electrode is formed on the gate insulating film. It has a structure.

  A semiconductor device (second semiconductor device) according to the present invention includes a gate electrode, a gate insulating film formed on the gate electrode, and a spacer formed on the gate insulating film on both sides above the gate electrode. A film, a source / drain electrode formed to protrude on the opposite side on each spacer film, and formed on the gate insulating film between the spacer films and on the lower surface side of each source / drain electrode It has a semiconductor layer formed so as to penetrate, and a part of the lower surface of each source / drain electrode is connected to the upper surface of both ends of the semiconductor layer.

  In the second semiconductor device of the present invention, the semiconductor layer is formed on the gate insulating film between the spacer films so as to enter the lower surface side of each source / drain electrode. It is connected to a part of the lower surface of the electrode. That is, a top contact type electrode in which the semiconductor layer is substantially connected to the lower surface of the source / drain electrode, while having a bottom contact type electrode structure in which the source / drain electrode is formed on the gate insulating film. It has a structure.

  A method of manufacturing a semiconductor device according to the present invention (first manufacturing method) includes a step of forming a gate insulating film on a gate electrode formed on a substrate, and forming a source / drain electrode on the gate insulating film separately. Connecting a part of the lower surface of each source / drain electrode to the recess; forming a recess that enters the lower surface side of each source / drain electrode in the gate insulating film between the source / drain electrodes; Forming a semiconductor layer to be formed.

  In the first method for manufacturing a semiconductor device of the present invention, a recess is formed in the gate insulating film between the source and drain electrodes, and a part of the lower surface of each source and drain electrode is formed in the recess. A semiconductor layer to be connected to is formed. A part of the upper surface of the semiconductor layer and a part of the lower surface of the source / drain electrode are connected to each other, and the connection part is substantially a top contact type source / drain electrode. Further, since the source / drain electrodes are formed connected to the gate insulating film, a bottom contact type electrode structure is obtained.

  The semiconductor device manufacturing method (second manufacturing method) according to the present invention includes a step of forming a gate insulating film on a gate electrode formed on a substrate, a step of forming a spacer film on the gate insulating film, Forming a source / drain electrode apart on the spacer film; removing the spacer film between the source / drain electrodes; and removing the spacer film so as to enter the lower surface side of each source / drain electrode Forming a recess, and forming a semiconductor layer connected to a part of the lower surface of each source / drain electrode in the recess.

  In the second manufacturing method of the semiconductor device of the present invention, a recess is formed in the spacer film on the side facing the source / drain electrode to expose a part of the lower surface of the source / drain electrode. A semiconductor layer connected to a part of the lower surface of the electrode is formed. Therefore, a part of the upper surface of the semiconductor layer and a part of the lower surface of the source / drain electrode are connected, and the connection part is substantially a top contact type source / drain electrode. Further, since the source / drain electrodes are formed on the gate insulating film through a spacer film, the source / drain electrodes can be a bottom contact type electrode structure.

  Each semiconductor device of the present invention has the advantage that the source / drain electrodes and the semiconductor layer equivalent to the top contact type can be arranged, so that the contact resistance is lowered and the effective mobility can be improved. In addition, since it has a bottom contact type electrode structure, it is possible to form a fine gate length, and there is an advantage that the element can be miniaturized.

  Each manufacturing method of the semiconductor device of the present invention enables the arrangement of the source / drain electrodes and the semiconductor layer equivalent to the top contact type, so that the contact resistance is reduced and the effective mobility can be improved. is there. In addition, since it has a bottom contact type electrode structure, it is possible to form a fine gate length, and there is an advantage that the element can be miniaturized.

Hereinafter, the best mode for carrying out the invention (hereinafter referred to as an embodiment) will be described.
1. 1st Embodiment (1st structural example of a semiconductor device).
2. 2nd Embodiment (2nd structural example of a semiconductor device).
3. 3rd Embodiment (1st manufacturing method of a semiconductor device).
4). 4th Embodiment (2nd manufacturing method of a semiconductor device).

<1. First Embodiment>
[First Configuration Example of Semiconductor Device]
A first embodiment (first configuration example of a semiconductor device) according to a semiconductor device of the present invention will be described with reference to a schematic sectional view of FIG.

As shown in FIG. 1, the first semiconductor device 1 has a gate electrode 11. The gate electrode 11 is formed on the substrate 10. The substrate 10 may be an insulating substrate formed on a semiconductor substrate, an insulating substrate (for example, a glass substrate, a ceramic substrate, a resin substrate, or the like).
A gate insulating film 12 is formed on the gate electrode 11. For the gate insulating film 12, for example, polyorganosilane or polyimide is used.
On the gate insulating film 12, source / drain electrodes 13 and 14 are formed apart from each other. The source / drain electrodes 13 and 14 are made of, for example, a metal material such as gold, platinum, silver, or copper.

A recess 15 is formed in the gate insulating film 12 between the source / drain electrodes 13, 14 so as to enter the lower surface side of the source / drain electrodes 13, 14. For example, the recess 15 has a depth of 3 nm or more and 100 nm or less, and more preferably a depth of 50 nm or less.
A semiconductor layer 16 is formed in the recess 15 so as to be in contact with the lower end of the source / drain electrodes 13 and 14. For example, the semiconductor layer 16 is formed with a film thickness equivalent to the depth of the recess 15.
For example, an organic semiconductor that can be formed by a coating method is used for the semiconductor layer 13. As the organic semiconductor, for example, Poly (3-hexylthiophene-2,5-diyl) (P3HT), 6,13-bis (triisopropylsilylyl) pentacene (TIPS pentacene), or the like is used.

In the first semiconductor device 1, the film thickness of the portion of the semiconductor layer 16 formed on the lower surface side of the source / drain electrodes 13, 14 and the source / drain electrodes 13, 14 from the surface of the gate insulating film 12 on the bottom surface of the recess 15. It is necessary that at least the height H up to the lower surface is equal. For example, the height H is desirably 3 nm or more and 100 nm or less, and more desirably 50 nm or less.
The reason is as follows. The semiconductor layer 16 needs to have a minimum film thickness of about 3 nm or more in order to ensure mobility. That is, if the film thickness of the semiconductor layer 16 is less than 3 nm, the function as a semiconductor layer cannot be performed sufficiently.
If the film thickness of the semiconductor layer 16 exceeds 100 nm, the contact resistance becomes too high, leading to a decrease in effective mobility.
For example, in the bottom contact type, it is known that the layer in which charge flows in the semiconductor layer 16 is about 3 nm to 5 nm.
Further, the overhanging length D of the source / drain electrodes 13 and 14 is preferably 50 nm to 100 nm or more, and when it is shorter than 50 nm, it is expected that it is difficult to sufficiently reduce the contact resistance. This is because the shape is close to the bottom contact type. When the recess 15 is formed by isotropic etching, the upper limit of the overhang length D is an etching length of 100 nm or less. In addition, when the amount of side etching can be adjusted with etching conditions, it is not necessary to set it within 100 nm. However, it is necessary to set the length so that the source / drain electrodes 13 and 14 can be stably connected to the gate insulating film 12.

  The source / drain electrodes 13 and 14 may be thiol-modified to reduce the contact resistance. When thiol modification is used, the electrode material of the source / drain electrodes 13 and 14 is a metal material that reacts with a thiol compound such as gold. In addition, modification of the thiol compound may increase the water repellency of the surface, and as a result, the physical contact of the electrode with the semiconductor layer 16 may be weakened. In this case, only the lower surface side of the source / drain electrodes 13 and 14 may be masked, and thiol modification may be performed.

  In the first semiconductor device 1, a recess 15 is formed in the gate insulating film 12 between the source / drain electrodes 13, 14 so as to enter the lower surface side of the source / drain electrodes 13, 14. Therefore, in the semiconductor layer 16 formed in the recess 15, a part of the lower surface of each source / drain electrode 13, 14 is connected to the upper surface on both ends of the semiconductor layer 16. That is, although the source / drain electrodes 13 and 14 are bottom contact type electrode structures formed on the gate insulating film 12, the semiconductor layer 16 is substantially formed on the lower surface of the source / drain electrodes 13 and 14. The top contact type electrode structure is connected.

  In the first semiconductor device 1, since the source / drain electrodes 13, 14 are directly connected to the gate insulating film 12, the source / drain electrodes 13, 14 may be formed before the semiconductor layer 16. This is a possible configuration. That is, the source / drain electrodes 13 and 14 can be processed so as to form a fine gate length without damaging the semiconductor layer 16.

<Modification 1>
[Modification of First Configuration Example of Semiconductor Device]
Next, a modification of the first semiconductor device will be described with reference to the schematic sectional view of FIG.

As shown in FIG. 2, the first semiconductor device 2 has a gate electrode 11. The gate electrode 11 is formed on the substrate 10. The substrate 10 may be an insulating substrate formed on a semiconductor substrate, an insulating substrate (for example, a glass substrate, a ceramic substrate, a resin substrate, or the like).
A gate insulating film 12 is formed on the gate electrode 11. For the gate insulating film 12, for example, polyorganosilane or polyimide is used.
On the gate insulating film 12, source / drain electrodes 13 and 14 are formed apart from each other. The source / drain electrodes 13 and 14 are made of, for example, a metal material such as gold, platinum, silver, or copper.

The gate insulating film 12 between the source / drain electrodes 13, 14 is formed with a recess 15 that enters the lower surface side of the source / drain electrodes 13, 14. For example, the recess 15 has a depth of 3 nm or more and 100 nm or less, and more preferably a depth of 50 nm or less.
A semiconductor layer 16 is formed in the recess 15 so as to be in contact with the lower end of the source / drain electrodes 13 and 14. Therefore, the semiconductor layer 16 is formed thicker than the depth of the recess 15. For example, the semiconductor layer 16 is formed so as to cover the side walls of the source / drain electrodes 13 and 14. Although not shown, the semiconductor layer 16 may be formed so as to cover the source / drain regions 13 and 14 as long as it is separated from a semiconductor layer of another adjacent semiconductor device. There is no.
For example, an organic semiconductor that can be formed by a coating method is used for the semiconductor layer 13. As the organic semiconductor, for example, Poly (3-hexylthiophene-2,5-diyl) (P3HT), 6,13-bis (triisopropylsilylyl) pentacene (TIPS pentacene), or the like is used.

In the first semiconductor device 2, the film thickness of the portion of the semiconductor layer 16 formed on the lower surface side of the source / drain electrodes 13 and 14 and the source / drain electrodes 13 and 14 from the surface of the gate insulating film 12 on the bottom surface of the recess 15. It is necessary that at least the height H up to the lower surface is equal. For example, the height H is desirably 3 nm or more and 100 nm or less, and more desirably 50 nm or less.
The reason is as follows. The semiconductor layer 16 needs to have a minimum film thickness of about 3 nm or more in order to ensure mobility. That is, if the film thickness of the semiconductor layer 16 is less than 3 nm, the function as a semiconductor layer cannot be performed sufficiently.
If the film thickness of the semiconductor layer 16 exceeds 100 nm, the contact resistance becomes too high, leading to a decrease in effective mobility.
For example, in the bottom contact type, it is known that the layer in which charge flows in the semiconductor layer 16 is about 3 nm to 5 nm.
Further, the overhanging length D of the source / drain electrodes 13 and 14 is preferably 50 nm to 100 nm or more, and when it is shorter than 50 nm, it is expected that it is difficult to sufficiently reduce the contact resistance. This is because the shape is close to the bottom contact type. When the recess 15 is formed by isotropic etching, the upper limit of the overhang length D is an etching length of 100 nm or less. In addition, when the amount of side etching can be adjusted with etching conditions, it is not necessary to set it within 100 nm. However, it is necessary to set the length so that the source / drain electrodes 13 and 14 can be stably connected to the gate insulating film 12.

  Similarly to the semiconductor device 1, the source / drain electrodes 13 and 14 can be thiol-modified to reduce the contact resistance.

In the first semiconductor device 2, a recess 15 is formed in the gate insulating film 12 between the source / drain electrodes 13, 14 so as to enter the lower surface side of the source / drain electrodes 13, 14.
Therefore, in the semiconductor layer 16 formed in the recess 15, a part of the lower surface of each source / drain electrode 13, 14 is connected to the upper surface on both ends of the semiconductor layer 16.
That is, although the source / drain electrodes 13 and 14 are bottom contact type electrode structures formed on the gate insulating film 12, the semiconductor layer 16 is substantially formed on the lower surface of the source / drain electrodes 13 and 14. The top contact type electrode structure is connected.
In the first semiconductor device 2, the semiconductor layer 16 is formed thicker than the depth of the recess 15. That is, the semiconductor layer 16 is formed so as to cover the side walls of the source / drain electrodes 13 and 14, but this does not impair the top contact type electrode structure.

  In the first semiconductor device 1, since the source / drain electrodes 13, 14 are directly connected to the gate insulating film 12, the source / drain electrodes 13, 14 may be formed before the semiconductor layer 16. This is a possible configuration. That is, the source / drain electrodes 13 and 14 can be processed so as to form a fine gate length without damaging the semiconductor layer 16.

<2. Second Embodiment>
[Second Configuration Example of Semiconductor Device]
Next, a second embodiment (second configuration example of the semiconductor device) according to the semiconductor device of the present invention will be described with reference to a schematic sectional view of FIG.

As shown in FIG. 3, the second semiconductor device 3 has a gate electrode 11. The gate electrode 11 is formed on the substrate 10. The substrate 10 may be an insulating substrate formed on a semiconductor substrate, an insulating substrate (for example, a glass substrate, a ceramic substrate, a resin substrate, or the like).
A gate insulating film 12 is formed on the gate electrode 11. For the gate insulating film 12, for example, polyorganosilane or polyimide is used.

Spacer films 21 and 22 are formed on the gate insulating film 12 on both sides above the gate electrode 11 so as to be separated from each other. The spacer films 21 and 22 are formed of a film that is selectively etched with respect to the gate insulating film 12. For example, a titanium film can be used as a material in which no current flows between the semiconductor layer 16 described later. The spacer films 21 and 22 are formed with a film thickness of, for example, 3 nm or more and 100 nm or less, preferably 50 nm or less.
On each of the spacer films 21 and 22, source / drain electrodes 13 and 14 are formed so as to protrude to the opposite sides. Therefore, the source / drain electrodes 13 and 14 are formed apart from each other. The source / drain electrodes 13 and 14 are made of a metal material such as gold, platinum, silver, or copper.

A semiconductor layer 16 is formed on the gate insulating film 12 between the spacer films 21 and 22 so as to be in contact with the lower end portions of the source / drain electrodes 13 and 14. For example, the semiconductor layer 16 is formed to be equal to or thicker than the film thickness of the spacer films 21 and 22.
Therefore, the thickness of the semiconductor layer 16 between the lower surfaces of the source / drain electrodes 13 and 14 and the gate insulating film 12 is 3 nm or more and 100 nm or less, preferably 50 nm or less.
For example, an organic semiconductor that can be formed by a coating method is used for the semiconductor layer 13. As the organic semiconductor, for example, Poly (3-hexylthiophene-2,5-diyl) (P3HT), 6,13-bis (triisopropylsilylyl) pentacene (TIPS pentacene), or the like is used.

In the second semiconductor device 3, the film thickness of the portion of the semiconductor layer 16 formed on the lower surface side of the source / drain electrodes 13, 14 and the surface from the surface of the gate insulating film 12 to the lower surfaces of the source / drain electrodes 13, 14. The height H needs to be at least equivalent. For example, the height H is preferably 3 nm or more and preferably 100 nm or less, and more preferably 50 nm or less.
The reason is that the semiconductor layer 16 needs a minimum film thickness in order to secure mobility and keeps the contact resistance low.
That is, when the thickness of the semiconductor layer 16 is less than 3 nm, the function as a semiconductor layer is not sufficiently performed, and when the thickness of the semiconductor layer 16 exceeds 100 nm, the contact resistance becomes too high and the effective mobility is increased. This is because it leads to a decline.
For example, in the bottom contact type, it is known that the layer in which charge flows in the semiconductor layer 16 is about 3 nm to 5 nm.
Further, the overhanging length D of the source / drain electrodes 13 and 14 is preferably 50 nm to 100 nm or more, and when it is shorter than 50 nm, it is expected that it is difficult to sufficiently reduce the contact resistance. This is because the shape is close to the bottom contact type. When the recess 15 is formed by isotropic etching, the upper limit of the overhang length D is an etching length of 100 nm or less. In addition, when the amount of side etching can be adjusted with etching conditions, it is not necessary to set it within 100 nm. However, it is necessary to set the length so that the source / drain electrodes 13 and 14 can be stably connected to the gate insulating film 12.

  Similarly to the semiconductor device 1, the source / drain electrodes 13 and 14 can be thiol-modified to reduce the contact resistance.

In the second semiconductor device 3, a recess 15 is formed in the gate insulating film 12 between the source / drain electrodes 13, 14 so as to enter the lower surface side of the source / drain electrodes 13, 14. Therefore, in the semiconductor layer 16 formed in the recess 15, a part of the lower surface of each source / drain electrode 13, 14 is connected to the upper surface on both ends of the semiconductor layer 16. That is, although the source / drain electrodes 13 and 14 are bottom contact type electrode structures formed on the gate insulating film 12, the semiconductor layer 16 is substantially formed on the lower surface of the source / drain electrodes 13 and 14. The top contact type electrode structure is connected.
In the second semiconductor device 3, the semiconductor layer 16 may be formed thicker than the depth of the recess 15. That is, even if the semiconductor layer 16 is formed so as to cover the side walls of the source / drain electrodes 13 and 14, the top contact type electrode structure is not impaired.

  In the second semiconductor device 3, since the source / drain electrodes 13, 14 are directly connected to the gate insulating film 12, the source / drain electrodes 13, 14 may be formed before the semiconductor layer 16. This is a possible configuration. That is, the source / drain electrodes 13 and 14 can be processed so as to form a fine gate length without damaging the semiconductor layer 16.

  Here, the resistance between the source and drain of the top contact type TFT and the resistance between the source and drain of the bottom contact type TFT (the lower this resistance, the higher the effective mobility in the short channel) was examined, and the results are shown in FIG. 4 shows. In FIG. 4, the vertical axis represents the resistance between the source and the drain, and the horizontal axis represents the gate length.

  As shown in FIG. 4, it can be seen that the resistance Rs between the source and the drain of the top contact (TC) type TFT is lower than the resistance between the source and the drain of the bottom contact (BC) type TFT. That is, the effective mobility of the top contact type TFT is higher than that of the bottom contact type TFT. As can be seen from this knowledge, the source / drain electrodes 13 and 14 of the present invention are configured such that a part of the semiconductor layer 16 is sandwiched between the gate insulating film 12 and the overhanging portion by providing the overhanging portion. It becomes. It turns out that the resistance between the source and the drain is low because the source / drain electrode is substantially a top contact type.

  Further, since the source / drain electrodes 13 and 14 can be formed before the semiconductor layer 16, the source / drain is formed so as to form a fine gate length without damaging the semiconductor layer 16. The electrodes 13 and 14 can be formed. That is, since the source / drain electrodes 13 and 14 can be formed by the lithography technique, the source / drain electrodes 13 and 14 can be miniaturized, for example. This means that the channel length can be miniaturized. Even if such miniaturization is performed, the semiconductor layer 16 that has been conventionally formed by a vapor deposition method can be formed by a coating method using an organic semiconductor. From this point, for example, the gate length can be miniaturized.

  Therefore, since the first semiconductor devices 1 and 2 and the second semiconductor device 3 can be arranged with the source / drain electrodes 13 and 14 equivalent to the top contact type, the resistance between the source and the drain becomes low, and the effective. Mobility can be improved. In addition, since a fine gate length can be formed, the element can be miniaturized. Further, since the first semiconductor devices 1 and 2 can be formed directly on the gate insulating film 12, there is an advantage that the connection between the source / drain electrodes 13 and 14 is strengthened.

<3. Third Embodiment>
[First Manufacturing Method of Semiconductor Device]
Next, a third embodiment (an example of a first method for manufacturing a semiconductor device) according to the present invention will be described with reference to the manufacturing process sectional views of FIGS.

  As shown in FIG. 5A, after forming the gate electrode 11 on the substrate 10 and further forming the gate insulating film 12 covering the gate electrode 11, the mask layer 31 is formed on the gate insulating film 12. . The gate electrode 11 is formed of a metal material such as gold, platinum, silver, copper, or aluminum. The gate insulating film 12 is made of, for example, polyorganosilane or polyimide. The mask layer 31 is formed using, for example, a positive resist. Next, an exposure mask 61 for exposure is prepared above the mask layer 31.

  Next, as shown in FIG. 5 (2), the mask layer 31 is exposed and developed using the exposure mask 61 (see FIG. 5 (1)) so that the source / drain electrodes are formed. Openings 32 and 33 are formed.

  Next, as shown in FIG. 5 (3), the source / drain electrode material 34 is deposited on the mask 31 in the openings 32 and 33, and the openings 32 and openings. Deposition is performed so that portions other than 33 that are deposited on the mask 31 are not connected. For the source / drain electrode material 34, for example, a metal material such as gold, platinum, silver, or copper is used.

  Next, as shown in FIG. 6 (4), the mask 31 (see FIG. 5 (3)) is removed. At the same time, the source / drain electrode material 34 (see FIG. 5 (3)) deposited on the mask 31 except for the inside of the opening 32 and the opening 33 (see FIG. 5 (3)) is removed. As a result, source / drain electrodes 13 and 14 are formed on the gate insulating film 12 with the source / drain electrode material 34 left in the opening 32 and the opening 33. Accordingly, the source / drain electrodes 13 and 14 are formed on the gate insulating film 12 apart from each other.

Next, as shown in FIG. 6 (5), a recess 15 is formed in the gate insulating film 12 between the source / drain electrodes 13, 14 so as to enter the lower surface side of the source / drain electrodes 13, 14. For example, wet etching is used to form the recess 15. The gate insulating film 12 is etched in the film thickness direction of the gate insulating film 12 by, for example, isotropic etching by wet etching, and the gate insulating film 12 is inserted into the lower surface side of the source / drain electrodes 13 and 14. Etch.
In the wet etching, when the gate insulating film 12 is formed of polyorganosilane, for example, an organic alkaline solution [TMAH] (Tetra-methyl-ammonium-hydroxide) solution is used as an etching solution.
Normally, side etching by wet etching varies depending on etching conditions. Therefore, the side etching amount can be controlled by selecting the etching conditions.

  Next, as shown in FIG. 6 (6), the semiconductor is connected to the recess 15 between the source / drain electrodes 13, 14 so as to be at least partially connected to the lower surface of the end of the source / drain electrodes 13, 14. Layer 16 is formed. For example, an organic semiconductor that can be formed by a coating method can be used for forming the semiconductor layer 16. As the organic semiconductor, for example, Poly (3-hexylthiophene-2,5-diyl) (P3HT), 6,13-bis (triisopropylsilylyl) pentacene (TIPS pentacene), or the like is used.

The film thickness of the portion of the semiconductor layer 16 formed on the lower surface side of the source / drain electrodes 143 and 154 and the height from the surface of the gate insulating film 12 to the lower surface of the source / drain electrodes 13 and 14 on the bottom surface of the recess 15 H must be at least equivalent. For example, the height H is desirably 3 nm or more and 100 nm or less, and more desirably 50 nm or less.
The reason is the same as described above. That is, the semiconductor layer 16 needs to have a minimum film thickness of about 3 nm or more in order to ensure mobility. That is, if the film thickness of the semiconductor layer 16 is less than 3 nm, the function as a semiconductor layer cannot be performed sufficiently.
If the film thickness of the semiconductor layer 16 exceeds 100 nm, the contact resistance becomes too high, leading to a decrease in effective mobility.
For example, in the bottom contact type, it is known that the layer in which charge flows in the semiconductor layer 16 is about 3 nm to 5 nm.
Further, the overhanging length D of the source / drain electrodes 13 and 14 is preferably 50 nm to 100 nm or more, and when it is shorter than 50 nm, it is expected that it is difficult to sufficiently reduce the contact resistance. This is because the shape is close to the bottom contact type. When the recess 15 is formed by isotropic etching, the upper limit of the overhang length D is an etching length of 100 nm or less. In addition, when the amount of side etching can be adjusted with etching conditions, it is not necessary to set it within 100 nm. However, it is necessary to set the length so that the source / drain electrodes 13 and 14 can be stably connected to the gate insulating film 12.

  Similarly to the semiconductor device 1, the source / drain electrodes 13 and 14 can be thiol-modified to reduce the contact resistance.

  In the first manufacturing method of the semiconductor device of the present invention, the recess 15 is formed in the gate insulating film 12 between the source / drain electrodes 13, 14 so as to enter the lower surface side of the source / drain electrodes 13, 14. Then, a semiconductor layer 16 connected to a part of the lower surface of each source / drain electrode 13, 14 is formed in the recess 15. Therefore, a part of the upper surface of the semiconductor layer 16 and a part of the lower surface of the source / drain electrodes 13, 14 are connected, and the top contact type source / drain electrodes 13, 14 are substantially connected at the connection part. It becomes.

  Further, since the source / drain regions 13 and 14 are directly connected to the gate insulating film 12, the source / drain regions 13 and 14 can be formed before the semiconductor layer 16. Therefore, the source / drain regions 13 and 14 can be processed so as to form a fine gate length without damaging the semiconductor layer 16.

<4. Fourth Embodiment>
[Second Method for Manufacturing Semiconductor Device]
Next, a fourth embodiment (an example of a second manufacturing method of a semiconductor device) according to the present invention will be described with reference to a manufacturing process sectional view of FIG.

  As shown in FIG. 7A, after forming the gate electrode 11 on the substrate 10 and further forming the gate insulating film 12 covering the gate electrode 11, the spacer film 41 is formed on the gate insulating film 12. . The gate electrode 11 is formed of a metal material such as gold, platinum, silver, copper, or aluminum. The gate insulating film 12 is made of, for example, cross-linked polyvinyl phenol or cross-linked polyethylene. The spacer film 41 is formed using, for example, a titanium film. Alternatively, the spacer film 41 can be formed using, for example, polyorganosilane or polyimide.

Next, as described with reference to FIGS. 5A and 5B, the source / drain electrodes 13 and 14 are formed apart from each other.
That is, the mask layer 31 is formed on the spacer film 41. The mask layer 31 is formed using, for example, a positive resist. Next, an exposure mask 61 for exposure is prepared above the mask layer 31.
Next, the mask layer 31 is exposed and developed using the exposure mask 61 (see FIG. 5A) to form openings 32 and 33 in portions where the source / drain electrodes are formed.
Next, as shown in FIG. 5 (3), the source / drain electrode material 34 is deposited on the mask 31 in the openings 32 and 33, and the openings 32 and openings. The deposition is performed so that the portion deposited on the mask 31 except the portion 33 is not connected. For the source / drain electrode material 34, for example, a metal material such as gold, platinum, silver, or copper is used.

  Next, the mask 31 (see FIG. 5 (3)) is removed, and at the same time, the source / drain deposited on the mask 31 except for the inside of the opening 32 and the opening 33 (see FIG. 6 (2)). The drain electrode material 34 is removed, and the source / drain electrodes 13 and 14 are formed on the gate insulating film 12 with the source / drain electrode material 34 left in the opening 32 and the opening 33. Accordingly, the source / drain electrodes 13 and 14 are formed on the gate insulating film 12 apart from each other.

Next, as shown in FIG. 7 (2), the spacer film 41 between the source / drain electrodes 13, 14 is removed and the spacer film so as to enter the lower surface side of the source / drain electrodes 13, 14. 41 is removed to form a recess 42.
For example, wet etching is used to form the recess 42. The spacer film 41 is etched in the film thickness direction of the spacer film 41 by, for example, isotropic etching by wet etching, and the spacer film 41 is etched so as to enter the lower surface side of the source / drain electrodes 13 and 14.
In the wet etching, when the gate insulating film 12 is made of polyvinylphenol and polyethylene and the source / drain electrodes 13 and 14 are made of gold, for example, an organic alkaline solution [TMAH] (Tetra) is used as an etching solution. -Methyl-ammonium-hydroxyde) solution].
Normally, side etching by wet etching varies depending on etching conditions. Therefore, the side etching amount can be controlled by selecting the etching conditions.

  Next, as shown in FIG. 7 (3), the semiconductor is connected to the recess 42 between the source / drain electrodes 13, 14 so as to be at least partially connected to the lower surfaces of the end portions of the source / drain electrodes 13, 14. Layer 16 is formed. For example, an organic semiconductor that can be formed by a coating method can be used for forming the semiconductor layer 16. As the organic semiconductor, for example, Poly (3-hexylthiophene-2,5-diyl) (P3HT), 6,13-bis (triisopropylsilylyl) pentacene (TIPS pentacene), or the like is used.

The thickness of the portion of the semiconductor layer 16 formed on the lower surface side of the source / drain electrodes 13, 14 and the height from the surface of the gate insulating film 12 on the bottom surface of the recess 42 to the lower surface of the source / drain electrodes 13, 14. H must be at least equivalent. For example, the height H is desirably 3 nm or more and 100 nm or less, and more desirably 50 nm or less.
The reason is the same as described above. That is, the semiconductor layer 16 needs to have a minimum film thickness of about 3 nm or more in order to ensure mobility. That is, if the film thickness of the semiconductor layer 16 is less than 3 nm, the function as a semiconductor layer cannot be performed sufficiently.
If the film thickness of the semiconductor layer 16 exceeds 100 nm, the contact resistance becomes too high, leading to a decrease in effective mobility.
For example, in the bottom contact type, it is known that the layer in which charge flows in the semiconductor layer 16 is about 3 nm to 5 nm.
Further, the overhanging length D of the source / drain electrodes 13 and 14 is preferably 50 nm to 100 nm or more, and when it is shorter than 50 nm, it is expected that it is difficult to sufficiently reduce the contact resistance. This is because the shape is close to the bottom contact type. When the recess 15 is formed by isotropic etching, the upper limit of the overhang length D is an etching length of 100 nm or less. In addition, when the amount of side etching can be adjusted with etching conditions, it is not necessary to set it within 100 nm. However, it is necessary to set the length so that the source / drain electrodes 13 and 14 can be stably connected to the gate insulating film 12.

  Similarly to the semiconductor device 1, the source / drain electrodes 13 and 14 can be thiol-modified to reduce the contact resistance.

[Modification of Second Manufacturing Method of Semiconductor Device]
Further, as shown in FIG. 8, the semiconductor layer 16 may be formed so as to cover a part of the side wall portions of the source / drain electrodes 13 and 14. It is only necessary that a part of the lower surface of the source / drain electrodes 13 and 14 is connected to a part of the upper surface of the semiconductor layer 16.

  In the second manufacturing method of the semiconductor device of the present invention, the spacer film 41 between the source / drain electrodes 13, 14 is removed to form a recess 42 that enters the lower surface side of each source / drain electrode 13, 14. Then, the semiconductor layer 16 connected to a part of the lower surface of each of the source / drain electrodes 13, 14 is formed in the recess 42. Therefore, a part of the upper surface of the semiconductor layer 16 and a part of the lower surface of the source / drain electrodes 13, 14 are connected, and the top contact type source / drain electrodes 13, 14 are substantially connected at the connection part. It becomes.

  Further, since the source / drain regions 13 and 14 are directly connected to the spacer film 41 formed on the gate insulating film 12, the source / drain regions 13 and 14 may be formed before the semiconductor layer 16. It becomes possible. Therefore, the source / drain regions 13 and 14 can be processed so as to form a fine gate length without damaging the semiconductor layer 16.

  As described above, the semiconductor device and the manufacturing method thereof according to the present invention have the characteristics of the top contact structure while the source / drain regions 13 and 14 have the bottom contact structure. Therefore, the contact resistance can be kept low. Further, conventionally, since the semiconductor layer 16 was formed by a vapor deposition method, miniaturization was limited by the size of the vapor deposition mask, but the semiconductor layer 16 can be formed by a coating method using an organic semiconductor. The element can be miniaturized.

  In each of the above manufacturing methods, the gate electrode 12 is formed to have a length equivalent to that of the semiconductor layer 16, but may be formed to be longer than the semiconductor layer 16.

1 is a schematic cross-sectional view showing a first embodiment (first configuration example of a semiconductor device) according to a semiconductor device of the present invention. FIG. 10 is a schematic cross-sectional view showing a modification of the first semiconductor device. FIG. 5 is a schematic cross-sectional view showing a second embodiment (second configuration example of a semiconductor device) according to the semiconductor device of the present invention. It is a drawing showing the resistance between the source and drain of the top contact type TFT and the resistance between the source and drain of the bottom contact type TFT. It is manufacturing process sectional drawing which showed 3rd Embodiment (an example of the 1st manufacturing method of a semiconductor device) concerning this invention. It is manufacturing process sectional drawing which showed 3rd Embodiment (an example of the 1st manufacturing method of a semiconductor device) concerning this invention. It is manufacturing process sectional drawing which showed 4th Embodiment (an example of the 2nd manufacturing method of a semiconductor device) which concerns on this invention. It is a schematic structure sectional view showing the modification of the 2nd manufacturing method of a semiconductor device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 11 ... Gate electrode, 12 ... Gate insulating film, 13, 14 ... Source-drain electrode, 15 ... Recessed part, 16 ... Semiconductor layer

Claims (8)

A gate electrode;
A gate insulating film formed on the gate electrode;
Source / drain electrodes formed on the gate insulating film apart from each other;
A recess formed in the gate insulating film between the source / drain electrodes and formed to enter the lower surface side of each source / drain electrode;
Having a semiconductor layer formed in the recess,
A semiconductor device in which a part of the lower surface of each of the source / drain electrodes is connected to the upper surfaces of both ends of the semiconductor layer. The semiconductor device according to claim 1, wherein the semiconductor layer is made of an organic semiconductor. The semiconductor device according to claim 1, wherein the semiconductor layer is also formed on a side portion of the source / drain electrode. A gate electrode;
A gate insulating film formed on the gate electrode;
A spacer film formed on and separated from the gate insulating film on both sides above the gate electrode;
A source / drain electrode formed on each spacer film so as to protrude on the opposite side;
A semiconductor layer formed on the gate insulating film between the spacer films and formed to enter the lower surface side of each of the source / drain electrodes;
A semiconductor device in which a part of the lower surface of each of the source / drain electrodes is connected to the upper surfaces of both ends of the semiconductor layer. The semiconductor device according to claim 4, wherein the semiconductor layer is made of an organic semiconductor. The semiconductor device according to claim 4, wherein the semiconductor layer is also formed on a side portion of the source / drain electrode. Forming a gate insulating film on the gate electrode formed on the substrate;
Forming a source / drain electrode on the gate insulating film apart from each other;
Forming a recess that enters the lower surface side of each source / drain electrode in the gate insulating film between the source / drain electrodes;
Forming a semiconductor layer connected to a part of the lower surface of each of the source / drain electrodes in the recess, in order. Forming a gate insulating film on the gate electrode formed on the substrate;
Forming a spacer film on the gate insulating film;
Forming a source / drain electrode apart on the spacer film;
Removing the spacer film between the source / drain electrodes and removing the spacer film so as to enter the lower surface side of each source / drain electrode;
Forming a semiconductor layer connected to a part of the lower surface of each of the source / drain electrodes in the recess, in order.

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