JP2010086980A - Method for manufacturing semiconductor device, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To avoid the problem of a processing process such as the collapse of a resist pattern at ends of a plurality of line patterns. <P>SOLUTION: After a member to be patterned is formed on a semiconductor substrate, the member to be patterned is patterned to form a plurality of line patterns in parallel, and dummy patterns are formed from the end of the line pattern in a direction perpendicular to the longitudinal direction of the line pattern at predetermined intervals. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device, and more particularly to a semiconductor device manufacturing method and a semiconductor device in which a plurality of line-shaped patterns are formed in parallel.

  Due to recent advances in microfabrication technology, the minimum processing size of semiconductor devices has fallen below 100 nm, and the difficulty of processing has become much higher. Among the semiconductor devices, the memory cell array of the NAND type nonvolatile semiconductor memory device has a structure in which the number of contacts per cell is reduced. Therefore, the layout of the wiring layer such as the word line and the bit line is the minimum processing size line & The layout requires a state-of-the-art microfabrication technique such as space (see, for example, Patent Document 1).

  In the case of such a NAND type nonvolatile semiconductor memory device layout, there is a possibility that the resist pattern collapses as the miniaturization progresses at the end of the word line on the side where the potential is not drawn to the wiring layer above the word line. is there. It is known that this is caused by the thinness and shape problem of the photoresist pattern due to the proximity effect and the like, and non-uniformity of water droplets remaining at the time of rinsing drying after development. In addition, depending on processing conditions and processing contents, it is known that resist collapse occurs during etching of a lower layer film of a photoresist using the photoresist as a mask.

  Conventionally, this phenomenon has been dealt with by reducing the film thickness of the photoresist. However, the film thickness of the photoresist is the film thickness necessary for processing the lower layer film under it to improve resolution. It has already become thinner to the limit, and it has become impossible to make a photoresist thin film easily.

  Therefore, a method of avoiding the occurrence of resist pattern collapse by expanding the end of the word line in terms of area is also considered. (For example, refer to Patent Document 2). However, this method cannot avoid an increase in layout pattern area.

Such a problem is not limited to the nonvolatile semiconductor memory device, and may be a problem in other semiconductor devices as well.
JP 2002-313970 A JP 2004-15056 A

  In view of the above problems, an object of the present invention is to provide a semiconductor device manufacturing method and a semiconductor device capable of avoiding problems in processing processes such as resist pattern collapse.

  In order to solve the above problems, a method for manufacturing a semiconductor device according to the present invention includes a step of forming a patterning member on a semiconductor substrate, and patterning the patterning member to form a plurality of line-shaped patterns in parallel. And a step of forming a dummy pattern in a direction perpendicular to the longitudinal direction so as to face the end portions of the plurality of line-shaped patterns at a predetermined interval from the longitudinal ends of the plurality of line-shaped patterns.

  Further, a semiconductor device according to the present invention includes a plurality of word lines whose longitudinal direction is formed along a predetermined direction on a semiconductor substrate, and end portions of the word lines at predetermined intervals from the end portions of the plurality of word lines. And a dummy pattern having a longitudinal direction formed along a direction orthogonal to a predetermined direction so as to face each other.

  According to the present invention, problems of processing processes such as photoresist pattern collapse can be avoided.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  In the first embodiment of the present invention, problems in processing processes such as resist pattern collapse that occur in areas requiring a fine wiring processing technique such as a memory cell array section in a NAND type nonvolatile semiconductor memory device are addressed. This is avoided by changing the pattern layout, and a stable and high yield can be realized.

  First, the configuration of the NAND-type nonvolatile semiconductor memory device according to this embodiment will be described with reference to FIGS. FIG. 1 is a plan view showing a configuration of end regions of a word line and a select gate line of the nonvolatile semiconductor memory device according to the present embodiment, and FIG. 2A is a cross-sectional view taken along line AA ′ in FIG. 2B is a cross-sectional view taken along the line BB ′, and FIG. 2C is a cross-sectional view taken along the line CC ′.

  As shown in FIG. 1, in the nonvolatile semiconductor memory device according to this embodiment, a plurality of active regions AA extending in the first direction X are formed in parallel on the surface of the semiconductor substrate. An element isolation region STI is formed on the surface of the semiconductor substrate between the active regions AA. A plurality of word lines WL extending in a second direction orthogonal to the first direction X are formed in parallel on the semiconductor substrate. A gate electrode MG of the memory cell transistor is formed between the word line and the active area AA. A select gate line SGL is provided in parallel with the word line WL, and a gate electrode SG of a select gate transistor is formed between the select gate line SGL and the active region AA. In the end regions of the plurality of word lines WL, dummy patterns WLD that face the end portions of the word lines WL with a predetermined interval S, extend in the first direction X, and have a width W in the short direction are formed. Has been. The dummy pattern WLD is formed in order to prevent the resist from thinning at the tip of the word line WL, or shorting of the pattern or opening of the pattern in the end region of the word line WL.

  As shown in FIG. 2, a plurality of element isolation insulating films 102 that form an element isolation region STI and are formed of a silicon oxide film are embedded in the surface of the semiconductor substrate 100 at a predetermined interval. The upper surface of each element isolation insulating film 102 protrudes upward from the surface of the semiconductor substrate 100. A tunnel insulating film 104 made of a silicon oxide film or the like is formed on each of the plurality of active regions AA partitioned by the element isolation insulating film 102. A first polycrystalline silicon film 106 constituting a floating gate electrode is formed on each tunnel insulating film 104. The side surface of the first polycrystalline silicon film 106 is formed to be flush with the side surface of the element isolation insulating film 102 protruding from the surface of the semiconductor substrate 100. Further, the height of the upper surface of the first polycrystalline silicon film 106 is formed to be higher than the height of the upper surface of the element isolation insulating film 102. An ONO film (silicon oxide film) is formed on the upper surface of the element isolation insulating film 102, the upper surface of the first polycrystalline silicon film 106, and the side surface of the first polycrystalline silicon film 106 positioned above the upper surface of the element isolation insulating film 102. , A laminated structure of a silicon nitride film and a silicon oxide film) is formed continuously. The interelectrode insulating film 108 is not limited to the ONO film, but is a high dielectric such as a NONON film (a silicon nitride film, a silicon oxide film, a silicon nitride film, a silicon oxide film, a silicon nitride film laminated structure), or alumina (Al 2 O 3). A rate of metal oxide film may be used. A second polycrystalline silicon film 110 is formed on the interelectrode insulating film 108, and a low resistance conductive film 112 is formed on the second polycrystalline silicon film 110. The low resistance conductive film 112 is composed of a tungsten silicide (WSi) film, a nickel silicide (NiSi) film, a cobalt silicide (CoSi) film, or the like. The second polycrystalline silicon film 110 and the low resistance conductive film 112 constitute a control gate electrode (word line WL). A silicon nitride film 114 as a mask is formed on the low resistance conductive film 112.

  In the end region of the word line WL, the element isolation insulating film 102 is formed so that the height of the upper surface thereof coincides with the height of the upper surface of the first polycrystalline silicon film 106. The interelectrode insulating film 108, the word line WL is formed on the upper surface of the element isolation insulating film 102. A dummy pattern WLD having a width W is formed on the element isolation insulating film 102 with a predetermined interval S from the end of the word line WL. This dummy pattern WLD is also composed of the interelectrode insulating film 108, the second polycrystalline silicon film 110, the low resistance conductive film 112, and the silicon nitride film 114, but does not function as a word line or a select gate line.

Next, a manufacturing process of the nonvolatile semiconductor memory device according to this embodiment will be described with reference to FIGS. Each of FIGS. 3A to 7A is a diagram for explaining a manufacturing process using a cross section taken along line AA ′ of FIG. 1, and each of FIGS. 3A to 7B is a line BB ′ of FIG. It is a figure explaining a manufacturing process using a line section, and each (c) of Drawing 3 thru / or Drawing 7 is a figure explaining a manufacturing process using a CC 'line section of Drawing 1.

  First, as shown in FIG. 3, a plurality of element isolation insulating films 102 are formed on the surface of the semiconductor substrate 100 by a known method, and a tunnel insulating film 104 and a first polycrystalline silicon film are formed on each active region AA. 106, and further, an interelectrode insulating film 108, a second polycrystalline silicon film 110, a low-resistance conductive film 112, and a silicon nitride film 114 are formed on the element isolation insulating film 102 and the first polycrystalline silicon film 106. To do.

  Next, as shown in FIG. 4, an antireflection film 120 is formed on the silicon nitride film 114. Subsequently, a photoresist 122 is formed on the antireflection film 120, and the photoresist 122 is processed into a desired pattern by a lithography technique. At this time, the photoresist 122 is processed according to each word line WL, and the photoresist 122 is processed so that the dummy pattern WLD is formed in the end region of the word line WL.

  Next, as shown in FIG. 5, the antireflection film 120 and the silicon nitride film 114 are etched by the RIE technique using the photoresist 122 processed into a desired pattern as a mask.

  Next, as shown in FIG. 6, the antireflection film 120 and the photoresist 122 are removed using an ashing technique.

  Next, using the silicon nitride film 114 as a mask, the low-resistance conductive film 112, the second polycrystalline silicon film, the interelectrode insulating film 108, and the first polycrystalline silicon film 106 are etched, and FIG. As shown, the floating gate electrode made of the first polycrystalline silicon film 106, the gate electrode of the memory cell made of the control gate electrode (word line WL) made of the second polycrystalline silicon film 110 and the low-resistance conductive film 112 As a result, a dummy pattern WLD is obtained.

  Next, in the formation of the dummy pattern WLD shown in FIG. 4, the preferable conditions of the width W of the dummy pattern WLD and the interval S between the dummy pattern WLD and the end of the word line WL will be described.

  In order to derive a combination effective for resist pattern collapse in the relationship between the width W of the dummy pattern WLD and the distance S between the end of the word line WL and the dummy pattern WLD shown in FIG. As a method for determining the fall prevention effect at the end of the word line WL, a method for deriving using the image intensity distribution at the end of the word line WL has been developed.

  FIG. 7 shows an image intensity distribution during the lithography process in the A-A ′ cross section in FIG. 1 with and without the dummy pattern WLD. The inventor determined that Contrast = (Imax−Ib ′) / (Imax + Ib ′) as the contrast at the end of the word line WL in the lithography process (here, the ratio of the image intensity to the Max intensity at the BB ′ sectional position). Focusing on the fact that the higher the value is, the more effective the prevention of the fall of the end of the line is.

  FIGS. 8 and 9 show the distance S between the contrast dummy pattern WLD and the end of the word line WL and the width W dependency of the dummy pattern WLD, respectively. The contrast values indicated by dotted lines in FIGS. 8 and 9 indicate the contrast when the dummy pattern WLD in FIG. 7 is not present.

  8 shows the case of W = λ / NA, and FIG. 9 shows the case of S = 1.2λ / NA (λ shows the exposure wavelength and the numerical aperture of the NA exposure apparatus).

  From these results, it was determined that a condition in which a contrast improvement effect of 10% or more was obtained as compared with the case where there was no dummy pattern was a suitable condition, and as a result, from FIG. The preferred condition for the interval S is S ≦ 2.2λ / NA, while FIG. 9 shows that the preferred condition for the width W of the dummy pattern WLD is also W ≦ 2.2λ / NA.

  However, if the interval S between the dummy pattern WLD and the end of the word line is too narrow, the problem of resist short-circuiting at the interval S will occur rather than a contrast surface at the end of the word line. Specifically, it is desirable that the line width L of the word line end pattern is 1.5 times or more from the resolution limit of resist omission.

  In addition, if the width W of the dummy pattern WLD is too short, the exposure margin of the dummy pattern WLD itself is lowered, so that the minimum dimension of the dummy pattern width from the point of the exposure margin of the dummy pattern WLD itself is 0. 3λ / NA or more is realistic.

  From the above, the preferable conditions for the width W of the dummy pattern WLD and the distance S between the dummy pattern WLD and the end of the word line are 1.5 × L ≦ S ≦ 2.2 × λ / NA, 0.3 It was found that the condition of × λ / NA ≦ W ≦ 2.2 × λ / NA should be satisfied.

  From the above, when the word line WL is formed by etching using the silicon nitride film 114 as a mask, the thinning of the resist pattern at the end (tip) of the word line WL is improved by the dummy pattern WLD. It is possible to provide a non-volatile semiconductor memory device with improved collapse margin and stable high yield.

  In the present embodiment, one dummy pattern WLD is formed. However, by providing a plurality of dummy patterns, the interlayer insulating film, which is not described in the above-described embodiment, is flattened. The load may be reduced.

In the above-described embodiments, the present invention has been described by taking the NAND type nonvolatile semiconductor memory device as an example. However, the present invention is also applied to other semiconductor devices such as a semiconductor memory device having a word line or a bit line. can do. That is, the present invention can be applied to any semiconductor device having a line pattern that causes pattern collapse. At that time, a material to be patterned which is an underlayer patterned with a resist is appropriately selected.

  Furthermore, in the above-described embodiment, the dummy pattern is provided only on one end side of the word line, which is a line pattern, but may be provided on both end sides of the word line.

  The line pattern is not limited to a word line but may be a pattern such as a bit line.

  Further, as a method for determining the effect of preventing the fall of the end of the word line, the contrast at the BB ′ position in the AA ′ section is used as an index from the image intensity distribution at the end of the word line. The determination means is not limited, and appropriate determination means may be used in a timely manner. For example, a B-B ′ section may be used instead of the A-A ′ section. Further, the image intensity distribution is not limited to that in the lithography process. For example, a latent image distribution in a resist may be used, and a determination method may be determined and applied from resist pattern shape information after development.

FIG. 2 is a plan view illustrating the configuration of the nonvolatile semiconductor memory device according to the first embodiment. Sectional drawing explaining the structure of the non-volatile semiconductor memory device which concerns on 1st Embodiment. The figure which shows typically the cross-sectional structure in the one stage in the middle of manufacture (the 1) A diagram schematically showing a cross-sectional structure at one stage during production (part 2) FIG. 3 schematically shows a cross-sectional structure at one stage during production (part 3). FIG. 4 schematically shows a cross-sectional structure at one stage during manufacture (part 4). The figure for demonstrating the image intensity distribution in the A-A 'cross section in FIG. 1 with and without a dummy pattern The figure for demonstrating the space | interval dependence of the dummy pattern of contrast and the edge part of a word line The figure for explaining the width dependence of contrast dummy pattern

Explanation of symbols

WL word line, SGL select gate line, WLD dummy pattern,
100 semiconductor substrate, 102 element isolation insulating film, 104 tunnel insulating film,
106 a first polycrystalline silicon film, 108 an interelectrode insulating film, 110
A second polycrystalline silicon film, 112 a low resistance conductive film, 114 a silicon nitride film,
120 anti-reflective coating, 122 photoresist

Claims (5)

Forming a member to be patterned on a semiconductor substrate;
The patterning member is patterned to form a plurality of line-shaped patterns in parallel, and at the end portions of the plurality of line-shaped patterns at predetermined intervals from the longitudinal ends of the plurality of line-shaped patterns. And a step of forming a dummy pattern in a direction perpendicular to the longitudinal direction so as to face each other. When the exposure wavelength of the exposure apparatus is λ, the numerical aperture of the projection lens of the exposure apparatus is NA, and the width of the line pattern is L, the distance S between the end side of the line pattern and the dummy pattern And the width W of the dummy pattern is 1.5 × L ≦ S ≦ 2.2 × λ / NA,
0.3 × λ / NA ≦ W ≦ 2.2 × λ / NA
2. The method of manufacturing a semiconductor device according to claim 1, wherein both of the conditions are satisfied.   3. The method of manufacturing a semiconductor device according to claim 1, wherein the line pattern is a word line of a memory cell transistor. A plurality of word lines whose longitudinal direction is formed along a predetermined direction on the semiconductor substrate;
A dummy pattern having a longitudinal direction formed along a direction orthogonal to the predetermined direction so as to face the end portions of the plurality of word lines at a predetermined interval from the end portions of the plurality of word lines. A featured semiconductor device. When the exposure wavelength of the exposure apparatus is λ, the numerical aperture of the projection lens of the exposure apparatus is NA, and the width of the word line is L, the predetermined interval S and the width W of the dummy pattern are 1.5 × L ≦ S ≦ 2.2 × λ / NA,
0.3 × λ / NA ≦ W ≦ 2.2 × λ / NA
5. The semiconductor device according to claim 4, wherein both of the conditions are satisfied.

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